TWI785751B - Variable resistance memory device - Google Patents

Abstract

Embodiments provide a variable resistance memory device that can efficiently read data. A first memory cell is coupled to first and third interconnects. A second memory cell is coupled to second and fourth interconnects. A first sense amplifier has a first terminal coupled to the first interconnect and a node of a first potential and a second terminal located close to a node of a second potential and coupled to the third interconnect and has a potential difference between the first and second terminals. A second sense amplifier has a third terminal coupled to the fourth interconnect and a node of a third potential and a fourth terminal located close to a node of a fourth potential and coupled to the second interconnect and has a potential difference between the third and fourth terminals.

Description

variable resistance memory device

Embodiments described herein generally relate to a variable resistance memory device.

A memory device is known that includes a memory cell that can have a resistance of a different magnitude based on a state.

The embodiment provides a variable resistance memory device capable of effectively reading data.

In general, according to an embodiment, a variable resistance memory device includes: a first interconnection; a second interconnection; a third interconnection; a fourth interconnection; a memory cell; a second memory cell; a first sense amplifier; and a second sense amplifier. The first memory cell is coupled to the first interconnection and the third interconnection, and has a variable resistance. The second memory cell is coupled to the second interconnection and the fourth interconnection, and has a variable resistance. The first sense amplifier has a first terminal and a second terminal, and there is a potential difference between the first terminal and the second terminal. The first terminal is coupled to the first interconnect and a node of a first potential. The second terminal is positioned proximate to a node of a second potential and is coupled to the third interconnect. The second sense amplifier has a third terminal and a fourth terminal, and there is a potential difference between the third terminal and the fourth terminal. The third terminal is coupled to the fourth interconnect and a node of a third potential. The fourth terminal is positioned close to a node of a fourth potential and is coupled to the second interconnect.

Embodiments will now be described with reference to these figures. In the following description, components having substantially the same functionality and configuration will be denoted by the same symbol, and repeated descriptions may be omitted. In order to distinguish components having substantially the same function and configuration from one another, an additional number or letter may be added to the end of each element symbol.

The entire description of a particular embodiment also applies to another embodiment unless otherwise explicitly mentioned or obviously omitted.

In this specification and the scope of the invention patent application, the phrase "coupled" to another second component includes that the first component is coupled to the second component directly or through one or more components that are always or selectively conductive. .

Embodiments will be described by using an xyz orthogonal coordinate system. In the following description, the term "below" and terms derived therefrom and terms related thereto refer to a position having one of the smaller coordinates on the z-axis, the term "above" and terms derived therefrom and terms related thereto Refers to a position with one of the larger coordinates on the z-axis. 1. The first embodiment 1.1. Structure (configuration) 1.1.1. Overall structure

FIG. 1 shows the functional blocks of a variable resistance memory device according to the first embodiment. As shown in FIG. 1, a memory device 1 includes a memory cell array 11, an input and output circuit 12, a control circuit 13, a column selector 14, a row selector 15, a write circuit 16 and a read circuit. Take circuit 17.

The memory cell array 11 includes memory cells MC, word lines WL and bit lines BL. The memory cell MC can store data in a non-volatile manner. Each memory cell MC is coupled to a single word line WL and a single bit line BL. Each word line WL is associated with a column. Each bit line BL is associated with one row. Selection of a column and selection of one or more rows designate one or more memory cells MC.

The input and output circuit 12 receives, for example, a control signal CNT of various types, a command CMD of various types, an address signal ADD, and data (writing data) DAT from a memory controller 2, and transmits the data (reading data) ) DAT is transmitted to, for example, the memory controller 2.

Column selector 14 receives address signal ADD from input and output circuit 12, and brings a single word line WL associated with the column specified by the received address signal ADD into a selected state.

Row selector 15 receives address signal ADD from input and output circuit 12, and brings bit line BL associated with the row specified by the received address signal ADD into a selected state.

The control circuit 13 receives a control signal CNT and a command CMD from the input and output circuit 12 . The control circuit 13 controls the writing circuit 16 and the reading circuit 17 based on the control indicated by the control signal CNT and the command CMD. Specifically, the control circuit 13 supplies the voltage for data writing to the writing circuit 16 during data writing into the memory cell array 11 . In addition, the control circuit 13 supplies voltage for data reading to the reading circuit 17 during data reading from the memory cell array 11 .

The writing circuit 16 receives the writing data DAT from the input and output circuit 12 , and supplies a voltage for data writing to the row selector 15 based on the control of the control circuit 13 and the writing data DAT.

The read circuit 17 includes a sense amplifier SA, and based on the control of the control circuit 13, uses the voltage for data read to determine the data stored in the memory cell MC. The determined data is supplied to the input and output circuit 12 as read data DAT. 1.1.2. Circuit configuration of memory cell array

FIG. 2 is a circuit diagram of a memory cell array 11 according to the first embodiment. As shown in FIG. 2 , the memory cell array 11 includes (M+1) word lines WLa (WLa<0>, WLa<1>, . . . and WLa<M>) and (M+1) word lines WLb (WLb<0>, WLb<1>, . . . and WLb<M>), wherein M is a natural number.

The memory cell array 11 also includes (N+1) bit lines BL (BL<0>, BL<1>, . . . , BL<N>), wherein N is a natural number.

Each of memory cells MC (MCa and MCb) includes two nodes: a first node N1 coupled to a single word line WL; and a second node N2 coupled to a single bit line BL. More specifically, memory cells MCa include memory cells MCa <α, β> for any combination of α and β, where α is an integer equal to or greater than 0 and equal to or less than M, and β is equal to or an integer greater than 0 and equal to or less than N, and the memory cell MCa<α,β> is coupled between the word line WLa<α> and the bit line BL<β>. Similarly, memory cell MCb includes memory cell MCb<α,β> for any combination of α and β, where α is an integer equal to or greater than 0 and equal to or less than M, and β is equal to or greater than 0 and equal to or less than an integer of N, and the memory cell MCb<α,β> is coupled between the word line WLb<α> and the bit line BL<β>.

Each memory cell MC includes a variable resistance element VR (VRa or VRb) and a switching element SE (SEa or SEb). More specifically, the memory cell MCa<α,β> includes a variable resistance element VRa<α,β> and a switching element SEa<α,β> for any combination of α and β, wherein α is equal to or an integer greater than 0 and equal to or less than M, and β is an integer equal to or greater than 0 and equal to or less than N. Moreover, the memory cell MCb<α, β> includes a variable resistance element VRb<α, β> and a switching element SEb<α, β> for any combination of α and β, wherein α is equal to or greater than is an integer equal to or less than M, and β is an integer equal to or greater than 0 and equal to or less than N.

In each memory cell MC, the variable resistance element VR and the switching element SE are coupled in series. The variable resistance element VR is coupled to a single word line WL, and the switching element SE is coupled to a single bit line BL.

The variable resistance element VR is switchable between a low resistance state and a high resistance state. The variable resistance element VR can use the difference of two resistance states to store 1-bit data.

For example, the switching element SE may be one of the switching elements described below. The switching element comprises two terminals, and when a voltage less than a first threshold value is applied in a first direction between the two terminals, the switching element is in a high resistance state, i.e., non-conductive (in an off state). off state). On the other hand, when a voltage equal to or greater than a first threshold value is applied in the first direction between the two terminals, the switching element is in a low resistance state, ie conducts (in an on state). The switching element is further equipped with a function similar to that of switching between a high resistance state and a low resistance state based on the magnitude of the voltage applied in the first direction (relative to a second direction opposite to the first direction). By turning on or off the switching element, control as to whether to supply a current to the variable resistance element VR coupled to the switching element (ie, whether to select the variable resistance element VR) can be performed. 1.1.3. Structure of memory cell array

3 and 4 show a cross-sectional structure of part of the memory cell array 11 of the first embodiment. Figure 3 shows a cross section along the xz plane and Figure 4 shows a cross section along the yz plane. 3 and 4 show an example in which the variable resistance element VR is a magnetoresistance effect element. The following description is based on this example.

As shown in FIGS. 3 and 4 , a plurality of conductors 21 are provided over a semiconductor substrate (not shown). Conductor 21 extends along the y-axis and is aligned along the x-axis. Each conductor 21 serves as a word line WL.

Each conductor 21 is coupled at its top surface to the bottom surfaces of the plurality of memory cells MCb. Each memory cell MCb has, for example, a circular shape in the xy plane. Memory cells MCb are aligned along the y-axis on each conductor 21, and this configuration provides a matrix of memory cells MCb above the xy plane. Each memory cell MCb includes a structure serving as a switching element SEb and a structure serving as a magnetoresistance effect element VRb. The structure serving as a switching element SEb and the structure serving as a magnetoresistance effect element VRb each have one or more layers, as will be described later.

A plurality of conductors 22 are provided above the memory cell MCb. Conductor 22 extends along the x-axis and is aligned along the y-axis. Each conductor 22 is coupled at its bottom surface to the top surface of a plurality of memory cells MCb aligned along the x-axis. Each conductor 22 serves as a bit line BL.

Each conductor 22 is coupled at its top surface to the bottom surface of the plurality of memory cells MCa. Each memory cell MCa has, for example, a circular shape in the xy plane. Memory cells MCa are aligned along the x-axis on each conductor 22, and this configuration provides a matrix of memory cells MCa above the xy plane. Each memory cell MCa includes a structure serving as a switching element SEa and a structure serving as a magnetoresistance effect element VRa. The structure serving as a switching element SEa and the structure serving as a magnetoresistance effect element VRa each have one or more layers, as will be described later.

A further conductor 21 is provided on the top surface of the memory cell MCa aligned along the y-axis.

The memory cell array 11 shown in FIG. 2 can be implemented by repeatedly providing the structure shown in FIGS. 3 and 4 from the layer of the lowest conductor 21 to the layer of the memory cell MCa along the z-axis.

The memory cell array 11 further includes an interlayer insulator in a region where the conductors 21 and 22 and the memory cell MC are not provided.

FIG. 5 shows a cross-section of an example of the structure of the memory cell MC according to the first embodiment. As shown in FIG. 5 , the switching element SE includes a lower electrode 24 , a variable resistance material (layer) 25 and an upper electrode 26 . The lower electrode 24 is positioned on a top surface of the conductor 21 or 22 (not shown). The variable resistance material 25 is positioned on a top surface of the lower electrode 24 . The upper electrode 26 is positioned on a top surface of the variable resistance material 25 .

Each of the lower electrode 24 and the upper electrode 26 contains or is made of, for example, titanium nitride (TiN).

The variable resistance material 25 is, for example, a switching element between two terminals. A first terminal of the two terminals is one of the top and bottom surfaces of the variable resistance material 25 , and a second terminal of the two terminals is the other of the top and bottom surfaces of the variable resistance material 25 .

A single magnetoresistance effect element VR is positioned on the top surface of each upper electrode 26 . The magnetoresistance effect element VR exhibits tunneling magnetoresistance and includes a magnetic tunnel junction (MTJ). In the embodiment, an MTJ device is used as a memory device for description. It should be noted that the MTJ element will hereinafter be referred to as a magnetoresistance effect element VR for convenience of description. More specifically, the magnetoresistance effect element VR includes a ferromagnetic layer 31 , an insulating layer 32 and a ferromagnetic layer 33 . As an example, as shown in FIG. 5 , insulating layer 32 is positioned on a top surface of ferromagnetic layer 31 , and ferromagnetic layer 33 is positioned on a top surface of insulating layer 32 .

The ferromagnetic layer 31 is in one direction penetrating the interface between the ferromagnetic layer 31, the insulating layer 32, and the ferromagnetic layer 33 (for example, at an angle of 45° to 90° relative to the interface, or in a direction perpendicular to the interface. One direction) has an easy axis of magnetization. Even when reading or writing data in the memory device 1, the magnetization direction of the ferromagnetic layer 31 is intended to remain unchanged. The ferromagnetic layer 31 can be used as a so-called reference layer. Ferromagnetic layer 31 may include a stacked ferromagnetic layer and/or conductive layer.

The insulating layer 32 contains or is made of, for example, magnesium oxide (MgO), and serves as a so-called "tunneling barrier".

The ferromagnetic layer 33 contains or is made of, for example, cobalt iron boron (CoFeB) or iron boride (FeB). The ferromagnetic layer 33 is in one direction penetrating the interface between the ferromagnetic layer 31, the insulating layer 32, and the ferromagnetic layer 33 (for example, at an angle of 45° to 90° relative to the interface, or in a direction perpendicular to the interface. One direction) has an easy axis of magnetization. The magnetization direction of the ferromagnetic layer 33 can be changed by data writing, and the ferromagnetic layer 33 can be used as a so-called "storage layer".

When the magnetization direction of the ferromagnetic layer 33 is parallel to the magnetization direction of the ferromagnetic layer 31, the magnetoresistance effect element VR is in a state having a lower resistance. When the magnetization direction of the ferromagnetic layer 33 is antiparallel to the magnetization direction of the ferromagnetic layer 31, the magnetoresistance effect element VR has a resistance higher than that in the case where the magnetization directions of the ferromagnetic layers 31 and 33 are antiparallel to each other. a state.

When a write current Iwp of a certain magnitude flows from the ferromagnetic layer 33 to the ferromagnetic layer 31 , the magnetization direction of the ferromagnetic layer 33 becomes parallel to the magnetization direction of the ferromagnetic layer 31 . In contrast, when a write current Iwap of another magnitude flows from the ferromagnetic layer 31 to the ferromagnetic layer 33 , the magnetization direction of the ferromagnetic layer 33 becomes antiparallel to the magnetization direction of the ferromagnetic layer 31 . In the case where a read current Ir is supplied to the magnetoresistance effect element VR, the resistance state of the magnetoresistance effect element VR can be determined based on the voltage across the magnetoresistance effect element VR when the read current is supplied.

The memory cell MC may further include a conductor, an insulator and/or a ferromagnet.

FIG. 6 shows details of some functional blocks of the memory device 1 according to the first embodiment. More specifically, FIG. 6 shows the components, connections and layout of portions of each of memory cell array 11 , column selector 14 , row selector 15 , and write circuit 16 .

As shown in FIG. 6 , the memory cell array 11 is divided into four parts. The four parts each have a rectangular shape in the xy plane, do not overlap each other, and will be referred to as sub-arrays 11ul, 11ur, 11dl, and 11dr hereinafter. The sub-arrays 11ul, 11ur, 11dl, and 11dr have equal or different areas, ie, include the same or different numbers of memory cells MC. The sub-arrays 11ul, 11ur, 11dl and 11dr are separated from each other. Subarrays 11ul, 11ur, 11dl, and 11dr each include word lines WL, bit lines BL, and memory cells MC. The sub-arrays 11ul, 11ur, 11dl and 11dr respectively occupy the upper left, upper right, lower left and lower right parts of the memory cell array 11 in the xy plane. The sub-arrays 11ul, 11ur, 11dl, and 11dr may be hereinafter referred to as an upper-left sub-array 11ul, an upper-right sub-array 11ur, a lower-left sub-array 11dl, and a lower-right sub-array 11dr, respectively.

The word line WL in the upper left sub-array 11ul and the word line WL in the upper right sub-array 11ur are common. In other words, each word line WL in the upper left sub-array 11ul extends above the upper left sub-array 11ul and the upper right sub-array 11ur. A word line WL extending above the upper left sub-array 11ul and the upper right sub-array 11ur may be referred to as an upper word line WLu hereinafter.

The word line WL in the lower left sub-array 11dl and the word line WL in the lower right sub-array 11dr are common. In other words, each word line WL in the lower left sub-array 11dl extends above the lower left sub-array 11dl and the lower right sub-array 11dr. A word line WL extending over the lower left sub-array 11dl and the lower right sub-array 11dr may be referred to as a lower word line WLd hereinafter.

The bit line BL in the upper left sub-array 11ul and the bit line BL in the lower left sub-array 11dl are common. In other words, the bit lines BL in the upper left sub-array 11ul extend above the upper left sub-array 11ul and the lower left sub-array 11dl. A bit line BL extending above the upper left sub-array 11ul and the lower left sub-array 11dl may be referred to as a left bit line BL1 hereinafter.

The bit line BL in the upper right sub-array 11ur and the bit line BL in the lower right sub-array 11dr are common. In other words, the bit lines BL in the upper right sub-array 11ur extend above the upper right sub-array 11ur and the lower right sub-array 11dr. A bit line BL extending above the upper right sub-array 11ur and the lower right sub-array 11dr may be referred to as a right bit line BLr hereinafter.

Each memory cell MC is positioned between a single word line WL and a single bit line BL, as described with reference to FIGS. 3 and 4 . A memory cell MC positioned between the upper word line WLu and the left bit line BL1 (i.e., one of the memory cells MC in the upper left sub-array 11ul) may hereinafter be referred to as an upper left memory cell MCul .

A memory cell MC positioned between the upper word line WLu and the right bit line BLr (ie, one of the memory cells MC in the upper right sub-array 11ur) may hereinafter be referred to as an upper right memory cell MCur .

A memory cell MC positioned between the lower word line WLd and the left bit line BL1 (ie, one of the memory cells MC in the lower left sub-array 11d1) may hereinafter be referred to as a lower left memory cell MCd1 .

A memory cell MC positioned between the lower word line WLd and the right bit line BLr (ie, one of the memory cells MC in the lower right sub-array 11dr) may hereinafter be referred to as a lower right memory cell MCdr.

The column selector 14 extends along the y-axis and is positioned in an area between the upper left sub-array 11ul and the upper right sub-array 11ur and in an area between the lower left sub-array 11dl and the lower right sub-array 11dr. The column selector 14 extends from the upper end of each of the upper left sub-array 11ul and the upper right sub-array 11ur to the lower end of each of the lower left sub-array 11dl and the lower right sub-array 11dr.

The column selector 14 is formed by a first portion 14u and a second portion 14d. The first part 14u is formed by a part of the area between the upper left sub-array 11ul and the upper right sub-array 11ur in the column selector 14 . The second portion 14d is formed by a part of the area between the lower left sub-array 11dl and the lower right sub-array 11dr in the column selector 14 . The first part 14u may hereinafter be referred to as an upper column selector 14u, and the second part 14d may hereinafter be referred to as a lower selector 14d.

The upper column selector 14u is coupled to all upper word lines WLu. The upper column selector 14u receives the address signal ADD, and couples one of the upper word lines WLu designated by the address signal ADD to a first node N1 of a sense amplifier SAul (to be described later). In addition, the upper column selector 14u couples one of the upper word lines WLu designated by the address signal ADD to a first node N1 of a sense amplifier SAur (to be described later).

The following selectors 14d are coupled to all lower word lines WLd. The following selector 14d receives the address signal ADD, and couples one of the lower word lines WLd designated by the address signal ADD to a first node N1 of a sense amplifier SAd1 (to be described later). In addition, the following selector 14d couples one of the lower word lines WLd designated by the address signal ADD to a first node N1 of a sense amplifier SAdr (to be described later).

The row selector 15 extends along the x-axis and is positioned in an area between the upper left sub-array 11ul and the lower left sub-array 11dl and in an area between the upper right sub-array 11ur and the lower right sub-array 11dr. The row selector 15 extends from the left end of each of the upper-left sub-array 11ul and the lower-left sub-array 11dl to the right end of each of the upper-right sub-array 11ur and the lower-right sub-array 11dr.

The row selector 15 is formed by a first part 15l and a second part 15r. The first portion 15l is formed by a part of the area between the upper left sub-array 11ul and the lower left sub-array 11dl in the row selector 15 . The second part 15r is formed by a part of the area between the upper right sub-array 11ur and the lower right sub-array 11dr in the row selector 15 . The first part 151 may hereinafter be referred to as a left row selector 151, and the second part 15r may be referred to hereinafter as a right row selector 15r.

Left row selector 151 is coupled to all left bit lines BL1. The left row selector 151 receives the address signal ADD, and couples one of the left bit lines BL1 designated by the address signal ADD to a second node N2 of the sense amplifier SAul. In addition, the left row selector 151 couples one of the left bit lines BL1 designated by the address signal ADD to a second node N2 of the sense amplifier SAd1.

Right row selector 15r is coupled to all right bit lines BLr. The right row selector 15r receives the address signal ADD, and couples one of the right bit lines BLr designated by the address signal ADD to a second node N2 of the sense amplifier SAur. In addition, the right row selector 15r couples one of the right bit lines BLr designated by the address signal ADD to a second node N2 of the sense amplifier SAdr.

Sense amplifiers SA (sense amplifiers SAul, SAur, SAdl, and SAdr) are included in read circuit 17 and perform at least some of the operations of read circuit 17 . The sense amplifiers SAul, SAur, SAdl, and SAdr may be referred to hereinafter as upper left sense amplifier SAul, upper right sense amplifier SAur, lower left sense amplifier SAdl, and lower right sense amplifier SAdr, respectively.

The first node N1 and the second node N2 of the upper left sense amplifier SAul may be respectively referred to as a first node N1ul and a second node N2ul hereinafter. The first node N1 and the second node N2 of the upper right sense amplifier SAur may be respectively referred to as a first node N1ur and a second node N2ur hereinafter. The first node N1 and the second node N2 of the lower left sense amplifier SAd1 may be respectively referred to as a first node N1d1 and a second node N2d1 hereinafter. The first node N1 and the second node N2 of the lower right sense amplifier SAdr may be respectively referred to as a first node N1dr and a second node N2dr in the following.

The first node N1ul of the upper left sense amplifier SAul is coupled to the upper column selector 14u. The first node N1ul of the upper left sense amplifier SAul may be coupled to one of the upper word lines WLu by the upper selector 14u, as described above.

The second node N2ul of the upper left sense amplifier SAul is coupled to the left row selector 151. The second node N2ul of the upper left sense amplifier SAul may be coupled to one of the left bit lines BL1 by the left row selector 151, as described above.

The upper left sense amplifier SAul is coupled at a second node N2ul to a node of a high potential (e.g., supply potential) in the upper left sense amplifier SAul and is coupled at a first node N1ul into the upper left sense amplifier SAul A node of a low potential (eg, ground potential). The potential of the second node N2ul is lower than the potential of the first node N1ul. The upper left sense amplifier SAul is configured to source a current from the second node N2ul and also sink current at the first node N1ul. In addition, the upper left sense amplifier SAul can obtain data stored in a read target memory cell MC (hereinafter referred to as a selected memory cell MCS) coupled to the upper left sense amplifier SAul. That is, the upper left sense amplifier SAul receives a reference voltage Vref, and can compare the reference voltage Vref with the voltage of a node (sometimes hereinafter referred to as a sense node SEN) in which the selected One voltage of the resistance state of the memory cell MCS. The upper left sense amplifier SAul can output the selected memory based on whichever of the two comparison voltages is higher by operating when the selected memory cell MCS is coupled between the first node N1ul and the second node N2ul. One of the states of the soma cell MCS voltage.

The first node N1ur of the upper right sense amplifier SAur is coupled to the upper column selector 14u. The first node N1ur of the upper right sense amplifier SAur may be coupled to one of the upper word lines WLu by the upper selector 14u, as described above.

The second node N2ur of the upper right sense amplifier SAur is coupled to the right row selector 15r. The second node N2ur of the upper right sense amplifier SAur may be coupled to one of the right bit lines BLr by the right row selector 15r, as described above.

The upper right sense amplifier SAur is coupled at a second node N2ur to a node of one of the upper right sense amplifiers SAur at a higher potential (e.g., power supply potential) and at a first node N1ur to one of the upper right sense amplifiers SAur One of the nodes at low potential (eg, ground potential). The potential of the second node N2ur is lower than the potential of the first node N1ur. The upper right sense amplifier SAur is configured to supply a current from the second node N2ur and sink current at the first node N1ur. In addition, the upper right sense amplifier SAur can obtain the data stored in the selected memory cell MCS coupled to the upper right sense amplifier SAur. That is, the upper right sense amplifier SAur receives the reference voltage Vref, and can compare the reference voltage Vref with the voltage of the sense node SEN of the upper right sense amplifier SAur. The upper right sense amplifier SAur can output the selected memory based on whichever of the two comparison voltages is higher by operating when the selected memory cell MCS is coupled between the first node N1ur and the second node N2ur. One of the states of the cell MCS voltage.

The first node N1dl of the lower left sense amplifier SAdl is coupled to the following selector 14d. The first node N1dl of the lower left sense amplifier SAdl may be coupled to one of the lower word lines WLd by the following selector 14d, as described above.

The second node N2dl of the lower left sense amplifier SAdl is coupled to the left row selector 15l. The second node N2dl of the lower left sense amplifier SAdl can be coupled to one of the left bit lines BLl by the left row selector 15l, as described above.

The lower left sense amplifier SAd1 is coupled at a first node N1d1 to a node of one of the lower left sense amplifiers SAd1 at a higher potential (eg, power supply potential) and at a second node N2d1 to one of the lower left sense amplifiers SAd1 One of the nodes at low potential (eg, ground potential). The potential of the first node N1dl is lower than the potential of the second node N2dl. The lower left sense amplifier SAd1 is configured to source a current from the first node N1d1 and sink current at the second node N2d1. In addition, the lower left sense amplifier SAd1 has access to the data stored in the selected memory cell MCS coupled to the lower left sense amplifier SAd1. That is, the lower left sense amplifier SAd1 receives the reference voltage Vref, and can compare the reference voltage Vref with the voltage of the sensing node SEN of the lower left sense amplifier SAd1. The lower left sense amplifier SAd1 can output the selected memory based voltage based on which of the two comparison voltages is higher by operating when the selected memory cell MCS is coupled between the first node N1d1 and the second node N2d1. One of the states of the cell MCS voltage.

The first node N1dr of the lower right sense amplifier SAdr is coupled to the following selector 14d. The first node N1dr of the lower right sense amplifier SAdr may be coupled to one of the lower word lines WLd by the following selector 14d, as described above.

The second node N2dr of the lower right sense amplifier SAdr is coupled to the right row selector 15r. The second node N2dr of the lower right sense amplifier SAdr can be coupled to one of the right bit lines BLr by the right row selector 15r, as described above.

The lower right sense amplifier SAdr is coupled at a first node N1dr to one of the lower right sense amplifiers SAdr at a higher potential (e.g., power supply potential) and at a second node N2dr to the lower right sense amplifier SAdr One of the nodes at a lower potential (eg, ground potential). The potential of the first node N1dr is lower than the potential of the second node N2dr. The lower right sense amplifier SAdr is configured to source a current from the first node N1dr and sink current at the second node N2dr. In addition, the lower right sense amplifier SAdr has access to the data stored in the selected memory cell MCS coupled to the lower right sense amplifier SAdr. That is, the lower right sense amplifier SAdr receives the reference voltage Vref, and can compare the reference voltage Vref with the voltage of the sensing node SEN of the lower right sense amplifier SAdr. The lower right sense amplifier SAdr can output a selected memory based on whichever of the two comparison voltages is higher by operating when the selected memory cell MCS is coupled between the first node N1dr and the second node N2dr. One of the states of the soma cell MCS voltage. 1.1.3.1. Details of Column Selector and Row Selector

Fig. 7 shows an example of components and connections of the column selector 14 and the row selector 15 according to the first embodiment.

As shown in FIG. 7 , the upper column selector 14u includes a plurality of local column switches TLYu, a local word line LWLu, a global column switch TGu, and a global word line GWLu. Each local column switch TLYu is coupled between a single upper word line WLu and local word line LWLu. Each local column switch TLYu receives at its control terminal one of the control signals LYu (LYu1, LYu2, . . . or LYut (t being a natural number)), and is turned on or off based on the control signal LYu. Each local column switch TLyu can be an n-type metal oxide semiconductor field effect transistor (MOSFET) and receives a control signal LYu at its gate terminal. The upper column selector 14u sets only the control signal LYu supplied to one of the plurality of local column switches TLYu designated by the address signal ADD to a level for designating selection (for example, a high level). Therefore, among the plurality of local column switches TLyu, only the local column switch TLyu that receives the control signal LYu for specifying the level of selection remains turned on.

When one of the plurality of local column switches TLYu is turned on, the word line WLu coupled to the local column switch TLYu is coupled to the local word line LWLu via the local column switch TLYu.

The local word line LWLu is coupled to the global word line GWLu via the global column switch TGYu. The global column switch TGYu receives at its control terminal a control signal GY from another component (not shown) in the column selector 14 and is turned on or off based on the control signal GY. The global column switch TGYu can be an n-type MOSFET and receives the control signal GY at its gate terminal.

The following selector 14d includes a plurality of local column switches TLYd, a local word line LWLd, a global column switch TGYd and a global word line GWLd. Each local column switch TLYd is coupled between a single lower word line WLd and a local word line LWLd. Each local column switch TLYd receives at its control terminal from another component (not shown) in the column selector 14 a control signal LYd (LYd1, LYd2, . . . or LYds (s is a natural number)), and is turned on or off based on the control signal LYd. Each local column switch TGYd may be an n-type MOSFET and receives control signal LYd at its gate terminal. The following selector 14d sets only the control signal LYd supplied to one of the plurality of local column switches TLYd designated by the address signal ADD to a level (for example, a high level) for designating selection. Therefore, among the plurality of local column switches TLYd, only the local column switch TLYd that receives the control signal LYd for specifying the level of selection remains turned on.

When one of the plurality of local column switches TLYd is turned on, the word line WLd coupled to the local column switch TLYd is coupled to the local word line LWLd via the local column switch TLYd.

The local word line LWLd is coupled to the global word line GWLd via the global column switch TGYd. Global column switch TGYd receives a control signal GY at its control terminal from another component (not shown) in column selector 14 and is turned on or off based on the control signal GY. The global column switch TGYd can be an n-type MOSFET and receives the control signal GY at its gate terminal.

The left row selector 151 includes a plurality of local row switches TLX1, a local bit line LBL1, a global row switch TGX1 and a global bit line GBL1. Each local row switch TLX1 is coupled between a single left bit line BL1 and local bit line LBL1. Each local row switch TLX1 receives at its control terminal one of the control signals LX1 (LX11, LX12, . . . or LXlp (p is a natural number)), and is turned on or off based on the control signal LX1. Each local row switch TLX1 can be an n-type MOSFET and receives control signal LY1 at its gate terminal. The left row selector 151 sets only the control signal LY1 supplied to one of the plurality of local row switches TLX1 designated by the address signal ADD to a level (for example, a high level) for designating selection. Therefore, among the plurality of local row switches TLX1, only the local row switch TLX1 that receives the control signal LY1 for specifying the level of selection remains turned on.

When one of the plurality of local row switches TLX1 is turned on, the left bit line BL1 coupled to the local row switch TLX1 is coupled to the local bit line LBL1 via the local row switch TLX1.

Local bit line LBL1 is coupled to global bit line GBL1 via global row switch TGX1. The global row switch TGX1 receives at its control terminal a control signal GX from another component (not shown) in the row selector 15, and is turned on or off based on the control signal GX. The global row switch TGX1 can be an n-type MOSFET and receives the control signal GX at its gate terminal.

The right row selector 15r includes a plurality of local row switches TLXr, a local bit line LBLr, a global row switch TGXr and a global bit line GBLr. Each local row switch TLXr is coupled between a single right bit line BLr and local bit line LBLr. Each local row switch TLXr receives at its control terminal from another component (not shown) in the row selector 15 a control signal LXr (LXr1, LXr2, . . . or LXrq (q being a natural number)), and is turned on or off based on the control signal LXr. Each local row switch TLXr can be an n-type MOSFET and receives control signal LYr at its gate terminal. The right row selector 15r sets only the control signal LYr supplied to one of the plurality of local row switches TLXr designated by the address signal ADD to a level (for example, a high level) for designating selection. Therefore, among the plurality of local row switches TLXr, only the local row switch TLXr that receives the control signal LYr for specifying the level of selection remains turned on.

When one of the plurality of local row switches TLXr is on, the right bit line BLr coupled to the local row switch TLXr is coupled to the local bit line LBLr via the local row switch TLXr.

The local bit line LBLr is coupled to the global bit line GBLr via the global row switch TGXr. The global row switch TGXr receives a control signal GX at its control terminal from another component (not shown) in the row selector 15 and is turned on or off based on the control signal GX. The global row switch TGXr can be an n-type MOSFET and receives the control signal GX at its gate terminal. 1.1.3.2. Sense amplifier details

Each of the upper left sense amplifier SAul and the upper right sense amplifier SAur may comprise any components and connections as long as it can supply a current from its second node N2, sink a current at its first node N1, and based on the sense node The voltage of SEN and the reference voltage Vref are read as described above. Similarly, each of the lower left sense amplifier SAd1 and the lower right sense amplifier SAdr may include any components and connections as long as it can source a current from its first node N1, sink a current at its second node N2, and The read data is obtained based on the voltage of the sensing node SEN and the reference voltage Vref.

Some detailed examples will be described below. However, details of the upper left sense amplifier SAul, upper right sense amplifier SAur, lower left sense amplifier SAdl, and lower right sense amplifier SAdr do not limit the first embodiment. 1.1.3.2.1. First instance

FIG. 8 shows a first example of components and connections of the upper left sense amplifier SAul or the upper right sense amplifier SAur according to the first embodiment. As shown in FIG. 8, each of the upper left sense amplifier SAul and the upper right sense amplifier SAur includes a p-type MOSFET TP11, n-type MOSFETs TN11 and TN12, and an operational amplifier OP1.

Transistor TP11 is coupled at its first terminal (one of source and drain) to a node of a supply potential (e.g., Vdd) and at its second terminal (the other of source and drain) is coupled to its gate and to a first terminal of transistor TN11. A gate of transistor TP11 is used as a sense node SEN, and is coupled to a non-inverting input terminal of operational amplifier OP1.

The operational amplifier OP1 receives a reference voltage Vref at its inverting input terminal. An output from the operational amplifier OP1 is received by a data latch in the reading circuit 17 .

A second terminal of transistor TN11 is coupled to a second node N2ul in the upper left sense amplifier SAul, and to a second node N2ur in the upper right sense amplifier SAur. One gate of the transistor TN11 receives an enabling signal EN. For example, an enable signal EN is supplied from the control circuit 13 .

A first terminal of transistor TN12 is coupled to a first node N1ul in the upper left sense amplifier SAul, and to a first node N1ur in the upper right sense amplifier SAur. A second terminal of transistor TN12 is coupled to a node at a common potential (eg, a ground potential Vss). One gate of the transistor TN12 receives the enabling signal EN.

FIG. 9 shows a first example of components and connections of the lower left sense amplifier SAdl or the lower right sense amplifier SAdr according to the first embodiment. As shown in FIG. 9, each of the lower left and right sense amplifiers SAdl and SAdr includes a p-type MOSFET TP21, n-type MOSFETs TN21 and TN22, and an operational amplifier OP2.

TP21 is coupled at its first terminal to a node of the supply potential and at its second terminal to its gate and to a first terminal of transistor TN21. A gate of transistor TP21 is used as a sense node SEN and is coupled to a non-inverting input terminal of operational amplifier OP2.

The operational amplifier OP2 receives a reference voltage Vref at its inverting input terminal. An output from operational amplifier OP2 is received by a data latch in read circuit 17 .

A second terminal of transistor TN21 is coupled to a first node Nldl in the lower left sense amplifier SAdl, and to a first node Nldr in the lower right sense amplifier SAdr. One gate of the transistor TN21 receives the enabling signal EN.

A first terminal of transistor TN22 is coupled to a second node N2dl in the lower left sense amplifier SAdl, and to a second node N2dr in the lower right sense amplifier SAdr. A second terminal of transistor TN22 is coupled to a node at ground potential. One gate of the transistor TN22 receives the enabling signal EN. 1.1.3.2.2. Second instance

FIG. 10 shows a second example of components and connections of the lower left sense amplifier SAdl or right lower sense amplifier SAdr according to the first embodiment. As shown in FIG. 10, each of the lower left sense amplifier SAdl and the lower right sense amplifier SAdr includes an n-type MOSFET TN31, p-type MOSFETs TP31 and TP32, and an operational amplifier OP3.

Transistor TP31 is coupled at its first terminal to a node of the supply potential. A second terminal of transistor TP31 is coupled to a first node Nldl in the lower left sense amplifier SAdl, and to a first node Nldr in the lower right sense amplifier SAdr. One gate of the transistor TP31 receives an enabling signal ¯EN. The symbol "¯" indicates that a signal added with "¯" has a logic obtained by inverting the logic of a signal not having a name of "¯".

Transistor TN31 is coupled at its first terminal to a second node N2dl in the lower left sense amplifier SAdl, and to a second node N2dr in the lower right sense amplifier SAdr. Transistor TN31 is coupled at its first terminal to its gate. The gate of transistor TN31 is used as sense node SEN and is coupled to a non-inverting input terminal of operational amplifier OP3. The operational amplifier OP3 receives a reference voltage Vref at its inverting input terminal. An output from operational amplifier OP3 is received by a data latch in read circuit 17 .

A second terminal of transistor TN31 is coupled to a first terminal of transistor TP32. Transistor TP32 is coupled at its second terminal to a node of ground potential and receives an enable signal ¯EN at its gate. 1.2. Operation

FIG. 11 shows a state during data reading from the memory device 1 according to the first embodiment. FIG. 11 shows the same components and areas as in FIG. 6 and represents a layout similar to FIG. 6 .

The memory device 1 selects the upper left memory cell MCulS from one of the upper left memory cells MCul in parallel and selects the lower right memory cell MCdrS from one of the lower right memory cells MCdr or selects the lower right memory cell MCdrS in parallel from the upper right memory cell MCur One of the selected upper right memory cell MCurS and one of the lower left memory cell MCd1 selects the lower left memory cell MCd1 to read data. 11 is an example of data read from a selected upper left memory cell MCulS and a selected lower right memory cell MCdrS. Figure 11 shows only the components associated with reading data from the selected upper left memory cell MCulS and the selected lower right memory cell MCdrS.

When local column switch TLYu (not shown) coupled to upper word line WLu coupled to selected upper left memory cell MCulS is turned on, upper word line WLu is coupled to local word line LWLu. Furthermore, when the global column switch TGyu (not shown) is turned on, the local word line LWLu is coupled to the first node N1ul of the upper left sense amplifier SAul. The upper word line WLu coupled to the selected upper left memory cell MCulS may hereinafter be referred to as a selected upper word line WLuS.

When local row switch TLX1 (not shown) coupled to left bit line BL1 coupled to selected upper left memory cell MCulS is turned on, left bit line BL1 is coupled to local bit line LBL1. Furthermore, when the global row switch TGX1 (not shown) is turned on, the local bit line LBL1 is coupled to the second node N2ul of the upper left sense amplifier SAul. The left bit line BL1 coupled to the selected upper left memory cell MCulS may hereinafter be referred to as a selected left bit line BL1S.

One of the selected upper left memory cells MCulS is coupled to the first node N1ul and the second node N2ul of the upper left sense amplifier SAul via the local column switch TLYu and the local row switch TLX1 which are coupled to the selected upper left memory cell MCulS and turned on. A state (as described above) may hereinafter be referred to as an upper left memory cell selected state.

When local column switch TLYd (not shown) coupled to lower word line WLd coupled to selected lower right memory cell MCdrS is turned on, lower word line WLd is coupled to local word line LWLd. Furthermore, when the global column switch TGYd (not shown) is turned on, the local word line LWLd is coupled to the first node N1dr of the lower right sense amplifier SAdr. The lower word line WLd coupled to the selected lower right memory cell MCdrS may hereinafter be referred to as a selected lower word line WLdS.

When local row switch TLXr (not shown) coupled to right bit line BLr coupled to selected lower right memory cell MCdrS is turned on, right bit line BLr is coupled to local bit line LBLr. Furthermore, when the global row switch TGXr (not shown) is turned on, the local bit line LBLr is coupled to the second node N2dr of the lower right sense amplifier SAdr. The right bit line BLr coupled to the selected lower right memory cell MCdrS may hereinafter be referred to as a selected right bit line BLrS.

One of the selected lower right memory cells MCdrS is coupled to the first node N1dr and the second node of the lower right sense amplifier SAdr via the local column switch TLYd and the local row switch TLXr which are coupled to the selected lower right memory cell MCdrS and turned on. A state of node N2dr (described above) may hereinafter be referred to as a lower right memory cell selected state.

Among the local column switches TLYu and TLYd and the local row switches TLX1 and TLXr, the formation of the upper left memory cell selected state and the lower right memory cell selected state is not caused during the upper left memory cell selected state and the lower right memory cell selected state. The switch for any one of the cell's selected states remains off.

In the state (as described above) where both the upper left memory cell selected state and the lower right memory cell selected state are formed (as described above), the enable signal EN of the upper left sense amplifier SAul and the lower right sense amplifier SAdr is set high allow. This enables the upper left sense amplifier SAul and the lower right sense amplifier SAdr to start a data read from the selected upper left memory cell MCulS and the selected lower right memory cell MCdrS.

With the start of data reading, in the upper left sub-array 11ul, the selected left bit line BL1S is coupled to the node of supply potential via the upper left sense amplifier SAul, and the selected upper word line WLuS is coupled to the ground potential via the upper left sense amplifier SAul the node. Therefore, a read current Irul flows from the selected left bit line BL1S to the selected upper word line WLuS in the selected upper left memory cell MCulS. The read current Irul has a magnitude based on the resistance state of the selected upper left memory cell MCulS and affects the voltage of the sense node SEN in the upper left sense amplifier SAul, i.e. the voltage of the non-inverting input terminal of the operational amplifier OP1 . The upper left sense amplifier SAul outputs a voltage based on the voltage of the non-inverting input terminal of the operational amplifier OP1. Therefore, the output voltage reflects the resistance state of the selected upper left memory cell MCulS and is the data read from the selected upper left memory cell MCulS.

With the start of data reading, in the lower right sub-array 11dr, the selected lower word line WLdS is coupled to the node of the power supply potential through the lower right sense amplifier SAdr, and the selected right bit line BLrS is coupled to the node of the power supply potential through the lower right sense amplifier SAdr. Node at ground potential. Therefore, a read current Irdr flows from the selected lower word line WLdS to the selected right bit line BLrS in the selected lower right memory cell MCdrS. Read current Irdr has a magnitude based on the resistance state of the selected lower right memory cell MCdrS and affects the voltage at sense node SEN in lower right sense amplifier SAdr, i.e., the non-inverting input terminal of operational amplifier OP2 The voltage. The lower right sense amplifier SAdr outputs a voltage based on the voltage of the non-inverting input terminal of the operational amplifier OP2. Therefore, the output voltage reflects the resistance state of the selected lower right memory cell MCdrS, and is the data read from the selected lower right memory cell MCdrS.

The read of data from the selected upper left memory cell MCulS and the read of data from the selected lower right memory cell MCdrS can occur in parallel.

FIG. 12 shows a state of the memory device according to the first embodiment. More specifically, FIG. 12 further shows some components not shown in FIG. 11 in the same upper left memory cell selected state and lower right memory cell selected state in FIG. 11 . In the following description, the word line WL and the bit line BL coupled to the node of the power supply potential via the sense amplifier SA are said to be at a high (H) level. The word line WL and bit line BL, which are coupled to a node at ground potential through sense amplifier SA, are said to be at a low (L) level.

As shown in FIG. 12, a high level voltage is applied to the selected left bit line BL1S to form the upper left memory cell selected state, and a high level voltage is applied to the selected lower word line WLdS to form the lower right memory cell Cell selection state. Selected left bit line BL1S at a high level applies a voltage at a high level to the lower left memory cell MCd1 coupled to the selected left bit line BL1S (which may hereinafter be referred to as a non-selected lower left memory cell MCdlh) the second node. However, a high level voltage is applied to the first node of the unselected lower left memory cell MCdlh by the high level selected lower word line WLdS. That is, the same voltage is applied to both terminals of the non-selected lower left memory cell MCdlh. Therefore, the read current does not flow at all or hardly in the unselected lower left memory cell MCdlh, and no data read from the unselected lower left memory cell MCdlh occurs. That is, the resistance state of the unselected lower left memory cell MCdlh is suppressed from interfering with data read from the selected upper left memory cell MCulS and the selected lower right memory cell MCdrS.

Similarly, a low-level voltage is applied to the selected upper word line WLuS to form the upper left memory cell selected state, and a low-level voltage is applied to the selected right bit line BLrS to form the lower right memory cell selected state. state. The selected upper word line WLuS of the low level applies a voltage of a low level to the upper right memory cell MCur (which may hereinafter be referred to as an unselected upper right memory cell MCurh) coupled to the selected left bit line BL1S first node. However, a low level voltage is applied to the second node of the unselected upper right memory cell MCurh by the low level selected right bit line BLrS. That is, the same voltage is applied to both terminals of the unselected upper right memory cell MCurh. Therefore, the read current does not flow at all or hardly in the unselected upper right memory cell MCurh, and no data read from the unselected upper right memory cell MCurh occurs. That is, the resistance state of the unselected upper right memory cell MCurh is suppressed from interfering with data read from the selected upper left memory cell MCulS and the selected lower right memory cell MCdrS.

Parallel data reading from one of the upper right memory cells MCur selected from the upper right memory cell MCurS and one of the lower left memory cells MCdl from the selected lower left memory cell MCdlS is similarly performed by the same as from the selected upper left memory cell MCulS And the principle of reading the data of the selected lower right memory cell MCdrS is executed. An overview is as follows.

FIG. 13 shows a state during data reading from the memory device 1 according to the first embodiment. FIG. 13 shows the same components and areas as in FIG. 6 and represents a layout similar to FIG. 6 . FIG. 13 is an example of data read from a selected upper right memory cell MCurS and a selected lower left memory cell MCdlS. Figure 13 shows only the components associated with reading data from the selected upper right memory cell MCurS and the selected lower left memory cell MCdlS.

The selected upper right memory cell MCurS is coupled to the first node N1ur of the upper right sense amplifier SAur via a local column switch TLYu (not shown) and a local row switch TLXr (not shown) coupled to the selected upper right memory cell MCurS and turned on and the second node N2ur. Therefore, a selected state of the upper right memory cell is formed.

In addition, the selected lower left memory cell MCdlS is coupled to the first of the lower left sense amplifier SAdl via a local column switch TLYd (not shown) and a local row switch TLXl (not shown) that are coupled to the selected lower left memory cell MCdlS and turned on. The node N1dl and the second node N2dl. Therefore, a lower left memory cell selection state is formed.

In a state in which one of the upper right memory cell selected state and the lower left memory cell selected state is formed, the enable signals EN of the upper right sense amplifier SAur and the lower left sense amplifier SAd1 are set to a high level. This enables the upper right sense amplifier SAur and the lower left sense amplifier SAdl.

In the upper right sub-array 11ur, the selected right bit line BLrS is coupled to the node of power potential via the upper right sense amplifier SAur, and the selected upper word line WLuS is coupled to the node of ground potential via the upper right sense amplifier SAur. Therefore, a read current Irur flows from the selected right bit line BLrS to the selected upper word line WLuS in the selected upper right memory cell MCurS. Therefore, the upper right sense amplifier SAur obtains the data read from the selected upper right memory cell MCurS.

In the lower left sub-array 11dl, the selected lower word line WLdS is coupled to the node at supply potential via the lower left sense amplifier SAdl, and the selected left bit line BL1S is coupled to the node at ground potential via the lower left sense amplifier SAdl. Therefore, a read current Ird1 flows from the selected lower word line WLdS to the selected left bit line BL1S in the selected lower left memory cell MCd1S. Therefore, the lower left sense amplifier SAd1 obtains the data read from the selected lower left memory cell MCd1S.

Also in the data read shown in FIG. 13, the data read from the selected upper right memory cell MCurS and the selected lower left memory cell MCdlS does not experience the resistance of the upper left memory cell MCul or the lower right memory cell MCdr state interference, as shown in Figure 14. FIG. 14 shows a state of the memory device according to the first embodiment.

To form the upper right memory cell selected state, a voltage of a high level is applied to the selected right bit line BLrS, and a voltage of a low level is applied to the selected upper word line WLuS. To form the lower left memory cell selected state, a voltage of a high level is applied to the selected lower word line WLdS, and a voltage of a low level is applied to the selected left bit line BL1S. The selected left bit line BL1S applies a voltage of a low level to the upper left memory cell Mcul (which may hereinafter be referred to as a non-selected upper left memory cell MCulh) of the selected upper word line WLuS coupled to the low level the second node. Therefore, the same voltage is applied to both terminals of the unselected upper left memory cell MCulh, and the read current does not flow at all or hardly flows in the unselected upper left memory cell MCulh.

Similarly, the selected lower word line WLdS applies a voltage of a high level to the lower right memory cell MCdr (which may hereinafter be referred to as a non-selected lower right memory cell) coupled to the selected right bit line BLrS of the high level The first node of cell MCdrh). Therefore, the same voltage is applied to both terminals of the unselected lower right memory cell MCdrh, and the read current does not flow at all or hardly flows in the unselected lower right memory cell MCdrh. 1.3. Advantages (favorable effect)

According to the first embodiment, as will be described below, it is possible to provide the memory device 1 that can efficiently read data while avoiding an increase in the area of each of the column selector 14 and the row selector 15 .

Data can be read from the memory cell array 11 including the upper left sub-array 11ul, the upper right sub-array 11ur, the lower left sub-array 11dl and the lower right sub-array 11dr, as follows.

FIG. 15 shows some components of a memory device 100 according to a first reference and a state during data reading. The memory device 100 includes only a single sense amplifier 41 a for the memory cell array 11 . The sense amplifier 41a includes the same components and connections as those of the upper left sense amplifier SAul or the upper right sense amplifier SAur, and supplies the read current Ir from the second node N2 to the first node N1. Since the memory device 100 only includes a single sense amplifier 41, a single data read operation can only read data from a single memory cell MC. In order to be able to read data from two memory cells MC with a single data read operation, consider a configuration shown in FIG. 16 .

FIG. 16 shows some components of a memory device 200 according to a second reference and a state during data reading. The memory device 200 includes two sense amplifiers 41a and 41b. Each of the sense amplifiers 41a and 41b includes the same components and connections as those of the upper left sense amplifier SAul, and supplies a read current Ir from its second node N2 to its first node N1. The first node N1 of the sense amplifier 41a is coupled to the global word line GWLu, and the second node N2 of the sense amplifier 41a is coupled to the global bit line GBL1. The first node N1 of the sense amplifier 41b is coupled to the global word line GWLu, and the second node N2 of the sense amplifier 41b is coupled to the global bit line GBLr.

As described with reference to FIG. 7 , a plurality of upper word lines WLu share a single local word line LWLu. Therefore, two memory cells MC from which data can be read in parallel need to be coupled to a single upper word line WLu. Data is read from the selected upper left memory cell MCulS and the selected upper right memory cell MCurS that meet the above conditions. For this purpose, a voltage of one of the high level is applied to the selected left bit line BL1S and the selected right bit line BLrS via sense amplifiers 41a and 41b, respectively. A voltage of one of the low levels is applied to the selected upper word line WLuS via the sense amplifiers 41a and 41b. When sense amplifiers 41a and 41b are enabled in this state, data can be read from the selected upper left memory cell MCulS and the selected upper right memory cell MCurS.

During data reading, the read current Irul flows from the sense amplifier 41a to the selected upper word line WLuS, and the read current Irur flows from the sense amplifier 41b to the selected upper word line WLuS. Accordingly, a current of a magnitude of Irul+Irur (ie, a current of a magnitude of twice the magnitude of the read current Ir) flows to the selected upper word line WLuS. In order to allow a current of this magnitude to flow from the selected upper word line WLuS to the local word line LWLu, one of the local column switches TLY1 that plays the same role as the local column switch TLYu between each upper word line WLu and the local word line LWLu needs to have The ability to conduct (or drive) a current (current drive capability) that is twice the current of the local column switch TLYu that has only the drive capability of the current Ir. The current driving capability of a transistor usually depends on the size of the transistor. All of the local column switches TLY1 need to have a size that is twice the size of the local column switches TLYu that have only the drive capability of the current Ir. Since the memory device contains hundreds or more than 1000 local column switches TLY1, the impact of size increase is large. Similarly, a global column switch TGY1 between the local word line LWLu and the global word line GWLu also needs to have a current driving capability twice that of the global column switch TGYu.

FIG. 17 shows some components of a memory device 300 according to a third reference and a state during data reading. The memory device 300 includes two sense amplifiers 41a and 41c. The sense amplifier 41c includes the same components and connections as those of the upper left sense amplifier SAul, and supplies the read current Ir from its second node N2 to its first node N1. A first node N1 of sense amplifier 41c is coupled to global word line GWLd, and a second node N2 of sense amplifier 41c is coupled to global bit line GBL1.

A plurality of left bit lines BL1 share a single local bit line LBL1. Therefore, two memory cells MC from which data can be read in parallel need to be coupled to a single left bit line BL1. Data is read from the selected upper left memory cell MCulS and the selected lower left memory cell MCdlS that meet the above conditions. For this purpose, a voltage of one of the low levels is applied to the selected upper word line WLuS and the selected lower word line WLdS via sense amplifiers 41a and 41c, respectively. A voltage of one of the high levels is applied to the selected left bit line BL1S via sense amplifiers 41a and 41c. It is considered that when sense amplifiers 41a and 41c are enabled in this state, data can be read from selected upper left memory cell MCulS and selected lower left memory cell MCdlS.

However, since the two selected memory cells MCS are coupled to a single selected left bit line BL1S, data reads from one of the two selected memory cells MCS are subject to the other selected memory cell MCS. The data is disturbed, and thus the data cannot be read correctly from either of the two selected memory cells MCS.

To address the above-described problems in memory devices 200 and 300, a configuration shown in FIG. 18 may be considered. FIG. 18 shows some components of a memory device 400 according to a fourth reference and a state during data reading. The memory device 400 includes two sense amplifiers 41a and 41d. The sense amplifier 41d includes the same components and connections as those of the upper left sense amplifier SAul, and supplies the read current Ir from its second node N2 to its first node N1. A first node N1 of sense amplifier 41d is coupled to global word line GWLd, and a second node N2 of sense amplifier 41d is coupled to global bit line GBLr.

By selecting a single upper left memory cell MCul and a single lower right memory cell MCdr, data can be read in parallel from the selected upper left memory cell MCulS and the selected lower right memory cell MCdrS. To perform this data read, a voltage of one of the high levels must be applied to the selected left bit line BL1S and the selected right bit line BLrS via sense amplifiers 41a and 41d, respectively. In addition, a voltage of a low level must be applied to the selected upper word line WLuS and the selected lower word line WLdS through the sense amplifiers 41a and 41d, respectively. However, by applying these voltages, the unselected upper right memory cell MCurh coupled to the selected right bit line BLrS and the selected upper word line WLuS is also set to a selected state. Additionally, unselected lower left memory cell MCdlh coupled to selected left bit line BL1S and selected lower word line WLdS is set to a selected state. Therefore, the data read from the selected upper left memory cell MCulS is subject to a voltage disturbance based on the state of the unselected lower left memory cell MCdlh and cannot be performed correctly. Similarly, a data read from the selected lower right memory cell MCdrS is subject to a voltage disturbance based on the state of the unselected upper right memory cell MCurh and cannot be performed correctly.

The memory device 1 according to the first embodiment includes a first sense amplifier SA and a second sense amplifier SA. The first sense amplifier SA supplies a read current Ir from a first selected bit line BL of a first bit line group to a first selected word line WL of a first word line group to a first bit line group. A selected memory cell MCS. The second sense amplifier SA supplies another read current from a second selected word line WL of a second word line group to a second selected bit line BL of a second bit line group to a The second selected memory cell MCS.

As a more detailed example, the upper left sense amplifier SAul is coupled at the second node N2ul to a selected left bit line BL1S and at the first node N1ul to a selected upper word line WLuS, causing the read current Ir to flow from the second Node N2ul flows to first node N1ul and reads data from selected upper left memory cell MCulS coupled between selected left bit line BL1S and selected upper word line WLuS. In addition, the lower right sense amplifier SAdr is coupled to a selected lower word line BLdS at the first node N1dr and to a selected right bit line BLrS at the second node N2dr and directs the read current Ir from the second node N2dr Flows to first node N1dr and reads data from selected lower right memory cell MCdrS coupled between selected lower word line WLdS and selected right bit line BLrS. This configuration creates one of the states required to read data from the selected upper left memory cell MCulS (i.e., the upper left memory cell selected state) and read from the selected lower right memory cell MCdrS without interfering with each other. Get one of the states required by the data (that is, the selected state of the lower right memory cell). Additionally, the state required to read data from the selected upper left memory cell MCulS and the state required to read data from the selected lower right memory cell MCdrS avoids inadvertently creating one of the states. This inhibits the read of correct data from the selected memory cell MCS. Therefore, the correct data can be read in parallel from the two selected memory cells MCS. 2. The second embodiment

The second embodiment differs from the first embodiment in the number of selected memory cells MCS from which data is read in parallel. Differences from the first embodiment will be mainly described below. Matters not mentioned can follow the description in the first embodiment.

A memory device 1 according to the second embodiment is different from the memory device according to the first embodiment in details of a column selector 14, details of a row selector 15, and control of a control circuit 13. The memory device 1, column selector 14, and row selector 15 according to the second embodiment may be referred to as a memory device 1B, a column selector 14B, and a row selector 15B hereinafter to distinguish them from those according to the first embodiment. A memory device 1 , a column selector 14 and a row selector 15 . 2.1. Structure (configuration)

FIG. 19 shows details of some functional blocks of the memory device 1B according to the second embodiment. More specifically, FIG. 19 shows the components, connections, and layout of portions of each of memory cell array 11 , column selector 14B, row selector 15B, and a write circuit 16 .

As shown in FIG. 19, an upper left sense amplifier SAul, an upper right sense amplifier SAur, a lower left sense amplifier SAdl, and a lower right sense amplifier SAdr are coupled to components different from those in the first embodiment.

Similar to the column selector 14 of the first embodiment, the column selector 14B includes an upper column selector 14Bu and a column selector 14Bd.

The row selector 15B corresponds to a configuration in which each of the left row selector 151 and the right row selector 15r of the first embodiment is divided into two individual parts. The left part (for example, the left half) of the left row selector 151 in the first embodiment will hereinafter be referred to as a left end row selector 15B1 and the remaining part will be referred to as a left row selector 15B1 hereinafter. Similarly, the right part (for example, the right half) of the right row selector 15r in the first embodiment will hereinafter be referred to as a right end row selector 15Brm and the remainder will be referred to as a right row selector hereinafter 15Br.

The left end row selector 15B1 is coupled to some of the left bit lines BL1 arranged consecutively, and the left row selector 15B1 is coupled to the remaining left bit lines BL1. For example, the left bit line BL1 positioned in the left half of all left bit lines BL1 is coupled to left end row selector 15B1m, and the left bit positioned in the right half of all left bit lines BL1 Line BL1 is coupled to left row selector 15B1. Left bit line BL1 coupled to left end row selector 15B1 will hereinafter be referred to as left end bit line BL1m, and left bit line BL1 coupled to left row selector 15B1 will hereinafter be referred to as left bit line BL1 .

The left-end row selector 15Blm couples one of the left-end bit lines BLlm designated by an address signal ADD to a second node N2ul of the upper-left sense amplifier SAul. The left row selector 15B1 couples one of the left bit lines BL1 designated by the address signal ADD to a second node N2d1 of the lower left sense amplifier SAd1.

The right end row selector 15Brm is coupled to some of the right bit lines BLr arranged consecutively, and the right row selector 15Br is coupled to the remaining right bit lines BLr. For example, the right bit line BLr located in the right half of all right bit lines BLr is coupled to the right end row selector 15Brm, and the right bit located in the left half of all right bit lines BLr Line BLr is coupled to right row selector 15Br. The right bit line BLr coupled to the right end row selector 15Brm will hereinafter be referred to as the right end bit line BLrm, and the right bit line BLr coupled to the right row selector 15Br will hereinafter be referred to as the right bit line BLr .

The right row selector 15Br receives the address signal ADD, and couples one of the right bit lines BLr designated by the address signal ADD to a second node N2ur of the upper right sense amplifier SAur. The right end row selector 15Brm couples one of the right end bit lines BLrm designated by the address signal ADD to a second node N2dr of the lower right sense amplifier SAdr. 2.1.1. Row selector details

Fig. 20 shows an example of components and connections of a row selector according to a second embodiment.

The above column selector 14Bu does not include the local column switch TLyu of the first embodiment, but includes the local column switch TLyu1. The above column selector 14Bu does not include the global column switch TGYu of the first embodiment, but includes a global column switch TGYu1.

The following selector 14Bd does not include the local column switch TLYd of the first embodiment, but includes the local column switch TLYd1. The following selector 14Bd does not include a global column switch TGYd, but includes a global column switch TGYd1.

The local column switches TLyu1 are provided in the column selector 14 of the first embodiment instead of the local column switches TLyu. The global column switch TGYu1 is provided in the column selector 14 of the first embodiment instead of the global column switch TGYu. The local column switches TLYd1 are provided in the column selector 14 of the first embodiment instead of the local column switches TLYd. The global column switch TGYd1 is provided in the column selector 14 of the first embodiment instead of the global column switch TGYd.

The local column switches TLYu1 and TLYd1 have a current driving capability higher than that of the local column switches TLYu and TLYd, respectively. For this purpose, the local column switches TLYu1 and TLYd1 may have a size (specifically, gate width) larger than the size (specifically, gate width) of the local column switches TLYu and TLYd, respectively. Each of the local column switches TLYu1 and TLYd1 has a drive capability capable of flowing a current that is twice the read current Ir.

The global column switches TGyu1 and TGYd1 have a current driving capability higher than that of the global column switches TGyu and TGYd, respectively. For this purpose, global column switches TGyu1 and TGYd1 may have a size (specifically gate width) larger than the size (specifically gate width) of global column switches TGyu and TGYd, respectively. Each of the global column switches TGYu1 and TGYd1 has a drive capability capable of flowing a current at least twice the read current Ir.

Each of the left row selector 15B1m, the left row selector 15B1, the right row selector 15Br, and the right row selector 15Brm has the same configuration and function as the left row selector 151 or the right row selector 15r of the first embodiment. The configuration and function. That is, each of the left end row selector 15Blm, left row selector 15B1, right row selector 15Br, and right end row selector 15Brm includes one of a plurality of local row switches, local bit lines, global row switches, and global bit lines gather. These collections are independent of each other. In each of the left end row selector 15Blm, left row selector 15B1, right row selector 15Br, and right end row selector 15Brm, a plurality of local row switches, local bit lines, global row switches, and global bit lines are coupled , similar to those of the left row selector 15l or the right row selector 15r of the first embodiment. Details as follow.

The left end row selector 15Blm includes a plurality of local row switches TLXlm, a local bit line LBLlm, a global row switch TGXlm and a global bit line GBLlm. Each local row switch TLXlm is coupled between a single left bit line BLlm and local bit line LBLlm. Similar to the local row switch TLX1 of the first embodiment, each local row switch TLX1m receives at its control terminal a control signal LX1 unique to the local row switch TLX1m. The local bit line LBLlm is coupled to the global bit line GBLlm via the global row switch TGXlm. The global row switch TGXlm receives a control signal GX1 at its control terminal. When a local row switch TLXlm and a global row switch TGXlm are turned on, a single left end bit line BLlm can be coupled to the second node N2ul of the upper left sense amplifier SAul.

The left row selector 151 includes a plurality of local row switches TLX1, a local bit line LBL1, a global row switch TGX1 and a global bit line GBL1. Each local row switch TLX1 is coupled between a single left bit line BL1 and local bit line LBL1. Similar to the local row switches TLX1 of the first embodiment, each local row switch TLX1 receives at its control terminal a control signal LX1 unique to the local row switch TLX1. Local bit line LBL1 is coupled to global bit line GBL1 via global row switch TGX1. The global row switch TGX1 receives the control signal GX1 at its control terminal. When a local row switch TLX1 and global row switch TGX1 are on, a single left bit line BL1 can be coupled to the second node N2d1 of the lower left sense amplifier SAd1.

The right row selector 15r includes a plurality of local row switches TLXr, a local bit line LBLr, a global row switch TGXr and a global bit line GBLr. Each local row switch TLXr is coupled between a single right bit line BLr and local bit line LBLr. Similar to the local row switch TLXr of the first embodiment, each local row switch TLXr receives at its control terminal a control signal LXr unique to the local row switch TLXr. The local bit line LBLr is coupled to the global bit line GBLr via the global row switch TGXr. The global row switch TGXr receives a control signal GXr at its control terminal. When a local row switch TLXr and global row switch TGXr are on, a single right bit line BLr can be coupled to the second node N2ur of the upper right sense amplifier SAur.

The right end row selector 15Brm includes a plurality of local row switches TLXrm, a local bit line LBLrm, a global row switch TGXrm and a global bit line GBLrm. Each local row switch TLXrm is coupled between a single right end bit line BLrm and local bit line LBLrm. Similar to the local row switch TLXr of the first embodiment, each local row switch TLXrm receives at its control terminal a control signal LXr unique to the local row switch TLXrm. The local bit line LBLrm is coupled to the global bit line GBLrm via the global row switch TGXrm. The global row switch TGXrm receives a control signal GXr at its control terminal. When a local row switch TLXrm and a global row switch TGXrm are on, a single right end bit line BLrm can be coupled to the second node N2dr of the lower right sense amplifier SAdr. 2.2. Operation

FIG. 21 shows a state during data reading from the memory device 1 according to the second embodiment. FIG. 21 shows the same range as in FIG. 19 and represents a layout similar to FIG. 19 .

The memory device 1B reads data in parallel from a total of four memory cells MC in an upper-left sub-array 11ul, an upper-right sub-array 11ur, a lower-left sub-array 11dl, and a lower-right sub-array 11dr. That is, the memory device 1B reads data in parallel from a selected upper left memory cell MCulS, a selected upper right memory cell MCurS, a selected lower left memory cell MCdlS, and a selected lower right memory cell MCdrS. 21 shows only the components associated with reading data from selected upper left memory cell MCulS, selected upper right memory cell MCurS, selected lower left memory cell MCdlS, and selected lower right memory cell MCdrS. An overview of the data read in the second embodiment corresponds to or is similar to where the parallel data read from the selected upper left memory cell MCulS and the selected lower right memory cell MCdrS ( FIG. 11 ) and from the selected upper right memory cell A situation in which the parallel reading of data from the cell MCurS and the selected lower left memory cell MCdlS ( FIG. 13 ) occurs in parallel.

The selected upper left memory cell MCulS and the selected upper right memory cell MCurS need to be coupled to the same upper word line WLu. The selected lower left memory cell MCdlS and the selected lower right memory cell MCdrS need to be coupled to the same lower word line WLd. Data can be read in parallel from four memory cells MC satisfying the above conditions.

The left end bit line BL1m coupled to the selected upper left memory cell MCulS will hereinafter be referred to as a selected left end bit line BL1mS. The left bit line BL1 coupled to the selected lower left memory cell MCd1S will hereinafter be referred to as a selected left bit line BL1S. The right bit line BLr coupled to the selected upper right memory cell MCurS will be referred to hereinafter as a selected right bit line BLrS. The one of the right end bit line BLrm coupled to the selected lower right memory cell MCdrS will be referred to as a selected right end bit line BLrmS hereinafter.

Similar to the method according to the first embodiment, an upper left memory cell selected state, an upper right memory cell selected state, a lower left memory cell selected state and a lower right memory cell selected state are formed. Details can be estimated from the description of the first embodiment, and are summarized as follows.

A selected upper word line WLuS is coupled to a first node N1ul of the upper left sense amplifier SAul via a local column switch TLYu1 (not shown) and a global column switch TGYu1 (not shown) coupled to the selected upper word line WLuS and turned on. One of the upper right sense amplifiers SAur is a first node N1ur.

A selected lower word line WLdS is coupled to a first node N1d1 of the lower left sense amplifier SAd1 via a local column switch TLYd1 (not shown) and a global column switch TGYd (not shown) coupled to the selected lower word line WLdS and turned on. A first node N1dr of one of the lower right sense amplifiers SAdr.

The selected left end bit line BLlmS is coupled to the second node N2ul of the upper left sense amplifier SAul via a local row switch TLXlm (not shown) and a global row switch TGXlm (not shown) coupled to the selected left end bit line BLlmS and turned on.

The selected left bit line BL1S is coupled to the second node N2d1 of the lower left sense amplifier SAd1 via a local row switch TLX1 (not shown) and a global row switch TGX1 (not shown) coupled to the selected left bit line BL1S and turned on.

The selected right bit line BLrS is coupled to the second node N2ur of the upper right sense amplifier SAur via a local row switch TLXr (not shown) and a global row switch TGXr (not shown) coupled to the selected right bit line BLrS and turned on.

The selected right end bit line BLrmS is coupled to the second node N2dr of the lower right sense amplifier SAdr via a local row switch TLXrm (not shown) and a global row switch TGXrm (not shown) coupled to the selected right end bit line BLrmS and turned on. .

In the state in which one of the upper left memory cell selected state, the upper right memory cell selected state, the lower left memory cell selected state, and the lower right memory cell selected state (as described above) is formed, similar to the first embodiment For example, upper left sense amplifier SAul, upper right sense amplifier SAur, lower left sense amplifier SAdl, and lower right sense amplifier SAdr are enabled. This starts reading data from the selected upper left memory cell MCulS, the selected upper right memory cell MCurS, the selected lower left memory cell MCdlS, and the selected lower right memory cell MCdrS.

As the data read begins, a voltage is applied to each interconnect associated with the data read as follows. A voltage of one of the low levels is applied to the selected upper word line WLuS. A voltage of one of the high levels is applied to the selected lower word line WLdS. A voltage of one of the high levels is applied to the selected left bit line BL1mS. A voltage of one of the low levels is applied to the selected left bit line BL1S. A voltage of one of the low levels is applied to the selected right bit line BLrS. A voltage of one of the low levels is applied to the selected right bit line BLrmS.

Applying voltages for data reads prevents data reads from selected upper left memory cell MCulS, from selected upper right memory cell MCurS, from selected lower left memory cell MCdlS, and from selected lower right memory cell MCdrS interfere with each other. Therefore, read data can be obtained as follows.

A read current Irul flows from the selected left end bit line BL1mS to the selected upper word line WLuS through the selected upper left memory cell MCulS. The upper left sense amplifier SAul outputs a voltage that reflects the resistance state of the selected upper left memory cell MCulS. This voltage corresponds to the data read from the selected upper left memory cell MCulS.

A read current Irur flows from the selected right bit line BLrS to the selected upper word line WLuS through the selected upper right memory cell MCurS. The upper right sense amplifier SAur outputs a voltage that reflects the resistance state of the selected upper right memory cell MCurS. This voltage corresponds to the data read from the selected upper right memory cell MCurS.

A read current Ird1 flows from the selected lower word line WLdS to the selected left bit line BL1S through the selected lower left memory cell MCd1S. The bottom left sense amplifier SAd1 outputs a voltage that reflects the resistance state of the selected bottom left memory cell MCd1S. This voltage corresponds to data read from the selected bottom left memory cell MCdlS.

A read current Irdr flows from the selected lower word line WLdS to the selected right end bit line BLrmS through the selected lower right memory cell MCdrS. The lower right sense amplifier SAdr outputs a voltage that reflects the resistance state of the selected lower right memory cell MCdrS. This voltage corresponds to the data read from the selected lower right memory cell MCdrS.

By performing a data read, a current in magnitude of 2×Ir can flow through local column switch TLYu1 (not shown) and global column switch TGyu1 (not shown) coupled to the selected upper word line WLuS. Additionally, a current of magnitude 2×Ir may flow through local column switch TLYd1 (not shown) and global column switch TGYd1 (not shown) coupled to the selected lower word line WLdS. 2.3. Advantages (favorable effects)

A local column switch with high current driving capability can be provided, such as local column switches TLYu1 and TLYd1. In this case, according to the second embodiment, correct data can be read in parallel from four memory cells MC, as will be described below.

Similar to the first embodiment, the memory device 1B includes a first sense amplifier SA and a second sense amplifier SA. The first sense amplifier SA supplies the read current Ir from a first selected bit line BLS of a first bit line group to a first selected word line WLS of a first word line group to a first bit line group. A selected memory cell MCS. The second sense amplifier SA supplies another read current Ir from a second selected word line WLS of a second word line group to a second selected bit line BLS of a second bit line group to A second selected memory cell MCS.

In addition, the memory device 1B includes a third sense amplifier SA and a fourth sense amplifier SA. The third sense amplifier SA supplies the read current Ir from the third selected bit line BLS to the first selected word line WLS of the third bit line group to a third selected memory cell MCS. The fourth sense amplifier SA supplies another read current Ir from the second selected word line WLS to a fourth selected bit line BLS of a fourth bit line group to a fourth selected memory cell MCS .

The states required to read data from the first to fourth selected memory cells MCS respectively can be formed without interfering with each other. Therefore, correct data can be read in parallel from the four memory cells MC. 2.4. Modification

An example corresponding to the configuration in which each of the left row selector 151 and the right row selector 15r of the first embodiment is divided into two individual parts has been described. However, the second embodiment is not limited thereto. That is, each of the left row selector 151 and the right row selector 15r of the first embodiment can be divided into three or more individual parts. 3. Modify

Each of the upper left sense amplifier SAul, the upper right sense amplifier SAur, the lower left sense amplifier SAdl, and the lower right sense amplifier SAdr may have a read current Ir supplied from its first node N1 and a read current drawn from its second node N2. Both the function of the current Ir and the function of supplying the read current Ir from its second node N2 and sinking the read current Ir from its first node N1. That is, each sense amplifier SA includes both the configuration shown in FIG. 8 and the configuration shown in FIG. 9 or 10, and can be configured to dynamically select the configuration shown in FIG. One of the configurations shown in 10.

The variable resistance element VR may include a phase change element, a ferroelectric element or another element. Phase change elements are used to set a phase change random access memory (PCRAM) to a crystalline state or an amorphous state by heat generated by a write current, thereby exhibiting a different resistance value depending on the state. The variable resistive element VR may comprise an element for a resistive RAM (ReRAM). For this variable resistance element VR, the resistance value of the variable resistance element VR depends on the width (pulse application period) or amplitude (current value or voltage value) of a write pulse and the application of the polarity of the write pulse (application direction) And change.

While specific embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in various other forms; moreover, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the invention. Cross References to Related Applications

This application is based on and claims priority to Japanese Patent Application No. 2020-157866 filed September 18, 2020 and U.S. Patent Application No. 17/198495 filed March 11, 2021, all of which The contents are incorporated herein by reference.

1: Magnetic storage device/memory device 2: Memory controller 11: Memory cell array 11ul: upper left subarray 11ur: upper right subarray 11dl: lower left subarray 11dr: Bottom right subarray 12: Input and output circuit 13: Control circuit 14: Column selection circuit/column selector 14Bu: Selectors listed above 14Bd: The following selectors 14u: Upper column selector / first part 14d: The following selector/second part 15: row selection circuit / row selector 15Bl: left row selector 15Blm: left row selector 15Br: Right row selector 15Brm: Right End Row Selector 15l: left row selector / first part 15r: Right row selector / second part 16: Write circuit 17: Read circuit 21: Conductor 22: Conductor 24: Lower electrode 25: Variable resistance material (layer) 26: Upper electrode 31: ferromagnetic layer 32: Insulation layer 33: ferromagnetic layer 41a: Sense amplifier 41b: Sense amplifier 41c: sense amplifier 41d: Sense amplifier 100: memory device 200: memory device 300: memory device 400: memory device BL: bit line BL1: left bit line BLlm: left end bit line BLlmS: Select left bit line BLlS: Select left bit line BLr: right bit line BLrm: right end bit line BLrmS: Select the right bit line BLrS: Select the right bit line BL<0> to BL<N>: bit line EN: enable signal ¯EN: enable signal GBL1: global bit line GBLlm: global bit line GBLr: global bit line GBLrm: global bit line GWLu: global word line GWLd: global word line GX: control signal GY: control signal Irul: read current Irdr: read current Irdl: read current Irur: read current Iwap: write current Iwp: write current LBLl: local bit line LBLlm: local bit line LBLr: local bit line LBLrm: local bit line LWLu: local word line LWLd: local word line LXl1 to LXlp: Control signals LXr1 to LXrq: Control signals LYu1 to LYut: control signals LYd1 to LYdS: Control signals MC: memory cell MCa: memory cell MCb: memory cell MCa<0,0> to MCa<M,N>: memory cell MCb<0,0> to MCb<M,N>: memory cell MCul: upper left memory cell MCulh: unselected upper left memory cell MCulS: Select the upper left memory cell MCur: upper right memory cell MCurh: unselected upper right memory cell MCurS: Select the upper right memory cell MCdl: lower left memory cell MCdlh: unselected lower left memory cell MCdlS: Select the lower left memory cell MCdr: lower right memory cell MCdrh: unselected lower right memory cell MCdrS: Select the lower right memory cell MCS: memory cell N1: the first node N1ul: the first node N1ur: the first node N1dl: first node N1dr: first node N2: second node N2ul: second node N2ur: second node N2dl: second node N2dr: second node OP1: operational amplifier OP2: operational amplifier OP3: operational amplifier SAul: upper left sense amplifier SAur: upper right sense amplifier SAdl: lower left sense amplifier SAdr: Lower Right Sense Amplifier SE: switching element SEa: switching element SEb: switching element SEa<0,0>: switching element SEb<0,0>: switching element SEN: Sensing Node TGXl: global row switch TGXlm: Global row switch TGXr: Global row switch TGXrm: global row switch TGYd: global column switch TGYd1: global column switch TGYu: global column switch TGYu1: global column switch TLXl: local row switch TLXlm: Local Line Switching TLXr: Local row switch TLXrm: Local row switch TLYd: local column switch TLYd1: local column switch TLYu: local column switch TLYu1: local column switch TN11: Transistor TN12: Transistor TN21: Transistor TN22: Transistor TN31: Transistor TP11: Transistor TP21: Transistor TP31: Transistor TP32: Transistor Vdd: power supply potential VR: variable resistance element VRa: variable resistance element VRb: variable resistance element VRa<0,0>: variable resistance element VRb<0,0>: variable resistance element Vref: reference voltage WL: word line WLu: upper word line WLuS: Select upper word line WLd: lower word line WLdS: Select the lower word line WLa<0> to WLa<M>: word line

FIG. 1 shows functional blocks of a memory device according to a first embodiment.

FIG. 2 is a circuit diagram of a memory cell array according to the first embodiment.

FIG. 3 shows a cross-sectional structure of a part of the memory cell array according to the first embodiment.

FIG. 4 shows a cross-sectional structure of a part of the memory cell array according to the first embodiment.

FIG. 5 shows a cross-section of an example of the structure of a memory cell according to the first embodiment.

FIG. 6 shows details of some functional blocks of the memory device according to the first embodiment.

FIG. 7 shows an example of components and connections of a column selector and a row selector according to the first embodiment.

Fig. 8 shows a first example of components and connections of a sense amplifier according to the first embodiment.

FIG. 9 shows a first example of components and connections of another sense amplifier according to the first embodiment.

Fig. 10 shows a second example of components and connections of a sense amplifier according to the first embodiment.

FIG. 11 shows a state during data reading from the memory device according to the first embodiment.

FIG. 12 shows a state of the memory device according to the first embodiment.

FIG. 13 shows a state during data reading from the memory device according to the first embodiment.

FIG. 14 shows a state of the memory device according to the first embodiment.

FIG. 15 shows a state during data reading from a memory device according to a first reference.

FIG. 16 shows a state during data reading from a memory device according to a second reference.

FIG. 17 shows a state during data reading from a memory device according to a third reference.

FIG. 18 shows components of a memory device according to a fourth reference and a state during data reading.

FIG. 19 shows details of some functional blocks of a memory device according to a second embodiment.

Fig. 20 shows an example of components and connections of a column selector and a row selector according to the second embodiment.

FIG. 21 shows a state during data reading from a memory device according to the second embodiment.

11ul: upper left subarray

11ur: upper right subarray

11dl: lower left subarray

11dr: Bottom right subarray

14u: Upper column selector / first part

14d: The following selector/second part

15l: left row selector / first part

15r: Right row selector / second part

BL1: left bit line

BLlS: Select left bit line

BLr: right bit line

BLrS: Select the right bit line

GBL1: global bit line

GBLr: global bit line

GWLu: global word line

GWLd: global word line

Irul: read current

Irdr: read current

LBLl: local bit line

LBLr: local bit line

LWLu: local word line

LWLd: local word line

MCul: upper left memory cell

MCulS: Select the upper left memory cell

MCdr: lower right memory cell

MCdrS: Select the lower right memory cell

N1ul: the first node

N1dr: first node

N2ul: second node

N2dr: second node

SAul: upper left sense amplifier

SAdr: Lower Right Sense Amplifier

WLu: upper word line

WLuS: Select upper word line

WLd: lower word line

WLdS: Select the lower word line

Claims (12)

A variable resistance memory device, comprising: a first interconnect; a second interconnect; a third interconnect; a fourth interconnect; a first memory cell coupled to the first interconnect and the third interconnect and having a variable resistance; a second memory cell coupled to the second interconnect and the fourth interconnect and having a variable resistance; a first sense amplifier having a first terminal and a second terminal with a potential difference between the first terminal and the second terminal, the first terminal being coupled to the first interconnect and a node of a first potential and the second terminal positioned proximate to a node of a second potential and coupled to the third interconnect; and a second sense amplifier having a third terminal and a fourth terminal with a potential difference between the third terminal and the fourth terminal, the third terminal being coupled to the fourth interconnect and A node of a third potential, and the fourth terminal is positioned proximate to a node of a fourth potential and coupled to the second interconnect. Such as the device of claim 1, wherein the first sense amplifier is configured to output a voltage based on a voltage of the second terminal, and The second sense amplifier is configured to output a voltage based on a voltage of the fourth terminal. Such as the device of claim 1, wherein the first sense amplifier is configured to output a voltage based on a voltage of the second terminal, and The second sense amplifier is configured to output a voltage based on a voltage of the third terminal. Such as the device of claim 1, wherein the first sense amplifier is configured to source a first current from the second terminal and sink the first current at the first terminal, and The second sense amplifier is configured to source a second current from the fourth terminal and sink the second current at the third terminal. The device of claim 1, wherein the first sense amplifier and the second sense amplifier are enabled in parallel. Such as the device of claim 1, further comprising: a first memory cell array including the first memory cell; a second memory cell array; a third memory cell array; a fourth memory cell array including the second memory cell; a first circuit positioned between the first memory cell array and the second memory cell array and including a first switch between the first terminal and the first interconnect; a second circuit positioned between the first memory cell array and the third memory cell array and including a second switch between the second terminal and the third interconnect; a third circuit positioned between the third memory cell array and the fourth memory cell array and including a third switch between the fourth terminal and the second interconnect; and A fourth circuit is positioned between the second memory cell array and the fourth memory cell array and includes a fourth switch between the third terminal and the fourth interconnect. Such as the device of claim 1, further comprising: a third memory cell coupled to the first interconnect and the fourth interconnect and having a variable resistance; and A fourth memory cell is coupled to the third interconnection and the second interconnection and has a variable resistance. Such as the device of claim 7, further comprising: a first memory cell array including the first memory cell; a second memory cell array including the third memory cell; a third memory cell array including the fourth memory cell; a fourth memory cell array including the second memory cell; a first circuit positioned between the first memory cell array and the second memory cell array and including a first switch between the first terminal and the first interconnect; a second circuit positioned between the first memory cell array and the third memory cell array and including a second switch between the second terminal and the third interconnect; a third circuit positioned between the third memory cell array and the fourth memory cell array and including a third switch between the fourth terminal and the second interconnect; and A fourth circuit is positioned between the second memory cell array and the third memory cell array and includes a fourth switch between the third terminal and the fourth interconnect. Such as the device of claim 7, further comprising: a third sense amplifier having a fifth terminal coupled to a node of a fifth potential and the first interconnect and a sixth terminal positioned less than the sixth terminal a fifth terminal closer to a node of a sixth potential higher than the fifth potential and coupled to the fourth interconnect; and a fourth sense amplifier having a seventh terminal coupled to a node of a seventh potential and the third interconnect and an eighth terminal positioned less than the A seventh terminal is closer to a node of an eighth potential higher than the seventh potential and is coupled to the second interconnection. Such as the device of claim 1, further comprising: a fifth interconnect; a sixth interconnect; a third memory cell coupled to the first interconnect and the fifth interconnect and having a variable resistance; a fourth memory cell coupled to the sixth interconnect and the second interconnect and having a variable resistance; a third sense amplifier having a fifth terminal coupled to a node of a fifth potential and the first interconnect and a sixth terminal positioned less than the sixth terminal a fifth terminal closer to a node of a sixth potential higher than the fifth potential and coupled to the fifth interconnect; and a fourth sense amplifier having a seventh terminal coupled to a node of a seventh potential and the sixth interconnect and an eighth terminal positioned less than the A seventh terminal is closer to a node of an eighth potential higher than the seventh potential and is coupled to the second interconnection. The device of claim 10, wherein the first sense amplifier, the second sense amplifier, the third sense amplifier and the fourth sense amplifier are enabled simultaneously. Such as the device of claim 10, further comprising: a first memory cell array including the first memory cell; a second memory cell array including the third memory cell; a third memory cell array including the fourth memory cell; a fourth memory cell array including the second memory cell; a first circuit positioned between the first memory cell array and the second memory cell array and including between the first terminal and the fifth terminal and the first interconnect a first switch; a second circuit positioned between the first memory cell array and the third memory cell array and including a second switch between the second terminal and the third interconnect; a third circuit positioned between the first memory cell array and the third memory cell array and including a third switch between the seventh terminal and the sixth interconnect; a fourth circuit positioned between the third memory cell array and the fourth memory cell array and including between the fourth terminal and the eighth terminal and the second interconnect a fourth switch; a fifth circuit positioned between the second memory cell array and the fourth memory cell array and including a fifth switch between the sixth terminal and the fifth interconnect; and A sixth circuit is positioned between the second memory cell array and the fourth memory cell array and includes a sixth switch between the third terminal and the fourth interconnect.

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