TW202411993A - Forming method of memory device - Google Patents

Abstract

According to one embodiment, a memory device includes first interconnects in a first direction, second interconnects in a second direction intersecting the first direction, and memory cells. Each of the memory cells is associated with a set of one of the first interconnects and one of the second interconnects between the first interconnects and the second interconnects and includes a variable resistance element and a switching element which are coupled in series. A forming method of the memory device includes: selecting a memory cell having a highest interconnect resistance from memory cells on which a forming process has not been performed; performing a forming process on a switching element in the selected memory cell; and repeating the selecting and the performing on the memory cells.

Description

Method for forming a memory device

Embodiments described herein generally relate to a method of forming a memory device.

A memory device using a variable resistance element as a storage element is known. A variable resistance element is used as a memory cell when coupled in series to a switching element. A 2-terminal type switching element is used as a switching element.

In general, according to one embodiment, a memory device includes a plurality of first interconnects in a first direction, a plurality of second interconnects in a second direction intersecting the first direction, and a plurality of memory cells. Each of the plurality of memory cells is associated with a set of one of the plurality of first interconnects and one of the plurality of second interconnects between the plurality of first interconnects and the plurality of second interconnects and includes a variable resistance element and a switching element coupled in series. A method of forming the memory device includes: selecting a memory cell having a highest interconnect resistance from memory cells for which a forming process has not yet been performed; performing a forming process on a switching element in the selected memory cell; and repeating the selection and the execution on the plurality of memory cells.

In the following, embodiments will be described with reference to the drawings. In the following description, components having the same function and configuration will be represented by the same element symbol. In order to distinguish multiple structural elements having a common element symbol from each other, an additional symbol is added after the common element symbol. 1. Embodiments

An embodiment will be described. 1.1 Configuration 1.1.1 Memory system

A configuration of a memory system including a memory device according to an embodiment will be described. Fig. 1 is a block diagram showing an example of a configuration of a memory system including a memory device according to an embodiment.

A memory system 1 is a storage device. The memory system 1 performs a data write process and a data read process. The memory system 1 includes a memory device 2 and a memory controller 3.

For example, the memory device 2 is a magnetic memory device (magnetoresistive random access memory, MRAM). The memory device 2 stores data in a non-volatile manner. The memory device 2 includes a plurality of storage elements. For example, the storage element is a magnetoresistive element. The magnetoresistive element is a type of variable resistance element having a magnetoresistive effect brought about by a magnetic tunnel junction (MTJ). The magnetoresistive element can be referred to as an MTJ element.

The memory controller 3 is configured as an integrated circuit (such as a system on a chip (SoC)). The memory controller 3 causes the memory device 2 to perform a write process and a read process in response to a request from an externally located host device (not shown). In a write process, the memory controller 3 sends data to be written to the memory device 2. In a read process, the memory controller 3 receives data read from the memory device 2. 1. 1. 2 Memory Device

Next, an internal configuration of a memory device according to an embodiment will be described with reference to FIG. 1.

The memory device 2 includes a memory cell array 10, a row selection circuit 11, a column selection circuit 12, a decoding circuit 13, a writing circuit 14, a reading circuit 15, a voltage generator 16, an input/output circuit 17 and a control circuit 18.

The memory cell array 10 is a data storage unit in the memory device 2. The memory cell array 10 includes a plurality of memory cells MC. Each memory cell MC is associated with a set of a column and a row. The memory cells MC in the same column are coupled to the same word line WL, and the memory cells MC in the same row are coupled to the same bit line BL.

The column selection circuit 11 is a circuit for selecting a column of the memory cell array 10. The column selection circuit 11 is coupled to the memory cell array 10 via the word line WL. A decoding result (column address) of an address ADD from the decoding circuit 13 is supplied to the column selection circuit 11. The column selection circuit 11 selects a word line WL corresponding to a column based on the decoding result of the address ADD. Hereinafter, a selected word line WL will be referred to as a "selected word line WL". Word lines WL other than the selected word line WL will be referred to as "non-selected word lines WL".

The row selection circuit 12 is a circuit for selecting a row of the memory cell array 10. The row selection circuit 12 is coupled to the memory cell array 10 via the bit line BL. A decoding result (row address) of an address ADD received from the decoding circuit 13 is supplied to the row selection circuit 12. The row selection circuit 12 selects a bit line BL corresponding to a row based on the decoding result of the address ADD. Hereinafter, a selected bit line BL will be referred to as a "selected bit line BL". Bit lines BL other than the selected bit line BL will be referred to as "non-selected bit lines BL".

A memory cell MC designated by a selected word line WL and a selected bit line BL is referred to as a “selected memory cell MC.” Memory cells MC other than the selected memory cell MC will be referred to as “non-selected memory cells MC.” A predetermined current may be caused to flow through a selected memory cell MC via a selected word line WL and a selected bit line BL.

The decoding circuit 13 is a decoder that decodes an address ADD received from the input/output circuit 17. The decoding circuit 13 supplies a decoding result of an address ADD to the row selection circuit 11 and the column selection circuit 12. The address ADD includes an address of a row to be selected and an address of a column to be selected.

For example, the write circuit 14 includes a write driver (not shown). The write circuit 14 writes data into a memory cell MC in a write process.

For example, the read circuit 15 includes a sense amplifier (not shown). The read circuit 15 reads data from a memory cell MC in a read process.

The voltage generator 16 generates voltages used for various types of processing in the memory cell array 10 using a power supply voltage supplied from a device (not shown) outside the memory device 2. For example, the voltage generator 16 generates various types of voltages required in a write process and outputs the voltages to the write circuit 14. In addition, for example, the voltage generator 16 generates various types of voltages required in a read process and outputs the voltages to the read circuit 15.

The input/output circuit 17 controls the communication with the memory controller 3. The input/output circuit 17 transmits an address ADD received from the memory controller 3 to the decoding circuit 13. The input/output circuit 17 also transmits a command CMD received from the memory controller 3 to the control circuit 18. The input/output circuit 17 allows various control signals CNT to be transmitted and received between the memory controller 3 and the control circuit 18. The input/output circuit 17 transmits the data DAT received from the memory controller 3 to the write circuit 14. The input/output circuit 17 outputs the data DAT transmitted from the read circuit 15 to the memory controller 3.

For example, the control circuit 18 includes a processor such as a central processing unit (CPU) and a read-only memory (ROM). The control circuit 18 controls the circuits included in the memory device 2, namely, the column selection circuit 11, the row selection circuit 12, the decoding circuit 13, the writing circuit 14, the reading circuit 15, the voltage generator 16 and the input/output circuit 17 based on a control signal CNT and a command CMD. 1. 1. 3 Memory cell array

Next, a circuit configuration of a memory cell array of a memory device according to an embodiment will be described.

FIG2 is a circuit diagram showing a circuit configuration example of a memory cell array according to an embodiment. In FIG2 , word lines WL and bit lines BL are distinguished by additional letters including indexes (“<>”). Word lines WL extend in a first direction and bit lines BL extend in a second direction intersecting the first direction.

The memory cell array 10 includes a plurality of memory cells MC, a plurality of word lines WL, and a plurality of bit lines BL. In the example shown in FIG. 2 , the plurality of memory cells MC include (M+1)×(N+1) memory cells, MC <0, 0>, …, MC <0, N>, …, MC <M, 0>, …, and MC <M, N> (each of M and N is an integer equal to or greater than 1). In the example of FIG. 2 , each of M and N is an integer equal to or greater than 1; however, the embodiment is not limited to this example. M and N may be 0. The plurality of word lines WL include (M+1) word lines, WL <0>, …, and WL <M>. The plurality of bit lines BL include (N+1) bit lines, BL <0>, . . . , and BL <N>.

A plurality of memory cells MC are arranged in a matrix pattern. Each memory cell MC is associated with a set of a single word line WL and a single bit line BL. In other words, a memory cell MC ＜m, n＞ (0 ≤ m ≤ M, 0 ≤ n ≤ N) is coupled to a word line WL ＜m＞ and a bit line BL ＜n＞. The memory cell MC ＜m, n＞ includes a switching element SW ＜m, n＞ and a variable resistance element SE ＜m, n＞. The switching element SW ＜m, n＞ and the variable resistance element SE ＜m, n＞ are coupled in series.

The switching element SW is a 2-terminal switching element. The 2-terminal switching element is different from a 3-terminal switching element (such as a transistor, etc.) in that it does not have a third terminal. More specifically, for example, if a voltage applied to a corresponding memory cell MC is lower than a critical voltage Vth, the switching element SW interrupts a current (turns to an off state), thereby acting as an insulator with a large resistance value. If a voltage applied to a corresponding memory cell MC is equal to or higher than the critical voltage Vth, the switching element SW transmits a current (turns to an on state), thereby acting as a conductor with a small resistance value. The switching element SW switches between passing and interrupting a current according to a magnitude of a voltage applied to a corresponding memory cell MC, regardless of the polarity of the voltage applied to the two terminals (in other words, regardless of the direction of the current passed between the two terminals).

According to the configuration described above, when a memory cell MC is selected, the switch element SW included in the selected memory cell MC is turned to an on state, thereby transmitting a current to the variable resistance element SE in the selected memory cell MC.

The variable resistance element SE is a storage element. The variable resistance element SE can switch its resistance value between a low resistance state and a high resistance state based on a current flowing when the switching element SW is in an on state. The variable resistance element SE stores data in a non-volatile manner according to the change of its resistance state. 1. 1. 4 Variable resistance element

Next, a configuration of a variable resistance element according to an embodiment will be described.

FIG3 is a cross-sectional view showing a configuration example of a variable resistance element according to an embodiment. FIG3 shows an example of a configuration of SE in a case where the variable resistance element SE is a magnetoresistive element (MTJ element). In a case where the variable resistance element SE is a magnetoresistive element, it includes a ferromagnetic layer 21, a nonmagnetic layer 22, and a ferromagnetic layer 23. The ferromagnetic layer 21, the nonmagnetic layer 22, and the ferromagnetic layer 23 are stacked on a semiconductor substrate (not shown).

The ferromagnetic layer 21 is a conductive film having ferromagnetic properties. The ferromagnetic layer 21 is used as a storage layer. The ferromagnetic layer 21 has an easy magnetization axis in a direction perpendicular to the layer stacking plane. The magnetization direction of the ferromagnetic layer 21 is variable. The ferromagnetic layer 21 includes iron (Fe). The ferromagnetic layer 21 may further include at least one of cobalt (Co) or nickel (Ni). The ferromagnetic layer 21 may further include boron (B). Specifically, the ferromagnetic layer 21 may include, for example, cobalt iron boron (FeCoB) or iron boride (FeB).

A non-magnetic layer 22 is disposed on the film surface of the ferromagnetic layer 21. The non-magnetic layer 22 is an insulating film having non-magnetic properties. The non-magnetic layer 22 is used as a tunneling barrier layer. The non-magnetic layer 22 is disposed between the ferromagnetic layer 21 and the ferromagnetic layer 23, and the two ferromagnetic layers are combined to form a magnetic tunneling junction. In addition, during a crystallization process of the ferromagnetic layer 21, the non-magnetic layer 22 is also used as a seed material, and the seed material is used as a crystal nucleus for growing a crystal film from an interface with the ferromagnetic layer 21. The non-magnetic layer 22 has a NaCl crystal structure whose film plane is oriented in a (001) plane. The non-magnetic layer 22 contains magnesium oxide (MgO).

The ferromagnetic layer 23 is disposed on a film plane of the non-magnetic layer 22 which is positioned opposite to a film plane on which the ferromagnetic layer 21 is disposed. The ferromagnetic layer 23 is a conductive film having ferromagnetic properties. The ferromagnetic layer 23 is used as a reference layer. The ferromagnetic layer 23 has an easy magnetization axis in a direction perpendicular to the film plane. The magnetization direction of the ferromagnetic layer 23 is fixed. In the example shown in FIG. 3 , the magnetization direction of the ferromagnetic layer 23 is in the magnetization direction of the ferromagnetic layer 21. "Fixed magnetization direction" indicates that the magnetization direction is not changed by a torque large enough to reverse the magnetization direction of the ferromagnetic layer 21. The ferromagnetic layer 23 includes at least one compound selected from the group consisting of, for example, cobalt platinum (CoPt), cobalt nickel (CoNi), and cobalt palladium (CoPd).

The magnetoresistive element can be in a low resistance state or a high resistance state depending on whether the relative relationship between the magnetization direction of the storage layer and the magnetization direction of the reference layer is parallel or antiparallel. In the following, a case where a spin injection writing method is used as a method for changing the resistance state of the magnetoresistive element will be explained. Using the spin injection writing method, a spin torque is generated by passing a write current through the magnetoresistive element. Then, the generated spin torque is used to control the magnetization direction of the storage layer relative to the magnetization direction of the reference layer.

When a write current Iw0 flows from the storage layer to the reference layer (in the direction of arrow A1 in FIG. 3 ) in the magnetoresistive element, the relative relationship of the magnetization directions between the storage layer and the reference layer becomes parallel. When the relationship is in a parallel state, the magnetoresistive element is set to a low resistance state. For example, the low resistance state is associated with data "0". The low resistance state is also called a "P (parallel) state".

When a write current Iw1 greater than the write current Iw0 flows from the reference layer to the storage layer (in the direction of arrow A2 in FIG. 3 ) in the magnetoresistive element, the relative relationship of the magnetization directions between the storage layer and the reference layer becomes antiparallel. When the relationship is in an antiparallel state, the magnetoresistive element is set to a high resistance state. For example, the high resistance state is associated with data "1". The high resistance state is also called an "AP (antiparallel) state".

When a read current Ir flows in the magnetoresistive element, the magnetization directions of the storage layer and the reference layer do not change. The read circuit 15 determines whether the resistance state of the magnetoresistive element is a P state or an AP state based on the read current Ir. In this way, the read circuit 15 can read data from a memory cell MC.

The correspondence between the resistance state and the data is not limited to the above examples. For example, a P state and an AP state can be associated with data "1" and data "0", respectively. The polarity of a read current Ir can be negative. 1. 2 Operation

Next, a forming process will be described as one of the operations in the memory device according to the embodiment. The forming process is a process for changing the current-voltage characteristic of the switching element SW from an initial state. For example, the forming process is performed before the shipment of the memory device 2. In other words, the memory device 2 is shipped after the current-voltage characteristic of the switching element SW is changed from the initial state by the forming process so that the write process and the read process can be performed. 1. 2. 1 Change of characteristics of the switching element

FIG. 4 is a diagram showing an example of current-voltage characteristics of a switching element before and after a formation process in a memory device according to an embodiment. The current-voltage characteristics shown in FIG. 4 indicate a logarithmic value of a current relative to a voltage. In the example of FIG. 4 , line L1 represents a current-voltage characteristic of a switching element SW that is mainly in an off state before the formation process (i.e., in an initial state). Line L2 represents a current-voltage characteristic of a switching element SW that is mainly in an off state after the formation process.

The forming process is performed by applying a voltage equal to or higher than a forming voltage Vf to the switching element SW. By applying a voltage equal to or higher than the forming voltage Vf to the switching element SW, the current-voltage characteristic of the switching element SW changes from the state represented by the line L1 to the state represented by the line L2.

As indicated by line L1, before the forming process, by applying a potential difference equal to or higher than the forming voltage Vf to the switching element SW, the switching element SW is turned to the on state. In other words, the forming voltage Vf can be regarded as a critical voltage of the switching element SW before the forming process is performed. On the other hand, as indicated by line L2, after the forming process, by applying a potential difference equal to or higher than the critical voltage Vth (which is lower than the forming voltage Vf) to the switching element SW, the switching element SW is turned to the on state. Therefore, the critical voltage of the switching element SW is reduced from the forming voltage Vf to the critical voltage Vth by the forming process. In addition, the amount of current flowing through the switching element SW in the off state is greater after the forming process than before the forming process. 1. 2. 2 Applied voltage

Fig. 5 is a view showing an example of voltage applied in a formation process of a memory cell in a memory device according to an embodiment. The example of Fig. 5 shows a voltage applied to a memory cell array 10 in a case where a formation process is performed on a switching element SW ＜m, n＞ of a memory cell MC ＜m, n＞.

In the case where the forming process is performed on the switching element SW <m, n>, the column selection circuit 11 applies a voltage VSS to, for example, the word line WL <m>. The row selection circuit 12 applies a voltage Vapp to, for example, the bit line BL <n>. For example, the voltage VSS is 0 V. The voltage Vapp is higher than the forming voltage Vf.

The column selection circuit 11 applies a voltage Vusel to all word lines WL except the word line WL <m>. The row selection circuit 12 applies a voltage Vusel to all bit lines BL except the bit line BL <n>. The voltage Vusel is higher than the voltage VSS and lower than the voltage Vapp. The voltage Vusel is a voltage that turns the switching element SW to the off state regardless of whether it is before or after the formation process. In other words, the voltage Vusel is lower than the threshold voltage Vth. For example, the voltage Vusel is Vapp/2.

Therefore, assuming that the interconnect resistance of the word line WL and the bit line BL is ignored, the potential difference Vapp is applied to the memory cell MC <m, n>. The state of the memory cell MC <m, n> is called a "selection state". For example, the potential difference Vapp/2 is applied to the memory cells coupled to the word line WL <m> or the bit line BL <n> other than the memory cell MC <m, n>, that is, the memory cells MC <0, n> to MC <m-1, n>, MC <m+1, n> to MC <M, n>, MC <m, 0> to MC <m, n-1> and MC <m, n+1> to MC <m, N> of all the memory cells. The state of memory cells MC <0, n> to MC <m-1, n>, MC <m+1, n> to MC <M, n>, MC <m, 0> to MC <m, n-1>, and MC <m, n+1> to MC <m, N> is called a "semi-selected state". There is no potential difference in any memory cell MC other than the memory cell MC coupled to the word line WL <m> or the bit line BL <n>. The state of all memory cells MC that are neither in a selected state nor in a semi-selected state is called a "non-selected state".

In an actual formation process, the interconnect resistance of the word line WL and the bit line BL may not be negligible. If the interconnect resistance of the word line WL and the bit line BL is not negligible, a potential difference Vcell applied to the memory cell MC ＜m,n＞ in the selected state is approximated by using the potential difference Vapp in the equation below. By applying a potential difference Vcell equal to or higher than the formation voltage Vf in the following equation, the current-voltage characteristic of the switching element SW ＜m, n＞ can be changed from the state of line L1 shown in Figure 4 to the state of line L2. Vcell = Vapp-(Vd_wl+Vd_bl) ≈ Vapp-(R_WL+R_BL)×(Icell+ΣIleak).

In the equation, Vd_wl and Vd_bl are the amounts of voltage drops occurring in the word line WL ＜m＞ and the bit line BL ＜n＞, respectively. R_WL is an interconnect resistance in a portion of the word line WL ＜m＞ from the column selection circuit 11 to the memory cell MC ＜m, n＞. R_BL is an interconnect resistance in a portion of the bit line BL ＜n＞ from the self-selection circuit 12 to the memory cell MC ＜m, n＞. Icell is a current flowing through the memory cell MC ＜m, n＞. Ileak is a leakage current flowing through the memory cell MC other than the memory cell MC ＜m, n＞. ΣIleak is a sum of the leakage currents Ileak (total leakage current).

In the formation process described above, the current Icell can be regarded as 0 during a period until the potential difference Vcell reaches the formation voltage Vf. Therefore, the difference between the potential difference Vapp and the potential difference Vcell can be regarded as caused by the leakage current Ileak and the product of the interconnect resistances R_WL and R_BL. 1. 2. 3 Flowchart

FIG. 6 is a flow chart showing an overview of a process of forming a memory cell array in a memory device according to an embodiment.

After receiving a command (START) to start the formation process from the memory controller 3, the control circuit 18 selects a memory cell MC having a highest interconnect resistance from the memory cells MC for which the formation process has not yet been performed (S10).

The control circuit 18 performs a forming process (S20) on the memory cell MC selected by the process of S10. Specifically, if the memory cell MC ＜m, n＞ is selected by the process of S10, the column selection circuit 11 applies the voltage VSS to the word line WL ＜m＞, and applies the voltage Vusel to all the word lines WL except the word line WL ＜m＞. The row selection circuit 12 applies the voltage Vapp to the bit line BL ＜n＞, and applies the voltage Vusel to all the bit lines BL except the bit line BL ＜n＞. Therefore, a potential difference Vcell equal to or higher than the forming voltage Vf is applied to the switching element SW ＜m, n＞ of the memory cell MC ＜m, n＞. Therefore, the current-voltage characteristic of the switching element SW <m, n> changes from the initial state.

After the process of S20, the control circuit 18 determines whether the formation process has been executed on all the memory cells MC (S30).

If there is a memory cell MC for which the formation process has not been performed (S30; No), the control circuit 18 selects a memory cell MC having a highest interconnect resistance from the memory cells MC for which the formation process has not been performed (S10). Then, the control circuit 18 performs the formation process on the memory cell MC selected by the process of S10 (S20). As described above, the processes of S10 and S20 are repeated until the formation process is performed on all memory cells MC.

If the formation process has been executed for all memory cells MC (S30; Yes), the formation process of the memory cell array 10 is terminated (End). 1. 3. Advantageous effects of the embodiment

According to the embodiment, the control circuit 18 selects one memory cell MC having a highest interconnect resistance (R_WL+R_BL) from the memory cells MC for which the formation process has not been performed. The control circuit 18 performs the formation process on the switching element SW in the selected memory cell MC. The control circuit 18 repeats the selection and execution on all the memory cells MC in the memory cell array 10. Therefore, the reliability of the switching element SW after the formation process can be improved. The effect will be described below.

FIG7 is a diagram showing an example of a relationship between a selection order of memory cells and an interconnect resistance in a formation process of a memory cell array in a memory device according to an embodiment. FIG8 is a diagram showing an example of a relationship between a selection order of memory cells and a total leakage current in a formation process of a memory cell array in a memory device according to an embodiment. FIG7 and FIG8 respectively show an interconnect resistance (R_WL+R_BL) and a total leakage current ΣIleak on a vertical axis relative to a selection order on a horizontal axis.

As shown in FIG. 7 , in the case where memory cells MC are selected in the order of one memory cell MC having a highest interconnect resistance (R_WL+R_BL) from among all memory cells MC for which the formation process has not yet been performed, the interconnect resistance (R_WL+R_BL) decreases in the selection order.

On the other hand, the number of memory cells MC for which the formation process has been executed increases in the order of selection. Therefore, the number of memory cells MC for which the formation process has been executed among all memory cells MC in the semi-selection state increases in the order of selection.

The leakage current Ileak flowing through the memory cell MC in the semi-selected state is greater in the case where the formation process has been performed on the memory cell MC in the semi-selected state than in the case where the formation process has not been performed in the semi-selected state. Therefore, as shown in FIG8, the total leakage current ΣIleak increases in the selection order.

As described above, according to the formation method of the embodiment, in a relatively early selected memory cell MC, the interconnect resistance (R_WL+R_BL) is relatively higher, while the total leakage current ΣIleak can be relatively smaller. In contrast, in a relatively late selected memory cell MC, the total leakage current ΣIleak is relatively larger, while the interconnect resistance (R_WL+R_BL) can be relatively lower. Therefore, a large change in the product of the interconnect resistance (R_WL+R_BL) and the total leakage current ΣIleak attributable to the selection sequence can be suppressed. Therefore, a change in the potential difference Vcell between the memory cells in an early sequence and in a late sequence can be suppressed. Therefore, by applying a potential difference Vcell lower than the forming voltage Vf, a failure (a forming failure) in changing the current-voltage characteristic of the switching element SW can be suppressed. By applying a potential difference Vcell excessively higher than the forming voltage Vf, for example, the insulation breakdown of the non-magnetic layer 22 of the variable resistance element SE of the selected memory cell MC can be suppressed. 2. Modifications, etc.

Various modifications are applicable to the embodiments described above. 2. 1. First modification

For example, the order in which the forming process is performed may be determined based on the length of an interconnect.

Fig. 9 is a flow chart showing an example of a forming procedure of a memory cell array in a memory device according to a first modification. Fig. 9 corresponds to Fig. 6 of the embodiment.

After receiving a command (start) to start the formation process from the memory controller 3, the control circuit 18 selects a memory cell MC whose sum of the length of an interconnection of the word line WL from the column selection circuit 11 and the length of an interconnection of the bit line BL from the bit selection circuit 12 is the largest among all the memory cells MC for which the formation process has not yet been performed (S10A).

The control circuit 18 executes the forming process on the memory cell MC selected by the process of S10A (S20).

After the process of S20, the control circuit 18 determines whether the formation process has been executed on all the memory cells MC (S30).

If there is a memory cell MC for which the formation process has not been performed (S30; No), the control circuit 18 selects a memory cell MC for which the sum of the length of an interconnection of the word line WL from the column selection circuit 11 and the length of an interconnection of the bit line BL from the bit selection circuit 12 is the largest among all the memory cells MC for which the formation process has not been performed (S10A). Then, the control circuit 18 performs the formation process on the memory cell MC selected by the process of S10A (S20). As described above, the processes of S10A and S20 are repeated until the formation process is performed on all the memory cells MC.

If the forming process has been executed for all the memory cells MC (S30; Yes), the forming process of the memory cell array 10 is terminated (End).

According to the first modification, without deteriorating the reliability of the switching element SW due to the formation process, a memory cell MC having a higher interconnect resistance can be selected more easily than in the case where the interconnect resistance is directly evaluated. 2. 2. Second modification

Alternatively, the order in which the formation process is performed may be determined based on a product of an interconnect length and a sheet resistance.

Fig. 10 is a flow chart showing an example of a forming procedure of a memory cell array in a memory device according to a second modification. Fig. 10 corresponds to Fig. 6 of the embodiment.

After receiving a command (start) to start the formation process from the memory controller 3, the control circuit 18 selects a memory cell MC whose sum of a product of a thin film resistance of the word line WL and a length of an interconnection of the word line WL from the column selection circuit 11 and a product of a thin film resistance of the bit line BL and a length of an interconnection of the bit line BL from the selection circuit 12 is the largest among all memory cells MC for which the formation process has not yet been performed (S10B).

The control circuit 18 executes the forming process on the memory cell MC selected by the process of S10B (S20).

After the process of S20, the control circuit 18 determines whether the formation process has been executed on all the memory cells MC (S30).

If there is a memory cell MC for which the formation process has not been performed (S30; No), the control circuit 18 selects a memory cell MC for which the sum of a product of a film resistance of the word line WL and a length of an interconnection of the word line WL from the column selection circuit 11 and a product of a film resistance of the bit line BL and a length of an interconnection of the bit line BL from the selection circuit 12 is the largest among all the memory cells MC for which the formation process has not been performed (S10B). Then, the control circuit 18 performs the formation process on the memory cell MC selected by the process of S10B (S20). As described above, the processes of S10B and S20 are repeated until the formation process is performed on all the memory cells MC.

If the forming process has been executed for all the memory cells MC (S30; Yes), the forming process of the memory cell array 10 is terminated (End).

According to the second modification, even if the thin film resistance of the word line WL and the bit line BL is different, the formation process can be performed sequentially on the memory cells MC in the order of the highest to the lowest interconnect resistance. Therefore, the same effect as in the embodiment can be obtained. 3. Others

In the embodiment, the first modification, and the second modification, a case is described in which the selection order in the formation process is determined based on the magnitude of the interconnect resistance (R_WL+R_BL) of the memory cell MC; however, the embodiment is not limited to this case. For example, if it is known that an address of a memory cell MC in which a large leakage current Ileak easily flows regardless of the magnitude of the interconnect resistance (R_WL+R_BL) of the memory cell MC due to the characteristics of the production process or the layout of the memory cell array 10, the formation process of this memory cell MC can be preferentially performed first. Alternatively, for example, if it is known that an address of a memory cell MC where a formation failure is likely to occur regardless of the magnitude of the interconnect resistance (R_WL+R_BL) of a memory cell MC due to the production process or the characteristics of the layout of the memory cell array 10, the formation process of this memory cell MC may be preferentially performed first.

In the aforementioned embodiment, the first modification, and the second modification, a case where the forming process is applied to a magnetic memory device such as an MRAM is described; however, the embodiment is not limited to this case. For example, the forming process described above is applicable to a resistance change memory similar to an MRAM, such as a phase change random access memory (PCRAM) and a resistive random access memory (ReRAM).

Although certain embodiments have been described, such embodiments are presented by way of example only and are not intended to limit the scope of the invention. In fact, the novel embodiments described herein may be embodied in various other forms; furthermore, various omissions, substitutions, and changes in the form of the embodiments described herein may be made without departing from the spirit of the invention. Modifications of the embodiments and the like are covered by the accompanying invention application and their equivalents, as would fall within the scope and spirit of the invention. Cross-references to Related Applications

This application is based upon and claims the benefit of priority of Japanese Patent Application No. 2022-143161 filed on September 8, 2022 and U.S. Patent Application No. 18/180003 filed on March 7, 2023, the entire contents of which are incorporated herein by reference.

1: Memory system 2: Memory device 3: Memory controller 10: Memory cell array 11: Column selection circuit 12: Row selection circuit 13: Decoding circuit 14: Write circuit 15: Read circuit 16: Voltage generator 17: Input/output circuit 18: Control circuit 21: Ferromagnetic layer 22: Nonmagnetic layer 23: Ferromagnetic layer S10: Program S10A: Program S10B: Program S20: Program S30: Program

FIG. 1 is a block diagram showing a configuration example of a memory system including a memory device according to an embodiment.

FIG. 2 is a circuit diagram showing an example of a circuit configuration of a memory cell array according to an embodiment.

FIG3 is a cross-sectional view showing a configuration example of a variable resistance element according to an embodiment.

4 is a graph showing an example of current-voltage characteristics of a switching element before and after a formation process in a memory device according to an embodiment.

FIG. 5 is a diagram showing an example of voltage applied in a formation process of a memory cell in a memory device according to an embodiment.

FIG. 6 is a flow chart showing an overview of a process of forming a memory cell array in a memory device according to an embodiment.

7 is a diagram showing an example of a relationship between a selection order of memory cells and an interconnect resistance in a formation process of a memory cell array in a memory device according to an embodiment.

8 is a diagram showing an example of a relationship between a selection order of memory cells and a total leakage current in a formation process of a memory cell array in a memory device according to an embodiment.

FIG. 9 is a flow chart showing a forming procedure of a memory cell array in a memory device according to a first modification.

FIG. 10 is a flow chart showing a forming procedure of a memory cell array in a memory device according to a second modification.

S10: Procedure

S20: Procedure

S30: Procedure

Claims (15)

A method for forming a memory device, the memory device includes a plurality of first interconnects in a first direction, a plurality of second interconnects in a second direction intersecting the first direction, and a plurality of memory cells, each of the plurality of memory cells is associated with a set of one of the plurality of first interconnects and one of the plurality of second interconnects between the plurality of first interconnects and the plurality of second interconnects and includes a variable resistance element and a switching element coupled in series, the method comprising: Selecting a memory cell having a highest interconnect resistance from memory cells for which a forming process has not yet been performed; Performing a forming process on a switching element in the selected memory cell; and Repeating the selection and the execution on the plurality of memory cells. A formation method as claimed in claim 1, wherein: the memory device includes a first circuit configured to select one of the plurality of first interconnects and a second circuit configured to select one of the plurality of second interconnects; and the selection includes selecting a memory cell in which a sum of a first interconnect length to the first circuit and a second interconnect length to the second circuit is the largest of the memory cells for which the formation process has not yet been performed. A formation method as claimed in claim 1, wherein: Each of the plurality of first interconnects has a first thin film resistor; Each of the plurality of second interconnects has a second thin film resistor; The memory device includes a first circuit configured to select one of the plurality of first interconnects and a second circuit configured to select one of the plurality of second interconnects; and The selection includes selecting a memory cell in which a sum of a product of the first thin film resistor and a first interconnect length to the first circuit and a sum of a product of the second thin film resistor and a second interconnect length to the second circuit is the largest among the memory cells for which the formation process has not yet been performed. A formation method as claimed in claim 3, wherein a first critical voltage of the switching element after performing the formation process is lower than a second critical voltage of the switching element before performing the formation process. A method of forming as claimed in claim 4, wherein the execution comprises: applying a first voltage to a first interconnect corresponding to the selected memory cell; applying a second voltage lower than the first voltage to a second interconnect corresponding to the selected memory cell; and applying a third voltage at a level between the first voltage and the second voltage to all first interconnects except the first interconnect corresponding to the selected memory cell and all second interconnects except the second interconnect corresponding to the selected memory cell. A method of forming a device as claimed in claim 5, wherein a difference between the first voltage and the second voltage is higher than the second threshold voltage. A formation method as claimed in claim 5, wherein a difference between the first voltage and the third voltage and a difference between the third voltage and the second voltage are lower than the first critical voltage. A formation method as claimed in claim 4, wherein the switching element after executing the formation process turns to an on state after applying a voltage higher than the first critical voltage, and turns to an off state after applying a voltage lower than the first critical voltage. A formation method as claimed in claim 8, wherein the switching element before performing the formation process turns to an on state after applying a voltage higher than the second critical voltage, and turns to an off state after applying a voltage lower than the second critical voltage. A forming method as claimed in claim 9, wherein a current flow in the off state of the switching element after executing the forming process is greater than a current flow in the off state of the switching element before executing the forming process. A method of forming as claimed in claim 1, wherein the switching element is a 2-terminal switching element. A method of forming as claimed in claim 1, wherein the memory unit is disposed between a pair of a first interconnect and a second interconnect corresponding to each other. The formation method of claim 1 further includes: After executing the formation procedure on the plurality of memory units, performing a write process and a read process on the plurality of memory units. The formation method of claim 1, wherein the variable resistance element comprises: a first ferromagnetic layer; a second ferromagnetic layer; and a non-magnetic layer interposed between the first ferromagnetic layer and the second ferromagnetic layer. A method of forming as claimed in claim 1, wherein the plurality of memory cells are arranged in a matrix pattern.