TWI784279B - DC-DC conversion circuit and information processing device - Google Patents

Abstract

A DC-DC conversion circuit, which has an input terminal coupled to an input voltage and an output terminal to provide an output voltage, and it includes a power transmission unit to periodically control the input voltage according to a PWM signal Electric energy is transmitted to the output terminal, and a control unit generates the PWM signal according to a feedback voltage and an input sensing current, wherein the feedback voltage is generated according to a ratio of the output voltage, characterized in that: the control unit A transconductance controllable voltage-to-current unit is provided to generate a first sensing current proportional to the product of the input voltage and a load current, and the sum of the first sensing current and the input sensing current is equal to the A second sensing current of an inductor in the power transmission unit enables the control unit to quickly respond to changes in input voltage and load current and adjust the output voltage in real time, thereby meeting the power supply quality requirements of various TDMA application environments.

Description

DC-DC conversion circuit and information processing device

The present invention relates to the related technical field of DC-DC conversion circuit, especially a DC-DC conversion circuit with fast transient response.

Due to the advantages of self-illumination, wide viewing angle, high contrast, low power consumption and high response rate, OLED displays have been widely used in various electronic products, which can be divided into PMOLED displays and AMOLED displays. Please refer to FIG. 1 , which shows a structure diagram of a conventional AMOLED display. As shown in FIG. 1 , a conventional AMOLED display includes: an AMOLED panel 1a, a gate driver module 2a, a source driver module 3a, a display controller 4a, and a power supply unit 5a. The current technology has been able to integrate the display controller 4a, the gate driver module 2a and the source driver module 3a into a single display driver chip. In FIG. 1, the power supply unit 5a is coupled to an external power supply, such as a power supply provided by a lithium battery, so as to provide an operating voltage VDD to the display controller 4a, the gate driver module 2a and the source driver module. group 3a, and provide a light-emitting working voltage ELVDD and a grounding working voltage ELVDD to the AMOLED panel 1a.

FIG. 2 shows a circuit topology diagram of a conventional power supply unit. The power supply unit 5a shown in Figure 1 is a step-up (boost) DC-DC converter, and includes: an input capacitor Cia, an inductor L1a, a first NMOS element Q2a, a first PMOS element Q1a, a A second PMOS element Qsa, a second PMOS element Qca, an operational amplifier A1a, a first voltage dividing resistor Rf1a, a second voltage dividing resistor Rf2a, an input capacitor Coa, an error amplifier A2a, a first resistor Rra, A second resistor Rea, a first capacitor Cra, a second capacitor Cea, a comparator A3a, a current source Ira, an oscillator 51a, an RS flip-flop 52a, and a driving unit 53a. Wherein, the first PMOS element Q1a is a freewheeling element for ensuring that the current _IL of the inductor L1a is continuous.

On the other hand, the first NMOS device Q2a functions as a switching device, and the second PMOS device Qsa functions as a current sensing device. Through the arrangement of the operational amplifier A1a and the second PMOS device Qca, the four-terminal voltages (ie, two drain terminals and two source terminals) of the first PMOS device Q1a and the second PMOS device Qsa will be the same. In such a design, the sampling current Isense transmitted from the second PMOS element Qsa to the switching element S1a is I _L /m, where m=WQ ₁ /WQ _sense . Here, WQ1 refers to the channel width of the _first PMOS device Q1a, and WQ _sense refers to the channel width of the second PMOS device Qsa.

，該誤差放大器A2a 基於該參考電壓V_REF和取自該第一分壓電阻Rf1a與該第二分壓電阻Rf2a的一回授電壓V_FB而輸出一誤差信號Vea至該比較器A3a的負輸入端。同時，該電流源Ira、該第一電容Cra和該第一電阻Rra提供一鋸齒波電壓信號Vramp至該比較器A3a的正輸入端。如此，基於該鋸齒波電壓信號Vramp和該誤差信號Vea，該比較器A3a輸出一比較信號至該RS正反器52a的一第一輸入端(即，R端)，且該振盪器51a提供一時鐘信號CLK至該RS正反器52a的一第二輸入端(即，S端)。最終，該RS正反器52a的輸出端(即，Q端)提供一PWM信號至該驅動單元53a，使該驅動單元53a依據該PWM信號而提供一第一閘極電壓信號至該第一NMOS元件Q2a的閘極端，且同時提供一第二閘極電壓信號至該第一PMOS元件Q1a和該第二PMOS元件Qsa的閘極端。應知道，所述PWM信號的占空比(Duty cycle)由該時鐘信號CLK所決定。 In more detail, the reference voltage

, the error amplifier A2a outputs an error signal Vea to the negative input of the comparator A3a based on the reference voltage V _REF and a feedback voltage V _FB obtained from the first voltage dividing resistor Rf1a and the second voltage dividing resistor Rf2a end. At the same time, the current source Ira, the first capacitor Cra and the first resistor Rra provide a sawtooth voltage signal Vramp to the positive input terminal of the comparator A3a. Thus, based on the sawtooth voltage signal Vramp and the error signal Vea, the comparator A3a outputs a comparison signal to a first input terminal (ie, R terminal) of the RS flip-flop 52a, and the oscillator 51a provides a The clock signal CLK is sent to a second input terminal (ie, S terminal) of the RS flip-flop 52a. Finally, the output terminal (ie, Q terminal) of the RS flip-flop 52a provides a PWM signal to the driving unit 53a, so that the driving unit 53a provides a first gate voltage signal to the first NMOS according to the PWM signal. the gate terminal of the device Q2a, and simultaneously provide a second gate voltage signal to the gate terminals of the first PMOS device Q1a and the second PMOS device Qsa. It should be known that the duty cycle of the PWM signal is determined by the clock signal CLK.

With the hot sales of smart phones, smart watches, smart bracelets, and sports watches, OLED displays have also been widely used. It must be known that mobile electronic devices need to send and receive multiple signals, including GSM signals, Wi-Fi signals and Bluetooth signals. However, the spectrum of wireless communication is limited, so the spectrum allocation of wireless communication is very strict. Interfering with each other during transmission. In order to solve the aforementioned problems, wireless communication engineers have developed various multiple access (Multiple Access) technologies to increase the utilization rate of spectrum, such as: time division multiple access (TDMA), frequency division multiple access (Frequency division multiple access (FDMA) and code division multiple access (Code division multiple access, CDMA).

Please also refer to FIG. 3 , which shows a working timing diagram of an input voltage signal and an output voltage signal of the conventional power supply unit shown in FIG. 2 . It should be noted that, in the case of using TDMA for wireless communication, there is a large difference between the power consumption of the mobile electronic device in a sending interval and the power consumption in a receiving interval. That is, the power consumption used in the transmission period is much larger than the power consumption used in the reception period, resulting in the generation of TDMA noise of a certain frequency. Practical experience shows that TDMA noise will also have adverse effects on the transient response of the voltage stabilizing power supply unit 5a. Therefore, the power drive management of AMOLED display is required to pass the relevant test of TDMA noise. As shown in Figure 3, the test content of TDMA noise is as follows: the input voltage signal Vin will be disturbed every once in a while, so that it jumps up or down by 500mV instantaneously within 10us, and after jumping up (or down) by 500mV , maintain this voltage level for 500us. Practical experience shows that when the aforementioned interference phenomenon occurs, the output voltage signal Vout of the step-up DC-DC converter (that is, the power supply unit 5a) shown in FIG. 2 will correspondingly have a transient downswing ( undershoot) or overshoot, resulting in system instability.

Therefore, industry standards put forward high requirements for step-up DC-DC converters used in mobile electronic devices, which require the aforementioned transient undershoot (undershoot) or overshoot (overshoot) disturbance within 200mA load It must be less than 20mV under normal conditions, and must be less than 60mV under load conditions within 1A.

As shown in FIG. 2 , in the design of a conventional step-up DC-DC converter (that is, the power supply unit 5a), the second resistor Rea and the second capacitor Cea are connected in series with each other, and are coupled to Between the negative input terminal of the comparator A3a and the ground terminal, it is used to compensate the stability of the entire boost loop (Boost loop) under different current load conditions. Unfortunately, as shown in FIG. 2 and FIG. 3 , when the input voltage signal Vin jumps up or down instantaneously, the system cannot immediately adjust the output voltage signal Vout correspondingly. The reason is that the error amplifier A2a outputs an error signal Vea to the comparator based on the reference voltage V _REF and the feedback voltage V _FB obtained from the first voltage dividing resistor Rf1a and the second voltage dividing resistor Rf2a A3a, making the comparator A3a output a comparison signal to the RS flip-flop 52a according to a sawtooth wave voltage signal Vramp and the error signal Vea. Finally, the RS flip-flop 52a outputs a PWM signal to the drive unit 53a according to the comparison signal and a clock signal CLK, so that the drive unit 53a controls the gate terminal of the first NMOS element Q2a, the gate terminal of the first NMOS element Q2a according to the PWM signal. A PMOS device Q1a and the second PMOS device Qsa modulate the output voltage signal Vout.

FIG. 4 shows the timing diagram of the actual measurement operation of the error signal Vea, the sawtooth voltage signal Vramp, and the output voltage signal Vout of the conventional power supply unit shown in FIG. 2 . The conventional step-up DC-DC converter voltage boost compensation loop used in mobile electronic devices cannot Vin jumps up or down instantaneously to make an immediate fast transient response (fast transient response). As shown in FIG. 4, when the input voltage signal Vin has an instantaneous ΔVin, the error signal Vea output by the error amplifier A2a will also have a ΔVea. The larger the value of ΔVea, the slower the adjustment of the duty cycle (Duty cycle) of the PWM signal output by the RS flip-flop 52a in the system's boost loop adjustment, so it appears above the output voltage signal Vout The greater the output voltage change △Vout. For example, the actual measurement data in Figure 4 shows that Vpp of △Vout=130mV.

It can be seen from the above description that there is an urgent need for a new type of DC-DC conversion circuit in this field.

The main purpose of the present invention is to provide a DC-DC conversion circuit, which basically includes an input capacitor, an inductor, a current source, a switching element, a freewheeling element, an output capacitor, a current sensing unit, a voltage A sensing unit and a control unit. In particular, in the present invention, a current pull-down unit is added in the DC-DC conversion circuit, which is coupled to the input end of the circuit, and coupled to the control unit and the current sensing unit at the same time. In such a design, when the input voltage signal has an input voltage variation due to the influence of TDMA noise, a feed-forward pull-down current of the current pull-down unit correspondingly has a pull-down current variation, so that the feed-forward adjustment is made by The output terminal of the circuit returns the value of a sensing current of the control unit, so that the control unit can generate a fast transient response immediately, so as to adjust the output adaptively before the feedback loop of the circuit completes the compensation for the output voltage signal Voltage signals to meet the TDMA test requirements in various application environments.

To achieve the above object, the present invention proposes an embodiment of the DC-DC conversion circuit, which includes: a circuit input terminal coupled to an input voltage signal; an input capacitor with a first terminal and a second terminal respectively coupled to the circuit input terminal and a ground terminal; an inductance coupled to the first terminal of the input capacitor with a first terminal; a first NMOS element coupled to a drain terminal and a source terminal respectively a second terminal of the inductor and the ground terminal; A first PMOS element, with a drain end coupled to the drain end of the first NMOS element; an output capacitor, with a first end and a second end respectively coupled to a source end of the first PMOS element and the ground terminal; a circuit output terminal coupled to the first terminal of the output capacitor for transmitting an output voltage signal; a current sensing unit having a drain terminal coupled to the first NMOS element and the A first end of the drain end of the first PMOS element, a second end coupled to a gate end of the first PMOS element, a third end coupled to the source end of the first PMOS element, and a a fourth terminal; a voltage sensing unit having a first terminal and a second terminal, and the first terminal is coupled to the first terminal of the output capacitor and the third terminal of the current sensing unit; a control A unit having a first terminal coupled to the second terminal of the voltage sensing unit, a second terminal, a third terminal coupled to a gate terminal of the first NMOS element, and coupled to the current sensing unit The second terminal of the unit and the fourth terminal, a fifth terminal, and a sixth terminal of the gate terminal of the first PMOS element; a current source, with a first terminal coupled to the input capacitor The first end and the first end of the inductor, and a second end coupled to the sixth end of the control unit; and a current pull-down unit, having the first end coupled to the circuit input end and the input capacitor. a first end of one end, and a second end coupled to the fifth end of the control unit and the second end of the voltage sensing unit at the same time, for generating a feedforward according to the input voltage signal pull-down current; wherein, the control unit receives a feedback voltage transmitted by the voltage sensing unit through the first terminal, receives a reference voltage through the second terminal, and receives the voltage through the fifth terminal. A sense current transmitted by the current sensing unit, and a current signal transmitted by the current source is received by the sixth terminal thereof, so as to transmit a first gate voltage signal to the first gate voltage signal by the third terminal thereof the gate terminal of the NMOS element, and transmit a second gate voltage signal to the gate terminal of the first PMOS element and the second terminal of the current sensing unit through the fourth terminal; Wherein, when the input voltage signal has an input voltage variation, the feed-forward pull-down current correspondingly has a pull-down current variation, so that the value of the sensing current is adjusted in a feed-forward manner, thereby adjusting the The output of the first gate voltage signal and the second gate voltage signal improves the fast transient response of the control unit 14 .

In one embodiment, the current pull-down unit includes an operational transconductance amplifier (Operational Transconductance Amplifier, OTA), which has a positive input terminal, a negative input terminal and an output terminal, wherein the positive input terminal serves as the current pull-down unit The first terminal of the negative input terminal is coupled to the ground terminal, and the output terminal serves as the second terminal of the current pull-down unit.

In one embodiment, the current sensing unit includes: a second PMOS element, with a drain terminal as the first terminal of the current sensing unit and a gate terminal as the first terminal of the current sensing unit. Two terminals; an operational amplifier having a positive input terminal, a negative input terminal and an output terminal, wherein the positive input terminal is coupled to a source terminal of the second PMOS element, and the negative input terminal is used as the current sensing unit The third terminal of the second NMOS element; and a second NMOS element, which is coupled to the positive input terminal of the operational amplifier and the source terminal of the second PMOS element at the same time with a drain terminal, and is coupled to the operational amplifier with a gate terminal. The output terminal, and a source terminal thereof is used as the fourth terminal of the current sensing unit.

In one embodiment, the voltage sensing unit includes: a first voltage dividing resistor, a first end of which is coupled to the first end of the output capacitor and the third end of the current sensing unit; a first end Two voltage-dividing resistors, one first end of which is coupled to the second end of the first voltage-dividing resistor, and one second end of which is coupled to the ground end; wherein, the first of the first voltage-dividing resistor Terminal serves as the first terminal of the voltage sensing unit, and a common point between the first voltage dividing resistor and the second voltage dividing resistor serves as the second terminal of the voltage sensing unit.

In one embodiment, the control unit includes: An error amplifier having a positive input terminal, a negative input terminal and an output terminal; wherein, the positive input terminal and the negative input terminal of the error amplifier serve as the first terminal and the second terminal of the control unit respectively, Thereby receiving the feedback voltage and the reference voltage respectively, so that the error amplifier generates an error signal according to the feedback voltage and the reference voltage; a comparator has a positive input terminal, a negative input terminal and an output terminal; wherein, the negative input terminal of the comparator is coupled to the output terminal of the error amplifier, and the positive input terminal of the comparator is coupled to the sixth terminal of the control unit; a first capacitor, with its A first terminal is coupled to the positive input terminal of the comparator and the sixth terminal of the control unit, and a second terminal is coupled to the fifth terminal of the control unit; a first resistor, with A first end of which is coupled to the second end of the first capacitor, and a second end thereof is coupled to the ground end; a switch element has a channel, and one end of the channel is simultaneously coupled to the comparator positive input end, the sixth end of the control unit and the first end of the first capacitor, and the other end of the channel is coupled to the second end of the first capacitor and the fifth end of the control unit terminal; the switching element is controlled by a reset signal to enable/close the channel; a second resistor, with a first terminal thereof coupled to the output terminal of the error amplifier and the negative input of the comparator end; a second capacitor, with a first end coupled to a second end of the second resistor, and a second end coupled to the ground end; an RS flip-flop, with a first input end, a second input terminal and an output terminal, wherein the first input terminal is coupled to the output terminal of the comparator, and the second input terminal is coupled to a clock signal transmitted from an oscillator; and a driving unit having An input terminal, a first output terminal and a second output terminal, wherein the input terminal is coupled to the output terminal of the RS flip-flop, and the first output terminal and the second output terminal are respectively used as the control unit The third end and the fourth end of .

In one embodiment, the current signal is a sawtooth wave current signal, the first terminal of the first capacitor generates a sawtooth wave voltage signal according to the current signal, and the comparator uses the positive output The input terminal and the negative input terminal receive the sawtooth wave voltage signal and the error signal respectively, so that the output terminal transmits a comparison signal to the first input terminal of the RS flip-flop, so that the RS flip-flop Send a PWM signal to the drive unit through the output terminal.

In one embodiment, the operational transconductance amplifier (OTA) further includes a digital programming terminal, and has a digitally programmable function (digitally programmable).

In one embodiment, the DC-DC conversion circuit of the present invention further includes: a load current detection unit, coupled between the output terminal of the circuit and the third terminal of the current sensing unit, for detecting a load current, thereby correspondingly generating a load terminal voltage; and a transconductance adjustment unit having a first terminal and a second terminal, wherein the first terminal is coupled to the load terminal voltage transmitted by the load current detection unit , and the second terminal is coupled to the digital programming terminal of the operational transconductance amplifier; wherein, according to the load terminal voltage, the transconductance adjustment unit transmits a digital signal to the digital programming terminal, so that the operational transconductance amplifier A transconductance is adjusted, thereby adjusting the variation of the pull-down current.

According to the above description, the present invention further proposes a DC-DC conversion circuit, which has an input end for coupling an input voltage and an output end for providing an output voltage, and it includes an electric energy transmission unit for a PWM signal controlling to transmit the power of the input voltage to the output terminal periodically, and a control unit to generate the PWM signal according to a feedback voltage and an input sense current, wherein the feedback voltage is proportional to the output voltage generation, which is characterized in that: the control unit has a transconductance controllable voltage-to-current unit to generate a first sensing current proportional to the input voltage and a load current, and the first sensing current is proportional to the input The sum of the sensing currents is equal to a second sensing current of an inductor in the power transmission unit.

The present invention also provides an information processing device, which has a central processing unit and a flat-panel display, and the flat-panel display includes a flat display panel, a gate driver module, a source driver module, a display controller, and a A power supply unit; it is characterized in that the power supply unit includes the DC-DC conversion circuit of the present invention as mentioned above, and in a possible embodiment, the information processing device It can be a smartphone, smart watch, smart bracelet, tablet, laptop, all-in-one computer, or access control device.

1a: AMOLED panel

2a: Gate driver module

3a: Source driver module

4a: Display Controller

5a: Power supply unit

Cia: input capacitance

Coa: output capacitance

Cra: the first capacitance

Cea: second capacitor

L1a: Inductance

Q2a: The first NMOS element

Q1a: The first PMOS component

Qca: the second PMOS element

Qsa: the second PMOS element

A1a: Operational amplifier

A2a: Error Amplifier

A3a: Comparator

Rf1a: the first voltage divider resistor

Rf2a: the second voltage divider resistor

Rra: the first resistance

Rea: the second resistance

Ira: current source

S1a: switching element

51a: Oscillator

52a: RS flip-flop

53a: Drive unit

1: DC-DC conversion circuit

10: Circuit input terminal

11: Circuit output terminal

12: Current sensing unit

121: first end

122: second end

123: third end

124: fourth end

13: Voltage sensing unit

131: first end

132: second end

14: Control unit

141: first end

142: second end

143: third end

144: fourth end

145: fifth end

146: sixth end

14OC: Oscillator

14RS: RS flip-flop

14DR: drive unit

15: Current pull-down unit

151: first end

152: second end

153: Digital programming terminal

16: Current source

17: Transduction adjustment unit

171: first end

172: second end

19: Class load current detection unit

Ci: input capacitance

Co: output capacitance

Cr: first capacitance

Ce: second capacitance

L1: inductance

Q2: The first NMOS element

Q1: The first PMOS component

Qc: the second PMOS element

Qs: The second PMOS element

Ap: Operational Transconductance Amplifier

A1: Operational amplifier

A2: Error amplifier

A3: Comparator

Rf1: the first voltage divider resistor

Rf2: the second voltage divider resistor

Rr: the first resistance

Re: second resistance

S1: switching element

Fig. 1 is a structural diagram of a known AMOLED display; Fig. 2 is a circuit topology diagram of a known power supply unit; Fig. 3 is an input voltage signal and an output of the known power supply unit shown in Fig. 2 The working timing diagram of voltage signal; Fig. 4 is the working timing diagram of the actual measurement of error signal, sawtooth wave voltage signal and output voltage signal of the conventional power supply unit shown in Fig. 2; Fig. 5 is a kind of DC- A block diagram of a first embodiment of the DC conversion circuit; Fig. 6 is a circuit topology diagram of the first embodiment of the DC-DC conversion circuit of the present invention; Fig. 7 is the DC-DC of the present invention shown in Fig. 6 The actual measurement work timing diagram of the error signal, sawtooth wave voltage signal and output voltage signal of the first embodiment of the conversion circuit; FIG. 8 is the first embodiment of the DC-DC conversion circuit of the present invention shown in FIG. 6 in different The actual measurement work timing diagram of the output voltage signal under the load current; Fig. 9 is a block diagram of a second embodiment of a DC-DC conversion circuit of the present invention; Fig. 10 is the first embodiment of the DC-DC conversion circuit of the present invention The circuit topological structure diagram of the second embodiment; and FIG. 11 is an actual measurement working timing diagram of the output voltage signal of the second embodiment of the DC-DC conversion circuit of the present invention shown in FIG. 10 under different load currents.

In order to enable your examiners to further understand the structure, features, purpose, and advantages of the present invention, drawings and detailed descriptions of preferred embodiments are hereby attached.

The principle of the DC-DC conversion circuit of the present invention is: (1) using a power transmission unit to periodically transmit the power of an input voltage to an output terminal according to the control of a PWM signal; (2) using a control unit to generate the PWM signal according to a feedback voltage and an input sensing current, wherein the feedback voltage is generated in proportion to an output voltage of the output terminal; and (3) the control unit has A transconductance controllable voltage-to-current unit to generate a first sensing current proportional to the input voltage and a load current, and the sum of the first sensing current and the input sensing current is equal to the power transmission unit A second sense current within one inductor.

According to this, when the input voltage changes due to TDMA noise interference, for example, when it becomes high/low, the first sensing current will increase/decrease accordingly, so that before the second sensing current has not changed, the The input sensing current becomes smaller/larger, so as to drive the duty cycle of the PWM signal smaller/larger so that the control unit can quickly generate a transient response, so as to ensure that the ripple of the output voltage is smaller than a required value; and when When the load current increases/hour, the second sensing current of the inductor will increase/decrease at the same time, and the first sensing current will increase/decrease accordingly, and due to the change of the second sensing current The amount will be greater than the change amount of the first sensing current, therefore, the input sensing current will increase/decrease accordingly, so as to drive the duty cycle of the PWM signal to increase/decrease so that the control unit can quickly generate a transient state response to ensure that the output voltage ripple is less than the required value.

first embodiment

FIG. 5 shows a block diagram of a first embodiment of a DC-DC conversion circuit of the present invention. As shown in Figure 5, the DC-DC conversion circuit 1 of the present invention is a boost DC-DC conversion circuit, which can be used in a mobile electronic device as a (stable) power supply unit , thereby converting the input voltage provided by the lithium battery into an output voltage, thereby providing a flat display panel (such as an AMOLED display panel) and related electronic chips of the mobile electronic device. It can be seen from FIG. 5 that the DC-DC conversion circuit 1 of the present invention includes: a circuit input terminal 10 coupled to an input voltage signal Vin, an input capacitor Ci, an inductor L1, a first NMOS element Q2 as a switching element, A first PMOS element Q1 as a freewheeling element, an output capacitor Co, a circuit output terminal 11, a current sensing unit 12, a voltage sensing unit 13, a control unit 14, a current source 16, and a current Pull down unit 15.

According to the design of the present invention, the input capacitor Ci is respectively coupled to the circuit input terminal 10 and a ground terminal of the DC-DC conversion circuit 1 with a first terminal and a second terminal thereof, and the inductance L1 is coupled with a first terminal thereof One end is coupled to the first end of the input capacitor Ci. It should be noted that the first NMOS element Q2 is used as a switching element of the boost DC-DC converter 1, and its drain terminal and a source terminal are respectively coupled to a second terminal of the inductor L1 and the end of the land. On the other hand, the first PMOS device Q1 is used as a freewheeling device to ensure that the current _IL of the inductor L1 is continuous, and a drain terminal thereof is coupled to the drain terminal of the first NMOS device Q2 . Moreover, a first end and a second end of the output capacitor Co are respectively coupled to a source end of the first PMOS element Q1 and the ground end, and the circuit output end 11 of the DC-DC converter 1 is coupled to The first end of the output capacitor Co is connected to transmit an output voltage signal Vout.

In more detail, the current sensing unit 12, the voltage sensing unit 13 and the control unit 14 are a feedback compensation system of the DC-DC conversion circuit 1, wherein the current sensing unit 12 is used to automatically The circuit output terminal 11 detects a sensing current Isense and transmits it to the control unit 14, and the voltage sensing unit 13 is used to detect a sensing voltage from the circuit output terminal 11 so as to transmit a feedback voltage V _FB to the control unit Unit 14. As shown in FIG. 5 , the current sensing unit 12 has a first terminal 121 , a second terminal 122 , a third terminal 123 , and a fourth terminal 124 . The first terminal 121 is coupled to the drain terminal of the first NMOS device Q2 and the drain terminal of the first PMOS device Q1 at the same time, the second terminal 122 is coupled to a gate terminal of the first PMOS device Q1, and the The third terminal 123 is coupled to the source terminal of the first PMOS device Q1. On the other hand, the voltage sensing unit 13 has a first end 131 and a second end 132, wherein the first end 131 is coupled to the first end of the output capacitor Co and the current sensing unit 12. The third end 123 .

According to the above description, the control unit 14 has a first end 141 , a second end 142 , a third end 143 , a fourth end 144 , a fifth end 145 , and a sixth end 146 . As shown in FIG. 5, the first end 141 is coupled to the second end 132 of the voltage sensing unit 13, the third end 143 is coupled to a gate terminal of the first NMOS element Q2, and the fourth end 144 The second terminal 122 of the current sensing unit 12 is coupled to the gate terminal of the first PMOS device Q1. It is supplemented that the current source 16 is coupled to the first terminal of the input capacitor Ci and the first terminal of the inductor L1 with a first terminal thereof, and is coupled to the control unit 14 with a second terminal thereof. The sixth end 146 . In the DC-DC conversion circuit 1 , the current source 16 transmits a current signal to the sixth terminal 146 of the control unit 14 , and the current signal is a sawtooth current signal Iramp.

In the case that the mobile electronic device does not generate TDMA noise, the control unit 14 receives a feedback voltage V FB transmitted by the voltage sensing unit 13 through its first terminal 141 , and receives a feedback voltage V _FB transmitted by its second terminal 142 . A reference voltage V _REF receives an input sense current Isense_in through the fifth terminal 145 thereof, the input sense current Isense_in is a sense current Isense transmitted by the current sense unit 12 and the first current pull-down unit 15 The differential current of a generated feed-forward pull-down current Isink, and receives a sawtooth current signal Iramp transmitted by the current source 16 with its sixth end 146, thereby transmitting a first a gate voltage signal to the gate terminal of the first NMOS device Q2, and transmits a second gate voltage signal to the gate terminal of the first PMOS device Q1 and the current sensing unit through the fourth terminal 144 thereof The second terminal 122 of 12 is used to stabilize and regulate an output voltage signal Vout transmitted by the output terminal 11 of the circuit, so that the DC-DC conversion circuit 1 can stably supply power to the mobile electronic device A flat display panel (such as an AMOLED display panel) and related electronic chips.

It is worth noting that when the mobile electronic device has TDMA noise, as shown in Figure 3, the input voltage signal Vin will be disturbed every once in a while, so that it jumps up or down by 500mV instantaneously within 10us, and in After jumping up (or down) by 500mV, maintain this voltage level for 500us. When the aforementioned interference phenomenon occurs, the output voltage signal Vout of the DC-DC converter 1 shown in FIG. Stablize.

Therefore, the present invention adds a current pull-down unit 15 in the DC-DC conversion circuit 1 . As shown in FIG. 5, the current pull-down unit 15 has a first end 151 and a second end 152, wherein the first end 151 is coupled to the circuit input end 10 and the first end of the input capacitor Ci, and The second terminal 152 is coupled to the fifth terminal 145 of the control unit 14 and the second terminal 132 of the voltage sensing unit 13 at the same time. In the DC-DC conversion circuit 1 , the first current pull-down unit 15 is used to generate a first feed-forward pull-down current Isink1 according to the input voltage signal Vin to affect the current value of the input sense current Isense_in.

Continuing to refer to FIG. 6 , it shows a circuit topology diagram of the first embodiment of the DC-DC conversion circuit of the present invention. In one embodiment, the current pull-down unit 15 includes an operational transconductance amplifier (Operational Transconductance Amplifier, OTA) Ap, which has a positive input terminal, a negative input terminal and an output terminal, wherein the positive input terminal is used as the The negative input end of the first end 151 of the current pull-down unit 15 is coupled to the ground end, and the output end serves as the second end 152 of the current pull-down unit 15 . In case the mobile electronic device has TDMA noise, the input voltage signal Vin will have an input voltage variation ΔVin; at this time, the feed-forward pull-down current Isink correspondingly has a pull-down current variation ΔIsink=gm*ΔVin, so as to adjust the inductance received by the control unit 14 through its fifth terminal 145 in a feed-forward manner. Measure the value of the current Isense_in, so that the control unit 14 adjusts the PWM signal and the PWMB signal to produce a fast transient response, so that before the feedback loop (feedback compensation system) of the circuit completes the compensation for the output voltage signal Vout, Adaptively adjust the output voltage signal Vout. In short, with the configuration of the current pull-down unit 15, the fastline transient response of the feedback loop (feedback compensation system) of the DC-DC conversion circuit 1 is significantly improved. It should be known that gm is the transconductance value of the operational transconductance amplifier Ap.

As shown in FIG. 6 , in one embodiment, the current sensing unit 12 includes: a second PMOS device Qs, an operational amplifier A1 and a second PMOS device Qc. Wherein, the second PMOS element Qs uses a drain terminal as the first terminal 121 of the current sensing unit 12 , and a gate terminal as the second terminal 122 of the current sensing unit 12 . Moreover, the operational amplifier A1 has a positive input terminal, a negative input terminal and an output terminal, wherein the positive input terminal is coupled to a source terminal of the second PMOS element Qs, and the negative input terminal serves as the current sensing unit The third end 123 of 12. On the other hand, a drain terminal of the second PMOS element Qc is simultaneously coupled to the positive input terminal of the operational amplifier A1 and the source terminal of the second PMOS element Qs, and a gate terminal is coupled to the operational amplifier A1. The output terminal of the current sensing unit 12 uses a source terminal as the fourth terminal 124 of the current sensing unit 12 .

Moreover, in an embodiment, the voltage sensing unit 13 is composed of a first voltage dividing resistor Rf1 and a second voltage dividing resistor Rf1. As shown in FIG. 6 , a first end of the first voltage dividing resistor Rf1 is coupled to the first end of the output capacitor Co and the third end 123 of the current sensing unit 12 . On the other hand, a first terminal of the second voltage dividing resistor Rf2 is coupled to the second terminal of the first voltage dividing resistor Rf1, and a second terminal thereof is coupled to the ground terminal. It can be seen from FIG. 6 that the first terminal of the first voltage dividing resistor Rf1 is used as the first terminal 131 of the voltage sensing unit 13, and the connection between the first voltage dividing resistor Rf1 and the second voltage dividing resistor Rf2 is A common contact is used as the second terminal 132 of the voltage sensing unit 13 .

To further illustrate, the control unit 14 includes: an error amplifier A2, a comparator A3, a first capacitor Cr, a first resistor Rr, a switching element S1, a second resistor Re, a second capacitor Ce, a RS flip-flop 14RS, and a driving unit 14DR. Wherein, the error amplifier A2 has a positive input terminal, a negative input terminal and an output terminal. As shown in FIG. 6, the positive input terminal and the negative input terminal of the error amplifier A2 serve as the first terminal 141 and the second terminal 142 of the control unit 14 respectively, so as to respectively receive the feedback voltage V _FB and the The reference voltage V _REF makes the error amplifier A2 generate an error signal Vea according to the feedback voltage V _FB and the reference voltage V _REF . On the other hand, the comparator A3 has a positive input terminal, a negative input terminal and an output terminal, wherein the negative input terminal of the comparator A3 is coupled to the output terminal of the error amplifier A2, and the comparator A3 The positive input terminal is coupled to the sixth terminal 146 of the control unit 14 .

Moreover, the first capacitor Cr is coupled to the positive input terminal of the comparator A3 and the sixth terminal 146 of the control unit 14 with its first terminal, and is coupled to the control unit 14 with its second terminal. Fifth end 145 . On the other hand, a first end of the first resistor Rr is coupled to the second end of the first capacitor Cr, and a second end is coupled to the ground end. In such a design, after the current source 16 generates a sawtooth current signal Iramp to the sixth terminal 146 of the control unit 14 according to the input voltage signal Vin, the sawtooth current signal Iramp is immediately at the first capacitor Cr. The first terminal forms a sawtooth voltage signal Vramp, so that the comparator A3 receives the sawtooth voltage signal Vramp and the error signal Vea through its positive input terminal and negative input terminal respectively.

According to the above description, the switch element S1 has a channel, and one end of the channel is simultaneously coupled to the positive input end of the comparator A3, the sixth end 146 of the control unit 14, and the first capacitor Cr. end, and the other end of the channel is coupled to the second end of the first capacitor Cr and the fifth end 145 of the control unit 14: the switching element S1 is controlled by a reset signal V _Reset to enable/disable its said channel. And, as shown in FIG. 6 , the second resistor Re is coupled to the output terminal of the error amplifier A2 and the negative input terminal of the comparator A3 through a first terminal thereof, and the second capacitor Ce is coupled to the negative input terminal of the comparator A3 through a first terminal thereof. The first terminal is coupled to a second terminal of the second resistor Re, and a second terminal thereof is coupled to the ground terminal.

Further, the RS flip-flop 14RS has a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to the output terminal of the comparator A3, and the second input terminal is coupled to Receive a clock signal CLK from an oscillator 14OC. Furthermore, the driving unit 14DR has an input terminal, a first output terminal and a second output terminal, wherein the input terminal is coupled to the output terminal of the RS flip-flop 14RS, and the first output terminal and the second output terminal The two output terminals serve as the third terminal 143 and the fourth terminal 144 of the control unit 14 respectively.

As shown in FIG. 6, based on the sawtooth voltage signal Vramp and the error signal Vea, the comparator A3 outputs a comparison signal to the first input terminal (ie, R terminal) of the 14RS flip-flop 52, and the oscillator 14OC provides a clock signal CLK to the second input terminal (ie, S terminal) of the RS flip-flop 14RS. Finally, the output terminal (ie, Q terminal) of the RS flip-flop 14RS provides a PWM signal to the driving unit 14DR, wherein the period of the PWM signal is determined by the clock signal CLK. Further, the driving unit 14DR provides a first gate voltage signal (ie, PWM signal) to the gate terminal of the first NMOS element Q2 according to the PWM signal, and simultaneously provides a second gate voltage signal (ie, PWMB signal) to the gate terminals of the first PMOS element Q1 and the second PMOS element Qs.

FIG. 7 shows the timing diagram of the actual measurement operation of the error signal Vea, the sawtooth voltage signal Vramp and the output voltage signal Vout of the DC-DC conversion circuit of the present invention shown in FIG. 6 . When the mobile electronic device has TDMA noise, the input voltage signal Vin will have an input voltage variation ΔVin; at this time, the feed-forward pull-down current Isink correspondingly has a pull-down current variation ΔIsink=gm*△ Vin makes the level of the sawtooth voltage signal Vramp change correspondingly by gm*ΔVin* R _r , thereby ensuring that the error signal Vea output by the error amplifier A2 does not change as much as possible. Therefore, under the condition that the reference voltage V _REF remains unchanged, the error signal Vea does not change as much as possible, which means that the change of the feedback voltage V _FB is very small, that is, the output voltage signal Vout has an output voltage change Δ The value of Vout changes very little accordingly. The actual measurement data in FIG. 7 shows that Vpp=30mV of the output voltage variation ΔVout.

Therefore, after comparing the measurement data of FIG. 7 and FIG. 4, it should be understood that a current pull-down unit 15 is added in the DC-DC conversion circuit 1, and it is coupled to the circuit input terminal 10, and at the same time coupled After connecting the control unit 14 and the current sensing unit 13, when the input voltage signal Vin has an input voltage variation ΔVin due to the influence of TDMA noise, a feed-forward pull-down current Isink of the current pull-down unit 15 is Correspondingly, there is a pull-down current variation ΔIsink, the value of an input sense current Isense_in passed into the control unit 14 from the fifth terminal 145, so that the control unit 14 can immediately generate a fast transient response, so that in the circuit Before the feedback loop (feedback compensation system) completes the compensation for the output voltage signal Vout, the output voltage signal Vout is adaptively adjusted to effectively ensure that the output voltage variation △Vout is less than or equal to 30mV.

second embodiment

It can be seen from the above description that when the input voltage signal Vin is affected by TDMA noise and there is an instantaneous input voltage variation ΔVin, the first embodiment of the DC-DC conversion circuit 1 of the present invention can instantly and quickly Control the variation of input voltage △Vout within 30mV. However, it must be noted that the aforesaid fast transient response is realized when the DC-DC conversion circuit 1 of the present invention operates under a fixed load. To explain in more detail, the variation gm*ΔVin* R _r of the level of the sawtooth voltage signal Vramp is used to ensure that the error signal Vea output by the error amplifier A2 does not change as much as possible. However, when the load state changes, the aforementioned variation gm*ΔVin* R _r cannot effectively compensate the change caused by the load current to the value of the error signal Vea. FIG. 8 is a timing diagram of actual measurement of output voltage signals of the first embodiment of the DC-DC conversion circuit of the present invention shown in FIG. 6 under different load currents. As shown in the actual measurement data in Figure 8, when the load current is 1mA, 300mA, and 600mA, the variation Vpp of the output voltage signal Vout of the first embodiment of the DC-DC conversion circuit 1 of the present invention also changes accordingly. (20mV→22mV→50mV). Therefore, the actual measurement data proves that when the load state changes, the above-mentioned variation gm*△Vin* R _r cannot effectively compensate the change caused by the load current to the value of the error signal Vea, resulting in a variation of the output voltage signal Vout Cannot be controlled within 30mV.

Based on the aforementioned reasons, the present invention also proposes a second embodiment of a DC-DC conversion circuit of the present invention. FIG. 9 shows a block diagram of a second embodiment of a DC-DC conversion circuit of the present invention. After comparing FIG. 9 with FIG. 5 , it can be easily known that the second embodiment of the DC-DC conversion circuit 1 of the present invention further includes: a transconductance adjustment unit 17 and a load current detection unit 19 . FIG. 10 is a circuit topology diagram of the second embodiment of the DC-DC conversion circuit of the present invention. In the second embodiment, the operational transconductance amplifier Ap used as the current pull-down unit 15 further includes a digital programming terminal 153 and has a digitally programmable function (digitally programmable). In other words, by sending a digital signal to the digital programming terminal 153 , the value of the transconductance gm of the operational transconductance amplifier Ap can be adjusted.

As shown in FIG. 10 , the load current detection unit 19 is coupled between the circuit output terminal 11 and the third terminal 123 of the current sensing unit 12 to detect a load current, thereby correspondingly generating a load terminal Voltage. On the other hand, the transconductance adjustment unit 17 has a first end 171 and a second end 172, which The first terminal 171 is coupled to the load terminal voltage transmitted by the load current detection unit 19 , and the second terminal 172 is coupled to the digital programming terminal 153 of the operational transconductance amplifier.

According to the design of the present invention, the function of the load current detection unit 19 is to convert the load current I _Load into a load terminal voltage V _CTRL = α ^* I _Load , and the function of the transconductance adjustment unit 17 is similar to an analog/digital converter , for generating a digital signal D _CTRL <X:0> based on the load terminal voltage V _CTRL . In the second embodiment, the current pull-down unit 15 is a digitally programmable operational transconductance amplifier (Operational Transconductance Amplifier, OTA) Ap. Therefore, by transmitting the digital signal D _CTRL <X: 0> to the digital programming terminal 153 of the operational transconductance amplifier Ap, the transconductance gm of the operational transconductance amplifier Ap will be adjusted correspondingly, in this way Adjust the pull-down current change amount △Isink=gm*△Vin under the feed-forward pull-down current Isink. With such a design, the second embodiment of the DC-DC conversion circuit 1 of the present invention can still quickly compensate the output voltage signal Vout even when the load current fluctuates, thereby effectively controlling the variation of the output voltage ΔVout. value.

FIG. 11 is a timing diagram of actual measurement of output voltage signals of the second embodiment of the DC-DC conversion circuit of the present invention shown in FIG. 10 under different load currents. As shown in the actual measurement data in FIG. 11 , when the load current is 1mA, 300mA, and 600mA, the variation Vpp of the output voltage signal Vout of the second embodiment of the DC-DC conversion circuit 1 of the present invention also changes accordingly. (9mV→15mV→25mV). It is worth noting that since the second embodiment further includes a transconductance adjustment unit 17 and a load current detection unit 19, the actual measurement data proves that the second embodiment of the DC-DC conversion circuit 1 of the present invention has a higher performance than the load current detection unit 19. In the case of fluctuations, the output voltage signal Vout can still be quickly compensated, so as to effectively control the value of the output voltage variation ΔVout.

Thus, the above has completely and clearly described a DC-DC conversion circuit of the present invention; and, through the above, it can be known that the present invention has the following advantages:

(1) The present invention discloses a DC-DC conversion circuit, which basically includes an input capacitor, an inductor, a current source, a switching element, a freewheeling element, an output capacitor, a current sensing unit, and a voltage sensor Measuring unit, and a control unit. In particular, in the present invention, a current pull-down unit is added in the DC-DC conversion circuit, which is coupled to the input end of the circuit, and coupled to the control unit and the current sensing unit at the same time. So designed, when the input voltage signal is affected by TDMA noise When there is a variation of the input voltage, a feed-forward pull-down current of the current pull-down unit has a corresponding variation of the pull-down current, so as to adjust in a feed-forward manner a sensing current sent back from the output end of the circuit to the control unit. value, enabling the control unit to produce a fast transient response immediately, thereby adaptively adjusting the output voltage signal before the feedback loop of the circuit completes compensation for the output voltage signal.

(2) The present invention also discloses a flat-panel display, which includes a flat-panel display panel, a gate driver module, a source driver module, a display controller, and a power supply unit; it is characterized in that the power supply unit includes As mentioned above, the DC-DC conversion circuit of the present invention.

(3) The present invention also discloses an information processing device, which has a central processing unit and the flat-panel display of the present invention as described above. Moreover, the information processing device can be an electronic device selected from the group consisting of a smart phone, a smart watch, a smart bracelet, a tablet computer, a notebook computer, an all-in-one computer, and an access control device.

It must be emphasized that what is disclosed in the above-mentioned case is a preferred embodiment, and all partial changes or modifications derived from the technical ideas of this case and easily deduced by those familiar with the technology are all inseparable from the patent of this case. category of rights.

To sum up, regardless of the purpose, means and efficacy of this case, it shows that it is very different from the conventional technology, and its first invention is practical, and it does meet the patent requirements of the invention. I implore your review committee to understand it clearly and grant a patent as soon as possible. Society is for the Most Prayer.

1: DC-DC conversion circuit

10: Circuit input terminal

11: Circuit output terminal

12: Current sensing unit

121: first end

122: second end

123: third end

124: fourth end

13: Voltage sensing unit

131: first end

132: second end

14: Control unit

141: first end

142: second end

143: third end

144: fourth end

145: fifth end

146: sixth end

15: Current pull-down unit

151: first end

152: second end

16: Current source

Ci: input capacitance

Co: output capacitance

L1: inductance

Q2: The first NMOS element

Q1: The first PMOS component

Claims (10)

A DC-DC conversion circuit, comprising: a circuit input terminal, coupled to an input voltage signal; an input capacitor, with a first terminal and a second terminal respectively coupled to the circuit input terminal and a ground terminal; an inductor , with a first end coupled to the first end of the input capacitor; a first NMOS element, with a drain end and a source end respectively coupled to a second end of the inductor and the ground end; a first NMOS element A PMOS element, with a drain end coupled to the drain end of the first NMOS element; an output capacitor, with a first end and a second end, respectively coupled to a source end of the first PMOS element and the first NMOS element a ground end; a circuit output end coupled to the first end of the output capacitor for transmitting an output voltage signal; a current sensing unit having the drain end coupled to the first NMOS element and the first end at the same time a first end of the drain end of the PMOS element, a second end coupled to a gate end of the first PMOS element, a third end coupled to the source end of the first PMOS element, and a fourth end terminal; a voltage sensing unit having a first terminal and a second terminal, and the first terminal is coupled to the first terminal of the output capacitor and the third terminal of the current sensing unit; a control unit, It has a first terminal coupled to the second terminal of the voltage sensing unit, a second terminal, a third terminal coupled to a gate terminal of the first NMOS element, and coupled to the current sensing unit. The second terminal and a fourth terminal, a fifth terminal, and a sixth terminal of the gate terminal of the first PMOS element; a current source, with a first terminal coupled to the first terminal of the input capacitor end and the first end of the inductor, and a second end coupled to the sixth end of the control unit; and a current pull-down unit, having the first end coupled to the circuit input end and the input capacitor a first end, and has a second end coupled to the fifth end of the control unit and the second end of the voltage sensing unit at the same time, for generating a feed-forward pull-down current according to the input voltage signal ; Wherein, the control unit receives a feedback voltage transmitted by the voltage sensing unit with its first end, receives a reference voltage _F with its second end, and receives the current with its fifth end A sensing current transmitted by the sensing unit, and receiving a current signal transmitted by the current source through the sixth end thereof, so as to transmit a first gate voltage signal to the first NMOS through the third end thereof The gate terminal of the element, and transmits a second gate voltage signal to the gate terminal of the first PMOS element and the second terminal of the current sensing unit through the fourth terminal; wherein, when the input When the voltage signal has an input voltage variation, the feed-forward pull-down current correspondingly has a pull-down current variation, whereby the value of the sensing current is adjusted in a feed-forward manner, thereby adjusting the first gate output by the control unit The pole voltage signal and the second gate voltage signal improve the fast transient response of the control unit. The DC-DC conversion circuit as described in Claim 1, wherein the current pull-down unit includes an operational transconductance amplifier having a positive input terminal, a negative input terminal and an output terminal, wherein the positive input terminal serves as the current The first terminal of the pull-down unit, the negative input terminal is coupled to the ground terminal, and the output terminal is used as the second terminal of the current pull-down unit. The DC-DC conversion circuit as described in claim 1, wherein the current sensing unit includes: a second PMOS element, with a drain end as the first end of the current sensing unit, and a gate The terminal serves as the second terminal of the current sensing unit; an operational amplifier has a positive input terminal, a negative input terminal and an output terminal, wherein the positive input terminal is coupled to a source terminal of the second PMOS element, and The negative input end is used as the third end of the current sensing unit; and a second NMOS element is coupled to the positive input end of the operational amplifier and the source end of the second PMOS element at the same time with a drain end thereof, A gate terminal thereof is coupled to the output terminal of the operational amplifier, and a source terminal thereof is used as the fourth terminal of the current sensing unit. The DC-DC conversion circuit as described in Claim 1, wherein the voltage sensing unit includes: a first voltage dividing resistor, a first end of which is coupled to the first end of the output capacitor and the current sensing The third terminal of the unit; a second voltage dividing resistor, with a first terminal coupled to the second terminal of the first voltage dividing resistor, and a second terminal coupled to the ground terminal; Wherein, the first end of the first voltage-dividing resistor is used as the first end of the voltage sensing unit, and a common point between the first voltage-dividing resistor and the second voltage-dividing resistor is used as the voltage sense the second end of the measuring unit. The DC-DC conversion circuit as described in claim 4, wherein the control unit includes: an error amplifier having a positive input terminal, a negative input terminal and an output terminal; wherein, the positive input terminal of the error amplifier is connected to The negative input end serves as the first end and the second end of the control unit respectively, so as to respectively receive the feedback voltage and the reference voltage, so that the error amplifier generates a voltage according to the feedback voltage and the reference voltage. Error signal; a comparator having a positive input terminal, a negative input terminal and an output terminal; wherein, the negative input terminal of the comparator is coupled to the output terminal of the error amplifier, and the positive input terminal of the comparator terminal is coupled to the sixth terminal of the control unit; a first capacitor is coupled to the positive input terminal of the comparator and the sixth terminal of the control unit with its first terminal, and is connected to the sixth terminal of the control unit with its first terminal. Two terminals are coupled to the fifth terminal of the control unit; a first resistor is coupled to the second terminal of the first capacitor with a first terminal, and is coupled to the ground terminal with a second terminal; A switching element, having a channel, one end of the channel is coupled to the positive input end of the comparator, the sixth end of the control unit and the first end of the first capacitor, and the other end of the channel Coupling the second end of the first capacitor and the fifth end of the control unit; the switching element is controlled by a reset signal to enable/close the channel; a second resistor, with a first One end is simultaneously coupled to the output end of the error amplifier and the negative input end of the comparator; a second capacitor is coupled to a second end of the second resistor with a first end thereof, and a second terminal is coupled to the ground terminal; an RS flip-flop has a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to the output terminal of the comparator, and the first input terminal is coupled to the output terminal of the comparator. Two input terminals are coupled to a clock signal transmitted from an oscillator; and A driving unit having an input terminal, a first output terminal and a second output terminal, wherein the input terminal is coupled to the output terminal of the RS flip-flop, and the first output terminal and the second output terminal as the third terminal and the fourth terminal of the control unit respectively. The DC-DC conversion circuit as described in Claim 5, wherein the current signal is a sawtooth current signal, the first terminal of the first capacitor generates a sawtooth voltage signal according to the current signal, and the comparator receiving the saw-tooth wave voltage signal and the error signal through the positive input terminal and the negative input terminal, so as to transmit a comparison signal to the first input terminal of the RS flip-flop through the output terminal, so that The RS flip-flop transmits a PWM signal to the driving unit through the output terminal. The DC-DC conversion circuit as described in Claim 2, wherein the operational transconductance amplifier further includes a digital programming terminal and has a digital programmable function. The DC-DC conversion circuit as described in Claim 7, further comprising: a load current detection unit coupled between the output terminal of the circuit and the third terminal of the current sensing unit for detecting a load current, Accordingly, a load terminal voltage is correspondingly generated; and a transconductance adjustment unit has a first terminal and a second terminal, wherein the first terminal is coupled to the load terminal voltage transmitted by the load current detection unit, and the The second terminal is coupled to the digital programming terminal of the operational transconductance amplifier; wherein, according to the load terminal voltage, the transconductance adjustment unit transmits a digital signal to the digital programming terminal, thereby a transconductance of the operational transconductance amplifier Adjustment is performed to adjust the variation of the pull-down current. A DC-DC conversion circuit has an input terminal for coupling an input voltage and an output terminal for providing an output voltage, and it includes a power transmission unit for periodically controlling the power of the input voltage according to a PWM signal transmitted to the output terminal, and a control unit to generate the PWM signal according to a feedback voltage and an input sensing current, wherein the feedback voltage is generated according to a ratio of the output voltage, characterized in that: the control unit has A transconductance controllable voltage-to-current unit to generate a first sensing current proportional to the product of the input voltage and a load current, and the sum of the first sensing current and the input sensing current is equal to the electric energy A second sensing current of an inductor in the transmission unit. An information processing device, which has a central processing unit and a flat-panel display, the flat-panel display includes a flat display panel, a gate drive module, a source drive module, a display controller, and a power supply unit; It is characterized in that the power supply unit includes the DC-DC conversion circuit described in any one of claims 1 to 9, and the information processing device is composed of a smart phone, a smart watch, a smart bracelet, a tablet computer, a notebook An electronic device selected from a group consisting of a computer, an all-in-one computer, and an access control device.

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