TWI754947B - DC-DC conversion circuit and information processing device - Google Patents

Abstract

A DC-DC conversion circuit has an input end coupled to an input voltage and an output end to provide an output voltage, and includes a power transmission unit to periodically change the input voltage according to the control of a PWM signal Electric energy is transmitted to the output end, and a control unit generates the PWM signal according to a feedback voltage and an input sensing current, wherein the feedback voltage is generated according to a ratio of the output voltage, and it is characterized in that: the control unit There is a voltage-to-current unit to generate a first sensing current proportional to the input voltage, and the sum of the first sensing current and the input sensing current is equal to an inductance in the power transmission unit and a second The current is sensed, so that the control unit can quickly respond to the change of the input voltage and adjust the output voltage in real time, so as to meet the power quality requirements of various TDMA application environments.

Description

DC-DC conversion circuit and information processing device

The present invention relates to a DC-DC conversion circuit, especially a DC-DC conversion circuit with fast transient response.

Due to its advantages of self-luminescence, wide viewing angle, high contrast, low power consumption and high response rate, OLED displays have been widely used in various electronic products, which can be divided into PMOLED displays and AMOLED displays. Please refer to FIG. 1 , which shows a structure diagram of a conventional AMOLED display. As shown in FIG. 1, a conventional AMOLED display includes: an AMOLED panel 1a, a gate driver module 2a, a source driver module 3a, a display controller 4a, and a power supply unit 5a. The current technology can already integrate the display controller 4a, the gate driver module 2a and the source driver module 3a into a single display driver chip. In FIG. 1, the power supply unit 5a is coupled to an external power source, such as a power source provided by a lithium battery, so as to provide a working voltage V _DD to the display controller 4a, the gate driver module 2a and the source driver. The module 3a provides a light-emitting working voltage ELV _DD and a grounding working voltage ELV _SS to the AMOLED panel 1a.

FIG. 2 shows a circuit topology diagram of a conventional power supply unit. The power supply unit 5a shown in FIG. 1 is a boost DC-DC converter, and includes: an input capacitor Cia, an inductor L1a, a first NMOS element Q2a, a first PMOS element Q1a, a A second PMOS element Qsa, a second NMOS element Qca, an operational amplifier A1a, a first voltage dividing resistor Rf1a, a second voltage dividing resistor Rf2a, an input capacitor Coa, an error amplifier A2a, a first resistor Rra, A second resistor Rea, a first capacitor Cra, a second capacitor Cea, a comparator A3a, a current source Ira, an oscillator 51a, an RS flip-flop 52a, and a driving unit 53a. The first PMOS element Q1a is a freewheeling element to ensure that the current _IL of the inductor L1a is continuous.

On the other hand, the first NMOS element Q2a serves as a switching element, and the second PMOS element Qsa serves as a current sensing element. Through the arrangement of the operational amplifier A1a and the second NMOS element Qca, the four-terminal voltages (ie, the two drain terminals and the two source terminals) of the first PMOS element Q1a and the second PMOS element Qsa will be the same. In this way, the sampling current Isense transmitted from the second PMOS element Qsa to the switching element S1a is _IL /m, where m=WQ ₁ /WQ _sense . Herein, WQ ₁ refers to the channel width of the first PMOS device Q1a, and WQ _sense refers to the channel width of the second PMOS device Qsa.

In more detail, the reference voltage V _REF =Vout*(Rf2a/(Rf1a+Rf2a)), the error amplifier A2a is based on the reference voltage V _REF and taken from the first voltage dividing resistor Rf1a and the second voltage dividing resistor Rf2a A feedback voltage V _FB is generated to output an error signal Vea to the negative input terminal of the comparator A3a. At the same time, the current source Ira, the first capacitor Cra and the first resistor Rra provide a sawtooth voltage signal Vramp to the positive input terminal of the comparator A3a. Thus, based on the sawtooth wave voltage signal Vramp and the error signal Vea, the comparator A3a outputs a comparison signal to a first input terminal (ie, the R terminal) of the RS flip-flop 52a, and the oscillator 51a provides a The clock signal CLK is supplied to a second input terminal (ie, the S terminal) of the RS flip-flop 52a. Finally, the output terminal (ie, the Q terminal) of the RS flip-flop 52a provides a PWM signal to the driving unit 53a, so that the driving unit 53a provides a first gate voltage signal to the first NMOS according to the PWM signal The gate terminal of the element Q2a is simultaneously provided with a second gate voltage signal to the gate terminals of the first PMOS element Q1a and the second PMOS element Qsa. It should be known that the duty cycle of the PWM signal is determined by the clock signal CLK.

With the hot sale of smart phones, smart watches, smart bracelets, and sports watches, OLED displays have also been widely used. It must be known that mobile electronic devices need to send and receive various signals, including GSM signals, Wi-Fi signals and Bluetooth signals. However, the spectrum of wireless communication is limited, so the spectrum allocation of wireless communication is very strict, otherwise different wireless signals will be will interfere with each other during transmission. In order to solve the aforementioned problems, wireless communication engineers have developed various multiple access (Multiple Access) technologies to increase the utilization rate of the spectrum, such as: Time division multiple access (TDMA), frequency division multiple access (Frequency division multiple access) division multiple access, FDMA) and code division multiple access (Code division multiple access, CDMA).

Please also refer to FIG. 3 , which shows a working timing diagram of an input voltage signal and an output voltage signal of the conventional power supply unit shown in FIG. 2 . It should be noted that in the case of using TDMA for wireless communication, there is a large difference between the power consumption used by the mobile electronic device in a transmission interval and the power consumption used in a reception interval. That is, the power consumption used in the transmission section is much larger than the power consumption used in the reception section, and TDMA noise of a certain frequency is generated. Practical experience shows that TDMA noise will also cause adverse effects on the transient response of the regulated power supply unit 5a. Therefore, the power drive management of AMOLED displays is required to pass TDMA noise related tests. As shown in Figure 3, the test content of TDMA noise is as follows: the input voltage signal Vin will be disturbed at intervals, so that it jumps up or down 500mV instantaneously within 10us, and after jumping up (or down) 500mV , maintain this voltage level for 500us. Practical experience shows that when the aforementioned interference phenomenon occurs, the output voltage signal Vout of the boost DC-DC converter (ie, the power supply unit 5a) as shown in FIG. 2 will correspondingly have a transient down-collision wave ( undershoot) or overshoot, resulting in system instability.

Therefore, industry standards place high demands on boost DC-DC converters used in mobile electronic devices, which require a load whose undershoot or overshoot disturbance is within 200mA during the aforementioned transient state. must be less than 20mV under load conditions and less than 60mV under load conditions within 1A.

As shown in FIG. 2, in the design of the conventional boost DC-DC converter (ie, the power supply unit 5a), the second resistor Rea and the second capacitor Cea are connected in series with each other and are coupled to Between the negative input terminal of the comparator A3a and the ground terminal, it is used to compensate the stability of the entire boost loop (Boost loop) under different current load conditions. Unfortunately, as shown in FIG. 2 and FIG. 3 , when the input voltage signal Vin jumps up or down instantaneously, the system cannot instantly modulate the output voltage signal Vout. The reason is that the error amplifier A2a outputs an error signal Vea to the comparator based on the reference voltage V _REF and the feedback voltage V _FB obtained from the first voltage dividing resistor Rf1a and the second voltage dividing resistor Rf2a A3a, the comparator A3a outputs a comparison signal to the RS flip-flop 52a according to a sawtooth voltage signal Vramp and the error signal Vea. Finally, the RS flip-flop 52a outputs a PWM signal to the driving unit 53a according to the comparison signal and a clock signal CLK, so that the driving unit 53a controls the gate terminal of the first NMOS element Q2a, the first NMOS element Q2a according to the PWM signal A PMOS element Q1a and the second PMOS element Qsa modulate the output voltage signal Vout.

時，由該誤差放大器A2a所輸出的誤差信號Vea也會有一個

。

的值越大，則系統的升壓環路調整對該RS正反器52a所輸出的PWM信號之占空比(Duty cycle)調整也就越慢，因此出現在輸出電壓信號Vout之上的輸出電壓變化

也就越大。例如，圖4的實際量測資料顯示

的Vpp=130mV。 FIG. 4 is a timing chart showing the actual measurement operation of the error signal Vea, the sawtooth wave voltage signal Vramp and the output voltage signal Vout of the conventional power supply unit shown in FIG. 2 . The boost compensation loop of the conventional boost DC-DC converter used in the mobile electronic device cannot make instant fast transient response according to the instantaneous up or down jump of the input voltage signal Vin. response). As shown in Figure 4, the input voltage signal Vin has an instantaneous

, the error signal Vea output by the error amplifier A2a will also have a

.

The larger the value of , the slower the duty cycle of the PWM signal output by the RS flip-flop 52a is adjusted by the boost loop of the system, so the output that appears above the output voltage signal Vout voltage change

also bigger. For example, the actual measurement data in Figure 4 shows

of Vpp=130mV.

It can be seen from the above description that there is an urgent need in the art for a novel DC-DC conversion circuit.

The main purpose of the present invention is to provide a DC-DC conversion circuit, which includes an input capacitor, an inductor, a current source, a switching element, a freewheeling element, an output capacitor, a current sensing unit, and a voltage sensing unit. unit and a control unit. In particular, the present invention adds a current pull-down unit in the DC-DC conversion circuit, which is coupled to the input end of the circuit, and is simultaneously coupled to the control unit and the current sensing unit. In this way, when the input voltage signal has an input voltage variation due to the influence of the TDMA noise, a feed-forward pull-down current of the current pull-down unit correspondingly generates a pull-down current variation, thereby feed-forward adjustment by The output end of the circuit returns a sensed current value of the control unit, so that the control unit can quickly generate a transient response, so as to adjust the output voltage signal in real time to meet the power supply quality requirements of various TDMA application environments.

In order to achieve the above object, the present invention proposes an embodiment of the DC-DC conversion circuit, which includes:

a power transmission unit for converting an input voltage into an output voltage according to the control of a PWM signal;

a current sensing unit for generating an inductor sensing current according to a ratio of an inductor current of the power transmission unit;

a control unit for determining the duty cycle of the PWM signal according to a feedback voltage and an input sensing current, the feedback voltage being proportional to the output voltage; and

a first current pull-down unit for generating a first feed-forward pull-down current according to the input voltage;

Wherein, the sum of the input sensing current and the first feed-forward pull-down current is equal to the inductor sensing current.

In one embodiment, the first current pull-down unit includes a first operational transconductance amplifier having a positive input terminal, a negative input terminal and an output terminal, wherein the positive input terminal is coupled to the input voltage, and the negative input terminal is coupled to the input voltage. The input terminal is coupled to a ground terminal, and the output terminal generates the first feed-forward pull-down current.

In one embodiment, the current sensing unit has a first end, a second end, a third end and a fourth end, and includes:

a second PMOS element, a drain terminal of which is used as the first terminal of the current sensing unit, and a gate terminal of which is used as the second terminal of the current sensing unit;

An operational amplifier has a positive input terminal, a negative input terminal and an output terminal, wherein the positive input terminal is coupled to a source terminal of the second PMOS element, and the negative input terminal serves as the first terminal of the current sensing unit three ends; and

A third PMOS element has a drain terminal coupled to both the positive input terminal of the operational amplifier and the source terminal of the second PMOS element, a gate terminal coupled to the output terminal of the operational amplifier, and A source terminal thereof serves as the fourth terminal of the current sensing unit.

In one embodiment, the voltage sensing unit includes a first voltage dividing resistor and a second voltage dividing resistor in a series configuration.

In one embodiment, the control unit includes:

An error amplifier has a positive input terminal, a negative input terminal and an output terminal, the positive input terminal and the negative input terminal are respectively coupled to the feedback voltage and a reference voltage, and the output terminal is used for providing an error signal generated by the difference between the feedback voltage and the reference voltage;

a comparator having a positive input terminal, a negative input terminal and an output terminal, the negative input terminal is coupled to the output terminal of the error amplifier, and the positive input terminal is coupled to a sawtooth voltage signal;

a first capacitor, having a first end and a second end, the first end is coupled to the positive input end of the comparator;

a first resistor coupled between the second end of the first capacitor and a ground end;

a switch element having a channel, the channel is coupled between the first end and the second end of the first capacitor, and the switch element is controlled by a reset signal to enable/disable the channel;

An RS flip-flop has a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to the output terminal of the comparator, and the second input terminal is coupled to the output terminal of the comparator. a clock signal of an oscillator; and

A driving unit has an input end, a first output end and a second output end, wherein the input end is coupled to the output end of the RS flip-flop, and the first output end and the second output end The PWM signal and the complementary signal of the PWM signal are respectively output.

In one embodiment, the DC level of the sawtooth voltage signal is determined by the voltage established by the input sensing current on the first resistor.

In order to achieve the aforementioned object, the present invention further provides a DC-DC conversion circuit, which has an input terminal coupled to an input voltage and an output terminal to provide an output voltage, and includes a power transmission unit to transmit power according to a PWM signal. Control periodically transmits the power of the input voltage to the output terminal, and a control unit generates the PWM signal according to a feedback voltage and an input sensing current, wherein the feedback voltage is proportional to the output voltage produced, characterized by:

The control unit has a voltage-to-current unit to generate a first sensing current proportional to the input voltage, and the sum of the first sensing current and the input sensing current is equal to the sum of an inductance in the power transmission unit a second sense current.

In order to achieve the aforementioned purpose, the present invention further proposes a DC-DC conversion circuit, which includes:

a power transmission unit for converting an input voltage into an output voltage according to the control of a PWM signal;

a current sensing unit for generating an inductor sensing current according to a ratio of an inductor current of the power transmission unit;

a control unit for determining the duty cycle of the PWM signal according to a feedback voltage and an input sensing current, the feedback voltage being proportional to the output voltage;

a first current pull-down unit for generating a first feed-forward pull-down current according to the input voltage; and

a second current pull-down unit for generating a second feed-forward pull-down current according to an output voltage of the analog multiplier, the output voltage being generated according to the product of the input voltage and a sensing voltage of a load current;

Wherein, the sum of the input sensing current, the first feed-forward pull-down current and the second feed-forward pull-down current is equal to the inductor sensing current.

In one embodiment, the second current pull-down unit includes a second operational transconductance amplifier having a positive input terminal, a negative input terminal and an output terminal, wherein the positive input terminal is coupled to the location of the analog multiplier. the output voltage, the negative input terminal is coupled to a ground terminal, and the output terminal is used for providing the second feed-forward pull-down current.

The present invention also provides an information processing device, which has a central processing unit and a flat panel display. The flat panel display includes a flat panel display panel, a gate driver module, a source driver module, a display controller, and a A power supply unit; characterized in that, the power supply unit includes the DC-DC conversion circuit of the present invention as described above, and in a possible embodiment, the information processing device can be a smart phone, a smart watch, a smart bracelet, or a tablet. Computers, laptops, all-in-one computers, or access control devices.

In order to enable your examiners to further understand the structure, characteristics, purpose, and advantages of the present invention, drawings and detailed descriptions of preferred embodiments are attached as follows.

The principle of the DC-DC conversion circuit of the present invention is:

(1) Using a power transmission unit to periodically transmit the power of an input voltage to an output end according to the control of a PWM signal;

(2) using a control unit to generate the PWM signal according to a feedback voltage and an input sensing current, wherein the feedback voltage is generated according to a ratio of an output voltage of the output terminal; and

(3) The control unit has a voltage-to-current unit to generate a first sensing current proportional to the input voltage, and the sum of the first sensing current and the input sensing current is equal to the sum of the power transmission unit An inductor and a second sense current.

Accordingly, when the input voltage changes due to the interference of TDMA noise, for example, when it becomes high/low, the first sensing current will increase/decrease accordingly, so that the second sensing current is not changed before the change. The input sensing current becomes smaller/larger to drive the duty cycle of the PWM signal to become smaller/larger so that the control unit can quickly generate a transient response to ensure that the ripple of the output voltage is less than a required value.

first embodiment

FIG. 5 shows a block diagram of a first embodiment of a DC-DC conversion circuit of the present invention. As shown in FIG. 5 , the DC-DC conversion circuit 1 of the present invention is a boost type (boost) DC-DC conversion circuit, which can be used in a mobile electronic device as a (stabilized) power supply unit , so that the input voltage provided by the lithium battery is converted into an output voltage, and the output voltage is provided to a flat display panel (such as an AMOLED display panel) of the mobile electronic device and related electronic chips (refer to FIG. 1 ). As can be seen from FIG. 5, the DC-DC conversion circuit 1 of the present invention includes: a circuit input terminal 10 coupled to an input voltage signal Vin, an input capacitor Ci, an inductor L1, a first NMOS element Q2 serving as a switching element, As a freewheeling element, a first PMOS element Q1, an output capacitor Co, a circuit output terminal 11, a current sensing unit 12, a voltage sensing unit 13, a control unit 14, a current source 16, and a first A current pull-down unit 15 .

According to the design of the present invention, a first terminal and a second terminal of the input capacitor Ci are respectively coupled to the circuit input terminal 10 of the DC-DC conversion circuit 1 and a ground terminal, and the inductor L1 is connected to a first terminal thereof. One end is coupled to the first end of the input capacitor Ci. It should be noted that the first NMOS element Q2 is used as a switching element of the boost DC-DC converter 1 and is controlled by a PWM signal, and a drain terminal and a source terminal thereof are respectively coupled to A second end of the inductor L1 and the ground end. On the other hand, the first PMOS element Q1 acts as a freewheeling element and is controlled by a PWMB signal to ensure that the current _IL of the inductor L1 is continuous, and a drain terminal of the first NMOS element is coupled to the first NMOS element The drain terminal of Q2, wherein the PWMB signal is the complementary signal of the PWM signal. In addition, a first terminal and a second terminal of the output capacitor Co are respectively coupled to a source terminal and the ground terminal of the first PMOS element Q1, and the circuit output terminal 11 of the DC-DC converter 1 is coupled to The first terminal of the output capacitor Co is connected to transmit an output voltage signal Vout.

In more detail, the current sensing unit 12 , the voltage sensing unit 13 and the control unit 14 are a feedback compensation system of the DC-DC conversion circuit 1 , wherein the current sensing unit 12 is used to automatically The circuit output terminal 11 detects a sensing current Isense and transmits it to the control unit 14 , and the voltage sensing unit 13 detects a sensing voltage from the circuit output terminal 11 to transmit a feedback voltage V _FB to the control unit 14 . unit 14. As shown in FIG. 5 , the current sensing unit 12 has a first end 121 , a second end 122 , a third end 123 , and a fourth end 124 . The first terminal 121 is simultaneously coupled to the drain terminal of the first NMOS element Q2 and the drain terminal of the first PMOS element Q1, the second terminal 122 is coupled to a gate terminal of the first PMOS element Q1, and the The third terminal 123 is coupled to the source terminal of the first PMOS element Q1. On the other hand, the voltage sensing unit 13 has a first terminal 131 and a second terminal 132 , wherein the first terminal 131 is coupled to the first terminal of the output capacitor Co and the current sensing unit 12 . The third end 123 .

According to the above description, the control unit 14 has a first end 141 , a second end 142 , a third end 143 , a fourth end 144 , a fifth end 145 , and a sixth end 146 . As shown in FIG. 5 , the first terminal 141 is coupled to the second terminal 132 of the voltage sensing unit 13 , the third terminal 143 is coupled to a gate terminal of the first NMOS element Q2 , and the fourth terminal 144 is coupled to The second terminal 122 of the current sensing unit 12 and the gate terminal of the first PMOS element Q1 are connected. It is added that a first end of the current source 16 is coupled to the first end of the input capacitor Ci and the first end of the inductor L1, and a second end of the current source 16 is coupled to the control unit 14 The sixth end 146 . In the DC-DC conversion circuit 1, the current source 16 transmits a current signal to the sixth terminal 146 of the control unit 14, and the current signal is a sawtooth current signal Iramp.

When the mobile electronic device does not generate TDMA noise, the control unit 14 receives a feedback voltage V FB transmitted by the voltage sensing unit 13 with the first terminal 141 , and receives the feedback voltage V _FB with the second terminal 142 . The fifth terminal 145 of a reference voltage V _REF receives an input sensing current Isense_in, and the input sensing current Isense_in is a sensing current Isense transmitted by the current sensing unit 12 and the first current pull-down unit 15 The difference current of a first feed-forward pull-down current Isink1 is generated, and the sixth terminal 146 receives a sawtooth current signal Iramp transmitted by the current source 16, thereby transmitting a sawtooth current signal Iramp transmitted by the third terminal 143 thereof The first gate voltage signal is sent to the gate terminal of the first NMOS element Q2, and the fourth terminal 144 thereof transmits a second gate voltage signal to the gate terminal of the first PMOS element Q1 and the current sense The second end 122 of the measuring unit 12 is used to regulate the voltage regulation of an output voltage signal Vout transmitted by the circuit output end 11, so that the DC-DC conversion circuit 1 can stably supply power to the mobile A flat display panel (such as an AMOLED display panel) of an electronic device and related electronic chips.

It is worth noting that in the case of the mobile electronic device with TDMA noise, as shown in FIG. 3 , the input voltage signal Vin will be disturbed at intervals, so that it jumps up or down by 500mV instantaneously within 10us, and at After jumping up (or down) by 500mV, maintain this voltage level for 500us. When the aforementioned interference phenomenon occurs, the output voltage signal Vout of the DC-DC converter 1 as shown in FIG. 5 will correspondingly have a transient undershoot or overshoot, resulting in a system malfunction. Stablize.

Therefore, the present invention particularly adds a first current pull-down unit 15 in the DC-DC conversion circuit 1 . As shown in FIG. 5 , the first current pull-down unit 15 has a first terminal 151 and a second terminal 152 , wherein the first terminal 151 is coupled to the circuit input terminal 10 and the first terminal of the input capacitor Ci , and the second end 152 is simultaneously coupled to the fifth end 145 of the control unit 14 and the second end 132 of the pressure sensing unit 13 . In the DC-DC conversion circuit 1 , the first current pull-down unit 15 is used for generating a first feed-forward pull-down current Isink1 according to the input voltage signal Vin to affect the current value of the input sensing current Isense_in.

；此時，該第一前饋下拉電流Isink1對應地具有一下拉電流變化量

，藉此前饋式地調整該控制單元14透過其第五端145所接收的該輸入感測電流的值，從而使該控制單元14能夠立即調整PWM信號和PWMB信號而產生快速暫態響應，故能在電路的回授環路(回授補償系統)完成對於輸出電壓信號Vout的補償之前，即時調整輸出電壓信號Vout。簡單地說，藉由所述第一電流下拉單元15之設置，該直流-直流轉換電路1之回授環路(回授補償系統)的快速暫態響應(fastline transient response)於是被顯著提升。應知道gm1為該第一運算轉導放大器Ap1所具有的轉導值。 Continue to refer to FIG. 6 , which shows a circuit topology diagram of the first embodiment of the DC-DC conversion circuit of the present invention. In one embodiment, the first current pull-down unit 15 includes a first operational transconductance amplifier (OTA) Ap1, which has a positive input terminal, a negative input terminal and an output terminal, wherein the positive input terminal is The terminal is used as the first terminal 151 of the first current pull-down unit 15 , the negative input terminal is coupled to the ground terminal, and the output terminal is used as the second terminal 152 of the first current pull-down unit 15 . When the mobile electronic device has TDMA noise, the input voltage signal Vin will have an input voltage variation

; At this time, the first feed-forward pull-down current Isink1 correspondingly has a pull-down current variation

, whereby the control unit 14 adjusts the value of the input sensing current received by the control unit 14 through its fifth terminal 145 in a feedforward manner, so that the control unit 14 can immediately adjust the PWM signal and the PWMB signal to generate a fast transient response, so The output voltage signal Vout can be adjusted immediately before the feedback loop (feedback compensation system) of the circuit completes the compensation for the output voltage signal Vout. In short, with the setting of the first current pull-down unit 15, the fast line transient response of the feedback loop (feedback compensation system) of the DC-DC conversion circuit 1 is significantly improved. It should be known that gm1 is the transconductance value of the first operational transconductance amplifier Ap1.

As shown in FIG. 6 , in one embodiment, the current sensing unit 12 includes: a second PMOS element Qs, an operational amplifier A1 and a third PMOS element Qc. A drain terminal of the second PMOS element Qs is used as the first terminal 121 of the current sensing unit 12 , and a gate terminal thereof is used as the second terminal 122 of the current sensing unit 12 . Moreover, the operational amplifier A1 has a positive input terminal, a negative input terminal and an output terminal, wherein the positive input terminal is coupled to a source terminal of the second PMOS element Qs, and the negative input terminal serves as the current sensing unit The third end 123 of 12. On the other hand, a drain terminal of the third PMOS element Qc is simultaneously coupled to the positive input terminal of the operational amplifier A1 and the source terminal of the second PMOS element Qs, and a gate terminal of the third PMOS element Qc is coupled to the operational amplifier A1 The output terminal of , and a source terminal thereof is used as the fourth terminal 124 of the current sensing unit 12 .

Moreover, in one embodiment, the voltage sensing unit 13 is composed of a first voltage dividing resistor Rf1 and a second voltage dividing resistor Rf1 . As shown in FIG. 6 , a first end of the first voltage dividing resistor Rf1 is coupled to the first end of the output capacitor Co and the third end 123 of the current sensing unit 12 . On the other hand, a first end of the second voltage dividing resistor Rf2 is coupled to the first end of the first voltage dividing resistor Rf1, and a second end of the second voltage dividing resistor Rf2 is coupled to the ground end. It can be seen from FIG. 6 that the first end of the first voltage dividing resistor Rf1 serves as the first end 131 of the voltage sensing unit 13 , and the connection between the first voltage dividing resistor Rf1 and the second voltage dividing resistor Rf2 is A common contact is used as the second terminal 132 of the voltage sensing unit 13 .

To further illustrate, the control unit 14 includes: an error amplifier A2, a comparator A3, a first capacitor Cr, a first resistor Rr, a switching element S1, a second resistor Re, a second capacitor Ce, An RS flip-flop 14RS, and a driving unit 14DR. The error amplifier A2 has a positive input terminal, a negative input terminal and an output terminal. As shown in FIG. 6 , the positive input terminal and the negative input terminal of the error amplifier A2 serve as the first terminal 141 and the second terminal 142 of the control unit 14, respectively, so as to receive the feedback voltage V _FB and the The reference voltage V _REF enables the error amplifier A2 to generate an error signal Vea according to the feedback voltage V _FB and the reference voltage V _REF . On the other hand, the comparator A3 has a positive input terminal, a negative input terminal and an output terminal, wherein the negative input terminal of the comparator A3 is coupled to the output terminal of the error amplifier A2, and the comparator A3 has a The positive input terminal is coupled to the sixth terminal 146 of the control unit 14 .

In addition, the first capacitor Cr has a first terminal coupled to the positive input terminal of the comparator A3 and the sixth terminal 146 of the control unit 14, and a second terminal of the first capacitor Cr is coupled to the control unit 14. Fifth end 145 . On the other hand, a first end of the first resistor Rr is coupled to the second end of the first capacitor Cr, and a second end of the first resistor Rr is coupled to the ground end. In this way, after the current source 16 generates a sawtooth wave current signal Iramp to the sixth terminal 146 of the control unit 14 according to the input voltage signal Vin, the sawtooth wave current signal Iramp is at the output of the first capacitor Cr. The first terminal forms a sawtooth wave voltage signal Vramp, so that the comparator A3 receives the sawtooth wave voltage signal Vramp and the error signal Vea with its positive input terminal and negative input terminal, respectively.

According to the above description, the switching element S1 has a channel, and one end of the channel is simultaneously coupled to the positive input end of the comparator A3, the sixth end 146 of the control unit 14 and the first end of the first capacitor Cr terminal, and the other terminal of the channel is coupled to the second terminal of the first capacitor Cr and the fifth terminal 145 of the control unit 14 . And, the switch element S1 is controlled by a reset signal V _Reset to enable/disable the channel. And, as shown in FIG. 6 , the second resistor Re is coupled to the output end of the error amplifier A2 and the negative input end of the comparator A3 with its first end, and the second capacitor Ce is coupled to its one end The first terminal is coupled to a second terminal of the second resistor Re, and a first terminal is coupled to the ground terminal.

Further, the RS flip-flop 14RS has a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to the output terminal of the comparator A3, and the second input terminal is coupled to A clock signal CLK transmitted from an oscillator 14OC is connected. Furthermore, the driving unit 14DR has an input terminal, a first output terminal and a second output terminal, wherein the input terminal is coupled to the output terminal of the RS flip-flop 14RS, and the first output terminal and the first output terminal are coupled to the output terminal of the RS flip-flop 14RS. The two output terminals serve as the third terminal 143 and the fourth terminal 144 of the control unit 14 respectively.

As shown in FIG. 6, based on the sawtooth voltage signal Vramp and the error signal Vea, the comparator A3 outputs a comparison signal to the first input terminal (ie, the R terminal) of the 14RS flip-flop 52, and the oscillator 14OC provides a clock signal CLK to the second input terminal (ie, the S terminal) of the RS flip-flop 14RS. Finally, the output terminal (ie, the Q terminal) of the RS flip-flop 14RS provides a PWM signal to the driving unit 14DR, wherein the period of the PWM signal is determined by the clock signal CLK. Further, the driving unit 14DR provides a first gate voltage signal (ie, PWM signal) to the gate terminal of the first NMOS element Q2 according to the PWM signal, and simultaneously provides a second gate voltage signal (ie, PWMB signal) to the gate terminals of the first PMOS element Q1 and the second PMOS element Qs.

；此時，該第一前饋下拉電流Isink1對應地具有一下拉電流變化量

，使得所述鋸齒波電壓信號Vramp的電平對應地變化了

，藉此方式保證由該誤差放大器A2所輸出之所述誤差信號Vea盡量沒有變化。因此，在參考電壓V _REF維持不變的情況下，所述誤差信號Vea盡量沒有變化的意思即為回授電壓V _FB的變化量很小，亦即輸出電壓信號Vout的一輸出電壓變化量

的值即隨之變化很小。圖7的實際量測資料顯示所述輸出電壓變化量

的Vpp=30mV。 FIG. 7 is a timing chart showing the actual measurement operation of the error signal Vea, the sawtooth wave voltage signal Vramp and the output voltage signal Vout of the DC-DC conversion circuit of the present invention shown in FIG. 6 . When the mobile electronic device has TDMA noise, the input voltage signal Vin will have an input voltage variation

; At this time, the first feed-forward pull-down current Isink1 correspondingly has a pull-down current variation

, so that the level of the sawtooth voltage signal Vramp changes correspondingly

, so as to ensure that the error signal Vea output by the error amplifier A2 does not change as much as possible. Therefore, when the reference voltage V _REF remains unchanged, the error signal Vea does not change as much as possible, which means that the variation of the feedback voltage V _FB is small, that is, an output voltage variation of the output voltage signal Vout

The value of , then changes little. The actual measurement data in Figure 7 shows the output voltage variation

of Vpp=30mV.

之時，該第一電流下拉單元15的一第一前饋下拉電流

即對應地具有一下拉電流變化量

，藉此前饋式地調整由所述第五端145傳入該控制單元14的一輸入感測電流Isense_in的值，使該控制單元14能夠立即產生快速暫態響應，從而在電路的回授環路(回授補償系統)完成對於輸出電壓信號Vout的補償之前，即適應性地調整輸出電壓信號Vout，有效地保證輸出電壓變化量

小於或等於30mV。 Therefore, after comparing the measurement data of FIG. 7 and FIG. 4 , it should be understood that a first current pull-down unit 15 is added in the DC-DC conversion circuit 1 and is coupled to the circuit input end 10 , and After the control unit 14 and the current sensing unit 13 are simultaneously coupled, when the input voltage signal Vin is affected by the TDMA noise, there is an input voltage variation

At this time, a first feed-forward pull-down current of the first current pull-down unit 15

That is, there is a corresponding pull-down current variation

, thereby adjusting the value of an input sensing current Isense_in from the fifth terminal 145 to the control unit 14 in a feedforward manner, so that the control unit 14 can immediately generate a fast transient response, so that in the feedback loop of the circuit Before the circuit (feedback compensation system) completes the compensation for the output voltage signal Vout, the output voltage signal Vout is adaptively adjusted to effectively ensure the output voltage variation

Less than or equal to 30mV.

Second Embodiment

之時，本發明之直流-直流轉換電路1的第一實施例能夠即時、快速地將輸入電壓的變化量

之控制在30mV以內。然而，必須加以說明的是，前述之快速暫態響應是在本發明之直流-直流轉換電路1操作在固定負載的情況下實現的。更詳細地說明，鋸齒波電壓信號Vramp的電平之變化量

，是用以保證由該誤差放大器A2所輸出之所述誤差信號Vea盡量沒有變化。但是，當負載狀態變動時，前述之變化量

不能有效補償負載電流對於誤差信號Vea之值所造成的變化。圖8為圖6所示之本發明之直流-直流轉換電路的第一實施例在不同負載電流下之輸出電壓信號之實際量測工作時序圖。如圖8的實際量測資料顯示，在負載電流為1mA、300mA、以及600mA的情況下，本發明之直流-直流轉換電路1的第一實施例的輸出電壓信號Vout的變化量之Vpp也跟著改變(20mVà22mVà50mV)。因此，實際量測資料證實了，當負載狀態變動時，前述之變化量

不能有效補償負載電流對於誤差信號Vea之值所造成的變化，導致輸出電壓信號Vout的變化量無法被控制在30mV以內。 It can be seen from the above description that the instantaneous input voltage variation occurs when the input voltage signal Vin is affected by the TDMA noise.

At this time, the first embodiment of the DC-DC conversion circuit 1 of the present invention can instantly and quickly convert the variation of the input voltage

It is controlled within 30mV. However, it must be noted that the aforementioned fast transient response is achieved under the condition that the DC-DC conversion circuit 1 of the present invention operates under a fixed load. In more detail, the amount of change in the level of the sawtooth voltage signal Vramp

, is used to ensure that the error signal Vea output by the error amplifier A2 does not change as much as possible. However, when the load state changes, the aforementioned amount of change

The variation caused by the load current to the value of the error signal Vea cannot be effectively compensated. FIG. 8 is a timing chart of the actual measurement operation of the output voltage signal of the first embodiment of the DC-DC conversion circuit of the present invention shown in FIG. 6 under different load currents. The actual measurement data shown in FIG. 8 shows that when the load current is 1 mA, 300 mA, and 600 mA, the variation Vpp of the output voltage signal Vout of the first embodiment of the DC-DC conversion circuit 1 of the present invention also follows Change (20mVà22mVà50mV). Therefore, the actual measurement data confirms that when the load state changes, the aforementioned variation

The variation caused by the load current to the value of the error signal Vea cannot be effectively compensated, so that the variation of the output voltage signal Vout cannot be controlled within 30mV.

Based on the aforementioned reasons, the present invention simultaneously proposes a second embodiment of a DC-DC conversion circuit of the present invention. FIG. 9 shows a block diagram of a second embodiment of a DC-DC conversion circuit of the present invention. After comparing FIG. 9 and FIG. 5 , it should be easily known that the second embodiment of the DC-DC conversion circuit 1 of the present invention further includes: a second current pull-down unit 17 , an analog multiplier 18 and a load current detection Unit 19.

FIG. 10 is a circuit topology diagram of the second embodiment of the DC-DC conversion circuit of the present invention. In the second embodiment, the second current pull-down unit 17 has a first end 171 and a second end 172, wherein the second end 172 is coupled to the fifth end 145 of the control unit 14 and the pressure-sensitive the second end 132 of the measuring unit 13 . In more detail, the second current pull-down unit 17 includes a second operational transconductance amplifier (OTA) Ap2, which has a positive input terminal, a negative input terminal and an output terminal, wherein the positive input terminal serves as the first The first terminal 171 of the current pull-down unit 17 , the negative input terminal is coupled to the ground terminal, and the output terminal serves as the second terminal 172 of the second current pull-down unit 17 . Moreover, the load current detection unit 19 is coupled between the circuit output terminal 11 and the third terminal 132 of the current sensing unit 12 for detecting a load current and correspondingly generating a load terminal voltage. Furthermore, the analog multiplier 18 has a first end 181 , a second end 182 , and a third end 183 , wherein the first end 181 is coupled to the first end 151 of the first current pull-down unit 15 at the same time With the circuit input terminal 10 , the second terminal 182 is coupled to the load terminal voltage, and the third terminal 183 is coupled to the first terminal 171 of the second current pull-down unit 17 .

時，下拉電流變化量即為

+

=

+

*β*(α*I _Load)*

。應知道，gm2為該第二運算轉導放大器Ap2所具有的轉導值。因此，I _Load即成為式中的變數，使得本發明之直流-直流轉換電路1的第二實施例在負載電流變動的情況下，仍舊可以快速地對輸出電壓信號Vout進行補償，從而有效地控制所述輸出電壓變化量

的值。 According to the design of the present invention, the function of the load current detection unit 19 is to convert the load current I _Load into a load terminal voltage V _CTRL =α*I _Load . Thus, the voltage signal sent by the analog multiplier 18 to the second feed-forward pull-down current Isink2 is V _multiple =β*V _CTRL *Vin=β*(α*I _Load )*Vin. In this way, when the input voltage signal Vin has an input voltage variation

, the pull-down current change is

+

=

+

*β*(α*I _Load )*

. It should be known that gm2 is the transconductance value of the second operational transconductance amplifier Ap2. Therefore, I _Load becomes a variable in the formula, so that the second embodiment of the DC-DC conversion circuit 1 of the present invention can still quickly compensate the output voltage signal Vout when the load current fluctuates, thereby effectively controlling The output voltage change amount

value of .

的值。 FIG. 11 is a timing chart of the actual measurement operation of the output voltage signal of the second embodiment of the DC-DC conversion circuit of the present invention shown in FIG. 10 under different load currents. The actual measurement data shown in FIG. 11 shows that when the load current is 1 mA, 300 mA, and 600 mA, the variation Vpp of the output voltage signal Vout of the second embodiment of the DC-DC conversion circuit 1 of the present invention also changes accordingly. (9mVà12mVà20mV). It is worth noting that, since the second embodiment further includes a second current pull-down unit 17, an analog multiplier 18 and a load current detection unit 19, the actual measurement data confirms that the DC-DC conversion circuit 1 of the present invention has In the second embodiment, when the load current varies, the output voltage signal Vout can still be quickly compensated, so as to effectively control the output voltage variation

value of .

In this way, the above has completely and clearly described a DC-DC conversion circuit of the present invention; and, through the above, it can be known that the present invention has the following advantages:

(1) The present invention discloses a DC-DC conversion circuit, which basically includes an input capacitor, an inductor, a current source, a switching element, a freewheeling element, an output capacitor, a current sensing unit, and a voltage sensing unit. measurement unit, and a control unit. In particular, in the present invention, a first current pull-down unit is added in the DC-DC conversion circuit, which is coupled to the circuit input end, and is simultaneously coupled to the control unit and the current sensing unit. In this way, when the input voltage signal has an input voltage variation due to the influence of TDMA noise, a feed-forward pull-down current of the first current pull-down unit correspondingly generates a pull-down current variation, whereby the feed-forward grounding Adjust the value of a sensing current returned to the control unit by the circuit output, so that the control unit can immediately generate a fast transient response, so that before the feedback loop of the circuit completes the compensation for the output voltage signal, adaptively Adjust the output voltage signal.

(2) The present invention also discloses a flat display, which includes a flat display panel, a gate driver module, a source driver module, a display controller, and a power supply unit; it is characterized in that, the power supply unit includes The DC-DC conversion circuit of the present invention is described above.

(3) The present invention also discloses an information processing device having a central processing unit and the flat panel display of the present invention as described above. Moreover, the information processing device can be an electronic device selected from a group consisting of a smart phone, a smart watch, a smart bracelet, a tablet computer, a notebook computer, an all-in-one computer, and an access control device.

It must be emphasized that the above-mentioned disclosure in this case is a preferred embodiment, and any partial changes or modifications originating from the technical ideas of this case and easily inferred by those who are familiar with the art are within the scope of the patent of this case. category of rights.

To sum up, regardless of the purpose, means and effect of this case, it shows that it is completely different from the conventional technology, and its first invention is practical, and it does meet the patent requirements of the invention. Society is to pray for the best.

1a: AMOLED panel 2a: Gate driver module 3a: source driver module 4a: Display Controller 5a: Power supply unit Cia: input capacitance Coa: output capacitance Cra: first capacitor Cea: the second capacitor L1a: Inductance Q2a: first NMOS element Q1a: first PMOS element Qca: Second NMOS element Qsa: Second PMOS element A1a: Operational Amplifier A2a: Error Amplifier A3a: Comparator Rf1a: first divider resistor Rf2a: second voltage divider resistor Rra: first resistance Rea: second resistor Ira: current source S1a: switching element 51a: Oscillator 52a: RS flip-flop 53a: Drive unit 1: DC-DC conversion circuit 10: circuit input 11: circuit output 12: Current sensing unit 121: First End 122: Second End 123: Third End 124: Fourth End 13: Voltage sensing unit 131: First End 132: Second End 14: Control unit 141: First End 142: Second End 143: Third End 144: Fourth End 145: Fifth End 146: Sixth End 14OC: Oscillator 14RS:RS flip-flop 14DR: Drive unit 15: The first current pull-down unit 151: First End 152: Second End 16: Current source 17: The second current pull-down unit 171: First End 172: Second End 18: Analog Multiplier 181: First End 182: Second End 183: Third End 19: Class load current detection unit Ci: input capacitance Co: output capacitance Cr: first capacitor Ce: second capacitor L1: Inductance Q2: The first NMOS element Q1: The first PMOS element Qc: the third PMOS element Qs: Second PMOS element Ap1: The first operational transconductance amplifier Ap2: Second Op-Transduct Amplifier A1: Operational Amplifier A2: Error Amplifier A3: Comparator Rf1: The first voltage divider resistor Rf2: The second voltage divider resistor Rr: first resistance Re: second resistor S1: Switching element

FIG. 1 is a schematic diagram of a conventional AMOLED display; Fig. 2 is a circuit topology diagram of a conventional power supply unit; 3 is a working timing diagram of an input voltage signal and an output voltage signal of the conventional power supply unit shown in FIG. 2; FIG. 4 is a working timing diagram of the actual measurement of the error signal, the sawtooth wave voltage signal and the output voltage signal of the conventional power supply unit shown in FIG. 2; 5 is a block diagram of a first embodiment of a DC-DC conversion circuit according to the present invention; 6 is a circuit topology diagram of the first embodiment of the DC-DC conversion circuit of the present invention; 7 is a timing chart of the actual measurement operation of the error signal, the sawtooth wave voltage signal and the output voltage signal of the first embodiment of the DC-DC conversion circuit of the present invention shown in FIG. 6; FIG. 8 is a timing chart of the actual measurement operation of the output voltage signal of the first embodiment of the DC-DC conversion circuit of the present invention shown in FIG. 6 under different load currents; 9 is a block diagram of a second embodiment of a DC-DC conversion circuit according to the present invention; 10 is a circuit topology diagram of a second embodiment of the DC-DC conversion circuit of the present invention; and FIG. 11 is a timing chart of the actual measurement operation of the output voltage signal of the second embodiment of the DC-DC conversion circuit of the present invention shown in FIG. 10 under different load currents.

1: DC-DC conversion circuit 10: circuit input 11: circuit output 12: Current sensing unit 121: First End 122: Second End 123: Third End 124: Fourth End 13: Voltage sensing unit 131: First End 132: Second End 14: Control unit 141: First End 142: Second End 143: Third End 144: Fourth End 145: Fifth End 146: Sixth End 15: The first current pull-down unit 151: First End 152: Second End 16: Current source Ci: input capacitance Co: output capacitance L1: Inductance Q2: The first NMOS element Q1: The first PMOS element

Claims (10)

A DC-DC conversion circuit, comprising: a power transmission unit for converting an input voltage into an output voltage according to the control of a PWM signal; a current sensing unit for inducting current according to an inductance of the power transmission unit a proportional to generate an inductor sensing current; a control unit for determining the duty cycle of the PWM signal according to a feedback voltage and an input sensing current, the feedback voltage is proportional to the output voltage; and a first a current pull-down unit for generating a first feed-forward pull-down current according to the input voltage; wherein the sum of the input sensing current and the first feed-forward pull-down current is equal to the inductor sensing current. The DC-DC conversion circuit of claim 1, wherein the first current pull-down unit comprises a first operational transconductance amplifier having a positive input terminal, a negative input terminal and an output terminal, wherein the positive input terminal The terminal is coupled to the input voltage, the negative input terminal is coupled to a ground terminal, and the output terminal generates the first feed-forward pull-down current. The DC-DC conversion circuit of claim 1, wherein the current sensing unit has a first end, a second end, a third end and a fourth end, and includes: a second PMOS element , with a drain terminal as the first terminal of the current sensing unit, and a gate terminal as the second terminal of the current sensing unit; an operational amplifier with a positive input terminal and a negative input terminal and an output terminal, wherein the positive input terminal is coupled to a source terminal of the second PMOS element, and the negative input terminal serves as the third terminal of the current sensing unit; and a third PMOS element with a drain The terminal is simultaneously coupled to the positive input terminal of the operational amplifier and the source terminal of the second PMOS element, a gate terminal thereof is coupled to the output terminal of the operational amplifier, and a source terminal thereof is used as the current sensing unit of the fourth end. The DC-DC conversion circuit of claim 1, wherein the feedback voltage is provided by a voltage sensing unit, and the voltage sensing unit includes a first voltage dividing resistor and a first voltage divider in a series configuration Two divider resistors. The DC-DC conversion circuit of claim 4, wherein the control unit comprises: an error amplifier having a positive input terminal, a negative input terminal and an output terminal, the positive input terminal and the negative input terminal are respectively coupled the feedback voltage and a reference voltage are connected, and the output terminal is used to provide an error signal generated according to the difference between the feedback voltage and the reference voltage; a comparator has a positive input terminal and a negative input terminal and an output terminal, the negative input terminal is coupled to the output terminal of the error amplifier, and the positive input terminal is coupled to a sawtooth voltage signal; a first capacitor has a first terminal and a second terminal, the The first end is coupled to the positive input end of the comparator; a first resistor is coupled between the second end of the first capacitor and a ground end; a switch element has a channel, the channel is coupled between the first end and the second end of the first capacitor, and the switch element is controlled by a reset signal to enable/disable the channel; an RS flip-flop has a first input end, a a second input terminal and an output terminal, wherein the first input terminal is coupled to the output terminal of the comparator, and the second input terminal is coupled to a clock signal transmitted from an oscillator; and a driving unit having an input terminal, a first output terminal and a second output terminal, wherein the input terminal is coupled to the output terminal of the RS flip-flop, and the first output terminal and the second output terminal output the PWM signal respectively and the complement of this PWM signal. The DC-DC conversion circuit of claim 5, wherein the DC level of the sawtooth voltage signal is determined by the voltage established by the input sensing current on the first resistor. A DC-DC conversion circuit has an input terminal coupled to an input voltage and an output terminal to provide an output voltage, and includes a power transmission unit to periodically control the power of the input voltage according to a PWM signal It is transmitted to the output end, and a control unit generates the PWM signal according to a feedback voltage and an input sensing current, wherein the feedback voltage is generated according to a ratio of the output voltage, and is characterized in that: The control unit has a voltage-to-current unit to generate a first sensing current proportional to the input voltage, and the sum of the first sensing current and the input sensing current is equal to the sum of an inductance in the power transmission unit a second sense current. A DC-DC conversion circuit, comprising: a power transmission unit for converting an input voltage into an output voltage according to the control of a PWM signal; a current sensing unit for inducting current according to an inductance of the power transmission unit A ratio generates an inductor sensing current; a control unit is used to determine the duty cycle of the PWM signal according to a feedback voltage and an input sensing current, the feedback voltage is proportional to the output voltage; a first a current pull-down unit for generating a first feed-forward pull-down current according to the input voltage; and a second current pull-down unit for generating a second feed-forward pull-down current according to an output voltage of the analog multiplier, the output voltage It is generated according to the product of the input voltage and a sensing voltage of a load current; wherein the sum of the input sensing current, the first feed-forward pull-down current and the second feed-forward pull-down current is equal to the inductor sensing current. The DC-DC conversion circuit of claim 8, wherein the second current pull-down unit comprises a second operational transconductance amplifier having a positive input terminal, a negative input terminal and an output terminal, wherein the positive input terminal The terminal is coupled to the output voltage of the analog multiplier, the negative input terminal is coupled to a ground terminal, and the output terminal is used for providing the second feed-forward pull-down current. An information processing device has a central processing unit and a flat panel display, the flat panel display includes a flat panel display panel, a gate driver module, a source driver module, a display controller, and a power supply unit; It is characterized in that, the power supply unit includes the DC-DC conversion circuit according to any one of the claims 1 to 9, and the information processing device is composed of a smart phone, a smart watch, a smart bracelet, a tablet computer, a notebook An electronic device selected from the group consisting of a computer, an all-in-one computer, and an access control device.

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