CN203596745U - DC-DC controller - Google Patents

DC-DC controller Download PDF

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Publication number
CN203596745U
CN203596745U CN201320722906.5U CN201320722906U CN203596745U CN 203596745 U CN203596745 U CN 203596745U CN 201320722906 U CN201320722906 U CN 201320722906U CN 203596745 U CN203596745 U CN 203596745U
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China
Prior art keywords
mentioned
signal
slope
ramp signal
controller
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Expired - Lifetime
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CN201320722906.5U
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Chinese (zh)
Inventor
郑闳轩
陈雅萍
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UPI Semiconductor Corp
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UPI Semiconductor Corp
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Abstract

The utility model discloses a direct current to current controller. The DC-DC controller includes an error amplifier, a ramp signal generator, a slope detection unit, a signal synthesis unit and a control unit. The error amplifier provides an error signal. The ramp signal generator provides a first ramp signal. The slope detection unit receives the error signal to provide a slope detection signal through the error signal. The signal synthesis unit synthesizes the first ramp signal and the slope detection signal into a second ramp signal. The control unit generates a pulse width modulation signal through the error signal and the second ramp signal.

Description

Direct current is to DC controller
Technical field
The utility model is relevant with power supply changeover device, particularly can produce slope detection signal according to error signal and changes the decline of ramp signal and the direct current of the rate of rise to DC controller, to promote its instantaneous velocity of reaction about a kind of.
Background technology
In recent years, power supply circuit has been widely used on different electronic products, such as portable electronic product, computer product etc.Power supply circuit can provide voltage or current conversion or provide the electric power with fixed voltage or electric current to use for electronic product.In power supply circuit, power IC (Power integrated circuit, Power IC) is one of necessary active member.
In at present traditional direct current to the operation configuration of DC power converter under, in transient response, because traditional ramp generator still can produce ramp signal constantly, in the time that ramp signal rises to higher position by its bottom, it is large that distance between ramp signal and error signal becomes, if it is again crossing with ramp signal that error signal is wanted, need expend the longer time, the time point that makes its ON time generator get ON time is slower, thereby cause the upper bridge switch of its output stage to be switched on more slowly, therefore its transient response speed is slower, therefore urgently improve.
Utility model content
Therefore, the utility model discloses a kind of direct current to DC controller, the problems referred to above that suffered to solve prior art.
Be that a kind of direct current is to DC controller according to a specific embodiment of the present utility model.In this embodiment, direct current comprises error amplifier, ramp signal generator, slope detecting unit, signal synthesis unit and control unit to DC controller.Slope detecting unit couples error amplifier.Signal synthesis unit couples ramp signal generator and slope detecting unit.Error amplifier provides an error signal.Ramp signal generator provides one first ramp signal.Slope detecting unit receives error signal so that a slope detection signal to be provided by error signal.Synthetic the first ramp signal of signal synthesis unit and slope detection signal become one second ramp signal.Control unit produces a pulse-width modulation signal by error signal and the second ramp signal.
In an embodiment, control unit comprises a comparator, and it couples ramp signal generator and signal synthesis unit.
In an embodiment, the slope of the second ramp signal is different from the slope of the first ramp signal.
In an embodiment, in the time that the first ramp signal and slope detection signal are synthesized the second ramp signal by signal synthesis unit, signal synthesis unit changes the slope of the first ramp signal to form the second ramp signal by slope detection signal, make the slope of the second ramp signal different from the slope of the first ramp signal.
In an embodiment, slope detecting unit comprises a differential circuit.
In an embodiment, slope detecting unit comprises a phase-lead treatment circuit.
In an embodiment, slope detecting unit comprises a first transistor switch, an electric capacity and a current source.The control end of the first transistor switch couples error amplifier.
In an embodiment, slope detecting unit comprises a first transistor switch, an electric capacity and a current source, the control end of the first transistor switch couples error amplifier, with by the operation of error signal control the first transistor switch, in order to providing slope detection signal with electric capacity and current source.
In an embodiment, signal synthesis unit comprises a transistor seconds switch and a resistance.The control end of transistor seconds switch couples ramp signal generator.
In an embodiment, control unit comprises a comparator and an ON time generator.Two inputs of comparator couple respectively slope detecting unit and signal synthesis unit.One output of comparator couples ON time generator, comparator comparison error signal and the second ramp signal, and produce pulse-width modulation signal according to comparative result control ON time generator.
In an embodiment, direct current also comprises one first current mirror and one second current mirror that are coupled to each other to DC controller.The first current mirror is coupled between an operating voltage and slope detecting unit.The second current mirror is coupled between signal synthesis unit and earth terminal.The slope detection signal that slope detecting unit produces produces to signal synthesis unit by the first current mirror and the second current mirror.
In an embodiment, direct current also comprises output and output capacitance to DC controller.Output is in order to provide an output signal.Output capacitance is coupled between output and earth terminal.Output capacitance is multilayer ceramic capacitor (Multi-layer Ceramic Capacitor, MLCC).
Compared to prior art, the direct current that the utility model proposes utilizes its output transient load to DC controller and takes out and carries a time error signal and have the significantly characteristic of slope variation, will after error signal differential, synthesize error signal slope variation is reacted to more sensitive new ramp signal with traditional ramp signal.Therefore, when the output transient load of direct current to DC controller or take out while carrying, new ramp signal can be comparatively fast crossing with error signal, therefore can improve system instantaneous velocity of reaction, the phenomenon that reduces power supply output overshoot (overshoot) occurs, to improve stiffness of system.
Can be further understood by following utility model detailed description and accompanying drawing about advantage of the present utility model and spirit.
Accompanying drawing explanation
Fig. 1 diagram is the schematic diagram to DC controller according to the direct current of a preferred embodiment of the present utility model.
Slope detecting unit 14 in Fig. 2 pictorial image 1 and an embodiment of signal synthesis unit 18.
Fig. 3 A illustrates the output voltage V of the direct current operating under normal condition to DC controller oUTwaveform sequential chart.
Fig. 3 B illustrates the waveform sequential chart of the first switch controlling signal S1 of the direct current operating under normal condition to DC controller.
Fig. 3 C diagram operates on direct current under normal condition error signal Vcomp, the first ramp signal Vramp to DC controller and the waveform sequential chart of the second ramp signal Vramprc.
Fig. 4 A diagram operates on direct current under the instantaneous output voltage V to DC controller oUTwaveform sequential chart.
Fig. 4 B diagram operates on the waveform sequential chart of direct current under instantaneous the first switch controlling signal S1 to DC controller.
Fig. 4 C diagram operates on direct current under instantaneous error signal Vcomp, the first ramp signal Vramp to DC controller and the waveform sequential chart of the second ramp signal Vramprc.
Main element symbol description:
1: direct current is to DC controller
10: error amplifier
12: compensating unit
14: slope detecting unit
16: ramp signal generator
18: signal synthesis unit
CT: control unit
24: driver element
26: output stage
28: output
L oUT: outputting inductance
R oUT: output resistance
C oUT: output capacitance
V oUT: output voltage
R1: the first divider resistance
R2: the second divider resistance
20: comparator
22: ON time generator
SW1: the first output switch
SW2: the second output switch
+: positive input terminal
-: negative input end
J, K: output
V rEF: reference voltage
V fB: feedback voltage
V iN: input voltage
Vcomp: error signal
Vramp: ramp signal
Vramprc: the second ramp signal
Id: slope detection signal
V dD: operating voltage
CM1: the first current mirror
CM2: the second current mirror
MNC: the first transistor switch
Cd: electric capacity
I: current source
MP1~MP4:P transistor npn npn switch
MN1~MN4:N transistor npn npn switch
MNR: transistor seconds switch
R: resistance
T oN: ON time
S1: the first switch controlling signal
S2: second switch control signal
T1~t4: very first time point~four time point
PWM: pulse-width modulation signal
Embodiment
Be that a kind of direct current is to DC controller according to a preferred embodiment of the present utility model.In fact, the direct current the utility model proposes can be to be applied to the direct current with constant on-time framework in power IC (Power IC) to DC power converter to DC controller, but not as limit.The utility model is also applicable to exchanging DC power converter or direct current in the framework of the power-switching circuits such as AC power transducer.
As shown in Figure 1, direct current comprises error amplifier 10, compensating unit 12, slope detecting unit 14, ramp signal generator 16, signal synthesis unit 18, control unit CT, driver element 24, output stage 26, outputting inductance L to DC controller 1 oUT, output resistance R oUT, output capacitance C oUT, output 28, the first divider resistance R1 and the second divider resistance R2.Wherein, control unit CT comprises comparator 20 and ON time generator 22; Output stage 26 comprises the first output switch SW1 and the second output switch SW2.In practical application, output capacitance C oUTcan adopt the multilayer ceramic capacitor (Multi-layer Ceramic Capacitor, MLCC) of higher-order, but not as limit.
The positive input terminal of error amplifier 10+couple reference voltage V rEF; The negative input end of error amplifier 10-be coupled between the first divider resistance R1 and the second divider resistance R2; The output K of error amplifier 10 be coupled to respectively the positive input terminal of compensating unit 12, slope detecting unit 14 and comparator 20+; Compensating unit 12 couples output K and the earth terminal of error amplifier 10; Slope detecting unit 14 couples output K and the signal synthesis unit 18 of error amplifier 10; Ramp signal generator 16 couples signal synthesis unit 18; Signal synthesis unit 18 couple the negative input end of comparator 20-; The output J of comparator 20 couples ON time generator 22; ON time generator 22 couples driver element 24; Driver element 24 couples respectively the first output switch SW1 and the second output switch SW2 of output stage 26; Outputting inductance L oUTone end be coupled between the first output switch SW1 and the second output switch SW2; Outputting inductance L oUTthe other end couple output 28; Output resistance R oUTcouple output 28; Output capacitance C oUTbe coupled to output resistance R oUTand between earth terminal; The first divider resistance R1 couples output 28; The second divider resistance R2 is coupled between the first divider resistance R1 and earth terminal.
The positive input terminal of error amplifier 10+and negative input end-receive respectively reference voltage V rEFand the first feedback voltage V between divider resistance R1 and the second divider resistance R2 fB, and according to reference voltage V rEFwith feedback voltage V fBafter producing error signal Vcomp, export by output K.In fact, error amplifier 10 can be with reference to voltage V rEFdeduct feedback voltage V fBand this voltage difference is enlarged into error signal Vcomp, but not as limit.Reference voltage V rEFit can be a preset value.Feedback voltage V fBthe output voltage V output 28 of DC controller 1 being provided for direct current oUTdividing potential drop, that is feedback voltage V fB=[R2/ (R1+R2)] * V oUT.Compensating unit 12 is in order to carry out suitable compensation to error signal Vcomp.
In this embodiment, slope detecting unit 14 comprises differential circuit/phase-lead treatment circuit.Slope detecting unit 14 can receive error signal Vcomp from the output K of error amplifier 10, and error signal Vcomp is carried out to differential or Phase Processing, to produce slope detection signal Id to signal synthesis unit 18.Signal synthesis unit 18 receives the first ramp signal Vramp and receives slope detection signal Id from slope detecting unit 14 from ramp signal generator 16, and synthetic the first ramp signal Vramp and slope detection signal Id become the second ramp signal Vramprc.In fact, in the time that the first ramp signal Vramp and slope detection signal Id are synthesized the second ramp signal Vramprc by signal synthesis unit 18, signal synthesis unit 18 changes the slope of the first ramp signal Vramp to form the second ramp signal Vramprc by slope detection signal Id, make the slope of the second ramp signal Vramprc different from the slope of the first ramp signal Vramp.
Please refer to Fig. 2, the slope detecting unit 14 in Fig. 2 pictorial image 1 and an embodiment of signal synthesis unit 18.As shown in Figure 2, the first current mirror CM1 is coupled to operating voltage V dDand between slope detecting unit 14, the second current mirror CM2 is coupled between signal synthesis unit 18 and earth terminal.The slope detection signal Id that slope detecting unit 14 produces produces to signal synthesis unit 18 by the first current mirror CM1 and the second current mirror CM2.
In this embodiment, slope detecting unit 14 comprises the first transistor switch MNC, capacitor C d and current source I.Current source I is coupled between the first transistor switch MNC and earth terminal; Capacitor C d is coupled between the first transistor switch MNC and earth terminal; Current source I is in parallel with capacitor C d.The gate of the first transistor switch MNC receives error signal Vcomp from the output K of error amplifier 10, and by the operation of error signal Vcomp control the first transistor switch MNC, in order to slope detection signal (differential current) Id is provided with electric capacity MNC and current source I.
The first current mirror CM1 and the second current mirror CM2 comprise respectively four P transistor npn npn switch MP1~MP4 and four N-type transistor switch MN1~MN4.The gate of four P transistor npn npn switch MP1~MP4 of the first current mirror CM1 is all coupled between the first current mirror CM1 and slope detecting unit 14.P transistor npn npn switch MP1 and MP2 are serially connected with operating voltage V dDand between slope detecting unit 14; P transistor npn npn switch MP3 and MP4 are serially connected with operating voltage V dDand between the second current mirror CM2.The gate of four N-type transistor switch MN1~MN4 of the second current mirror CM2 is all coupled between the first current mirror CM1 and the second current mirror CM2.N-type transistor switch MN1 and MN2 are serially connected with between the first current mirror CM1 and earth terminal; N-type transistor switch MN3 and MN4 are serially connected with between signal synthesis unit 18 and earth terminal.
Slope detection signal (differential current) Id that slope detecting unit 14 produces can first produce to the second current mirror CM2 by P transistor npn npn switch MP1~MP4 of the first current mirror CM1, then produces to signal synthesis unit 18 by N-type transistor switch MN1~MN4 of the second current mirror CM2.
Signal synthesis unit 18 comprises transistor seconds switch MNR and resistance R.Transistor seconds switch MNR is coupled to operating voltage V dDand between resistance R.The gate of transistor seconds switch MNR receives the first ramp signal Vramp from ramp signal generator 16, and slope detection signal (differential current) the Id resistance R of flowing through produces a voltage drop (Id*R), the second ramp signal Vramprc producing according to the first ramp signal Vramp and slope detection signal Id is the first ramp signal Vramp and deducts above-mentioned voltage drop (Id*R).
Then, the positive input terminal of comparator 20+receive the negative input end of error signal Vcomp and comparator 20-receive the second ramp signal Vramprc from signal synthesis unit 18 from the output K of error amplifier 10.Comparator 20 is in order to the size of comparison error signal Vcomp and the second ramp signal Vramprc, and outputs control signals to ON time generator 22 according to comparative result by output J, produces and comprises ON time T to control ON time generator 22 oNpulse-width modulation signal PWM to driver element 24.Driver element 24 is optionally exported the first output switch SW1 of the first switch controlling signal S1 to output stage 26 according to pulse-width modulation signal PWM, or output second switch control signal S2 is to the second output switch SW2 of output stage 26, controls thus the first output switch SW1 of output stage 26 and the unlatching of the second output switch SW2 or closes.
Please refer to Fig. 3 A to Fig. 3 C, Fig. 3 A illustrates the output voltage V of the direct current operating under normal condition to DC controller oUTwaveform sequential chart.Fig. 3 B illustrates the waveform sequential chart of the first switch controlling signal S1 of the direct current operating under normal condition to DC controller.Fig. 3 C diagram operates on direct current under normal condition error signal Vcomp, the first ramp signal Vramp to DC controller and the waveform sequential chart of the second ramp signal Vramprc.As seen from the figure, in the time that error signal Vcomp increases, the second ramp signal Vramprc can come lowly by the first ramp signal Vramp originally; In the time that error signal Vcomp diminishes, the second ramp signal Vramprc can become greatly, even also high than the first ramp signal Vramp originally.
Also please refer to Fig. 4 A to Fig. 4 C, Fig. 4 A diagram operates on direct current under the instantaneous output voltage V to DC controller oUTwaveform sequential chart.Fig. 4 B diagram operates on the waveform sequential chart of direct current under instantaneous the first switch controlling signal S1 to DC controller.Fig. 4 C diagram operates on direct current under instantaneous error signal Vcomp, the first ramp signal Vramp to DC controller and the waveform sequential chart of the second ramp signal Vramprc.
Because error amplifier 10 is according to reference voltage V rEFdeduct feedback voltage V fBproduce error signal Vcomp, and feedback voltage V fBthe output voltage V output 28 of DC controller 1 being provided for direct current oUTdividing potential drop, when direct current is during to output 28 transient load of DC controller 1, the output voltage V of direct current to DC controller 1 oUTstart to diminish, it is large that error signal Vcomp can become, slope detection signal (differential current) Id that error signal Vcomp produces capacitor C d by the first transistor switch MNC also can become large, and slope detection signal (differential current) the Id voltage drop (Id*R) that resistance R produces of flowing through also becomes large thereupon, so deducting the second ramp signal Vramprc of voltage drop (Id*R) gained according to the first ramp signal Vramp can decline sooner on the contrary, that is the descending slope of the second ramp signal Vramprc can be greater than the descending slope of the first ramp signal Vramp originally.
The descending slope that becomes large and the second ramp signal Vramprc due to error signal Vcomp becomes large, will make error signal Vcomp to rise to the second ramp signal Vramprc and to equate at time point (as the very first time point t1 in Fig. 4 C) faster.If adopt the first ramp signal Vramp originally, because the descending slope of the first ramp signal Vramp is less, so error signal Vcomp must wait until that slower time point (as the second time point t2 in Fig. 4 C) can rise to the first ramp signal Vramp and equate.
In very first time point t1, comparator 20 decision errors signal Vcomp equate with the second ramp signal Vramprc, can export control signal control ON time generator 22 and produce pulse-width modulation signal PWM to driver element 24, the the first output switch SW1 that makes driver element 24 export the first switch controlling signal S1 control output stage 26 according to pulse-width modulation signal PWM opens, therefore can accelerate the instantaneous velocity of reaction of direct current to DC controller 1, with effective elevator system stability.
In the time that direct current unloads the output 28 of DC controller 1, the output voltage V of direct current to DC controller 1 oUTstart to increase, error signal Vcomp can diminish, slope detection signal (differential current) Id that error signal Vcomp produces capacitor C d by the first transistor switch MNC also can diminish, the voltage drop (Id*R) that resistance R produces and slope detection signal (differential current) Id flows through also diminishes thereupon, so deducting the second ramp signal Vramprc of voltage drop (Id*R) gained according to ramp signal Vramp can rise sooner on the contrary, that is the rate of rise of the second ramp signal Vramprc can be greater than the rate of rise of the first ramp signal Vramp originally.
Because error signal Vcomp diminishes and the rate of rise of the second ramp signal Vramprc becomes large, will make error signal Vcomp to drop to the second ramp signal Vramprc and to equate at time point (as the 3rd time point t3 in Fig. 4 C) faster.If adopt the first ramp signal Vramp originally, because the rate of rise of the first ramp signal Vramp is less, error signal Vcomp must wait until that slower time point (as the 4th time point t4 in Fig. 4 C) can drop to the first ramp signal Vramp and equate.
In the 3rd time point t3, comparator 20 decision errors signal Vcomp equate with the second ramp signal Vramprc, can export control signal control ON time generator 22 and produce pulse-width modulation signal PWM to driver element 24, the the first output switch SW1 that makes driver element 24 export the first switch controlling signal S1 control output stage 26 according to pulse-width modulation signal PWM closes, therefore can accelerate the instantaneous velocity of reaction of direct current to DC controller 1, with effective elevator system stability.
Compared to prior art, the direct current that the utility model proposes utilizes its output transient load to DC controller and takes out and carries a time error signal and have the significantly characteristic of slope variation, will after error signal differential, synthesize error signal slope variation is reacted to more sensitive new ramp signal with traditional ramp signal.Therefore, when the output transient load of direct current to DC controller or take out while carrying, new ramp signal can be comparatively fast crossing with error signal, therefore can improve system instantaneous velocity of reaction, the phenomenon that reduces power supply output overshoot (overshoot) occurs, to improve stiffness of system.
By the above detailed description of preferred embodiments, be to wish more to know to describe feature of the present utility model and spirit, and not with above-mentioned disclosed preferred embodiment, category of the present utility model limited.On the contrary, its objective is that hope can contain in the category of the scope of the claims that is arranged in the wish application of the utility model institute of various changes and tool equality.

Claims (12)

1. direct current, to a DC controller, is characterized in that, above-mentioned direct current comprises DC controller:
One error amplifier, provides an error signal;
One ramp signal generator, provides one first ramp signal;
One slope detecting unit, couples above-mentioned error amplifier, and receives above-mentioned error signal, so that a slope detection signal to be provided by above-mentioned error signal;
One signal synthesis unit, couples above-mentioned ramp signal generator and above-mentioned slope detecting unit, to synthesize above-mentioned the first ramp signal and above-mentioned slope detection signal becomes one second ramp signal; And
One control unit, couples above-mentioned error amplifier and above-mentioned signal synthesis unit, to produce a pulse-width modulation signal by above-mentioned error signal and above-mentioned the second ramp signal.
2. direct current as claimed in claim 1, to DC controller, is characterized in that, above-mentioned control unit comprises a comparator, and it couples above-mentioned ramp signal generator and above-mentioned signal synthesis unit.
3. direct current as claimed in claim 1, to DC controller, is characterized in that, the slope of above-mentioned the second ramp signal is different from the slope of above-mentioned the first ramp signal.
4. direct current as claimed in claim 1 is to DC controller, it is characterized in that, in the time that above-mentioned the first ramp signal and above-mentioned slope detection signal are synthesized above-mentioned the second ramp signal by above-mentioned signal synthesis unit, above-mentioned signal synthesis unit changes the slope of above-mentioned the first ramp signal to form above-mentioned the second ramp signal by above-mentioned slope detection signal, make the slope of above-mentioned the second ramp signal different from the slope of above-mentioned the first ramp signal.
5. direct current as claimed in claim 1, to DC controller, is characterized in that, above-mentioned slope detecting unit comprises a differential circuit.
6. direct current as claimed in claim 1, to DC controller, is characterized in that, above-mentioned slope detecting unit comprises a phase-lead treatment circuit.
7. direct current as claimed in claim 1, to DC controller, is characterized in that, above-mentioned slope detecting unit comprises a first transistor switch, an electric capacity and a current source, and the control end of above-mentioned the first transistor switch couples above-mentioned error amplifier.
8. direct current as claimed in claim 1 is to DC controller, it is characterized in that, above-mentioned slope detecting unit comprises a first transistor switch, an electric capacity and a current source, the control end of above-mentioned the first transistor switch couples above-mentioned error amplifier, with by the operation of the above-mentioned the first transistor switch of above-mentioned error signal control, in order to providing above-mentioned slope detection signal with above-mentioned electric capacity and above-mentioned current source.
9. direct current as claimed in claim 1, to DC controller, is characterized in that, above-mentioned signal synthesis unit comprises a transistor seconds switch and a resistance, and the control end of above-mentioned transistor seconds switch couples above-mentioned ramp signal generator.
10. direct current as claimed in claim 1 is to DC controller, it is characterized in that, above-mentioned control unit comprises a comparator and an ON time generator, two inputs of above-mentioned comparator couple respectively above-mentioned slope detecting unit and above-mentioned signal synthesis unit, one output of above-mentioned comparator couples above-mentioned ON time generator, the more above-mentioned error signal of above-mentioned comparator and above-mentioned the second ramp signal, and produce above-mentioned pulse-width modulation signal according to the above-mentioned ON time generator of comparative result control.
11. direct currents as claimed in claim 1 are to DC controller, it is characterized in that, also comprise one first current mirror and one second current mirror that are coupled to each other, above-mentioned the first current mirror is coupled between an operating voltage and above-mentioned slope detecting unit, above-mentioned the second current mirror is coupled between above-mentioned signal synthesis unit and earth terminal, and the above-mentioned slope detection signal that above-mentioned slope detecting unit produces produces to above-mentioned signal synthesis unit by above-mentioned the first current mirror and above-mentioned the second current mirror.
12. direct currents as claimed in claim 1 to DC controller, is characterized in that, also comprise:
One output, in order to provide an output signal; And
One output capacitance, is coupled between above-mentioned output and earth terminal,
Wherein above-mentioned output capacitance is multilayer ceramic capacitor.
CN201320722906.5U 2013-08-19 2013-11-13 DC-DC controller Expired - Lifetime CN203596745U (en)

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TW102215556 2013-08-19

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104682679A (en) * 2013-11-27 2015-06-03 力智电子股份有限公司 Power converter, slope detection controller and method of slope detection controller

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104682679A (en) * 2013-11-27 2015-06-03 力智电子股份有限公司 Power converter, slope detection controller and method of slope detection controller
CN104682679B (en) * 2013-11-27 2017-09-01 力智电子股份有限公司 Power supply changeover device and its slope detecting controller and method

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