CN218514287U - Conduction time control circuit, step-down DC converter, power management chip and wearable bluetooth device - Google Patents
Conduction time control circuit, step-down DC converter, power management chip and wearable bluetooth device Download PDFInfo
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- CN218514287U CN218514287U CN202220867613.5U CN202220867613U CN218514287U CN 218514287 U CN218514287 U CN 218514287U CN 202220867613 U CN202220867613 U CN 202220867613U CN 218514287 U CN218514287 U CN 218514287U
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Abstract
The utility model discloses a conduction time control circuit, step-down DC converter, power management chip and wearable bluetooth equipment, include: first timing module, comparator, variable resistance module and control voltage generation module, wherein: the first timing module comprises a first capacitor, one end of the first capacitor is an input end of the first timing module, and the other end of the first capacitor is grounded; the control end of the variable resistance module is connected to the output end of the control voltage generation module to receive the control voltage output by the control voltage generation module, so that the resistance value of the equivalent resistor of the variable resistance module is controlled to change along with the change of the control voltage, and the size of the timing current is changed; the control voltage generation module is used for outputting the changed control voltage to the control end of the variable resistance module according to a preset rule; and when the voltage of the first input end of the comparator and the voltage of the second input end of the comparator reach a preset condition, outputting a turn-off signal for turning off the synchronous tube to the digital logic control module. The disturbance of the switching frequency by the switching of the load state is reduced.
Description
Technical Field
The utility model relates to a switching power supply technical field, concretely relates to on-time control circuit and direct current converter who has it.
Background
The ACOT BUCK dc (adaptive constant on-time BUCK dc converter) is applied to various power supply systems requiring fast transient response as a BUCK type voltage-stabilizing dc converter having fast transient response, and the power supply provided by the DCDC is often required to have smaller output voltage ripple in these power supply systems, so as to be beneficial to the stability of the next application: such as a power supply for the bluetooth module.
Referring to fig. 1, a schematic diagram of a conventional ACOT BUCK DCDC circuit structure is shown, which has the following principle: the synchronous tube MP1 and the rectifier MN1 are periodically controlled by a loop to alternately conduct to generate a stable output voltage VOUT, for example, when the output voltage is lower than the set output voltage VOUT, the conduction duration of the synchronous tube MP1 needs to be increased, and the on-time ton of the synchronous tube MP1 is determined according to the input voltage VIN and the set output voltage VOUT; then, the synchronous tube MP1 is opened according to the determined opening time of the synchronous tube MP1, and the rectifier tube MN1 is closed at the same time, so that the voltage-stabilized output is realized.
The self-adaptive constant-on-time step-down direct-current converter can work in a continuous working mode and a discontinuous working mode respectively according to the size of a load, and the working modes can be switched when the load condition changes. However, switching in both load states can cause disturbances in the switching frequency.
Therefore, how to reduce the disturbance of the switching frequency caused by the switching of the load state becomes an urgent technical problem to be solved for the adaptive constant on-time buck dc converter.
SUMMERY OF THE UTILITY MODEL
Based on the above current situation, the present invention provides a conduction time control circuit and a dc converter having the same to reduce the disturbance of the switching frequency caused by the switching of the load state.
In order to achieve the above object, the utility model adopts the following technical scheme:
in a first aspect, an embodiment of the present invention discloses a conduction time control circuit for a self-adaptive constant conduction time step-down dc converter, including: first timing module, comparator, variable resistance module and control voltage generation module, wherein:
the first timing module comprises a first capacitor, one end of the first capacitor is an input end of the first timing module, and the other end of the first capacitor is grounded;
the input end of the variable resistance module is connected with the input voltage end of the direct current converter and used for receiving input voltage; the output end of the variable resistance module is connected to the input end of the first timing module and used for providing timing current for the first timing module and charging the first capacitor;
the control end of the variable resistance module is connected to the output end of the control voltage generation module to receive the control voltage output by the control voltage generation module, so that the resistance value of the equivalent resistor of the variable resistance module is controlled to change along with the change of the control voltage, and the size of the timing current is changed;
the input end of the control voltage generation module is connected with the input voltage end of the direct current converter; the control voltage generation module is used for outputting the changed control voltage to the control end of the variable resistance module according to a preset rule;
the first input end of the comparator is connected to the input end of the first timing module; the second input end of the comparator is used for receiving the output voltage of the direct current converter; the output end of the comparator is used for being connected with a digital logic control module in the direct current converter, so that when the voltage of the first input end of the comparator and the voltage of the second input end of the comparator reach a preset condition, a turn-off signal for turning off the synchronous tube is output to the digital logic control module.
Optionally, the variable resistance module comprises:
the control electrode of the transistor is the control end of the variable resistance module; the transistor operates in the variable resistance region under control of a control voltage.
Optionally, the variable resistance module further comprises: current mirror, first equivalent resistance and second equivalent resistance, wherein:
the input end of the current mirror is the input end of the variable resistance module; a first output branch of the current mirror is connected to one end of a first equivalent resistor, and the other end of the first equivalent resistor is grounded; the second output branch of the current mirror is connected to the input end of the first timing module;
one end of the second equivalent resistor is connected to the second pole of the transistor; the first pole of the transistor is connected to one end of the first equivalent resistor, and the other end of the second equivalent resistor is grounded.
Optionally, the variable resistance module further comprises: a current mirror and a first equivalent resistance, wherein:
the input end of the current mirror is the input end of the variable resistance module; a first output branch of the current mirror is connected to one end of a first equivalent resistor, and the other end of the first equivalent resistor is grounded;
the second output branch of the current mirror is connected to the input end of the first timing module;
the third output branch of the current mirror is connected to the first pole of the transistor, and the second pole of the transistor is connected to the input end of the first timing module.
Optionally, each transistor in the current mirror is a P-type transistor;
the transistor is an N-type transistor.
Optionally, each transistor in the current mirror is a P-type transistor;
the transistor is a P-type transistor.
Optionally, the variable resistance module further comprises: first divider resistance, second divider resistance, operational amplifier unit and N type transistor, wherein:
the first voltage-dividing resistor and the second voltage-dividing resistor are connected in series between the input voltage end of the direct current converter and the ground;
a first input end of the operational amplifier unit is connected to the connecting end of the first voltage-dividing resistor and the second voltage-dividing resistor; the second input end of the operational amplifier unit is connected to one end of the first equivalent resistor;
the first pole of the N-type transistor is connected to the first output branch of the current mirror, and the second pole of the N-type transistor is connected to one end of the first equivalent resistor; and the control electrode of the N-type transistor is connected to the output end of the operational amplifier unit.
Optionally, the first timing module further comprises:
and a release transistor having first and second poles connected to one end and the other end of the first capacitor, respectively, the release transistor turning off the first and second poles of the release transistor in response to a control signal during the on period of the sync pipe.
Optionally, the control voltage generation module includes: the circuit comprises a mirror current source, a second timing unit, a differential amplification unit, a transmission gate and an output capacitor;
the input end of the mirror current source is connected to the input voltage end of the direct current converter and used for receiving input voltage; the first output end of the mirror current source is grounded, and the second output end of the mirror current source is connected to the high potential end of the second timing unit;
the first input end and the second input end of the differential amplification unit are respectively connected to one and the other of the high-potential end and the reference voltage end of the second timing unit, and the differential amplification unit is used for comparing the voltages input by the first input end and the second input end of the differential amplification unit to obtain differential amplification current;
the output end of the differential amplification unit is connected to the input end of the transmission gate; the transmission gate is connected to one end of the output capacitor, and the other end of the output capacitor is grounded; in each timing period, the transmission gate conducts and transmits differential amplification current in a time window with a preset size;
one end of the output capacitor is used for outputting a control voltage.
Optionally, the mirror current source comprises: the circuit comprises a current source, a transistor, a timing resistor, a first mirror image branch and a second mirror image branch;
the input end of the current source is the input end of the mirror current source, the output end of the current source is connected to the first pole of the transistor, and the second pole of the transistor is grounded;
the input end of the first mirror image branch is connected to the input end of the current source, the output end of the first mirror image branch is connected to one end of the timing resistor, and the other end of the timing resistor is connected to the second pole of the transistor;
the input end of the second mirror image branch is connected to the input end of the current source, and the output end of the second mirror image branch is connected to the high potential end of the second timing unit.
Optionally, the differential amplifying unit includes: a first N-type transistor and a second N-type transistor;
the first pole of the first N-type transistor and the first pole of the second N-type transistor are connected to the input voltage end through respective P-type transistors; the first electrode of the second N-type transistor is the output end of the differential amplification unit;
the second pole of the first N-type transistor and the second pole of the second N-type transistor are connected and grounded;
the control electrode of the first N-type transistor and the control electrode of the second N-type transistor are respectively a first input end and a second input end of the differential amplification unit.
Optionally, the control electrode of the first N-type transistor is connected to the high potential end of the second timing unit; the control electrode of the second N-type transistor is connected to the control electrode of the transistor.
Optionally, a control electrode of the second N-type transistor is connected to a high potential end of the second timing unit; the control electrode of the first N-type transistor is connected to the control electrode of the transistor.
Optionally, the width-to-length ratios of the transistors, the first N-type transistor, and the second N-type transistor are the same.
Optionally, the second timing unit comprises: a switch tube and a timing capacitor;
the first pole of the switch tube is connected with one end of the timing capacitor to obtain a high potential end of the second timing unit;
the second pole of the switch tube is grounded, and the other end of the timing capacitor is grounded;
the switch tube is used for responding to the timing reset signal to conduct after the transmission gate conducts the transmission differential amplification current so as to discharge the timing capacitor.
In a second aspect, an embodiment of the present invention discloses a self-adaptive constant on-time step-down dc converter, including:
the on-time control circuit disclosed in the first aspect.
The embodiment of the utility model discloses power management chip, include:
the on-time control circuit disclosed in the first aspect above.
In a fourth aspect, the embodiment of the utility model discloses a wearable bluetooth device, include:
a Bluetooth module;
the power management chip disclosed in the third aspect is configured to manage an adaptive constant on-time buck dc converter that supplies power to a bluetooth module.
[ PROBLEMS ] the present invention
According to the embodiment of the utility model discloses an on-time control circuit and have its direct current converter, the input end of variable resistance module is connected to the input voltage end of direct current converter for receiving input voltage; the first timing module comprises a first capacitor, one end of the first capacitor is an input end of the first timing module, and the other end of the first capacitor is grounded; the output end of the variable resistance module is connected to the input end of the first timing module and used for providing timing current for the first timing module and charging the first capacitor; when the voltage of the first input end of the comparator reaches the output voltage, the comparator outputs a turn-off signal; the control voltage generation module is used for outputting changed control voltage to the control end of the variable resistance module according to a preset rule, the resistance value of the equivalent resistance of the variable resistance module changes along with the change of the control voltage, so that the size of the timing current is gradually changed, the voltage of the first input end of the comparator is gradually changed, the time of the comparator outputting a turn-off signal is gradually changed, namely the turn-on time of the synchronous tube is gradually changed, when the direct current converter is switched into a state, the direct current converter can be gradually switched from one load state to another load state, and the disturbance of the load state switching on the switching frequency is reduced.
Other advantages of the present invention will be described in the detailed description, and those skilled in the art can understand the technical advantages brought by the technical features and technical solutions through the descriptions of the technical features and the technical solutions.
Drawings
Embodiments of the present invention will be described below with reference to the accompanying drawings. In the figure:
FIG. 1 is a schematic diagram of a conventional ACOT BUCK DCDC circuit;
FIG. 2 is a schematic diagram of a structure of a conduction time control circuit;
fig. 3 is a schematic diagram of a structure of an on-time control circuit for an adaptive constant on-time buck dc converter according to the present embodiment;
fig. 4 is a schematic diagram of another structure of the on-time control circuit disclosed in the present embodiment;
fig. 5 is a schematic diagram of an on-time control timing sequence disclosed in the present embodiment.
Detailed Description
The present invention will be described below based on examples, but the present invention is not limited to only these examples. In the following detailed description of the present invention, certain specific details are set forth in order to avoid obscuring the spirit of the present invention, well-known methods, procedures, flows, and components have not been described in detail.
Further, those of ordinary skill in the art will appreciate that the drawings provided herein are for illustrative purposes and are not necessarily drawn to scale.
Unless the context clearly requires otherwise, throughout the description and the claims, the words "comprise", "comprising", and the like are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is, what is meant is "including, but not limited to".
In the description of the present invention, it is to be understood that the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. In addition, in the description of the present invention, "a plurality" means two or more unless otherwise specified.
In this application, if it is not specifically stated that the first electrode (or the second electrode) of the transistor is a source (or a drain), the correspondence relationship between the first electrode and the second electrode and the source and the drain may be interchanged.
In order to reduce the disturbance to switching frequency because of the state switches among the self-adaptation constant on-time step-down DC converter, the embodiment of the utility model discloses an on-time control circuit and DC converter who has it, for the technical matter that technical personnel in the field understand, it is now right for the embodiment of the utility model discloses the technical problem who discovers is described further:
referring to fig. 1, a schematic diagram of a conventional ACOT BUCK DCDC circuit is shown, in which an adaptive constant on-time BUCK dc converter includes: synchronous pipe MP1 and rectifier tube MN1, digital logic control part and the conduction time control part that connect gradually, wherein: the connecting point of the synchronous tube MP1 and the rectifier tube MN1 obtains an output voltage VOUT after passing through the LRC circuit; the digital logic control part respectively controls the conduction states of the synchronous tube MP1 and the rectifier tube MN 1; the conduction time control part is connected to the digital logic control part and is used for outputting a control signal of the conduction time ton of the synchronous tube MP1 to the digital logic control part so as to control the conduction time ton of the synchronous tube MP 1.
The on-time control portion of fig. 1 is to implement the fixed period function, and the operating principle of the on-time control portion is to generate a synchronous tube on-time related to the output voltage VOUT and the input voltage VIN. The on-time ton of the synchronous tube MP1 is mainly calculated by the input voltage VIN and the set output voltage VOUT, and according to the relationship of the duty ratio, the fixed period can be determined:
ton＝VOUT/VIN*T
wherein VOUT is set output voltage; VIN is the input voltage, and T is the set period.
It should be noted that, in the following, the on-time control portion of the synchronous tube MP1 in fig. 1 is mainly described, and other reference numerals not described in fig. 1 are not described herein again, and the functions of each device module, such as the ripple compensation module, the transconductance amplifier EA and its reference voltage Vref, the loop compensation capacitors Cea1 and Cea, the feedback signal FB, etc., may be determined by referring to relevant data; the output voltage of the synchronizing tube MP1 may also be output after passing through the LRC circuit, and the feedback signal FB may also be obtained by dividing the voltage by the voltage dividing resistors R1 and R2.
Please refer to fig. 2, which is a schematic diagram of a structure principle of a turn-on time control circuit, and mainly includes an operational amplifier OP, a comparator, an N-type transistor N1, an N-type transistor N2, and a control signal hson _ N thereof, P-type transistors P1 and P2, voltage dividing resistors R1 and R2 (different from the voltage dividing resistor of fig. 1), a resistor R0, a capacitor C1, and the like, and specific connection relationships are shown in fig. 2 and will not be described herein again. The on-time control circuit shown in fig. 2 operates as follows:
the P-type transistors P1 and P2 form a current mirror, when the synchronous tube is turned on, the control signal hson _ N of the N-type transistor N2 is at a low level, a current I1 related to VIN is generated to charge the capacitor C1, when the voltage V1 of the capacitor C1 is equal to Vout, a turn-off signal ton _ rst is generated to turn off the synchronous tube, that is, the on-time ton of the synchronous tube is generated, as follows:
therefore, the required fixed period T can be obtained by adjusting the VIN partial pressure ratio, the ratio of R1 to R2, the value of R0, the ratio of the width-length ratio (w 1/l 1) of P1 to the width-length ratio (w 2/l 2) of MP 2.
In the fixed and fixed (output capacitance C, output inductance L) condition of external components and parts cycle, because the electric capacity that adopts now is ceramic paster electric capacity, the ESR is very little, neglects basically, and its output ripple is under continuous mode:
wherein Ipeak is the peak-to-peak current, T is the period, C is the output capacitance, L is the output inductance, and ton is the on-time of the synchronous tube.
It can be seen that when the input voltage and the output voltage are determined, the output ripple in the continuous mode is fixed, so that when the application condition is fixed, i.e. the external component and the period are determined, the output ripple in the continuous mode is fixed and is independent of the output load.
When the output load is relatively small, the DCDC enters a discontinuous mode, and the switching period of the DCDC is as follows:
wherein T is Is not For the period in the discontinuous mode, io is the output load current
The output ripple at this time is
Where Io is the output load current.
As can be seen from the above formula, when the input voltage and the output voltage are determined, under the condition that the application condition is fixed, that is, under the condition that the external devices (the capacitor C and the inductor L) are fixed, the period of the DCDC is not fixed any more in the discontinuous mode, so the ripple under the light load is mainly determined by the on-time ton and the load current Io of the synchronous tube, when the load current is smaller and smaller, the switching period is larger and larger, and the ripple is larger and larger.
The ripple variation is large at switching and the switching frequency of the DCDC also varies greatly, which will cause the DCDC to switch back and forth between different loads causing disturbances in the switching frequency at different loads.
In order to reduce the disturbance of load state switching to switching frequency, the embodiment of the utility model discloses a conduction time control circuit, please refer to fig. 3, for the disclosed conduction time control circuit structure principle schematic diagram that is used for self-adaptation constant conduction time step-down DC converter of this embodiment, this conduction time control circuit is used for self-adaptation constant conduction time step-down DC converter, can turn off the turn-off signal ton _ rst of synchronous pipe MP1 to digital logic control module output among the DC converter, this conduction time control circuit includes first timing module 1, comparator 2, variable resistance module 3 and control voltage generation module 4, wherein:
the first timing module 1 comprises a first capacitor C0, one end of the first capacitor C0 is an input end of the first timing module 1, and the other end of the first capacitor C0 is grounded;
the input end of the variable resistance module 3 is connected to the input voltage end of the direct current converter and is used for receiving an input voltage VIN; the output end of the variable resistance module 3 is connected to the input end of the first timing module 1, and is used for providing a timing current I1 to the first timing module 1 to charge the first capacitor C0. In a specific implementation, when the first timing module 1 receives the timing current I1, the input terminal (i.e., the high potential terminal) of the first timing module 1 generates a voltage V1 to ground.
The control terminal of the variable resistance module 3 is connected to the output terminal of the control voltage generation module 4 to receive the control voltage Vset output by the control voltage generation module 4, so as to control the resistance value of the equivalent resistor of the variable resistance module to change along with the change of the control voltage Vset, thereby changing the magnitude of the timing current I1.
The input end of the control voltage generation module 4 is connected with the input voltage end of the direct current converter; the control voltage generating module 4 is configured to output the varying control voltage Vset to the control terminal of the variable resistance module 3 according to a preset rule.
A first input terminal of the comparator 2 is connected to an input terminal of the first timing module 1 to input a voltage to ground V1 at a high potential terminal of the first timing module 1; a second input end of the comparator 1 is used for receiving the output voltage VOUT of the dc converter; the output end of the comparator is used for connecting a digital logic control module in the direct current converter; when the voltage of the first input end of the comparator 2 has a relationship with the voltage of the second input end, which reaches a preset condition (for example, the voltage of the first input end reaches the voltage of the second input end), the comparator 2 outputs a turn-off signal ton _ rst for turning off the synchronous pipe MP1 to the digital logic control module. The turn-off signal ton _ rst can be high level or low level, and is specifically determined by a controlled transistor; conversely, when the voltage input by the first input terminal of the comparator 2 is smaller than the voltage input by the second input terminal, the output terminal of the comparator 2 outputs the conducting signal to control the controlled transistor to be maintained in the conducting state, in this embodiment, the time for which the synchronous transistor MP1 of the controlled transistor is continuously conducted is the conducting time ton.
In this embodiment, the resistance value of the equivalent resistor of the variable resistor module 3 is variable between the first resistance value and the second resistance value to change the magnitude of the timing current I1 provided by the first timing module 1. As can be seen from the above equations 1 to 4 and 5 to 8, the output ripple can be adjusted by configuring the equivalent resistance of the variable resistance module 3. For different load modes, the variable resistance module 3 should be adapted with different equivalent resistances to reduce the output ripple. In this embodiment, the resistance value of the equivalent resistor is variable between the first resistance value and the second resistance value, and the change from the first resistance value to the second resistance value (or from the second resistance value to the first resistance value) needs to be performed for a plurality of times. That is, the bidirectional variation between the first resistance value and the second resistance value is small step-wise, so that the timer current I1 gradually varies following the gradual variation of the equivalent resistance.
In an embodiment, each time the variation of the control voltage Vset is smaller than the predetermined value, the predetermined value can be determined empirically as long as the resistance of the equivalent resistor of the variable resistance module 3 needs to be changed from the first resistance to the second resistance (or from the second resistance to the first resistance) several times. In this embodiment, the variation of the control voltage Vset may be equal or unequal every time. In a specific implementation, the control voltage generation module 4 may change the magnitude of the control voltage Vset in small steps; the small step size may be determined empirically, and may be equal or different, as long as the control voltage Vset is satisfied to change from 0 to the maximum (or vice versa) through several changes.
Referring to fig. 3 and fig. 4, wherein fig. 4 is a schematic diagram of another structure of a turn-on time control circuit disclosed in this embodiment, the variable resistance module 3 includes: the transistor M0, the control electrode of the transistor M0 is the control end of the variable resistance module 3; the transistor M0 operates in the variable resistance region under the control of the control voltage Vset. In this embodiment, the transistor M0 operates in the variable resistance region under the control of the control voltage Vset, so that the equivalent resistance of the variable resistance module 3 changes following the change of the control voltage Vset.
In the embodiment, by using the non-saturation characteristic of the transistor, when the transistor is in the non-saturation state, the resistance of the transistor and, for example, V GS Roughly linear, and in particular, substantially inversely proportional. Therefore, when the control voltage Vset applied to the control electrode of the transistor M0 operates in the variable resistance region, the equivalent resistance of the transistor M0 decreases little by little as the control voltage Vset increases little by little; conversely, as the control voltage Vset decreases slightly, the equivalent resistance of the transistor M0 increases slightly. Thus, the transistor M0 is operated in the variable resistance region under the control of the control voltage Vset, so that the equivalent resistance gradually changes following the gradual change of the control voltage Vset.
In a specific implementation process, the variable resistance module 3 may be implemented by a parallel resistor, or may be implemented by a transistor, specifically:
in one embodiment, referring to fig. 3, the current mirror, the first equivalent resistor R10 and the second equivalent resistor R11, wherein:
the current mirror can be implemented by two P-type transistors (a transistor P1 and a transistor P2), specifically, a first pole of the P-type transistor P1 and a first pole of the P-type transistor P2 are connected as an input end of the current mirror, and the input end of the current mirror is an input end of the variable resistance module 3; the control electrode of the P type transistor P1 is connected with the control electrode of the P type transistor P2; the control electrode of the P-type transistor P1 is connected to the second electrode of the P-type transistor P1 to serve as a first output branch of the current mirror; the second pole of the P-type transistor P2 serves as the second output branch of the current mirror.
A first output branch of the current mirror is connected to one end of a first equivalent resistor R10, and the other end of the first equivalent resistor R10 is grounded; a second output branch of the current mirror is connected to an input end of the first timing module 1 and is used for providing timing current I1 for the timing module 1; one end of the second equivalent resistor R11 is connected to the second pole of the transistor M0; the first pole of the transistor M0 is connected to one end of the first equivalent resistor R10, and the other end of the second equivalent resistor R11 is grounded.
In another embodiment, referring to fig. 4, the variable resistance module 3 further includes: a current mirror and a first equivalent resistance R10, wherein:
the current mirror can be implemented by two P-type transistors (a transistor P1 and a transistor P2), specifically, a first pole of the P-type transistor P1 and a first pole of the P-type transistor P2 are connected as an input end of the current mirror, and the input end of the current mirror is an input end of the variable resistance module 3; the control electrode of the P-type transistor P1 is connected with the control electrode of the P-type transistor P2; the control electrode of the P-type transistor P1 is connected to the second electrode of the P-type transistor P1 to serve as a first output branch of the current mirror; the second pole of the P-type transistor P2 serves as the second output branch of the current mirror.
A first output branch of the current mirror is connected to one end of a first equivalent resistor R10, and the other end of the first equivalent resistor R10 is grounded; the second output branch of the current mirror is connected to the input end of the first timing module 1, and is used for providing a timing current I1 to the timing module 1.
In this embodiment, the current mirror further includes: the third output branch of the current mirror is connected to the first pole of the transistor M0, and the second pole of the transistor M0 is connected to the input terminal of the first timing module 1.
Specifically, the current mirror includes: a P-type transistor P3, a first pole of the P-type transistor P3 is connected to first poles of the P-type transistors P1 and P2 for receiving an input voltage VIN of the dc converter; the control electrode of the P-type transistor P3 is connected with the control electrodes of the P-type transistors P1 and P2; the second pole of the P-type transistor P3 serves as the third output branch of the current mirror.
In this embodiment, the P-type transistor P1, the P-type transistor P2 and the P-type transistor P3 form a current mirror, and the two poles of the P-type transistor P3 are connected in series with the two poles of the transistor M0, so that the conduction condition of the P-type transistor P3 is affected by the transistor M0, specifically, when the transistor M0 operates in the variable resistance region, the P-type transistor P3 also operates in the variable resistance region, thereby linearly changing the timing current I1 of the timing module 1, that is, changing the slope of V1. Therefore, the timing voltage V1 of the input terminal of the timing module 1 to the ground can be adjusted in small steps.
In the implementation process, the transistor M0 may be an N-type transistor or a P-type transistor. That is, in one embodiment, each transistor in the current mirror is a P-type transistor; the transistor M0 is an N-type transistor. In another embodiment, each transistor in the current mirror is a P-type transistor; the transistor M0 is a P-type transistor. When the transistor M0 is an N-type transistor or a P-type transistor, the conduction mode is different, and the application mode of the control voltage Vset is different.
Referring to fig. 3 and 4, the variable resistance module 3 further includes: first divider resistance R01, second divider resistance R02, operational amplifier unit and N type transistor N1, wherein:
the first voltage-dividing resistor R01 and the second voltage-dividing resistor R02 are connected in series between the input voltage end of the direct current converter and the ground; a first input end of the operational amplifier unit is connected to the connecting end of the first voltage-dividing resistor R01 and the second voltage-dividing resistor R02; a second input end of the operational amplifier unit is connected to one end of the first equivalent resistor R10; a first pole of the N-type transistor N1 is connected to a first output branch of the current mirror, and a second pole of the N-type transistor N1 is connected to one end of the first equivalent resistor R10; the control electrode of the N-type transistor N1 is connected to the output end of the operational amplifier unit. When the input voltage VIN is provided at the input voltage end of the dc converter, the operational amplifier unit turns on the first pole and the second pole of the N-type transistor N1, and at this time, the first equivalent resistor R10 is connected to the circuit; on the contrary, when there is no input voltage VIN, the operational amplifier unit turns off the first and second poles of the N-type transistor N1, and at this time, the first equivalent resistor R10 is out of operation. Therefore, the first equivalent resistor R10 can be automatically connected or automatically disconnected.
Referring to fig. 3 and fig. 4, the first timing module 1 further includes: release transistor N2, wherein:
the first and second poles of the release transistor N2 are connected to one and the other ends of the first capacitor C0, respectively, and the release transistor N2 turns off the first and second poles of the release transistor N2 in response to the control signal hson _ N during the on period of the sync pipe MP 1. In one embodiment, the release transistor N2 may be an N-type transistor, and the control signal hson _ N is at a low level when the sync pipe MP1 is turned on in response to a high level, whereas the control signal hson _ N is at a high level when the sync pipe MP1 is turned on in response to a low level. In other embodiments, the release transistor N2 may also be a P-type transistor, and the on/off signal is opposite to the on/off signal of the N-type transistor.
In this embodiment, the first capacitor C0 can be smoothly charged during the period when the dc converter supplies the timing current I1 to the first capacitor C0 by releasing the off control of the transistor N2.
Referring to fig. 3 and 4, the control voltage generation module 4 includes: a mirror current source 41, a second timing unit 42, a differential amplification unit 43, a transmission gate 44, and an output capacitor C1, wherein:
an input terminal of the mirror current source 41 is connected to an input voltage terminal of the dc converter for receiving an input voltage VIN; a first output terminal of the mirror current source 41 is grounded, and a second output terminal of the mirror current source 41 is connected to the high potential terminal of the second timing unit 42, for providing a charging current to the second timing unit 42, so that the high potential terminal of the second timing unit 42 obtains a timing voltage Vt;
a first input terminal and a second input terminal of the differential amplifying unit 43 are respectively connected to one and the other of a high potential terminal and a reference voltage terminal of the second timing unit 42, wherein the reference voltage terminal is used for providing a reference voltage Vref _ t; the differential amplifying unit 43 is configured to compare voltages input by the first input terminal and the second input terminal of the differential amplifying unit to obtain a differential amplifying current; that is, the differential amplifying unit 43 differentially amplifies the clocking voltage Vt and the reference voltage Vref _ t and outputs a differential amplified current;
the output terminal of the differential amplifying unit 43 is connected to the input terminal of the transmission gate 44; the transmission gate 44 is connected to one end of the output capacitor C1, and the other end of the output capacitor C1 is grounded; in each timing period, the transmission gate 44 conducts and transmits the differential amplification current in a time window with a preset size; one end of the output capacitor C1 is used for outputting the control voltage Vset. In this embodiment, the transmission gate 44 turns on the transmission differential amplification result in a small step to charge or discharge the output capacitor C1 in a small step, so that one end of the output capacitor C1 changes the magnitude of the control voltage Vset in a small step. In a specific embodiment, the time window with the preset size may be determined according to practical experience, and generally, the time window is much smaller than the switching period of the sync pipe MP1, for example, it may be one-N times of the switching period of the sync pipe MP1, where N > 3;
as an example, the differential amplifying unit 43 compares the timing voltage Vt with the reference voltage Vref _ t, and when the timing voltage Vt is greater than the reference voltage Vref _ t, for example, the differential amplifying unit 43 outputs a differential amplifying current to the capacitor C1, thereby charging the output capacitor C1; the transmission gate 4 is turned on to transmit the differential amplification current within a time window with a preset size, so that the charging of the output capacitor C1 is also in small steps. Of course, in the implementation, when the timing voltage Vt is less than or equal to the reference voltage Vref _ t, the output current of the differential amplifying unit 43 is 0, and the output capacitor C1 is discharged in small steps through the transmission gate 44.
Referring to fig. 3 and 4, in a specific implementation process, the transmission gate 44 may be formed by a pair of N-type transistor and P-type transistor, a first pole of the N-type transistor and a first pole of the P-type transistor are connected in parallel to form an input end of the transmission gate 44, a second pole of the N-type transistor and a second pole of the P-type transistor are connected in parallel to form an output end of the transmission gate 44, and a control pole of the N-type transistor and a control pole of the P-type transistor are turned on in response to respective transmission gate control signals (op _ d, op _ N), so as to turn on the input end and the output end of the transmission gate 44.
Referring to fig. 3 and 4, in the implementation process, the mirror current source 41 includes: current source I0, transistor N41, timing resistance Rt, first mirror image branch and second mirror image branch, wherein:
the input end of the current source I0 is the input end of the mirror current source 41, and is used for receiving the input voltage VIN of the dc converter; the output end of the current source I0 is connected to the first pole of the transistor N41, and the second pole of the transistor N41 is grounded; the input end of the first mirror image branch is connected to the input end of the current source I0, the output end of the first mirror image branch is connected to one end of a timing resistor Rt, and the other end of the timing resistor Rt is connected to the second pole of the transistor N41; the input terminal of the second mirror branch is connected to the input terminal of the current source I0, and the output terminal of the second mirror branch is connected to the high potential terminal of the second timing unit 42. In this embodiment, the timing resistor Rt is a resistor capable of forming a voltage difference between its two ends when a current flows.
In a specific embodiment, the first mirror branch and the second mirror branch may be implemented by two transistors, specifically, a first pole of the first mirror transistor P41 serves as an input terminal of the first mirror branch; the first pole of the second mirror transistor P42 serves as the input terminal of the second mirror branch; the control electrode and the second electrode of the first mirror image transistor P41 are connected to be used as the output end of the first mirror image branch circuit; the second pole of the second mirror transistor P42 serves as the output end of the second mirror branch; the control electrode of the first mirror transistor P41 is connected to the control electrode of the second mirror transistor P42.
In an alternative embodiment, the first mirror branch may be connected to a first pole of the transistor N42, a second pole of the transistor N42 is connected to one end of the timing resistor Rt, and a control pole of the transistor N42 is connected to a first pole of the transistor N41, so that the connection of the first mirror branch and the timing resistor Rt may be turned on or off through the transistor N42. When there is an input voltage VIN, the transistor N42 turns on the connection between the first mirror branch and the timing resistor Rt, and when there is no input voltage VIN, the transistor N42 turns off the connection between the first mirror branch and the timing resistor Rt, so that the current supplied to the timing resistor Rt is controllable.
In this embodiment, the second mirror branch provides a charging current to the second timing unit 42 based on the first reference current It, so that the high potential end of the second timing unit 42 obtains the timing voltage Vt. Specifically, since the second mirror branch and the first mirror branch are mirror current sources, when the first reference current It flows through the first mirror branch, the second mirror branch will also generate a corresponding mirror current, so as to provide the charging current to the second timing unit 42, and thus, the high potential end of the second timing unit 42 obtains the timing voltage Vt.
Referring to fig. 3 and 4, in a specific implementation process, the differential amplifying unit 43 includes: a first N-type transistor N44 and a second N-type transistor N45, wherein:
a first pole of the first N-type transistor N44 and a first pole of the second N-type transistor N45 are connected to the input voltage terminal through respective P-type transistors; a first electrode of the second N-type transistor N45 is an output end of the differential amplifying unit 43; the second pole of the first N-type transistor N44 and the second pole of the second N-type transistor N45 are connected and grounded; a control electrode of the first N-type transistor N44 and a control electrode of the second N-type transistor N45 are a first input terminal and a second input terminal of the differential amplifying unit 43, respectively. As an example, a first pole of the P-type transistor P43 and a first pole of the P-type transistor P44 are connected to the input voltage terminal of the dc converter; the second pole of the P-type transistor P43 is connected to the first pole of the first N-type transistor N44, and the second pole of the P-type transistor P44 is connected to the first pole of the second N-type transistor N45; the control electrode of the P-type transistor P43 is connected to the second electrode of the P-type transistor P43, and the control electrode of the P-type transistor P43 is connected to the control electrode of the P-type transistor P44.
When the types of the transistors M0 in the variable resistance module 3 are different, the connection modes of the first input terminal and the second input terminal of the differential amplifying unit 43 are different, specifically:
in one embodiment, when the transistor M0 in the variable resistance module 3 is an N-type transistor, referring to fig. 3 and 4, a control electrode of the first N-type transistor N44 is connected as a first input terminal of the differential amplifying unit 43 to a high potential terminal of the second timing unit 42 for inputting the timing voltage Vt; a control electrode of the second N-type transistor N45 is connected as a second input terminal of the differential amplifying unit 43 to the control electrode of the transistor N41 for inputting the reference voltage Vref _ t.
In another embodiment, when the transistor M0 in the variable resistance module 3 is a P-type transistor (not shown in the figure), the control electrode of the second N-type transistor N45 is connected as the first input terminal of the differential amplifying unit 43 to the high potential terminal of the second timing unit 42 for inputting the timing voltage Vt; a control electrode of the first N-type transistor N44 is connected as a second input terminal of the differential amplifying unit 43 to a control electrode of the transistor N41 for inputting the reference voltage Vref _ t.
In order to facilitate setting the control period of the on-time control circuit, in an alternative embodiment, referring to fig. 3 and 4, the width-to-length ratios of the transistor N41, the first N-type transistor N44 and the second N-type transistor N45 are the same. As an example, when the current I2=2I0 flowing through the ground of the differential amplification unit 43 is set, vref _ t = Vt = Vgs at the time of loop balance of the differential amplification unit N41 Wherein Vgs is N41 Is the gate-source voltage of transistor N41; and the first reference current It = Vgs N41 As can be seen from fig. 3 and 4, the cycle of loop balancing is: vt = It T/Ct, i.e. T = Rt Ct, where T is the control period of the on-time control circuit.
Referring to fig. 3 and 4, in the implementation process, the second timing unit 42 includes: a switch tube N43 and a timing capacitor Ct, wherein:
the first pole of the switch tube N43 is connected to one end of the timing capacitor Ct to obtain a high potential end of the second timing unit 42; the second pole of the switch tube N43 is grounded, and the other end of the timing capacitor Ct is grounded; the switch N43 is used to respond to the timing reset signal en _ time to turn on after the transmission gate 44 turns on the transmission differential amplification current, so as to discharge the timing capacitor Ct. In a specific implementation, the timing reset signal en _ time may be provided by a signal generating circuit, such as a pulse generator. In this embodiment, two adjacent timing reset signals en _ time are a control cycle, and specifically, when a cycle starts, the switching tube N43 responds to the timing reset signal en _ time (for example, high level) to discharge the timing capacitor Ct; after the discharge is completed, the timing reset signal en _ time becomes, for example, a low level, and the switching tube N43 is turned off; subsequently, the mirror current source 41 supplies a charging current to the timing capacitor Ct in the timing unit 42 through the second mirror branch, and the voltage at the two ends of the timing capacitor Ct rises to obtain a timing voltage Vt; the differential amplification unit 43 differentially amplifies the clocking voltage Vt and the reference voltage Vref _ t and outputs a differential amplification current; the pass gate 44 turns on the pass differential amplification current in small steps to charge or discharge the output capacitor C1 in small steps, so that one end of the output capacitor C1 changes the magnitude of the control voltage Vset in small steps, thereby completing the control of the period control voltage Vset; after these operations are completed, the timer reset signal en _ time (e.g., high level) comes again, thereby starting on-time control of the next cycle.
In an alternative embodiment, the time interval between two signals of the timing reset signal en _ time is slightly larger than the switching period of the dc converter. Thereby, the control voltage Vset output by the control voltage generation module 4 in the continuous mode is made 0V, so that the switching frequency in the continuous mode is not affected;
in the preferred embodiment, the timing reset signal en _ time is immediately after the transmission gate 44 completes the transmission. So that the timing capacitor Ct is discharged in time before the next cycle.
The embodiment also discloses an adaptive constant on-time buck dc converter, which includes: the on-time control circuit disclosed in the above embodiments.
This embodiment also discloses a power management chip, includes: the on-time control circuit disclosed in the above embodiments.
This embodiment also discloses a wearable bluetooth equipment, includes: a Bluetooth module; the power management chip disclosed in the above embodiment is configured to manage a self-adaptive constant on-time buck dc converter that supplies power to the bluetooth module. Wearable bluetooth devices can be, for example, watches, bracelets, bluetooth headsets, etc., and these bluetooth devices can also establish bluetooth connected products in low power consumption state, generally pursue that the power supply ripple is comparatively small.
According to the embodiment of the utility model discloses an on-time control circuit and have its direct current converter, the input of variable resistance module is connected to the input voltage end of direct current converter for receive input voltage; the first timing module comprises a first capacitor, one end of the first capacitor is an input end of the first timing module, and the other end of the first capacitor is grounded; the output end of the variable resistance module is connected to the input end of the first timing module and used for providing timing current for the first timing module and charging the first capacitor; when the voltage of the first input end of the comparator reaches the output voltage, the comparator outputs a turn-off signal; the control voltage generation module is used for outputting changed control voltage to the control end of the variable resistance module according to a preset rule, the resistance value of the equivalent resistance of the variable resistance module changes along with the change of the control voltage, so that the size of the timing current is gradually changed, the voltage of the first input end of the comparator is gradually changed, the time of the comparator outputting a turn-off signal is gradually changed, namely the turn-on time of the synchronous tube is gradually changed, when the direct current converter is switched into a state, the direct current converter can be gradually switched from one load state to another load state, and the disturbance of the load state switching on the switching frequency is reduced.
It should be understood that the above-described embodiments are illustrative only and not restrictive, and that various obvious or equivalent modifications and substitutions may be made by those skilled in the art without departing from the basic principles of the invention, and are intended to be included within the scope of the appended claims.
Claims (18)
1. An on-time control circuit for an adaptive constant on-time buck dc converter, comprising: -a first timing module (1), -a comparator (2), -a variable resistance module (3) and-a control voltage generation module (4), wherein:
the first timing module (1) comprises a first capacitor (C0), one end of the first capacitor (C0) is an input end of the first timing module (1), and the other end of the first capacitor (C0) is grounded;
the input end of the variable resistance module (3) is connected to the input voltage end of the direct current converter and used for receiving an input Voltage (VIN); the output end of the variable resistance module (3) is connected to the input end of the first timing module (1) and is used for providing timing current (I1) for the first timing module (1) and charging the first capacitor (C0);
the control end of the variable resistance module (3) is connected to the output end of the control voltage generation module (4) to receive the control voltage (Vset) output by the control voltage generation module (4), so that the resistance value of the equivalent resistance of the variable resistance module is controlled to change along with the change of the control voltage (Vset) to change the size of the timing current (I1);
the input end of the control voltage generation module (4) is connected to the input voltage end of the direct current converter; the control voltage generation module (4) is used for outputting the changed control voltage (Vset) to the control end of the variable resistance module (3) according to a preset rule;
a first input end of the comparator (2) is connected to an input end of the first timing module (1); a second input end of the comparator (2) is used for receiving the output Voltage (VOUT) of the direct current converter; the output end of the comparator is used for being connected with a digital logic control module in the direct current converter, so that when the voltage of the first input end of the comparator (2) and the voltage of the second input end of the comparator reach a preset condition, a turn-off signal (ton _ rst) for turning off the synchronous tube (MP 1) is output to the digital logic control module.
2. The on-time control circuit according to claim 1, wherein the variable resistance module (3) comprises:
a transistor (M0), a control electrode of the transistor (M0) being a control terminal of the variable resistance module (3); the transistor (M0) operates in a variable resistance region under the control of the control voltage (Vset).
3. The on-time control circuit according to claim 2, wherein the variable resistance module (3) further comprises: a current mirror, a first equivalent resistance (R10) and a second equivalent resistance (R11), wherein:
the input end of the current mirror is the input end of the variable resistance module (3); a first output branch of the current mirror is connected to one end of a first equivalent resistor (R10), and the other end of the first equivalent resistor (R10) is grounded; the second output branch of the current mirror is connected to the input end of the first timing module (1);
one end of the second equivalent resistor (R11) is connected to the second pole of the transistor (M0); the first pole of the transistor (M0) is connected to one end of the first equivalent resistor (R10), and the other end of the second equivalent resistor (R11) is grounded.
4. The on-time control circuit according to claim 2, wherein the variable resistance module (3) further comprises: a current mirror and a first equivalent resistance (R10), wherein:
the input end of the current mirror is the input end of the variable resistance module (3); a first output branch of the current mirror is connected to one end of a first equivalent resistor (R10), and the other end of the first equivalent resistor (R10) is grounded;
the second output branch of the current mirror is connected to the input end of the first timing module (1);
the third output branch of the current mirror is connected to the first pole of the transistor (M0), and the second pole of the transistor (M0) is connected to the input end of the first timing module (1).
5. The on-time control circuit of claim 4,
each transistor in the current mirror is a P-type transistor;
the transistor (M0) is an N-type transistor.
6. The on-time control circuit of claim 4,
each transistor in the current mirror is a P-type transistor;
the transistor (M0) is a P-type transistor.
7. The on-time control circuit according to any one of claims 3 to 6, wherein the variable resistance module (3) further comprises: a first voltage dividing resistor (R01), a second voltage dividing resistor (R02), an operational amplifier unit, and an N-type transistor (N1), wherein:
the first voltage-dividing resistor (R01) and the second voltage-dividing resistor (R02) are connected in series between an input voltage end of the direct current converter and the ground;
a first input end of the operational amplifier unit is connected to the connecting end of a first voltage-dividing resistor (R01) and a second voltage-dividing resistor (R02); a second input end of the operational amplifier unit is connected to one end of the first equivalent resistor (R10);
a first pole of the N-type transistor (N1) is connected to a first output branch of the current mirror, and a second pole of the N-type transistor (N1) is connected to one end of the first equivalent resistor (R10); and the control electrode of the N-type transistor (N1) is connected to the output end of the operational amplifier unit.
8. The on-time control circuit according to any of claims 1-6, characterized in that the first timing module (1) further comprises:
a release transistor (N2), a first pole and a second pole of the release transistor (N2) being connected to one end and the other end of the first capacitor (C0), respectively, the release transistor (N2) switching off the first pole and the second pole of the release transistor (N2) in response to a control signal (hson _ N) during the turn-on of the sync transistor (MP 1).
9. The on-time control circuit according to any one of claims 1 to 6, wherein the control voltage generation module (4) comprises: a mirror current source (41), a second timing unit (42), a differential amplification unit (43), a transmission gate (44) and an output capacitor (C1);
an input terminal of the mirror current source (41) is connected to an input voltage terminal of the dc converter for receiving an input Voltage (VIN); a first output terminal of the mirror current source (41) is grounded, and a second output terminal of the mirror current source (41) is connected to a high potential terminal of the second timing unit (42);
the first input end and the second input end of the differential amplification unit (43) are respectively connected to one and the other of the high potential end and the reference voltage end of the second timing unit (42), and the differential amplification unit (43) is used for comparing the voltages input by the first input end and the second input end to obtain differential amplification current;
the output end of the differential amplifying unit (43) is connected to the input end of the transmission gate (44); the transmission gate (44) is connected to one end of an output capacitor (C1), and the other end of the output capacitor (C1) is grounded; in each timing period, the transmission gate (44) conducts and transmits the differential amplification current in a time window with a preset size;
one end of the output capacitor (C1) is used for outputting the control voltage (Vset).
10. The on-time control circuit of claim 9, wherein the mirror current source (41) comprises: the circuit comprises a current source (I0), a transistor (N41), a timing resistor (Rt), a first mirror image branch and a second mirror image branch;
the input end of the current source (I0) is the input end of the mirror current source (41), the output end of the current source (I0) is connected to the first pole of the transistor (N41), and the second pole of the transistor (N41) is grounded;
the input end of the first mirror image branch is connected to the input end of the current source (I0), the output end of the first mirror image branch is connected to one end of the timing resistor (Rt), and the other end of the timing resistor (Rt) is connected to the second pole of the transistor (N41);
the input end of the second mirror branch is connected to the input end of the current source (I0), and the output end of the second mirror branch is connected to the high potential end of the second timing unit (42).
11. On-time control circuit according to claim 10, characterized in that the differential amplifying unit (43) comprises: a first N-type transistor (N44) and a second N-type transistor (N45);
a first pole of the first N-type transistor (N44) and a first pole of the second N-type transistor (N45) are connected to the input voltage terminal through respective P-type transistors; a first electrode of the second N-type transistor (N45) is an output end of the differential amplification unit (43);
a second pole of the first N-type transistor (N44) and a second pole of the second N-type transistor (N45) are connected and grounded;
the control electrode of the first N-type transistor (N44) and the control electrode of the second N-type transistor (N45) are respectively a first input end and a second input end of the differential amplification unit (43).
12. The on-time control circuit according to claim 11, wherein a control electrode of the first N-type transistor (N44) is connected to a high potential terminal of the second timing unit (42); the control electrode of the second N-type transistor (N45) is connected to the control electrode of the transistor (N41).
13. The on-time control circuit according to claim 11, wherein a control electrode of the second N-type transistor (N45) is connected to a high potential terminal of the second timing unit (42); the control electrode of the first N-type transistor (N44) is connected to the control electrode of the transistor (N41).
14. The on-time control circuit of claim 11, wherein the width-to-length ratios of the transistor (N41), the first N-type transistor (N44), and the second N-type transistor (N45) are the same.
15. The on-time control circuit of claim 9, wherein the second timing unit (42) comprises: a switch tube (N43) and a timing capacitor (Ct);
the first pole of the switch tube (N43) is connected with one end of the timing capacitor (Ct) to obtain a high potential end of the second timing unit (42);
the second pole of the switch tube (N43) is grounded, and the other end of the timing capacitor (Ct) is grounded;
the switch tube (N43) is used for responding to a timing reset signal (en _ time) to conduct after the transmission gate (44) conducts and transmits the differential amplification current so as to discharge the timing capacitor (Ct).
16. An adaptive constant on-time buck dc converter, comprising:
an on-time control circuit as claimed in any one of claims 1 to 15.
17. A power management chip, comprising:
the on-time control circuit of any one of claims 1-15.
18. A wearable Bluetooth device, comprising:
a Bluetooth module;
the power management chip of claim 17, configured to manage an adaptive constant on-time buck dc converter that supplies power to the bluetooth module.
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| CN116169856A (en) * | 2023-02-24 | 2023-05-26 | 芯洲科技(北京)股份有限公司 | Power supply apparatus |
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