TWI784117B - Manufacturing method of laminated body, laminated body, and manufacturing method of electronic device - Google Patents
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- TWI784117B TWI784117B TW108100792A TW108100792A TWI784117B TW I784117 B TWI784117 B TW I784117B TW 108100792 A TW108100792 A TW 108100792A TW 108100792 A TW108100792 A TW 108100792A TW I784117 B TWI784117 B TW I784117B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/27—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Laminated Bodies (AREA)
- Ceramic Capacitors (AREA)
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Abstract
[課題]抑制具有電子零件之層積體的翹曲。 [解決手段]層積體之製造方法,係包含有如下述之步驟:經由藉由預定處理而產生變質的分離層(3),層積具有由模製材料(M)所模製之電子零件(E)的基板(5)與熱膨脹係數為3ppm/K以上14ppm/K以下的支撐體(2)。[Problem] Suppress warping of laminates with electronic components. [Solution] A method of manufacturing a laminate comprising the steps of: laminating an electronic part molded from a molding material (M) through a separation layer (3) degraded by a predetermined treatment (E) The substrate (5) and the support (2) having a coefficient of thermal expansion of not less than 3 ppm/K and not more than 14 ppm/K.
Description
本發明,係關於層積體之製造方法,層積體,及電子裝置之製造方法。The present invention relates to a method for manufacturing a laminate, a method for manufacturing a laminate, and an electronic device.
在半導體領域中,係近年來,使用在晶圓級、面板級填埋電子零件的封裝。例如,扇出型封裝,係「半導體晶片(晶片)上所形成之再配線擴展至比晶片的外形更外側而形成」之構造的封裝,且由於可實現封裝之小型化或配線之高密度化,故備受矚目。作為像這樣的扇出型封裝之半導體之製造方法,已知如下述般的方法:在將複數個電子零件搭載於支撐體,且由模製材料進行密封而形成配線構造(再配線)後,從層積體去除支撐體並進行單片化(例如,下述之專利文獻1)。 [先前技術文獻] [專利文獻]In the field of semiconductors, in recent years, packages for filling electronic components at the wafer level and panel level have been used. For example, the fan-out package is a package with a structure in which "the rewiring formed on the semiconductor chip (chip) is extended to the outer side of the chip", and because it can realize the miniaturization of the package or the high density of the wiring , so it has attracted much attention. As a method of manufacturing such a fan-out packaged semiconductor, a method is known in which a plurality of electronic components are mounted on a support and sealed with a molding material to form a wiring structure (rewiring), The support body is removed from the laminated body and singulated (for example, the following patent document 1). [Prior Art Literature] [Patent Document]
[專利文獻1]日本特開2008-306071號公報[Patent Document 1] Japanese Patent Laid-Open No. 2008-306071
以往,如專利文獻1般之具備有電子零件的層積體,係有發生翹曲的情形。當層積體發生翹曲時,則產生位置偏移等,從而容易在電子零件發生不良並導致良率變低。尤其,在進行封裝之小型化、配線之高密度化的情況下,容易發生電子零件之不良。因此,本案發明者,係針對如上述般的層積體之各部的材料等進行研究,結果發現可藉由使用預定熱膨脹係數之支撐體的方式,抑制層積體之翹曲的情形,從而完成本發明。Conventionally, warping may occur in laminates including electronic components as in
有鑑於如上述般的情事,本發明,係以抑制具有電子零件之層積體翹曲的情形為目的。 In view of the above circumstances, the present invention aims at suppressing warping of a laminate having electronic components.
根據本發明之第1態樣,提供一種層積體之製造方法,係包含有如下述之步驟:經由藉由預定處理而產生變質的分離層,層積具有由模製材料所模製之電子零件的基板與熱膨脹係數為3ppm/K以上14ppm/K以下的支撐體。According to the first aspect of the present invention, there is provided a method of manufacturing a laminate, which includes the following steps: through a separation layer that is degenerated by a predetermined treatment, and laminated with electrons molded from a molding material. The substrate of the part and the support body whose thermal expansion coefficient is not less than 3ppm/K and not more than 14ppm/K.
根據本發明之第2態樣,提供一種層積體,其係依熱膨脹係數為3ppm/K以上14ppm/K以下的支撐體與藉由預定處理而產生變質的分離層與接著層與基板該順序層積而成。According to the second aspect of the present invention, there is provided a laminate, which is a support having a coefficient of thermal expansion of 3 ppm/K to 14 ppm/K, a separation layer, an adhesive layer, and a substrate that are degraded by a predetermined treatment. layered.
根據本發明之第3態樣,提供一種電子裝置之製造方法,其係包含:藉由上述之層積體之製造方法來製造層積體;使分離層變質,從層積體分離支撐體;及從基板去除接著層及分離層,獲得含有電子零件的電子裝置。 According to a third aspect of the present invention, there is provided a method of manufacturing an electronic device, which includes: manufacturing a laminate by the above-mentioned method of manufacturing a laminate; changing the quality of the separation layer, and separating the support from the laminate; And removing the adhesive layer and the separation layer from the substrate to obtain an electronic device including electronic components.
本發明之層積體之製造方法,係可製造抑制了翹曲的層積體。又,本發明之層積體,係翹曲得到抑制。又,由於本發明之電子裝置之製造方法,係使用抑制了翹曲的層積體,因此,可提高所製造之電子零件的良率。 The method for producing a laminate of the present invention can produce a laminate in which warpage is suppressed. Also, in the laminate of the present invention, warpage is suppressed. Also, since the method of manufacturing an electronic device of the present invention uses a laminated body in which warping is suppressed, the yield of the manufactured electronic parts can be improved.
說明關於實施形態。在以下的說明中,適宜地參照圖1等所示的XYZ正交座標系統。該XYZ正交座標系統,係X方向及Y方向為水平方向(橫方向),Z方向為垂直方向。又,在各方向上,適宜地將與箭頭之前端相同側稱為+側(例如+Z側),並將與箭頭之前端相反側稱為-側(例如-Z側)。例如,在垂直方向(Z方向)上,上方為+Z側,下方為-Z側。此外,在圖式中,係為了說明實施形態,而示意地記載一部分或全部,並且將一部分放大或強調而記載等,且含有適宜地變更縮尺所表現的部分。 Embodiments will be described. In the following description, the XYZ orthogonal coordinate system shown in FIG. 1 etc. is referred suitably. In the XYZ orthogonal coordinate system, the X direction and the Y direction are the horizontal direction (horizontal direction), and the Z direction is the vertical direction. Also, in each direction, the same side as the front end of the arrow is referred to as + side (for example, +Z side), and the side opposite to the front end of the arrow is called - side (for example, -Z side) as appropriate. For example, in the vertical direction (Z direction), the upper side is the +Z side, and the lower side is the -Z side. In addition, in the drawings, in order to explain the embodiment, a part or the whole is schematically described, a part is enlarged or highlighted and described, etc., and a part represented by changing the scale as appropriate is included.
說明關於本實施形態的層積體。圖1,係從表示本實施形態之層積體的-Y側所觀看的剖面圖。層積體1,係如圖1所示般,具備有:支撐體2;分離層3;接著層4;及基板5,具有電子零件E。在層積體1中,係依支撐體2、分離層3、接著層4及具有電子零件E的基板5該順序層積而成。層積體1,係用於製造具備有電子零件E之電子裝置10(參閱圖9(B))。層積體1,係包含「電子零件E上所形成之再配線層R擴展至比電子零件E的外形更外側而形成」之構造即所謂的扇出型封裝之構造。另外,在本實施形態中,雖係將層積體1設成為包含所謂的扇出型面板級封裝之構造者而進行說明,但亦可為其他態樣。The laminated body of this embodiment is demonstrated. Fig. 1 is a cross-sectional view viewed from the -Y side of a laminate showing the present embodiment. The laminated
(支撐體)
支撐體2,係支撐分離層3、接著層4及基板5。在支撐體2之一方的面(在圖1中,係+Z側的面),係層積有分離層3。支撐體2之大小、厚度及形狀,係可分別任意地設定。例如,支撐體2,係可將一邊或直徑等的外形之大小設成為10mm以上1000mm以下左右。又,例如,從抑制層積體1之翹曲的觀點來看,支撐體2之厚度,係設成為400μm以上1200μm以下為較佳。又,從抑制層積體1之翹曲的觀點來看,支撐體2之厚度,係比後述說明之基板5的厚度更厚為較佳。又,例如,支撐體2之形狀,係其外形可設成為矩形狀、圓形狀等的板狀等的形狀。(support body)
The
支撐體2,係熱膨脹係數(coefficient of thermal expansion, CTE)為3ppm/K以上14ppm/K以下、4ppm/K以上9ppm/K以下為較佳、5ppm/K以上8ppm/K以下為更佳。在支撐體2之熱膨脹係數為上述範圍的情況下,可抑制層積體1之翹曲。吾人認為這是因為在支撐體2之熱膨脹係數為上述範圍的情況下,會與基板5之熱膨脹係數相匹配的緣故。其中,支撐體2之熱膨脹係數與基板5之熱膨脹係數,係在將(支撐體2之熱膨脹係數/基板5之熱膨脹係數)設成為X時,X,係滿足0.5≦X≦1.2為較佳,且滿足0.8≦X≦1.0為更佳。另外,基板5之熱膨脹係數,係4ppm/K以上12ppm/K以下為較佳,且5ppm/K以上10ppm/K以下為更佳。另外,支撐體2及基板5之熱膨脹係數,係可分別藉由習知的熱膨脹率測定裝置等來求出。
又,在本發明中,存在如下述般的情形:支撐體2上所設置之模製材料M的膨脹收縮行為對於層積體1之翹曲具有支配性影響。在該情況下,基板5之熱膨脹係數,係可視為與模製材料M的熱膨脹係數相等。
在像這樣的觀點下,模製材料M之熱膨脹係數,係4ppm/K以上12ppm/K以下為較佳,且5ppm/K以上10ppm/K以下為更佳。
另外,該模製材料M之熱膨脹係數,係可另外藉由使其與用於密封用之組成物硬化的方式獲得試驗片,並藉由熱膨脹率測定裝置分析該試驗片而求出。The
支撐體2之形成材料,雖係不特別限定而為任意,但後述說明之分離層3,係在藉由光而產生變質的情況下,由使分離層3變質之波長的光能透過之材料所形成為較佳。在該情況下,由於可通過支撐體2,對分離層3照射使分離層3變質的光,因此,可簡單地施予使分離層3變質的處理(參閱圖8(B))。The material for forming the
如上述般的支撐體2之形成材料,係例如玻璃、陶瓷、單晶材料等。其中,從材料之成本、材料之取得容易性等的觀點來看,支撐體2之形成材料,係玻璃為較佳。另外,在支撐體2之形成材料為玻璃的情況下,玻璃之組成,係不特別限定而為任意。像這樣的玻璃,係可使用習知之玻璃。The material for forming the above-mentioned
(分離層)
分離層3,係被形成於支撐體2上。分離層3,係在層積體1上,被形成於支撐體2與接著層4(基板5)之間。分離層3,係藉由預定處理而產生變質。藉此,層積體1,係可藉由使分離層3變質的方式,使支撐體2與基板5分離。例如,分離層3,係可使用藉由光之吸收、加熱、使分離層3變質(例如,分解、溶解)之與化合物的作用而產生變質者(材料)。在分離層3藉由光之吸收而產生變質的情況下,可簡單地施予使分離層3特異性地變質的處理。(separation layer)
The
另外,在本說明書中,分離層3「產生變質」,係意味著變化成與分離層3相接之層的接著力降低之狀態的情形。分離層3,係變質成分離層3受到些許外力而被破壞之狀態為較佳。作為變質之結果,分離層3,係失去變質之前的強度或接著性。例如,分離層3,係藉由變質而變脆。分離層3之變質,係作為上述之預定處理的結果而產生,並可進行控制。在本實施形態中,分離層3,係被設定為藉由預定處理,使支撐體2相對於分離層3移動,藉此,變質成分離層3被破壞的程度。藉此,層積體1,係可使基板5從支撐體2輕易分離。In addition, in this specification, the
分離層3之形成材料,係不特別限定而為任意。在分離層3之形成材料為藉由光之吸收而產生變質的材料之情況下,可使用國際公開第2013/008540號所記載的材料即氟碳化物、於其重複單位中包含具有光吸收性之構造的聚合體、無機物、具有紅外線吸收性之構造的化合物等。在分離層3之形成材料為上述的材料之情況下,因吸收光而產生變質且失去吸收光之前的強度或接著性,並可藉由施加些許外力(例如,使支撐體2相對於分離層3移動等)進行破壞,並容易分離支撐體2與基板5。另外,在分離層3之形成材料為藉由光之吸收而產生變質的材料之情況下,光之吸收率是80%以上為較佳。又,在分離層3為藉由光之吸收而產生變質的材料之情況下,使變質產生之光的波長為任意。在分離層3為藉由光之吸收而產生變質的材料之情況下,分離層3,係例如藉由吸收從雷射所照射的光而產生變質。The material for forming the
又,在分離層3之形成材料為藉由加熱而產生變質的材料之情況下,例如可使用以預定溫度而產生變質之習知的熱分解性樹脂。在該情況下,分離層3產生變質之預定溫度,係可藉由層積體1之製造方法適宜地設定,並藉由熱分解性樹脂之材料進行調整。Also, when the material for forming the
又,分離層3,係藉由預定之溶劑而溶解的材料為較佳,以便容易從基板5進行去除。溶解分離層3之溶劑,雖係不特別限定而為任意,但例如在分離層3為吸收上述之光而產生變質的材料之情況下,可使用包含一級、二級、三級之脂肪族胺、脂環胺、芳香族胺、雜環胺等的胺化合物等的溶劑。In addition, it is preferable that the
分離層3之厚度,雖係不特別限定,但例如0.05μm以上50μm以下的範圍為較佳。在分離層3之厚度為上述範圍的情況下,可藉由簡單之處理(例如,短時間之光的照射及低能量之光的照射等),使分離層3更確實地變質。The thickness of the
(接著層)
接著層4,係被形成於分離層3上。接著層4,係在層積體1上,被形成分離層3與基板5之間。接著層4,係用於接著分離層3與基板5。(next layer)
接著層4,係由熱可塑性之材料所構成為較佳。在接著層4由熱可塑性之材料所構成的情況下,由於能以藉由熱使其溶解並冷卻的方式進行硬化,因此,製造時之操作、控制較為容易。接著層4,係模數(拉伸應力)為0.05MPa以上5.00MPa以下為較佳,且0.1MPa以上3.00MPa以下為更佳。在接著層4之模數為上述範圍的情況下,可抑制接著層4所致之層積體1的翹曲。The
接著層4之形成材料,係不特別限定而為任意。例如,接著層4之形成材料,係具有接著性之樹脂,其中,烴類樹脂、丙烯酸-苯乙烯系樹脂、馬來醯亞胺系樹脂、彈性體樹脂、聚碸系樹脂之任一或該些之組合的樹脂為較佳。接著層4,係藉由預定之溶劑而溶解的材料為較佳,以便容易從基板5進行去除。溶解接著層4之溶劑,雖係不特別限定而為任意,但例如可設成為己烷、庚烷、辛烷、壬烷、異壬烷、甲基辛烷、癸烷、十一烷、十二烷、十三烷等之直鏈狀烴、碳數4至15之分支鏈狀之烴,例如環己烷、環庚烷、環辛烷、萘、十氫萘、四氫萘等之環狀烴,對-薄荷烷、鄰-薄荷烷、間-薄荷烷、二苯基甲烷等。像這樣的接著層4,係例如可使用TOKYO OHKA KOGYO股份有限公司製、TZNR(註冊商標)-A4017、A3007等來形成。The material for forming the
接著層4之厚度,雖係不特別限定,但例如從接著性、接著層4之去除之容易度的觀點來看, 10μm以上150μm以下為較佳。The thickness of the
另外,接著層4,係亦可具有上述之分離層3的特性即藉由預定處理而產生變質的特性。亦即,分離層3亦可兼作為接著層4。在該情況下,層積體1,係亦可不具備有接著層4。像這樣的分離層3之形成材料,係例如將吸收光之材料混合於具有接著性之樹脂的材料等,例如將碳黑等混合於丙烯酸系紫外線硬化樹脂的材料、將玻璃泡之紅外線吸收材料等混合於黏著性樹脂的材料等。In addition, the
(基板)
基板5,係被形成於接著層4上。基板5,係具有由模製材料M所模製(密封)之複數個電子零件E、再配線層R(RDL(Redistribution Layer))及凸塊B。本實施形態之基板5,係具有扇出型封裝構造的密封體基板。基板5,係被單片化(切割)而成為複數個電子裝置10(參閱圖9(B))。
在此,接著層4,係其大部分被「藉由具備於該基板5中之模製材料M與電子零件E的組合所斷續構成」之構件被覆。(substrate)
The
各電子零件E,係由模製材料M所模製。模製材料M,係以覆蓋電子零件E的方式,進行模製。模製材料M,係在各電子零件E上,對接著層4之相反面(+Z側的面)及側面(±X側的面及±Y側的面)進行模製。模製材料M之厚度,係不特別限定而為任意。模製材料M之形成材料,係不特別限定而為任意。模製材料M之形成材料,係例如環氧系的樹脂、矽系的樹脂等。又,電子零件E,係不特別限定而為任意。例如,電子零件E,係半導體晶片、MEMS(Micro Electro Mechanical Systems)、電晶體、電容、電阻等。另外,複數個電子零件E,係亦可為相同種類或不同種類。像這樣的由模製材料M所模製之電子零件E,係例如亦可為由模製材料M所模製之複數個電子零件E(模塑晶圓),或亦可為由模製材料M所模製之各個電子零件E。又,由模製材料M所模製之電子零件E,係亦可為單層,或亦可為多層。Each electronic component E is molded from molding material M. The molding material M is molded so as to cover the electronic parts E. The molding material M is used to mold the opposite surface (the surface on the +Z side) and the side surfaces (the surface on the ±X side and the surface on the ±Y side) of the
再配線層R,係構成連接電子零件E之端子T等的配線之薄膜的配線體。再配線層R,係在介電質Ra上,藉由導電體Rb形成有配線者。再配線層R之配線構造,係可任意地設定。例如,再配線層R,係亦可為單層,或亦可為複數層的構造。介電質Ra及導電體Rb之材料,係不特別限定而為任意。介電質Ra之材料,係例如聚醯亞胺系樹脂、氧化矽(SiOx
)、感光性環氧等的感光性樹脂等。導電體Rb之材料,係例如鋁、銅、鈦、鎳、金等的金屬等。再配線層R之厚度,係不特別限定而為任意,例如,從穩定性、基板5之薄膜化的觀點來看,被設定為數μm以上數10μm左右。The rewiring layer R is a wiring body of a thin film constituting wiring connected to terminals T and the like of the electronic component E. The rewiring layer R is formed on the dielectric material Ra, and the wiring is formed through the conductor Rb. The wiring structure of the rewiring layer R can be set arbitrarily. For example, the redistribution layer R may be a single layer or may have a multi-layer structure. The materials of the dielectric Ra and the conductor Rb are not particularly limited and are arbitrary. The material of the dielectric Ra is, for example, photosensitive resin such as polyimide resin, silicon oxide (SiO x ), photosensitive epoxy, and the like. The material of the conductor Rb is, for example, metals such as aluminum, copper, titanium, nickel, and gold. The thickness of the rewiring layer R is not particularly limited, but is arbitrary, and is set to, for example, several μm or more and several tens of μm from the viewpoint of stability and thinning of the
凸塊B,係被連接於再配線層R而形成,並用於與其他電子零件之連接等的電極。凸塊B之形狀、大小、種類,係不特別限定而為任意。凸塊B之形成材料,係不特別限定而為任意,例如可使用金、銀、銅、錫及焊錫材料等。The bump B is formed to be connected to the rewiring layer R, and is used as an electrode for connection to other electronic components. The shape, size, and type of the bump B are not particularly limited and are optional. The material for forming the bump B is not particularly limited and is arbitrary, and for example, gold, silver, copper, tin, and solder materials can be used.
基板5,係如上述般,其熱膨脹係數滿足與支撐體2之熱膨脹係數的預定關係為較佳。又,基板5之厚度,雖係不特別限定,但從抑制層積體1之翹曲的觀點來看,100μm以上1000μm以下為較佳。As mentioned above, it is preferable that the thermal expansion coefficient of the
另外,上述的基板5,係一例且亦可為其他形態。例如,基板5,係只要至少具備電子零件E即可,例如亦可不具備再配線層R及凸塊B的至少1個。又,基板5之形狀為任意,亦可不是層狀、板狀。In addition, the above-mentioned board|
(層積體之翹曲)
層積體1,係每單位長度之翹曲量為10μm/mm以下,較佳為5.0μm/mm以下,更佳為3.0μm/mm以下。另外,「每單位長度之翹曲量」,係指在將未層積支撐體2之分離層3的側之面的預定剖面中之最大高低差設成為D並將預定剖面之長度(兩端之距離)設成為L時,以D/L所表示的量。該最大高低差D,係可藉由雷射位移計等進行測定。如此一來,本實施形態之層積體1,係翹曲被加以抑制。藉此,層積體1,係可抑制位置偏移等,並可提高所製造之電子零件E(電子裝置10)的良率。因此,層積體1,係可適用於後述說明之電子裝置10的製造等。(warping of laminated body)
In the
[層積體之製造方法]
其次,說明本實施形態之層積體之製造方法。本層積體之製造方法,係製造上述之本實施形態之層積體1的方法。圖2及圖3,係表示本實施形態之層積體之製造方法的流程圖。圖4~圖6,係說明本實施形態之層積體之製造方法的圖。另外,在本層積體之製造方法中,針對層積體1的各部(分離層3、接著層4、基板5)之特性等的與上述之本實施形態之層積體1相同的部分,係適宜地省略說明。[Manufacturing method of laminated body]
Next, a method for manufacturing the laminate of this embodiment will be described. The manufacturing method of this laminated body is the method of manufacturing the above-mentioned
層積體之製造方法,係如圖2(A)的步驟S1所示般,包含有如下述之步驟:經由藉由預定處理而產生變質的分離層3,層積具有由模製材料M所模製之電子零件E的基板5與熱膨脹係數為3ppm/K以上14ppm/K以下的支撐體2。The manufacturing method of the laminated body, as shown in step S1 of FIG. The
例如,步驟S1,係如圖2(B)所示的步驟S2所示般,包含有如下述之步驟:依上述之支撐體2、分離層3、接著層4及基板5該順序層積。步驟S2,係例如藉由圖2(B)所示的步驟S3~步驟S5而進行。For example, step S1, as shown in step S2 shown in FIG. 2(B), includes the following steps: stacking the above-mentioned
在步驟S3中,係將分離層3層積於支撐體2。在步驟S3中,係首先,準備上述的支撐體2(參閱圖4(A))。此時,如上述般,支撐體2,係在將(支撐體2之熱膨脹係數/基板5之熱膨脹係數)設成為X時,X,係滿足0.5≦X≦1.2為較佳。In step S3 , the
又,支撐體2之熱膨脹係數,係基於使用複數個不同之熱膨脹係數的支撐體2所製造之層積體1的翹曲量來加以設定為較佳。這是因為層積體1之翹曲可依構成層積體1的材料、大小、厚度、製造方法(處理方法)等的複數個要因而變化之緣故。本案發明者發現到,如後述作為參考例所說明般,在層積體1中,當支撐體2以外之構成及製造方法相同的情況下,層積體1之翹曲量,係與支撐體2的熱膨脹率相關。例如,在使用熱膨脹係數為A1之支撐體2所製造的層積體之翹曲量是W1且使用熱膨脹係數為A2之支撐體2所製造的層積體之翹曲量是W2的情況下,上述熱膨脹率(A1、A2)與翹曲量(W1、W2)具有相關關係。藉此,所使用的支撐體2之熱膨脹係數,係可基於上述的相關關係,預測並設定層積體1之翹曲量減少之支撐體2的熱膨脹係數。在該情況下,可確實地抑制層積體1之翹曲。Moreover, it is preferable to set the thermal expansion coefficient of the
其次,將分離層3層積於所準備的支撐體2。例如,將形成以溶劑使上述之分離層3的形成材料溶解之分離層3的液體塗佈於支撐體2之一方的面,並使其乾燥且使溶劑蒸發,藉此,如圖4(B)所示般,將分離層3層積於支撐體2上。塗佈之方法,係例如可使用旋轉塗佈、浸漬、輪刀片、噴霧塗佈、狹縫塗佈等的方法。Next, the
接著,在步驟S4中,將接著層4層積於分離層3。例如,將形成以溶劑使上述之接著層4的形成材料溶解之接著層4的液體塗佈於分離層3上,並使其乾燥且使溶劑蒸發,藉此,如圖4(C)所示般,將接著層4層積於分離層3。塗佈之方法,係與步驟S3相同。另外,如上述般,在分離層3兼作為接著層4的情況下,亦可不進行步驟S4。Next, in step S4 , the
接著,在步驟S5中,將具有由模製材料M所模製之電子零件E的基板5層積於接著層4。在本實施形態之層積體之製造方法中,步驟S5,雖係說明在扇出型封裝之製造方法中,對被稱為所謂的晶片優先(RDL優先)之電子零件E形成再配線層R的方法,但亦可為其他態樣。例如,作為將上述基板5層積於接著層4之方法,係亦可使用在形成被稱為所謂的RDL優先之再配線層R後,對再配線層R層積電子零件E的方法,或亦可預先將由模製材料M所模製之複數個電子零件E(模塑晶圓)層積於接著層4,或亦可預先將複數個由模製材料M所模製之各個電子零件E層積於接著層4。Next, in step S5 , the
例如,步驟S5,係藉由圖3所示的步驟S6~步驟S10而進行。例如,在步驟S6中,將電子零件E層積於接著層4。如圖5(A)所示般,在接著層4,係以預定排列,排列有複數個電子零件E。例如,以預定排列,預先將複數個電子零件E排列成接著性之支撐體等,並將其轉印至接著層4,藉此,進行電子零件E對接著層4的層積。另外,將電子零件E層積於接著層4之方法,係不限定於上述的方法而為任意。For example, step S5 is performed through steps S6 to S10 shown in FIG. 3 . For example, in step S6 , the electronic component E is laminated on the
接著,在圖3之步驟S7中,由模製材料M模製電子零件E。例如,藉由塗佈裝置,以覆蓋電子零件E的方式,塗佈以溶劑使上述之模製材料M的形成材料溶解之模製材料,並使其乾燥且使溶劑蒸發,藉此,如圖5(B)所示般,由模製材料M模製電子零件E整體。模製材料M之熱膨脹係數,係4ppm/K以上12ppm/K以下為較佳,且5ppm/K以上10ppm/K以下為更佳。另外,電子零件E對接著層4的層積,係不限定於上述的方法,亦可為其他方法。例如,電子零件E對接著層4的層積,係亦可在以預定排列,排列有複數個電子零件E的狀態下,預先製作由封裝材薄片等的模製材料M所模製之電子零件E的層,並將該層層積於接著層4。Next, in step S7 of FIG. 3 , the electronic part E is molded from the molding material M. As shown in FIG. For example, a molding material that dissolves the forming material of the above-mentioned molding material M is coated with a solvent in such a manner as to cover the electronic part E by a coating device, and dried and the solvent is evaporated, thereby, as shown in FIG. 5(B), the entire electronic component E is molded from the molding material M. As shown in FIG. The thermal expansion coefficient of the molding material M is preferably not less than 4 ppm/K and not more than 12 ppm/K, and more preferably not less than 5 ppm/K and not more than 10 ppm/K. In addition, the lamination|stacking of the electronic component E with respect to the
接著,在圖3之步驟S8中,使電子零件E之端子T從模製材料M露出。例如,如圖5(C)所示般,對模製材料M之表面(+Z側的面)施予磨削、研磨、切削等的處理,藉此,使電子零件E之端子從模製材料M露出。Next, in step S8 of FIG. 3, the terminal T of the electronic component E is exposed from the molding material M. As shown in FIG. For example, as shown in FIG. 5(C), the surface of the molding material M (the surface on the +Z side) is subjected to grinding, grinding, cutting, etc., whereby the terminal of the electronic part E is molded from The material M is exposed.
接著,在圖3之步驟S9中,在使電子零件E之端子T露出的模製材料M上形成再配線層R。再配線層R之形成方法,係不特別限定而為任意。例如,在本實施形態中,係首先,藉由相減法、半加成法等,在使電子零件E之端子T露出的模製材料M上形成導電體Rb之層,並在導電體Rb之層上形成預定圖案的光阻,在蝕刻了不需要的導電體Rb後,剝離光阻而形成預定的配線圖案。而且,在配線圖案上形成介電質Ra之保護層,如圖6(A)所示般,在介電質Ra形成再配線層R,該再配線層R,係形成有導電體Rb的配線圖案。另外,再配線層R之形成方法,係不限定於上述的方法而可使用任意方法。Next, in step S9 of FIG. 3 , a rewiring layer R is formed on the molding material M exposing the terminals T of the electronic component E. As shown in FIG. The method for forming the rewiring layer R is not particularly limited and is arbitrary. For example, in the present embodiment, firstly, a layer of the conductor Rb is formed on the molding material M exposing the terminal T of the electronic component E by a subtractive method, a semi-additive method, etc., and a layer of the conductor Rb is formed. A photoresist with a predetermined pattern is formed on the layer, and after the unnecessary conductor Rb is etched, the photoresist is peeled off to form a predetermined wiring pattern. Furthermore, a protective layer of dielectric material Ra is formed on the wiring pattern, and as shown in FIG. 6(A), a rewiring layer R is formed on the dielectric material Ra. This rewiring layer R is a wiring on which conductor Rb is formed. pattern. In addition, the formation method of the rewiring layer R is not limited to the above-mentioned method, Any method can be used.
接著,在圖3之步驟S10中,在再配線層R形成凸塊B。例如,凸塊B,係去除介電質Ra之層的預定部分,使再配線層R露出,並將凸塊B之材料供給至露出的部分,藉此,如圖6(B)所示般,在再配線層R形成凸塊B。藉由以上之步驟,可製造圖1所示的上述之本實施形態的層積體1。另外,是否形成凸塊B為任意。Next, in step S10 of FIG. 3 , bumps B are formed on the rewiring layer R. Referring to FIG. For example, bump B is to remove a predetermined portion of the layer of dielectric Ra to expose the rewiring layer R, and supply the material of bump B to the exposed portion, thereby, as shown in FIG. 6(B) , forming the bump B on the redistribution layer R. Through the above-mentioned steps, the above-mentioned
[電子裝置之製造方法]
其次,說明本實施形態之電子裝置之製造方法。本電子裝置之製造方法,係使用上述之本實施形態的層積體1來製造電子裝置10的方法。圖7,係表示本實施形態之電子裝置之製造方法的流程圖。圖8及圖9,係說明本實施形態之電子裝置之製造方法的圖。另外,在本說明書中,「電子裝置」,係意味著具備有電子零件E的裝置、元件、零件。[Manufacturing method of electronic device]
Next, a method of manufacturing the electronic device of this embodiment will be described. The manufacturing method of this electronic device is a method of manufacturing the
電子裝置之製造方法,係包含:藉由上述之層積體之製造方法來製造層積體;使分離層3變質,從層積體1分離支撐體2;及從基板5去除接著層4及分離層3,獲得含有電子零件E的電子裝置10。電子裝置之製造方法,係例如可藉由圖7所示的步驟S11~步驟S15而進行。The method for manufacturing an electronic device includes: manufacturing a laminate by the method for manufacturing a laminate described above; changing the quality of the
例如,在步驟S11中,以支撐構件8支撐上述的基板5。例如,支撐構件8,係可使用支撐具有黏著性之膠帶(薄片)等的基板5且可從基板5拆卸的構件。For example, in step S11 , the above-mentioned
接著,在步驟S12中,藉由預定處理,使分離層3變質。該預定處理,係基於分離層3之性質而決定。例如,該預定處理,係指在分離層3吸收光而產生變質的情況下,使分離層3吸收光之處理,在分離層3藉由加熱而產生變質的情況下,加熱分離層3之處理,在分離層3藉由化合物而產生變質之處理的情況下,使化合物作用(接觸)於分離層3之處理。其中,在電子裝置之製造方法中,支撐體2,係由光能透過之材料所形成,且分離層3,係由吸收光而產生變質的材料所形成,預定處理,係通過支撐體2且照射光的方式,使分離層3吸收光之處理為較佳。在該情況下,可藉由簡單的處理使分離層3特異性地變質。例如,如圖8(B)所示般,藉由產生使分離層3變質之波長的光之雷射等,通過支撐體2,對分離層3照射光。分離層3,係變質成受到些許外力而被破壞之狀態為較佳。另外,在圖8(B)中,符號「3a」,係表示已變質之狀態。Next, in step S12, the
接著,在步驟S13中,從層積體1分離支撐體2。在本實施形態中,分離層3,係變質成受到些許外力而被破壞之狀態,例如,如圖8(C)所示般,使支撐體2相對於分離層3移動,藉此,分離層3被破壞,可使基板5從支撐體2輕易分離。Next, in step S13 , the
接著,在步驟S14中,從基板5去除分離層3及接著層4。在本實施形態中,如上述般,分離層3及接著層4,係被設定為藉由預定溶劑進行溶解,如圖9(A)所示般,藉由預定溶劑進行處理,藉此,從基板5去除分離層3及接著層4。在去除分離層3及接著層4後,洗淨溶劑並使其乾燥。Next, in step S14 , the
接著,在步驟S15中,對基板5進行切割。例如,在步驟S15中,如圖9(B)所示般,以預定單位對基板5進行切割。切割之方法,係不特別限定而為任意。例如,該切割,係可藉由刃切割、雷射切割等來進行。藉此,製造已對層積體1之基板5進行單片化的電子裝置10。由於在本實施形態中,係使用抑制了翹曲的層積體1,因此,可提高所製造之電子零件的良率。Next, in step S15, the
如以上所說明般,本實施形態之層積體之製造方法,係可製造抑制了翹曲的層積體。又,本發明之層積體,係翹曲得到抑制。又,由於本實施形態之電子裝置之製造方法,係使用抑制了翹曲的層積體,因此,可提高所製造之電子零件的良率。 [實施例]As described above, the method for producing a laminate according to this embodiment can produce a laminate in which warpage is suppressed. Also, in the laminate of the present invention, warpage is suppressed. Also, since the method of manufacturing an electronic device according to this embodiment uses a laminate in which warpage is suppressed, the yield of the manufactured electronic components can be improved. [Example]
以下,雖藉由實施例更詳細地說明本發明,但本發明並不受該些例子的任何限定。Hereinafter, although an Example demonstrates this invention in more detail, this invention is not limited to these examples at all.
[實施例1~6]
在實施例1~6中,係使用熱膨脹係數不同之複數個支撐體,製造圖1所示的層積體1,並評估層積體1之翹曲。[Example 1~6]
In Examples 1 to 6, the
(層積體之製造)
實施例1~6之層積體1,係如下述般,使用上述之本實施形態之層積體之製造方法來製造。各實施例之層積體,係使用以下的材料來製造。在各實施例中,支撐體2,係設成為直徑為200mm、厚度為700μm、熱膨脹係數為3.2~10.5ppm/K(圖10所示)、圓板狀的玻璃。分離層3,係將形成材料設成為氟碳化物系分離層,將厚度設成為0.4μm。接著層4,係使用TOKYO OHKA KOGYO股份有限公司、TZNR(註冊商標)-A4017(模數0.27MPa),以厚度30μm來形成。基板5,係複數個電子零件E由模製材料M所模製者。在各實施例中,基板5之厚度,係設成為300μm及490μm。另外,在實施例1~6中,基板5之熱膨脹係數,係8~10ppm/K的範圍。分離層3及接著層4,係在藉由塗佈裝置塗佈了使材料溶解的材料液後,藉由加熱來形成。又,基板5與接著層4之層積,係藉由下述來進行:將具有由模製材料M進行模製之複數個電子零件E(模塑晶圓)的基板5層積於層積體1。(manufacturing of laminates)
The
(翹曲之測定)
將所製造之層積體1載置於平台上,藉由雷射位移計,測定層積體1的預定剖面中之最大高低差D。另外,預定之剖面圖,係設成為圓板狀之層積體1的直徑方向。在圖10中,表示各實施例中之層積體1的翹曲。另外,在圖10中,層積體1之翹曲的「+」符號,係表示圖1所示之層積體1朝向上方突出之方向的翹曲(向上翹曲),層積體1之翹曲的「-」符號,係表示圖1所示之層積體1朝向下方突出之方向的翹曲(向下翹曲)。(Determination of Warpage)
The manufactured
另外,層積於接著層4之前的狀態之基板5的翹曲亦由雷射位移計來計測。其結果,厚度為300μm之基板5,係沿著中央朝向下方突出的方向(-方向),最大高低差為2022μm(每單位長度之翹曲量10.1μm/mm),厚度為490μm之基板,係沿著中央朝向上方突出的方向(+方向),最大高低差為3429μm(每單位長度之翹曲量17.1μm/mm)。In addition, the warpage of the
又,在實施例1~6中,藉由下述式,求出層積體1之每單位長度的翹曲量。
式:「層積體1之每單位長度的翹曲量」=「層積體1之翹曲量的絕對值(μm)」/支撐體之直徑(200mm)
將其結果表示於下述。又,亦表示翹曲之方向。
實施例1:
300μm厚之基板:1544μm/200mm=7.720μm/mm(+方向)
490μm厚之基板:1989μm/200mm=9.945μm/mm(+方向)
實施例2:
300μm厚之基板:1665μm/200mm=8.325μm/mm(+方向)
490μm厚之基板:1602μm/200mm=8.010μm/mm(+方向)
實施例3:
300μm厚之基板:972μm/200mm=4.86μm/mm(+方向)
490μm厚之基板:1063μm/200mm=5.315μm/mm(+方向)
實施例4:
300μm厚之基板:660μm/200mm=3.3μm/mm(+方向)
490μm厚之基板:658μm/200mm=3.29μm/mm(+方向)
實施例5:
300μm厚之基板:810μm/200mm=4.05μm/mm(-方向)
490μm厚之基板:222μm/200mm=1.11μm/mm(-方向)
實施例6:
300μm厚之基板:2012μm/200mm=10.06μm/mm(-方向)
490μm厚之基板:1842μm/200mm=9.21μm/mm(-方向)Moreover, in Examples 1-6, the warpage amount per unit length of the
(結果)
確認到:本實施形態之層積體1,係如圖10所示般,翹曲得到抑制。又,從實施例1~6之結果確認到:層積體1之翹曲,係依存於支撐體2之熱膨脹係數,且翹曲之方向會連續變化。又,確認到:在實施例1~6所進行之使用複數個不同之熱膨脹係數的支撐體2所製造之層積體1的翹曲量,係與支撐體2之熱膨脹係數具有相關性,層積體1之翹曲量,係被預測為支撐體2的熱膨脹係數為6.5左右且接近0。(result)
It was confirmed that the
另外,本發明之技術範圍,係不限定於在上述的實施形態等所說明之態樣者。在上述的實施形態等所說明之要件的1個以上,係有時被省略。又,在上述的實施形態等所說明之要件,係可適宜地組合。又,在法令所容許的範圍內,援用上述之實施形態等所引用的所有文獻之揭示作為本文之記載的一部分。In addition, the technical scope of the present invention is not limited to the aspects described in the above-mentioned embodiments and the like. One or more of the requirements described in the above-mentioned embodiments and the like may be omitted. In addition, the requirements described in the above-mentioned embodiments and the like can be appropriately combined. In addition, within the scope permitted by laws and regulations, the disclosures of all documents cited in the above-mentioned embodiments and the like are incorporated as a part of the description herein.
1‧‧‧層積體
2‧‧‧支撐體
3‧‧‧分離層
4‧‧‧接著層
5‧‧‧基板
8‧‧‧支撐構件
10‧‧‧電子裝置
B‧‧‧凸塊
E‧‧‧電子零件
M‧‧‧模製材料
R‧‧‧再配線層
Ra‧‧‧介電質
Rb‧‧‧導電體
T‧‧‧端子1‧‧‧
[圖1]表示實施形態之層積體的圖。 [ Fig. 1 ] A view showing a laminated body according to an embodiment.
[圖2](A)及(B),係表示實施形態之層積體之製造方法的流程圖。 [FIG. 2] (A) and (B) are flow charts which show the manufacturing method of the laminated body of an embodiment.
[圖3]接續於圖2,表示層積體之製造方法的流程圖。 [FIG. 3] Following FIG. 2, it is a flow chart showing a method of manufacturing a laminate.
[圖4](A)~(C),係層積體之製造方法的說明圖。 [ Fig. 4 ] (A) to (C), are explanatory diagrams of the manufacturing method of the laminated body.
[圖5]接續於圖4,(A)~(C),係層積體之製造方法的說明圖。 [ Fig. 5 ] Continuing from Fig. 4 , (A) to (C), explanatory diagrams of a method of manufacturing a laminate.
[圖6]接續於圖5,(A)及(B),係層積體之製造方法的說明圖。 [ Fig. 6 ] Following Fig. 5 , (A) and (B) are explanatory diagrams of a method of manufacturing a laminate.
[圖7]表示實施形態之電子裝置之製造方法的流程圖。 [ Fig. 7 ] A flowchart showing a method of manufacturing an electronic device according to the embodiment.
[圖8](A)~(C),係電子裝置之製造方法的說明圖。 [FIG. 8] (A) to (C) are explanatory diagrams of a manufacturing method of an electronic device.
[圖9]接續於圖8,(A)及(B),係電子裝置之製造方法的說明圖。 [FIG. 9] Following FIG. 8, (A) and (B), it is an explanatory diagram of a manufacturing method of an electronic device.
[圖10]表示實施例1~6之層積體之翹曲量的曲線圖。[ Fig. 10 ] A graph showing the amount of warpage of laminates in Examples 1 to 6.
Claims (11)
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JP6466252B2 (en) * | 2014-06-19 | 2019-02-06 | 株式会社ジェイデバイス | Semiconductor package and manufacturing method thereof |
TW201800539A (en) * | 2016-02-29 | 2018-01-01 | 富士軟片股份有限公司 | Temporary adhesive composition and laminate |
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