TWI781714B - Method for equalizing input signal to generate equalizer output signal and parametric equalizer - Google Patents

Method for equalizing input signal to generate equalizer output signal and parametric equalizer Download PDF

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TWI781714B
TWI781714B TW110128847A TW110128847A TWI781714B TW I781714 B TWI781714 B TW I781714B TW 110128847 A TW110128847 A TW 110128847A TW 110128847 A TW110128847 A TW 110128847A TW I781714 B TWI781714 B TW I781714B
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signal
input
equalizer
protection
circuit
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TW110128847A
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TW202307825A (en
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邱信源
林琮富
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晶豪科技股份有限公司
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Abstract

A parametric equalizer includes an equalizer circuit, a first protection circuit, a second protection circuit, and a first addition circuit. The equalizer circuit is arranged to receive an input signal, and process the input signal to generate an output signal. The first protection circuit is arranged to generate a first protection signal according to the output signal, the input signal, and a first processed signal. The second protection circuit is arranged to generate a second protection signal according to the input signal and a second processed signal. The first addition circuit is coupled to the first protection circuit and the second protection circuit, and is arranged to combine the first protection signal and the second protection signal to generate an equalizer output signal.

Description

用以等化輸入訊號以產生等化器輸出訊號的方法以及參數等 化器 The method and parameters used to equalize the input signal to generate the output signal of the equalizer Converter

本發明係有關於頻率響應補償，尤指一種用以等化一輸入訊號以產生一等化器輸出訊號的方法以及相關參數等化器。 The present invention relates to frequency response compensation, especially a method for equalizing an input signal to generate an output signal of an equalizer and related parameter equalizers.

參數等化器係一種可以配置參數(諸如中心頻率(center frequency)及品質因數(quality factor,Q))以對輸入訊號進行輸出頻率響應調變的等化器。藉由利用參數等化器，當輸入至參數等化器的訊號之位準(level)太大時，可避免發生訊號的削波(clipping)，然而，當輸入至參數等化器的訊號之位準太小時，藉由利用固定增益衰減的參數等化器無法達到良好的聽覺效果，因此，為了解決上述問題，極需一種用以針對輸入訊號之位準來補償輸出頻率響應的方法以及相關參數等化器。 A parametric equalizer is an equalizer that can configure parameters such as a center frequency (center frequency) and a quality factor (quality factor (Q)) to modulate an output frequency response to an input signal. By using the parametric equalizer, when the level of the signal input to the parametric equalizer is too large, clipping of the signal can be avoided. However, when the signal input to the parametric equalizer is If the level is too small, good hearing effects cannot be achieved by using a parametric equalizer with fixed gain attenuation. Therefore, in order to solve the above problems, a method for compensating the output frequency response for the level of the input signal and related Parametric equalizer.

因此，本發明的目的之一在於提供一種用以等化一輸入訊號以產生一等化器輸出訊號的方法以及相關參數等化器，以解決上述問題。 Therefore, one object of the present invention is to provide a method for equalizing an input signal to generate an output signal of an equalizer and a related parametric equalizer to solve the above problems.

根據本發明之一實施例，揭露了一種參數等化器。該參數等化器可包含一等化器電路、一第一保護電路、一第二保護電路以及一第一加法電路，等化器電路可用以接收一輸入訊號，並且處理輸入訊號以產生一輸出訊號，第一保護電路可用以根據輸出訊號、輸入訊號以及一第一處理訊號來產生一第一保護訊號，其中第一保護訊號的一峰值位準受保護而小於或等於第一保護電路所使用的一第一門檻值，第二保護電路可用以根據輸入訊號以及一第二處理訊號來產生一第二保護訊號，其中第一處理訊號涉及第二處理訊號的產生，第二處理訊號涉及第一處理訊號的產生，以及第一處理訊號的一峰值位準受保護而小於或等於第二保護電路所使用的一第二門檻值，第一加法電路可耦接於第一保護電路以及第二保護電路，並且用以將第一保護訊號與第二保護訊號結合以產生一等化器輸出訊號。 According to an embodiment of the present invention, a parameter equalizer is disclosed. The parametric equalizer may include an equalizer circuit, a first protection circuit, a second protection circuit and a first summing circuit, the equalizer circuit may receive an input signal and process the input signal to generate an output signal, the first protection circuit can be used to generate a first protection signal according to the output signal, the input signal and a first processing signal, wherein a peak level of the first protection signal is protected to be less than or equal to that used by the first protection circuit A first threshold value of the second protection circuit can be used to generate a second protection signal according to the input signal and a second processing signal, wherein the first processing signal is related to the generation of the second processing signal, and the second processing signal is related to the first The processing signal is generated, and a peak level of the first processing signal is protected to be less than or equal to a second threshold used by the second protection circuit. The first summing circuit can be coupled to the first protection circuit and the second protection circuit. The circuit is used to combine the first protection signal and the second protection signal to generate an equalizer output signal.

根據本發明之一實施例，揭露了一種用以等化一輸入訊號以產生一等化器輸出訊號的方法。該方法可包含：接收輸入訊號，並且處理輸入訊號以產生一輸出訊號；根據輸出訊號、輸入訊號以及一第一處理訊號來產生一第一保護訊號，其中第一保護訊號的一峰值位準受保護而小於或等於一第一門檻值；根據輸入訊號以及一第二處理訊號來產生一第二保護訊號，其中第一處理訊號涉及第二處理訊號的產生，第二處理訊號涉及第一處理訊號的產生，以及第一處理訊號的一峰值位準受保護而小於或等於一第二門檻值；以及將第一保護訊號與第二保護訊號結合以產生等化器輸出訊號。 According to an embodiment of the present invention, a method for equalizing an input signal to generate an output signal of an equalizer is disclosed. The method may include: receiving an input signal, and processing the input signal to generate an output signal; generating a first protection signal according to the output signal, the input signal and a first processed signal, wherein a peak level of the first protection signal is controlled by The protection is less than or equal to a first threshold value; a second protection signal is generated according to the input signal and a second processing signal, wherein the first processing signal is related to the generation of the second processing signal, and the second processing signal is related to the first processing signal and a peak level of the first processed signal is protected to be less than or equal to a second threshold; and combining the first protected signal and the second protected signal to generate an equalizer output signal.

100,200,700:參數等化器 100,200,700: parameter equalizer

12,22:等化器電路 12,22: equalizer circuit

14,16,202,204:保護電路 14, 16, 202, 204: protection circuit

18,34:平均電路 18,34: average circuit

20,26,36:加法電路 20,26,36: Adding circuit

A_IN:輸入訊號 A_IN: input signal

EQ_OUT:輸出訊號 EQ_OUT: output signal

PROCESS_1:第一處理訊號 PROCESS_1: first process signal

PROCESS_2:第二處理訊號 PROCESS_2: second processing signal

PROTECT_1:第一保護訊號 PROTECT_1: First protection signal

PROTECT_2:第二保護訊號 PROTECT_2: Second protection signal

PEQ_OUT:等化器輸出訊號 PEQ_OUT: equalizer output signal

TH1:第一門檻值 TH1: the first threshold

TH2:第二門檻值 TH2: the second threshold

AV:平均值 AV: average value

24,32:減法電路 24,32: Subtraction circuit

28,30:自動增益控制電路 28,30: Automatic gain control circuit

PAD:預調整訊號 PAD: pre-adjustment signal

RMS:均方根 RMS: root mean square

702,704:多工器 702,704: multiplexer

S1:第一選擇訊號 S 1 : The first selection signal

S2:第二選擇訊號 S 2 : Second selection signal

MUX_OUT_1:第一多工器輸出訊號 MUX_OUT_1: The first multiplexer output signal

MUX_OUT_2:第二多工器輸出訊號 MUX_OUT_2: Second multiplexer output signal

S50~S64:步驟 S50~S64: steps

第1圖為依據本發明一實施例之參數等化器的方塊圖。 FIG. 1 is a block diagram of a parameter equalizer according to an embodiment of the present invention.

第2圖為依據本發明一實施例之第1圖所示之參數等化器的示意圖。 FIG. 2 is a schematic diagram of the parameter equalizer shown in FIG. 1 according to an embodiment of the present invention.

第3圖為依據本發明一實施例之第2圖所示之參數等化器操作於案例1下的操作示意圖。 FIG. 3 is a schematic diagram of the operation of the parameter equalizer shown in FIG. 2 in Case 1 according to an embodiment of the present invention.

第4圖為依據本發明一實施例之第2圖所示之參數等化器操作於案例2下的操作示意圖。 FIG. 4 is a schematic diagram of the operation of the parameter equalizer shown in FIG. 2 in Case 2 according to an embodiment of the present invention.

第5圖為依據本發明一實施例之第2圖所示之參數等化器操作於案例3下的操作示意圖。 FIG. 5 is a schematic diagram of the operation of the parameter equalizer shown in FIG. 2 in Case 3 according to an embodiment of the present invention.

第6圖為依據本發明一實施例之藉由第2圖所示之參數等化器所取得的頻率響應示意圖。 FIG. 6 is a schematic diagram of the frequency response obtained by the parameter equalizer shown in FIG. 2 according to an embodiment of the present invention.

第7圖為依據本發明另一實施例之參數等化器的示意圖。 FIG. 7 is a schematic diagram of a parameter equalizer according to another embodiment of the present invention.

第8圖為依據本發明一實施例之一種用以等化一輸入訊號以產生一等化器輸出訊號的方法之流程圖。 FIG. 8 is a flowchart of a method for equalizing an input signal to generate an output signal of an equalizer according to an embodiment of the present invention.

第1圖為依據本發明一實施例之參數等化器100的方塊圖。參數等化器100可接收一輸入訊號A_IN諸如一音頻訊號(audio signal)，並且等化輸入訊號A_IN以產生一等化器輸出訊號PEQ_OUT，如第1圖所示，參數等化器100可包含有一等化器電路12、複數個保護電路14以及16、一平均電路18以及一加法電路20。等化器電路12可用以接收輸入訊號A_IN，並且處理輸入訊號A_IN以產生一輸出訊號EQ_OUT。保護電路14可用以根據輸出訊號EQ_OUT、輸入訊號A_IN以及一第一處理訊號PROCESS_1來產生一第一保護訊號PROTECT_1，其中第一保護訊號PROTECT_1的一峰值位準(peak level)受保護而小於或等於保護電路14所使用的一第一門檻值TH1，舉例來說，第一門檻值TH1可以為一使用者可程式化(user-programmable)參數。保護電路16可用以根據輸入訊號A_IN以及一第二處 理訊號PROCESS_2來產生一第二保護訊號PROTECT_2，其中第一處理訊號PROCESS_1涉及第二保護訊號PROTECT_2的產生，第二處理訊號PROCESS_2涉及第一保護訊號PROTECT_1的產生，以及第一處理訊號PROCESS_1的一峰值位準受保護而小於或等於保護電路16所使用的一第二門檻值TH2。平均電路18可用以產生輸入訊號A_IN之一平均值AV以作為第二門檻值TH2(亦即TH2=AV)，舉例來說，平均值AV可以為輸入訊號A_IN之一均方根(root-mean-square,RMS)值，也就是說，第二門檻值TH2等於輸入訊號A_IN之均方根值，但是本發明不限於此。加法電路20可耦接於保護電路14以及保護電路16，並且可用以將第一保護訊號PROTECT_1與第二保護訊號PROTECT_2結合，以產生等化器輸出訊號PEQ_OUT(亦即PEQ_OUT=PROTECT_1+PROTECT_2)。 FIG. 1 is a block diagram of a parameter equalizer 100 according to an embodiment of the present invention. The parameter equalizer 100 can receive an input signal A_IN such as an audio signal (audio signal), and equalize the input signal A_IN to generate an equalizer output signal PEQ_OUT, as shown in FIG. 1 , the parameter equalizer 100 can include There is an equalizer circuit 12 , a plurality of protection circuits 14 and 16 , an averaging circuit 18 and an adding circuit 20 . The equalizer circuit 12 can receive an input signal A_IN, and process the input signal A_IN to generate an output signal EQ_OUT. The protection circuit 14 can be used to generate a first protection signal PROTECT_1 according to the output signal EQ_OUT, the input signal A_IN and a first processing signal PROCESS_1, wherein a peak level of the first protection signal PROTECT_1 is protected to be less than or equal to A first threshold TH1 used by the protection circuit 14, for example, the first threshold TH1 may be a user-programmable parameter. The protection circuit 16 can be used according to the input signal A_IN and a second Processing signal PROCESS_2 to generate a second protection signal PROTECT_2, wherein the first processing signal PROCESS_1 is related to the generation of the second protection signal PROTECT_2, the second processing signal PROCESS_2 is related to the generation of the first protection signal PROTECT_1, and a peak value of the first processing signal PROCESS_1 The level is protected to be less than or equal to a second threshold TH2 used by the protection circuit 16 . The average circuit 18 can be used to generate an average value AV of the input signal A_IN as the second threshold value TH2 (that is, TH2=AV). For example, the average value AV can be a root-mean square value of the input signal A_IN -square, RMS) value, that is to say, the second threshold TH2 is equal to the root mean square value of the input signal A_IN, but the present invention is not limited thereto. The adding circuit 20 can be coupled to the protection circuit 14 and the protection circuit 16 and can be used to combine the first protection signal PROTECT_1 and the second protection signal PROTECT_2 to generate the equalizer output signal PEQ_OUT (ie PEQ_OUT=PROTECT_1+PROTECT_2).

參數等化器100能夠根據輸入訊號A_IN之位準來動態地調整應用於輸入訊號A_IN的等化(equalization)，第2圖為依據本發明一實施例之第1圖所示之參數等化器100的示意圖。第1圖所示之參數等化器100可藉由第2圖所示之一參數等化器200來實作(亦即參數等化器200也採用第1圖所示之參數等化器100之架構)，參數等化器200可包含有一等化器電路22、複數個保護電路202以及204(例如複數個保護電路14以及16可藉由複數個保護電路202以及204來實作)、一平均電路34以及一加法電路36，等化器電路22可用以接收輸入訊號A_IN，並且處理輸入訊號A_IN以產生輸出訊號EQ_OUT。 The parameter equalizer 100 can dynamically adjust the equalization applied to the input signal A_IN according to the level of the input signal A_IN. FIG. 2 is the parameter equalizer shown in FIG. 1 according to an embodiment of the present invention. 100 schematic diagrams. The parameter equalizer 100 shown in FIG. 1 can be implemented by a parameter equalizer 200 shown in FIG. 2 (that is, the parameter equalizer 200 also uses the parameter equalizer 100 shown in FIG. 1 structure), the parameter equalizer 200 may include an equalizer circuit 22, a plurality of protection circuits 202 and 204 (for example, a plurality of protection circuits 14 and 16 may be implemented by a plurality of protection circuits 202 and 204), a The averaging circuit 34 and an adding circuit 36, the equalizer circuit 22 can receive the input signal A_IN, and process the input signal A_IN to generate the output signal EQ_OUT.

在本實施例中，保護電路202可包含有一減法電路24、一加法電路26以及一自動增益控制電路28。減法電路24可耦接於等化器電路22，並且用以接收輸入訊號A_IN，以及自輸出訊號EQ_OUT減去輸入訊號A_IN以產生第二處理 訊號PROCESS_2(亦即PROCESS_2=EQ_OUT-A_IN)。加法電路26可耦接於減法電路24以及保護電路204，並且可以用以將第一處理訊號PROCESS_1與第二處理訊號PROCESS_2結合以產生一預調整(pre-adjusted)訊號PAD(亦即PAD=PROCESS_1+PROCESS_2)。自動增益控制電路28可耦接於加法電路26，並且可用以根據預調整訊號PAD以及第一門檻值TH1來產生第一保護訊號PROTECT_1，其中第一保護訊號PROTECT_1的一峰值位準受保護而小於或等於自動增益控制電路28所使用的第一門檻值TH1。 In this embodiment, the protection circuit 202 may include a subtraction circuit 24 , an addition circuit 26 and an automatic gain control circuit 28 . The subtraction circuit 24 can be coupled to the equalizer circuit 22, and is used for receiving the input signal A_IN, and subtracting the input signal A_IN from the output signal EQ_OUT to generate the second processing Signal PROCESS_2 (ie PROCESS_2=EQ_OUT-A_IN). The addition circuit 26 can be coupled to the subtraction circuit 24 and the protection circuit 204, and can be used to combine the first processing signal PROCESS_1 and the second processing signal PROCESS_2 to generate a pre-adjusted signal PAD (ie, PAD=PROCESS_1 +PROCESS_2). The automatic gain control circuit 28 can be coupled to the adding circuit 26, and can be used to generate the first protection signal PROTECT_1 according to the preset adjustment signal PAD and the first threshold value TH1, wherein a peak level of the first protection signal PROTECT_1 is protected to be less than Or equal to the first threshold TH1 used by the automatic gain control circuit 28 .

保護電路204可包含有一自動增益控制電路30以及一減法電路32。自動增益控制電路30可耦接於減法電路24以及加法電路26，並且可用以根據第二處理訊號PROCESS_2以及第二門檻值TH2來產生第一處理訊號PROCESS_1，其中第一處理訊號PROCESS_1的一峰值位準受保護而小於或等於自動增益控制電路30所使用的第二門檻值TH2。減法電路32可耦接於自動增益控制電路30，並且可用以自輸入訊號A_IN減去第一處理訊號PROCESS_1以產生第二保護訊號PROTECT_2(亦即PROTECT_2=A_IN-PROCESS_1)。平均電路34可用以產生輸入訊號A_IN之平均值AV以作為第二門檻值TH2，其中平均值AV可以為輸入訊號A_IN之均方根值(亦即第二門檻值TH2等於輸入訊號A_IN之均方根值，但是本發明不以此為限)。加法電路36可耦接於保護電路202以及保護電路204，並且可用以將第一保護訊號PROTECT_1與第二保護訊號PROTECT_2結合，以產生等化器輸出訊號PEQ_OUT。 The protection circuit 204 may include an automatic gain control circuit 30 and a subtraction circuit 32 . The automatic gain control circuit 30 can be coupled to the subtraction circuit 24 and the addition circuit 26, and can be used to generate the first processing signal PROCESS_1 according to the second processing signal PROCESS_2 and the second threshold value TH2, wherein a peak value of the first processing signal PROCESS_1 is quasi-protected and less than or equal to the second threshold TH2 used by the automatic gain control circuit 30 . The subtraction circuit 32 can be coupled to the automatic gain control circuit 30 and can be used to subtract the first processing signal PROCESS_1 from the input signal A_IN to generate the second protection signal PROTECT_2 (ie PROTECT_2=A_IN−PROCESS_1). The average circuit 34 can be used to generate the average value AV of the input signal A_IN as the second threshold value TH2, wherein the average value AV can be the root mean square value of the input signal A_IN (that is, the second threshold value TH2 is equal to the mean square value of the input signal A_IN root value, but the present invention is not limited thereto). The adding circuit 36 can be coupled to the protection circuit 202 and the protection circuit 204 , and can be used to combine the first protection signal PROTECT_1 and the second protection signal PROTECT_2 to generate the equalizer output signal PEQ_OUT.

根據輸入訊號A_IN之一輸入位準、輸出訊號EQ_OUT之一峰值位準以及第一門檻值TH1，本發明中等化輸入訊號A_IN以產生等化器輸出訊號PEQ_OUT的處理可劃分為3個案例(例如案例1、案例2以及案例3)。 According to the input level of the input signal A_IN, the peak level of the output signal EQ_OUT and the first threshold value TH1, the processing of the present invention to equalize the input signal A_IN to generate the equalizer output signal PEQ_OUT can be divided into three cases (for example Case 1, Case 2 and Case 3).

請搭配參照第2圖以及第3圖，第3圖為依據本發明一實施例之第2圖所示之參數等化器200操作於案例1下的操作示意圖。在案例1中，輸入訊號A_IN之輸入位準以及輸出訊號EQ_OUT之峰值位準皆小於或等於第一門檻值TH1，舉例來說，輸入訊號A_IN之輸入位準係為1，等化器電路22的一峰值增益係為30(亦即輸出訊號EQ_OUT之峰值位準係為30)，以及第一門檻值TH1被設置為50。自動增益控制電路28之目的在於保護第一保護訊號PROTECT_1之峰值位準以使得第一保護訊號PROTECT_1之峰值位準小於或等於第一門檻值TH1，並且預調整訊號PAD之峰值位準等於輸出訊號EQ_PUT之峰值位準(例如預調整訊號PAD之峰值位準等於30)，由於預調整訊號PAD之峰值位準小於或等於第一門檻值TH1，因此當預調整訊號PAD通過自動增益控制電路28時，無需箝制(clamp)第一保護訊號PROTECT_1之峰值位準，如此一來，第一保護訊號PROTECT_1之峰值位準與以及等化器輸出訊號PEQ_OUT之峰值位準皆會與預調整訊號PAD之峰值位準相同(例如第一保護訊號PROTECT_1之峰值位準以及等化器輸出訊號PEQ_OUT之峰值位準皆等於30)，此外，第一保護訊號PROTECT_1之峰值位準大於輸入訊號A_IN之輸入位準，藉由通過加法電路36來將第一保護訊號PROTECT_1與第二保護訊號PROTECT_2結合，等化器輸出訊號PEQ_OUT之最小位準等於輸入訊號A_IN之輸入位準(例如等化器輸出訊號PEQ_OUT之最小位準等於1)。對於案例1來說，參數等化器200作為一尖峰濾波器(peaking filter)，其在中心頻率(center frequency)附近提供一升壓(boost)，而無需位準箝制(level clamping)，並且具有遠離中心頻率之單位增益(unity gain)。 Please refer to FIG. 2 and FIG. 3 together. FIG. 3 is a schematic diagram of the operation of the parameter equalizer 200 shown in FIG. 2 in case 1 according to an embodiment of the present invention. In Case 1, both the input level of the input signal A_IN and the peak level of the output signal EQ_OUT are less than or equal to the first threshold value TH1. For example, the input level of the input signal A_IN is 1, and the equalizer circuit 22 A peak gain is 30 (that is, the peak level of the output signal EQ_OUT is 30), and the first threshold TH1 is set to 50. The purpose of the automatic gain control circuit 28 is to protect the peak level of the first protection signal PROTECT_1 so that the peak level of the first protection signal PROTECT_1 is less than or equal to the first threshold value TH1, and the peak level of the pre-adjustment signal PAD is equal to the output signal The peak level of EQ_PUT (for example, the peak level of the pre-adjustment signal PAD is equal to 30), since the peak level of the pre-adjustment signal PAD is less than or equal to the first threshold value TH1, when the pre-adjustment signal PAD passes through the automatic gain control circuit 28 , there is no need to clamp the peak level of the first protection signal PROTECT_1, so that the peak level of the first protection signal PROTECT_1 and the peak level of the equalizer output signal PEQ_OUT will be equal to the peak value of the pre-adjustment signal PAD The levels are the same (for example, the peak level of the first protection signal PROTECT_1 and the peak level of the equalizer output signal PEQ_OUT are both equal to 30), in addition, the peak level of the first protection signal PROTECT_1 is greater than the input level of the input signal A_IN, By combining the first protection signal PROTECT_1 and the second protection signal PROTECT_2 through the addition circuit 36, the minimum level of the equalizer output signal PEQ_OUT is equal to the input level of the input signal A_IN (for example, the minimum level of the equalizer output signal PEQ_OUT quasi-equal to 1). For Case 1, the parametric equalizer 200 acts as a peaking filter, which provides a boost near the center frequency without level clamping, and has Unity gain away from the center frequency.

請搭配參照第2圖以及第4圖，第4圖為依據本發明一實施例之第2圖所示之參數等化器200操作於案例2下的操作示意圖。在案例2中，輸入訊號A_IN 之輸入位準小於或等於第一門檻值TH1，而輸出訊號EQ_OUT之峰值位準大於第一門檻值TH1，舉例來說，輸入訊號A_IN之輸入位準係為30，等化器電路22的一峰值增益係為30(亦即輸出訊號EQ_OUT之峰值位準係為900)，以及第一門檻值TH1被設置為50，預調整訊號PAD之峰值位準等於輸出訊號EQ_PUT之峰值位準(例如預調整訊號PAD之峰值位準等於900)，自動增益控制電路28之目的在於保護第一保護訊號PROTECT_1之峰值位準以使得第一保護訊號PROTECT_1之峰值位準小於或等於第一門檻值TH1，由於預調整訊號PAD之峰值位準大於第一門檻值TH1，因此當預調整訊號PAD通過自動增益控制電路28時，第一保護訊號PROTECT_1之峰值位準被限制在第一門檻值TH1(例如第一保護訊號PROTECT_1之峰值位準被限制在50)，如此一來，等化器輸出訊號PEQ_OUT之峰值位準等於第一保護訊號PROTECT_1之峰值位準(亦即等化器輸出訊號PEQ_OUT之峰值位準等於50)，此外，第一保護訊號PROTECT_1之箝制後的峰值位準大於輸入訊號A_IN之輸入位準，因此，藉由通過加法電路36來將第一保護訊號PROTECT_1與第二保護訊號PROTECT_2結合，等化器輸出訊號PEQ_OUT之最小位準等於輸入訊號A_IN之輸入位準(例如等化器輸出訊號PEQ_OUT之最小位準等於30)。對於案例2來說，參數等化器200作為一尖峰濾波器，其在中心頻率附近利用位準箝制來提供升壓，並且具有遠離中心頻率之單位增益。 Please refer to FIG. 2 and FIG. 4 together. FIG. 4 is a schematic diagram of the operation of the parameter equalizer 200 shown in FIG. 2 in Case 2 according to an embodiment of the present invention. In case 2, input signal A_IN The input level is less than or equal to the first threshold value TH1, and the peak level of the output signal EQ_OUT is greater than the first threshold value TH1, for example, the input level of the input signal A_IN is 30, one of the equalizer circuit 22 The peak gain is 30 (that is, the peak level of the output signal EQ_OUT is 900), and the first threshold TH1 is set to 50, the peak level of the preset signal PAD is equal to the peak level of the output signal EQ_PUT (for example, the preset The peak level of the adjustment signal PAD is equal to 900), the purpose of the automatic gain control circuit 28 is to protect the peak level of the first protection signal PROTECT_1 so that the peak level of the first protection signal PROTECT_1 is less than or equal to the first threshold value TH1, because The peak level of the pre-adjustment signal PAD is greater than the first threshold value TH1, so when the pre-adjustment signal PAD passes through the automatic gain control circuit 28, the peak level of the first protection signal PROTECT_1 is limited to the first threshold value TH1 (for example, the first The peak level of the protection signal PROTECT_1 is limited to 50), so that the peak level of the equalizer output signal PEQ_OUT is equal to the peak level of the first protection signal PROTECT_1 (that is, the peak level of the equalizer output signal PEQ_OUT is equal to 50), in addition, the clamped peak level of the first protection signal PROTECT_1 is greater than the input level of the input signal A_IN, therefore, by combining the first protection signal PROTECT_1 and the second protection signal PROTECT_2 through the addition circuit 36, The minimum level of the equalizer output signal PEQ_OUT is equal to the input level of the input signal A_IN (for example, the minimum level of the equalizer output signal PEQ_OUT is equal to 30). For Case 2, the parametric equalizer 200 acts as a spike filter that uses level clamping around the center frequency to provide boost and has unity gain away from the center frequency.

請搭配參照第2圖以及第5圖，第5圖為依據本發明一實施例之第2圖所示之參數等化器200操作於案例3下的操作示意圖。在案例3中，輸入訊號A_IN之輸入位準與輸出訊號EQ_OUT之峰值位準皆大於第一門檻值TH1，舉例來說，輸入訊號A_IN之輸入位準係為70，等化器電路22的一峰值增益係為30(亦即輸出訊號EQ_OUT之峰值位準係為2100)，以及第一門檻值TH1被設置為50，預調 整訊號PAD之峰值位準等於輸出訊號EQ_PUT之峰值位準(例如預調整訊號PAD之峰值位準等於2100)，自動增益控制電路28之目的在於保護第一保護訊號PROTECT_1之峰值位準以使得第一保護訊號PROTECT_1之峰值位準小於或等於第一門檻值TH1，由於預調整訊號PAD之峰值位準大於第一門檻值TH1，因此當預調整訊號PAD通過自動增益控制電路28時，第一保護訊號PROTECT_1之峰值位準被限制在第一門檻值TH1(例如第一保護訊號PROTECT_1之峰值位準被限制在50)，此外，第一保護訊號PROTECT_1之箝制後的峰值位準小於輸入訊號A_IN之輸入位準，因此，藉由通過加法電路36來將第一保護訊號PROTECT_1與第二保護訊號PROTECT_2結合，等化器輸出訊號PEQ_OUT之最大位準等於輸入訊號A_IN之輸入位準(例如等化器輸出訊號PEQ_OUT之最大位準等於70)，以及等化器輸出訊號PEQ_OUT之最小位準等於第一保護訊號PROTECT_1之峰值位準(例如等化器輸出訊號PEQ_OUT之谷值位準(valley level)等於50)。對於案例3來說，參數等化器200作為一陷波濾波器(notch filter)，其在中心頻率附近利用位準箝制來提供抑制(suppression)，並且具有遠離中心頻率之單位增益。 Please refer to FIG. 2 and FIG. 5 together. FIG. 5 is a schematic diagram of the operation of the parameter equalizer 200 shown in FIG. 2 in case 3 according to an embodiment of the present invention. In Case 3, both the input level of the input signal A_IN and the peak level of the output signal EQ_OUT are greater than the first threshold value TH1. For example, the input level of the input signal A_IN is 70, and one of the equalizer circuit 22 The peak gain is 30 (that is, the peak level of the output signal EQ_OUT is 2100), and the first threshold value TH1 is set to 50, the preset The peak level of the whole signal PAD is equal to the peak level of the output signal EQ_PUT (for example, the peak level of the preset signal PAD is equal to 2100), the purpose of the automatic gain control circuit 28 is to protect the peak level of the first protection signal PROTECT_1 so that the second The peak level of a protection signal PROTECT_1 is less than or equal to the first threshold value TH1. Since the peak level of the pre-adjustment signal PAD is greater than the first threshold value TH1, when the pre-adjustment signal PAD passes through the automatic gain control circuit 28, the first protection The peak level of the signal PROTECT_1 is limited to the first threshold value TH1 (for example, the peak level of the first protection signal PROTECT_1 is limited to 50), in addition, the clamped peak level of the first protection signal PROTECT_1 is smaller than the input signal A_IN The input level, therefore, by combining the first protection signal PROTECT_1 and the second protection signal PROTECT_2 through the addition circuit 36, the maximum level of the equalizer output signal PEQ_OUT is equal to the input level of the input signal A_IN (such as the equalizer The maximum level of the output signal PEQ_OUT is equal to 70), and the minimum level of the equalizer output signal PEQ_OUT is equal to the peak level of the first protection signal PROTECT_1 (for example, the valley level of the equalizer output signal PEQ_OUT is equal to 50). For Case 3, the parametric equalizer 200 acts as a notch filter, which utilizes level clamping around the center frequency to provide suppression and has unity gain away from the center frequency.

第6圖為依據本發明一實施例之藉由第2圖所示之參數等化器200所取得的頻率響應示意圖。如第6圖所示，假設參數等化器200以及等化器電路200的中心頻率係為103赫茲(hertz,Hz)，第一門檻值TH1係為30分貝(decibel,dB)，以及輸入訊號A_IN的輸入位準係為0分貝至50分貝，其中0分貝至20分貝係為上述案例1，30分貝係為上述案例2，以及40分貝至50分貝係為上述案例3。 FIG. 6 is a schematic diagram of a frequency response obtained by the parameter equalizer 200 shown in FIG. 2 according to an embodiment of the present invention. As shown in Fig. 6, it is assumed that the center frequency of the parametric equalizer 200 and the equalizer circuit 200 is 10 3 hertz (hertz, Hz), the first threshold value TH1 is 30 decibels (decibel, dB), and the input The input level of the signal A_IN is 0 dB to 50 dB, wherein 0 dB to 20 dB is the above case 1, 30 dB is the above case 2, and 40 dB to 50 dB is the above case 3.

在案例1中，由於輸入訊號A_IN之輸入位準以及輸出訊號EQ_OUT之峰值位準皆小於或等於第一門檻值TH1，參數等化器200僅在中心頻率103赫茲的位置放大(amplify)輸入訊號A_IN，而無需保護第一保護訊號PROTECT_1之峰 值位準以使得第一保護訊號PROTECT_1之峰值位準小於或等於自動增益控制電路28所使用的第一門檻值TH1。 In Case 1, since both the input level of the input signal A_IN and the peak level of the output signal EQ_OUT are less than or equal to the first threshold value TH1, the parametric equalizer 200 only amplifies the input at the center frequency of 103 Hz. The signal A_IN does not need to protect the peak level of the first protection signal PROTECT_1 such that the peak level of the first protection signal PROTECT_1 is less than or equal to the first threshold TH1 used by the automatic gain control circuit 28 .

在案例2中，由於輸入訊號A_IN之輸入位準小於或等於第一門檻值TH1，而輸出訊號EQ_OUT之峰值位準大於第一門檻值TH1，參數等化器200可保護第一保護訊號PROTECT_1之峰值位準以使得第一保護訊號PROTECT_1之峰值位準小於或等於自動增益控制電路28所使用的第一門檻值TH1，因此，第一保護訊號PROTECT_1之峰值位準被限制在第一門檻值TH1(例如第一保護訊號PROTECT_1之峰值位準被限制在30分貝)，以及等化器輸出訊號PEQ_OUT之峰值位準等於第一保護訊號PROTECT_1之峰值位準(亦即等化器輸出訊號PEQ_OUT之峰值位準等於30分貝)。 In case 2, since the input level of the input signal A_IN is less than or equal to the first threshold value TH1, and the peak level of the output signal EQ_OUT is greater than the first threshold value TH1, the parametric equalizer 200 can protect the first protection signal PROTECT_1. The peak level is such that the peak level of the first protection signal PROTECT_1 is less than or equal to the first threshold TH1 used by the automatic gain control circuit 28, therefore, the peak level of the first protection signal PROTECT_1 is limited to the first threshold TH1 (For example, the peak level of the first protection signal PROTECT_1 is limited to 30 dB), and the peak level of the equalizer output signal PEQ_OUT is equal to the peak level of the first protection signal PROTECT_1 (that is, the peak value of the equalizer output signal PEQ_OUT level is equal to 30 decibels).

在案例3中，由於輸入訊號A_IN之輸入位準與輸出訊號EQ_OUT之峰值位準皆大於第一門檻值TH1，參數等化器200可保護第一保護訊號PROTECT_1之峰值位準以使得第一保護訊號PROTECT_1之峰值位準小於或等於自動增益控制電路28所使用的第一門檻值TH1，因此，第一保護訊號PROTECT_1之峰值位準被限制在第一門檻值TH1(例如第一保護訊號PROTECT_1之峰值位準被限制在30分貝)，此外，由於輸入訊號A_IN之輸入位準高於第一保護訊號PROTECT_1之峰值位準，因此等化器輸出訊號PEQ_OUT(PEQ_OUT=PROTECT_1+PROTECT_2)具有一谷值位準其等於第一保護訊號PROTECT_1之峰值位準(亦即等化器輸出訊號PEQ_OUT的谷值位準等於30分貝)。 In Case 3, since both the input level of the input signal A_IN and the peak level of the output signal EQ_OUT are greater than the first threshold value TH1, the parametric equalizer 200 can protect the peak level of the first protection signal PROTECT_1 so that the first protection The peak level of the signal PROTECT_1 is less than or equal to the first threshold value TH1 used by the automatic gain control circuit 28. Therefore, the peak level of the first protection signal PROTECT_1 is limited to the first threshold value TH1 (for example, the first protection signal PROTECT_1 The peak level is limited to 30 dB), in addition, because the input level of the input signal A_IN is higher than the peak level of the first protection signal PROTECT_1, the equalizer output signal PEQ_OUT (PEQ_OUT=PROTECT_1+PROTECT_2) has a valley value The level is equal to the peak level of the first protection signal PROTECT_1 (that is, the valley level of the equalizer output signal PEQ_OUT is equal to 30 dB).

為了進行本發明之參數等化器的多個操作模式，2個2對1(2-to-1)多工器(multiplexer,MUX)可耦接至參數等化器200，第7圖為依據本發明另一實 施例之參數等化器700的示意圖。參數等化器700可包含有參數等化器200以及複數個多工器702以及704，並且可支援3種操作模式：純PEQ模式、APEQ單一模式以及APEQ限制模式。 In order to perform multiple operation modes of the parameter equalizer of the present invention, two 2-to-1 (2-to-1) multiplexers (multiplexer, MUX) can be coupled to the parameter equalizer 200, and FIG. 7 is based on Another embodiment of the present invention A schematic diagram of the parameter equalizer 700 of an embodiment. The parametric equalizer 700 can include the parametric equalizer 200 and a plurality of multiplexers 702 and 704 , and can support three operation modes: pure PEQ mode, APEQ single mode and APEQ limited mode.

如第7圖所示，多工器702可具有一第一輸入埠(於第7圖中標記為“1”)、一第二輸入埠(於第7圖中標記為“0”)以及一第一輸出埠，其中第一輸入埠可用以接收輸入訊號A_IN，第二輸入埠可耦接於參數等化器200，並且可用以根據一第一選擇訊號S1來將第一輸出埠耦接至第一輸入埠以及第二輸入埠的其中一個，以產生一第一多工器輸出訊號MUX_OUT_1。 As shown in FIG. 7, the multiplexer 702 may have a first input port (marked as "1" in Fig. 7), a second input port (marked as "0" in Fig. 7) and a The first output port, wherein the first input port can be used to receive the input signal A_IN, the second input port can be coupled to the parameter equalizer 200, and can be used to couple the first output port according to a first selection signal S1 to one of the first input port and the second input port to generate a first multiplexer output signal MUX_OUT_1.

當參數等化器700需要被操作於APEQ單一模式並且參數等化器200的輸入訊號A_IN之輸入位準大於第一門檻值TH1時，第一選擇訊號S1可被設置為一邏輯位準(例如S1=“1”)，其指示多工器702應將第一輸出埠耦接至第一輸入埠(亦即第一多工器輸出訊號MUX_OUT_1等於輸入訊號A_IN)，此外，當參數等化器700需要被操作於APEQ限制模式並且參數等化器200的輸入訊號A_IN之輸入位準小於或等於第一門檻值TH1時，第一選擇訊號S1可被設置為另一邏輯位準(例如S1=“0”)，其指示多工器702應將第一輸出埠耦接至第二輸入埠(亦即第一多工器輸出訊號MUX_OUT_1等於等化器輸出訊號PEQ_OUT)。 When the parametric equalizer 700 needs to be operated in the APEQ single mode and the input level of the input signal A_IN of the parametric equalizer 200 is greater than the first threshold TH1, the first selection signal S1 can be set to a logic level ( For example, S 1 = "1"), which indicates that the multiplexer 702 should couple the first output port to the first input port (that is, the output signal MUX_OUT_1 of the first multiplexer is equal to the input signal A_IN). In addition, when parameters such as When the equalizer 700 needs to be operated in the APEQ limited mode and the input level of the input signal A_IN of the parametric equalizer 200 is less than or equal to the first threshold value TH1, the first selection signal S1 can be set to another logic level ( For example, S 1 = "0"), which indicates that the multiplexer 702 should couple the first output port to the second input port (that is, the first multiplexer output signal MUX_OUT_1 is equal to the equalizer output signal PEQ_OUT).

如第7圖所示，多工器704可具有一第三輸入埠(於第7圖中標記為“0”)、一第四輸入埠(於第7圖中標記為“1”)以及一第二輸出埠，其中第三輸入埠可耦接至參數等化器200之等化器電路22，並且可用以接收輸出訊號EQ_OUT，第四輸入埠可耦接至多工器702的第一輸出埠，並且可用以接收第一多工器輸出訊號MUX_OUT_1，以及多工器704可用以根據一第二選擇訊號S2來 將第二輸出埠耦接至第三輸入埠以及第四輸入埠的其中一個，以產生一第二多工器輸出訊號MUX_OUT_2。 As shown in Figure 7, the multiplexer 704 may have a third input port (marked "0" in Figure 7), a fourth input port (marked "1" in Figure 7), and a The second output port, wherein the third input port can be coupled to the equalizer circuit 22 of the parameter equalizer 200 and can be used to receive the output signal EQ_OUT, and the fourth input port can be coupled to the first output port of the multiplexer 702 , and can be used to receive the first multiplexer output signal MUX_OUT_1, and the multiplexer 704 can be used to couple the second output port to one of the third input port and the fourth input port according to a second selection signal S2 , to generate a second multiplexer output signal MUX_OUT_2.

當參數等化器700需要被操作於APEQ單一模式或APEQ限制模式時，第二選擇訊號S2可被設置為一邏輯位準(例如S2=“1”)，其指示多工器704應將第二輸出埠耦接至第四輸入埠(亦即第二多工器輸出訊號MUX_OUT_2等於第一多工器輸出訊號MUX_OUT_1)，此外，當參數等化器700需要被操作於純PEQ模式時，第二選擇訊號S2可被設置為另一邏輯位準(例如S2=“0”)，其指示多工器704應將第二輸出埠耦接至第三輸入埠(亦即第二多工器輸出訊號MUX_OUT_2等於輸出訊號EQ_OUT)。 When the parametric equalizer 700 needs to be operated in the APEQ single mode or the APEQ limited mode, the second selection signal S2 can be set to a logic level (for example, S2=" 1 "), which instructs the multiplexer 704 to be The second output port is coupled to the fourth input port (that is, the second multiplexer output signal MUX_OUT_2 is equal to the first multiplexer output signal MUX_OUT_1), in addition, when the parameter equalizer 700 needs to be operated in pure PEQ mode , the second selection signal S 2 can be set to another logic level (for example, S 2 = "0"), which indicates that the multiplexer 704 should couple the second output port to the third input port (ie, the second The multiplexer output signal MUX_OUT_2 is equal to the output signal EQ_OUT).

第8圖為依據本發明一實施例之一種用以等化輸入訊號A_IN以產生等化器輸出訊號PEQ_OUT的方法之流程圖。假若可以得到相同的結果，則步驟不一定要完全遵照第8圖所示的流程來依序執行，舉例來說，第8圖所示之方法可由參數等化器100/200來加以實現。 FIG. 8 is a flowchart of a method for equalizing an input signal A_IN to generate an equalizer output signal PEQ_OUT according to an embodiment of the present invention. If the same result can be obtained, the steps do not have to be executed sequentially according to the flow shown in FIG. 8 . For example, the method shown in FIG. 8 can be implemented by the parameter equalizer 100/200.

在步驟S50中，對輸入訊號A_IN進行平均值計算以產生輸入訊號A_IN的平均值AV來作為第二門檻值TH2。 In step S50 , an average value calculation is performed on the input signal A_IN to generate an average value AV of the input signal A_IN as the second threshold TH2 .

在步驟S52中，接收並且等化輸入訊號A_IN，以產生輸出訊號EQ_OUT。 In step S52, the input signal A_IN is received and equalized to generate the output signal EQ_OUT.

在步驟S54中，接收輸入訊號A_IN並且自輸出訊號EQ_OUT減去輸入訊號A_IN，以產生第二處理訊號PROCESS_2。 In step S54, the input signal A_IN is received and subtracted from the output signal EQ_OUT to generate the second processing signal PROCESS_2.

在步驟S56中，根據第二處理訊號PROCESS_2以及第二門檻值TH2來產生第一處理訊號PROCESS_1。 In step S56, the first processing signal PROCESS_1 is generated according to the second processing signal PROCESS_2 and the second threshold TH2.

在步驟S58中，將第一處理訊號PROCESS_1與第二處理訊號PROCESS_2結合，以產生預調整訊號PAD。 In step S58 , the first processing signal PROCESS_1 and the second processing signal PROCESS_2 are combined to generate a pre-adjustment signal PAD.

在步驟S60中，根據預調整訊號PAD以及第一門檻值TH1來產生第一保護訊號PROTECT_1。 In step S60, a first protection signal PROTECT_1 is generated according to the pre-adjustment signal PAD and the first threshold TH1.

在步驟S62中，自輸入訊號A_IN減去第一處理訊號PROCESS_1，以產生第二保護訊號PROTECT_2。 In step S62 , the first processing signal PROCESS_1 is subtracted from the input signal A_IN to generate the second protection signal PROTECT_2 .

在步驟S64中，將第一保護訊號PROTECT_1與第二保護訊號PROTECT_2結合，以產生等化器輸出訊號PEQ_OUT。 In step S64 , the first protection signal PROTECT_1 and the second protection signal PROTECT_2 are combined to generate an equalizer output signal PEQ_OUT.

由於熟習技藝者可透過有關參數等化器100以及參數等化器200的說明書內容而輕易瞭解第8圖所示各步驟的操作，為了簡明起見，於本實施例中類似的內容在此不重複贅述。 Since those skilled in the art can easily understand the operation of each step shown in FIG. 8 through the contents of the description of the parameter equalizer 100 and the parameter equalizer 200, for the sake of brevity, similar content in this embodiment will not be omitted here. Repeat.

以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.

100:參數等化器 100: Parametric equalizer

12:等化器電路 12: Equalizer circuit

14,16:保護電路 14,16: Protection circuit

18:平均電路 18: Average circuit

20:加法電路 20:Addition circuit

A_IN:輸入訊號 A_IN: input signal

EQ_OUT:輸出訊號 EQ_OUT: output signal

PROCESS_1:第一處理訊號 PROCESS_1: first process signal

PROCESS_2:第二處理訊號 PROCESS_2: second processing signal

PROTECT_1:第一保護訊號 PROTECT_1: First protection signal

PROTECT_2:第二保護訊號 PROTECT_2: Second protection signal

PEQ_OUT:等化器輸出訊號 PEQ_OUT: equalizer output signal

TH1:第一門檻值 TH1: the first threshold

TH2:第二門檻值 TH2: the second threshold

AV:平均值 AV: average value

Claims (18)

一種參數等化器，包含有：一等化器電路，用以接收一輸入訊號，並且處理該輸入訊號以產生一輸出訊號；一第一保護電路，用以根據該輸出訊號、該輸入訊號以及一第一處理訊號來產生一第一保護訊號，其中該第一保護訊號的一峰值位準受保護而小於或等於該第一保護電路所使用的一第一門檻值；一第二保護電路，用以根據該輸入訊號以及一第二處理訊號來產生一第二保護訊號，其中該第一處理訊號涉及該第二處理訊號的產生，該第二處理訊號涉及該第一處理訊號的產生，以及該第一處理訊號的一峰值位準受保護而小於或等於該第二保護電路所使用的一第二門檻值；以及一第一加法電路，耦接於該第一保護電路以及該第二保護電路，並且用以將該第一保護訊號與該第二保護訊號結合以產生一等化器輸出訊號。 A parameter equalizer includes: an equalizer circuit for receiving an input signal and processing the input signal to generate an output signal; a first protection circuit for according to the output signal, the input signal and a first processing signal to generate a first protection signal, wherein a peak level of the first protection signal is protected to be less than or equal to a first threshold used by the first protection circuit; a second protection circuit, for generating a second protection signal based on the input signal and a second processed signal, wherein the first processed signal involves generation of the second processed signal, the second processed signal involves generation of the first processed signal, and A peak level of the first processed signal is protected to be less than or equal to a second threshold used by the second protection circuit; and a first summing circuit coupled to the first protection circuit and the second protection circuit The circuit is used for combining the first protection signal and the second protection signal to generate an equalizer output signal. 如申請專利範圍第1項所述之參數等化器，其中該第一保護電路包含有：一第一減法電路，耦接於該等化器電路，並且用以接收該輸入訊號，以及自該輸出訊號減去該輸入訊號以產生該第二處理訊號；一第二加法電路，耦接於該第一減法電路以及該第二保護電路，並且用以將該第一處理訊號與該第二處理訊號結合以產生一預調整訊號；以及一第一自動增益控制電路，耦接於該第二加法電路，並且用以根據該預調整訊號以及該第一門檻值來產生該第一保護訊號。 The parametric equalizer as described in item 1 of the scope of the patent application, wherein the first protection circuit includes: a first subtraction circuit, coupled to the equalizer circuit, and used to receive the input signal, and from the subtracting the input signal from the output signal to generate the second processing signal; a second adding circuit, coupled to the first subtracting circuit and the second protection circuit, and used for combining the first processing signal with the second processing The signals are combined to generate a pre-adjustment signal; and a first automatic gain control circuit is coupled to the second addition circuit and used to generate the first protection signal according to the pre-adjustment signal and the first threshold value. 如申請專利範圍第2項所述之參數等化器，其中該第二保護電路包含有：一第二自動增益控制電路，耦接於該第一減法電路以及該第二加法電路，並且用以根據該第二處理訊號以及該第二門檻值來產生該第一處理訊號；以及一第二減法電路，耦接於該第二自動增益控制電路，並且用以自該輸入訊號減去該第一處理訊號來產生該第二保護訊號。 The parametric equalizer described in item 2 of the scope of the patent application, wherein the second protection circuit includes: a second automatic gain control circuit, coupled to the first subtraction circuit and the second addition circuit, and used for Generate the first processing signal according to the second processing signal and the second threshold value; and a second subtraction circuit, coupled to the second automatic gain control circuit, and used for subtracting the first processing signal from the input signal The signal is processed to generate the second protection signal. 如申請專利範圍第1項所述之參數等化器，另包含有：一平均電路，用以產生該輸入訊號之一平均值以作為該第二門檻值。 The parametric equalizer described in item 1 of the scope of the patent application further includes: an averaging circuit, used to generate an average value of the input signal as the second threshold value. 如申請專利範圍第4項所述之參數等化器，其中該平均值係為該輸入訊號之一均方根值。 The parametric equalizer as described in item 4 of the scope of the patent application, wherein the average value is a root mean square value of the input signal. 如申請專利範圍第1項所述之參數等化器，其中該輸入訊號之一輸入位準以及該輸出訊號之一峰值位準皆小於或等於該第一門檻值，以及該等化器輸出訊號與該輸出訊號相同。 The parametric equalizer described in item 1 of the scope of patent application, wherein an input level of the input signal and a peak level of the output signal are both less than or equal to the first threshold value, and the output signal of the equalizer Same as the output signal. 如申請專利範圍第1項所述之參數等化器，其中該輸入訊號之一輸入位準小於或等於該第一門檻值，該輸出訊號之一峰值位準大於該第一門檻值，該等化器輸出訊號之一峰值位準被限制於該第一門檻值，以及該等化器輸出訊號之一最小位準等於該輸入訊號之該輸入位準。 The parametric equalizer described in item 1 of the scope of the patent application, wherein an input level of the input signal is less than or equal to the first threshold value, a peak level of the output signal is greater than the first threshold value, the A peak level of the output signal of the equalizer is limited to the first threshold, and a minimum level of the output signal of the equalizer is equal to the input level of the input signal. 如申請專利範圍第1項所述之參數等化器，其中該輸入訊號之一輸 入位準以及該輸出訊號之一峰值位準皆大於該第一門檻值，該等化器輸出訊號之一谷值被限制於該第一門檻值，以及該等化器輸出訊號之一最大位準等於該輸入訊號之該輸入位準。 As the parametric equalizer described in item 1 of the scope of the patent application, one of the input signals is output Both the input level and a peak level of the output signal are greater than the first threshold value, a valley value of the equalizer output signal is limited to the first threshold value, and a maximum level of the equalizer output signal is equal to the input level of the input signal. 如申請專利範圍第1項所述之參數等化器，另包含有：一第一多工器電路，具有一第一輸入埠、一第二輸入埠以及一第一輸出埠，其中該第一輸入埠係用以接收該輸入訊號，該第二輸入埠係用以接收該等化器輸出訊號，以及該第一多工器電路係用以根據一第一選擇訊號來將該第一輸出埠耦接至該第一輸入埠以及該第二輸入埠的其中一個；以及一第二多工器電路，具有一第三輸入埠、一第四輸入埠以及一第二輸出埠，其中該第三輸入埠係用以接收該輸出訊號，該第四輸入埠係用以接收在該第一多工器電路之該第一輸出埠的一輸出，以及該第二多工器電路係用以根據一第二選擇訊號來將該第二輸出埠耦接至該第三輸入埠以及該第四輸入埠的其中一個。 The parametric equalizer described in Item 1 of the scope of the patent application further includes: a first multiplexer circuit having a first input port, a second input port and a first output port, wherein the first The input port is used to receive the input signal, the second input port is used to receive the equalizer output signal, and the first multiplexer circuit is used to select the first output port according to a first selection signal coupled to one of the first input port and the second input port; and a second multiplexer circuit having a third input port, a fourth input port and a second output port, wherein the third The input port is used to receive the output signal, the fourth input port is used to receive an output at the first output port of the first multiplexer circuit, and the second multiplexer circuit is used to receive the output signal according to a The second selection signal is used to couple the second output port to one of the third input port and the fourth input port. 一種用以等化一輸入訊號以產生一等化器輸出訊號的方法，包含有：接收該輸入訊號，並且處理該輸入訊號以產生一輸出訊號；根據該輸出訊號、該輸入訊號以及一第一處理訊號來產生一第一保護訊號，其中該第一保護訊號的一峰值位準受保護而小於或等於一第一門檻值；根據該輸入訊號以及一第二處理訊號來產生一第二保護訊號，其中該第一處理訊號涉及該第二處理訊號的產生，該第二處理訊號涉及該第一處 理訊號的產生，以及該第一處理訊號的一峰值位準受保護而小於或等於一第二門檻值；以及將該第一保護訊號與該第二保護訊號結合以產生該等化器輸出訊號。 A method for equalizing an input signal to generate an output signal of an equalizer, comprising: receiving the input signal, and processing the input signal to generate an output signal; according to the output signal, the input signal and a first processing the signal to generate a first protection signal, wherein a peak level of the first protection signal is protected to be less than or equal to a first threshold value; generating a second protection signal according to the input signal and a second processing signal , wherein the first processed signal involves the generation of the second processed signal involving the first generation of a processing signal, and a peak level of the first processing signal is protected to be less than or equal to a second threshold value; and combining the first protection signal and the second protection signal to generate the equalizer output signal . 如申請專利範圍第10項所述之方法，其中根據該輸出訊號、該輸入訊號以及該第一處理訊號來產生該第一保護訊號的步驟包含有：自該輸出訊號減去該輸入訊號以產生該第二處理訊號；將該第一處理訊號與該第二處理訊號結合以產生一預調整訊號；以及根據該預調整訊號以及該第一門檻值來產生該第一保護訊號。 The method described in claim 10, wherein the step of generating the first protection signal according to the output signal, the input signal and the first processing signal includes: subtracting the input signal from the output signal to generate the second processing signal; combining the first processing signal and the second processing signal to generate a pre-adjustment signal; and generating the first protection signal according to the pre-adjustment signal and the first threshold. 如申請專利範圍第11項所述之方法，其中根據該輸入訊號以及該第二處理訊號來產生該第二保護訊號的步驟包含有：根據該第二處理訊號以及該第二門檻值來產生該第一處理訊號；以及自該輸入訊號減去該第一處理訊號以產生該第二保護訊號。 The method described in claim 11 of the patent application, wherein the step of generating the second protection signal according to the input signal and the second processing signal includes: generating the second protection signal according to the second processing signal and the second threshold value a first processing signal; and subtracting the first processing signal from the input signal to generate the second protection signal. 如申請專利範圍第10項所述之方法，另包含有：對該入訊號進行平均值計算來產生該輸入訊號之一平均值以作為該第二門檻值。 The method described in item 10 of the patent application further includes: performing average calculation on the input signal to generate an average value of the input signal as the second threshold value. 如申請專利範圍第13項所述之方法，其中該平均值係為該輸入訊號之一均方根值。 The method described in claim 13, wherein the average value is a root mean square value of the input signal. 如申請專利範圍第10項所述之方法，其中該輸入訊號之一輸入位準以及該輸出訊號之一峰值位準皆小於或等於該第一門檻值，以及該等化器 輸出訊號與該輸出訊號相同。 The method described in claim 10, wherein both an input level of the input signal and a peak level of the output signal are less than or equal to the first threshold value, and the equalizer The output signal is the same as the output signal. 如申請專利範圍第10項所述之方法，其中該輸入訊號之一輸入位準小於或等於該第一門檻值，該輸出訊號之一峰值位準大於該第一門檻值，該等化器輸出訊號之一峰值位準被限制於該第一門檻值，以及該等化器輸出訊號之一最小位準等於該輸入訊號之該輸入位準。 The method described in claim 10 of the scope of the patent application, wherein an input level of the input signal is less than or equal to the first threshold value, a peak level of the output signal is greater than the first threshold value, and the equalizer outputs A peak level of the signal is limited to the first threshold, and a minimum level of the equalizer output signal is equal to the input level of the input signal. 如申請專利範圍第10項所述之方法，其中該輸入訊號之一輸入位準以及該輸出訊號之一峰值位準皆大於該第一門檻值，該等化器輸出訊號之一谷值被限制於該第一門檻值，以及該等化器輸出訊號之一最大位準等於該輸入訊號之該輸入位準。 The method described in claim 10, wherein both an input level of the input signal and a peak level of the output signal are greater than the first threshold value, and a valley value of the output signal of the equalizer is limited At the first threshold, and a maximum level of the equalizer output signal is equal to the input level of the input signal. 如申請專利範圍第10項所述之方法，另包含有：根據一第一選擇訊號來對該輸入訊號以及該等化器輸出訊號進行一第一多工操作，以產生一第一多工輸出；以及根據一第二選擇訊號來對該輸出訊號以及該第一多工輸出進行一第二多工操作，以產生一第二多工輸出。 The method described in item 10 of the scope of patent application further includes: performing a first multiplexing operation on the input signal and the output signal of the equalizer according to a first selection signal to generate a first multiplexing output ; and perform a second multiplexing operation on the output signal and the first multiplexing output according to a second selection signal to generate a second multiplexing output.
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Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5101292B2 (en) * 2004-10-26 2012-12-19 ドルビー ラボラトリーズ ライセンシング コーポレイション Calculation and adjustment of audio signal's perceived volume and / or perceived spectral balance
CN104079247A (en) * 2013-03-26 2014-10-01 杜比实验室特许公司 Equalizer controller and control method
US9053697B2 (en) * 2010-06-01 2015-06-09 Qualcomm Incorporated Systems, methods, devices, apparatus, and computer program products for audio equalization
CN107409256A (en) * 2015-02-16 2017-11-28 歌拉利旺株式会社 Sound field correcting apparatus, field calibration method and sound field correction program
US9870783B2 (en) * 2015-10-12 2018-01-16 Microsoft Technology Licensing, Llc Audio signal processing
CN109845288A (en) * 2016-10-14 2019-06-04 诺基亚技术有限公司 Method and apparatus for the output signal equilibrium between microphone
TWI662788B (en) * 2009-02-18 2019-06-11 瑞典商杜比國際公司 Complex exponential modulated filter bank for high frequency reconstruction or parametric stereo
CN110024419A (en) * 2016-10-11 2019-07-16 Dts公司 Balanced (GPEQ) filter of gain-phase and tuning methods for asymmetric aural transmission audio reproduction

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5101292B2 (en) * 2004-10-26 2012-12-19 ドルビー ラボラトリーズ ライセンシング コーポレイション Calculation and adjustment of audio signal's perceived volume and / or perceived spectral balance
TWI662788B (en) * 2009-02-18 2019-06-11 瑞典商杜比國際公司 Complex exponential modulated filter bank for high frequency reconstruction or parametric stereo
US9053697B2 (en) * 2010-06-01 2015-06-09 Qualcomm Incorporated Systems, methods, devices, apparatus, and computer program products for audio equalization
CN104079247A (en) * 2013-03-26 2014-10-01 杜比实验室特许公司 Equalizer controller and control method
US10044337B2 (en) * 2013-03-26 2018-08-07 Dolby Laboratories Licensing Corporation Equalizer controller and controlling method
CN107409256A (en) * 2015-02-16 2017-11-28 歌拉利旺株式会社 Sound field correcting apparatus, field calibration method and sound field correction program
US9870783B2 (en) * 2015-10-12 2018-01-16 Microsoft Technology Licensing, Llc Audio signal processing
CN110024419A (en) * 2016-10-11 2019-07-16 Dts公司 Balanced (GPEQ) filter of gain-phase and tuning methods for asymmetric aural transmission audio reproduction
CN109845288A (en) * 2016-10-14 2019-06-04 诺基亚技术有限公司 Method and apparatus for the output signal equilibrium between microphone

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