TWI780653B - Method for identifying flash memory type and device thereof - Google Patents

Abstract

A method for identifying flash memory type and a device are provided. The method is executed by a processor, comprising: driving a flash memory interface in a specific setting state to transmit a read command for reading the flash memory identity to the flash memory module using a specific communication protocol; if a read attempt fails, change the setting state of the flash memory interface, the communication protocol, or both, and then perform a read operation until the pre-determined adjustments have been tried; and if the reading attempt successes, the read flash memory identity is stored in non-volatile memory, allowing an electronic device to write the corresponding firmware to the specified address in the non-volatile memory or/and flash module in the master IC based on the flash identification code.

Description

Method and device for identifying type of flash memory

The invention relates to a storage device, and in particular to a method and device for identifying the type of flash memory.

Many types of NAND flash memory are used in various storage products such as Solid-state disk (SSD), Pen-drive, Secure Digital Memory Card (SD card) , For example, manufacturers include Intel (Intel), Micron (Micron), Toshiba (TOSHIBA), Samsung (SAMSUNG), Hynix (HYNIX), and the categories include single-level cell (Single-level cell; SLC), multi-level cell (Multi-level cell) cell; MLC), three-level cell (Triple-level cell; TLC), four-level cell (Quad-level cell; QLC), the interface has a single data rate (Single data rate; SDR), the first generation double data rate Transmission rate (Double data rate; DDR), second-generation double data rate (Double data rate 2; DDR2), third-generation double data rate (Double data rate 3; DDR3), etc. Different manufacturers and different types of NAND flash memory support different command formats, so you need to know the specific type of NAND flash memory before you can issue the correct command to read and write NAND flash memory and get the correct result .

The method in the prior art is to obtain information such as the manufacturer and category of the NAND flash memory connected to the main control by manual means before the card is opened, and then assign the corresponding NAND flash memory identification code (Identity ; ID) into the electronic fuse (eFuse) structure in the main control, and write the corresponding NAND flash memory firmware (Firmware; FW) into the main control according to the information in the electronic fuse after the reset (Reset). In the non-volatile memory or NAND flash memory in the controller, it is used to allow the host to read and write the NAND flash memory through the firmware running on the main control integrated circuit (Integrated Circuit; IC) after the storage product leaves the factory and access the data in it. However, the cost of the electronic fuse structure is relatively high. In addition, once the information of the electronic fuse is burned, it cannot be erased, so that after replacing it with a different manufacturer or a different type of NAND flash memory, the information stored in the electronic fuse structure The ID of the NAND flash memory is inconsistent with the newly set NAND flash memory. If the firmware obtained according to the old NAND flash memory ID, cannot correctly read and write the newly configured NAND flash memory. Therefore, once the NAND flash memory installed on the printed circuit board is replaced, the main control IC used to operate the NAND flash memory must also be replaced together, making it inflexible in manufacturing storage products. In view of this, how to alleviate or eliminate the deficiencies in the above-mentioned related fields is a problem to be solved.

In some embodiments, a method of identifying a type of flash memory is performed by a processor when loading and executing program code. The method includes driving the flash memory interface in a specific setting state to issue a read command for reading the flash memory identification code to the flash memory module by using a specific communication protocol. If the read fails, change the setting state of the flash memory interface, the communication protocol, or both, and perform a read operation again until all preset adjustments have been tried. And if the reading is successful, store the read flash memory identification code in the non-volatile memory, so that the electronic device writes the corresponding firmware into the non-volatile memory in the main control integrated circuit according to the flash memory identification code. The specified address in the non-volatile memory or/and the flash memory module; wherein, the settings that the flash memory interface can adjust include the digital voltage supplied to the flash memory module and the digital voltage sent to the flash memory module The number of clock cycles of the address information of .

In some embodiments, a device for identifying a flash memory type includes a flash memory interface, a non-volatile memory, and a processor. The flash memory interface is coupled to the flash memory module, and the processor is coupled to the flash memory interface and the non-volatile memory. When the processor is used for loading and executing related program codes, the above-mentioned method steps are realized.

In summary, according to some embodiments of the method and device for identifying the type of flash memory of the present invention, the type of NAND flash memory can be automatically identified, and the identified NAND flash memory identification code can be automatically stored in a non-volatile memory. Memory, so that the electronic device writes the corresponding firmware into the non-volatile memory in the main control integrated circuit or the specified address in the NAND flash memory module according to the NAND flash memory identification code, and can Solve the shortcomings of high cost and low manufacturing flexibility caused by traditional manual identification and reprogramming of electronic fuses.

Embodiments of the present invention will be described below in conjunction with related drawings. In these drawings, the same reference numerals indicate the same or similar elements or method flows.

It must be understood that words such as "comprising" and "including" used in this specification are used to indicate the existence of specific technical features, values, method steps, operations, components and/or components, but do not exclude possible Add more technical features, values, method steps, job processing, components, components, or any combination of the above.

Words such as "first", "second", and "third" used in the present invention are used to modify the elements in the claims, and are not used to indicate that there is a priority order, a prior relationship between them, or that a component comes first. The reference to another element, or the chronological order in which method steps are performed, are only used to distinguish elements with the same name.

It must be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, intervening elements may be present. In contrast, when an element is described as being "directly connected" or "directly coupled" to another element, there are no intervening elements present. Other words used to describe the relationship between elements may be interpreted in a similar manner, such as "between" versus "directly between," or "adjacent" versus "directly adjacent," and so forth.

Please refer to FIG. 1 , which is a block diagram of an embodiment of a storage device according to the present application. The storage product 100 includes a main control integrated circuit (Integrated Circuit; IC) 110 and a plurality of NAND flash memory modules 131 - 138 . The storage product 100 can be a solid-state disk (Solid-state disk; SSD), a pen-drive (Pen-drive), a secure digital memory card (Secure Digital Memory Card; SD card), etc., through serial advanced technology attachment (Serial advanced technology attachment) ; SATA), fast peripheral component interconnection (Peripheral component interconnect express; PCI-E), universal serial bus (Universal serial bus; USB) interface and associated communication protocols from the host (Host) to receive read, write, Commands such as erasing, as well as related parameters and data, are then executed accordingly.

The main control IC 110 can be connected to multiple memory banks (Memory banks), and each memory bank can contain multiple NAND flash memory modules, for example, the first memory bank contains NAND flash memory modules 131 and 132. The second memory bank includes NAND flash memory modules 133 and 134, and so on, so that the NAND flash memory modules in the same memory bank can share data lines. The main control IC 110 can use Open NAND Flash Memory (Open NAND Flash Interface; ONFI), Switch (Toggle) or other communication protocols to communicate with the NAND Flash Memory Modules 131-138, and is used to transfer from a specific NAND Flash Memory The module reads data, writes data to a specific NAND flash memory module, or erases the data of a specified physical block in a specific NAND flash memory module. NAND flash memory modules 131-138 can be manufactured by Intel (Intel), Micron (Micron), Toshiba (TOSHIBA), Samsung (SAMSUNG), Hynix (HYNIX), provide a large amount of data storage capacity, usually digital Hundreds of gigabytes (Gigabytes), or even trillions of megabytes (Terabytes). NAND flash memory modules 131-138 can be single-level cell (Single-level cell; SLC), multi-level cell (Multi-level cell; MLC), triple-level cell (Triple-level cell; TLC), quadruple-level cell (Quad-level cell; QLC) and other different types of modules. NAND flash memory modules 131-138 can include single data rate (Single data rate; SDR), second generation double data rate (Double data rate 2; DDR2), third generation double data rate (Double data rate 3; DDR3) and other different types of interfaces.

Please refer to FIG. 2 . FIG. 2 is a block diagram of an embodiment of the main control integrated circuit 110 according to the present application. In some embodiments, the main control IC 110 includes a processor 210 , a host interface 230 , a flash memory interface 250 and a non-volatile memory (Non-volatile memory) 270 . The non-volatile memory 270 can be realized by using a static random access memory (SRAM), and is used for storing the program code of the self-adjusting identification module 272 . The processor 210 can be implemented using general-purpose hardware (for example, a single processor, a multi-processor with parallel processing capability, a graphics processing unit, or other processors with computing capabilities), and when loading and executing the self-adjusting identification module 272 code, complete the self-tuning method for identifying the type of flash memory described later. The non-volatile memory 270 can also be used to store the identification result 274 , for example, the state of the memory bank, the identification codes (Identity; ID) of the NAND flash memory modules 131 - 138 , and the like. The host interface 230 is coupled to the host, the flash memory interface 250 is coupled to the NAND flash memory modules 131 - 138 , and the processor 210 is coupled to the host interface 230 , the flash memory interface 250 and the non-volatile memory 270 . The processor 210 can communicate with the host through the host interface 230 , and communicate with the NAND flash memory modules 131 - 138 through the flash memory interface 250 . The flash memory interface 250 includes a plurality of registers, so that the processor 210 can adjust the physical configurations (Physical configurations) of the flash memory interface 250 by changing the contents of the registers.

In order to overcome the disadvantages of using manual work with electronic fuses, from one aspect, the embodiment of the present invention proposes that the main control IC 110 executes automatic processing to obtain the NAND flash memory ID before the card is activated successfully. But at the beginning, the main control IC110 does not know whether there is a NAND flash memory module on the memory bank, and the type of the NAND flash memory module. Therefore, the main control IC110 performs a self-adjustment to identify the type of the flash memory method, including a trial-and-error-like mechanism. That is to say, the processor 210 has a plurality of identification modes, and the main control IC 110 will sequentially use different identification modes to issue a read command for reading the ID of the NAND flash memory to the NAND flash memory module 131˜ One or more of 138 until the read succeeds. When the reading is successful, it means that the main control IC 110 has learned the type of the NAND flash memory module. In one embodiment, the identification mode includes flash memory interface configuration and communication protocol. In detail, when the processor 210 loads and executes the program code of the self-adjustment identification module 272, it drives the flash memory interface 250 in a specific setting state to use a specific communication protocol to send a message for reading the NAND flash memory ID. The read command is sent to one or more of the NAND flash memory modules 131-138. If the read fails, the processor 210 changes the setting state of the flash memory interface 250, the communication protocol used, or both, and performs a read operation again until all preset adjustments have been tried. Once the reading is successful, the processor 210 stores the read NAND flash memory ID into the non-volatile memory 270, so that an electronic device can write the corresponding firmware into the non-volatile memory according to the NAND flash memory ID. The specified addresses of the specified physical blocks in the memory 270 or the NAND flash memory modules 131-138 are used to complete the card opening operation. If all preset adjustments have been tried and the NAND flash memory ID has not been successfully read, an error message will be fed back to the host or the operator for further detection and error removal or manual setting. Among them, the adjustable communication protocol includes SDR protocol and DDR2 protocol, and the adjustable configuration in the flash memory interface 250 includes the digital voltage (VCCQ) provided to the NAND flash memory modules 131-138 and the digital voltage (VCCQ) sent to the NAND flash memory modules 131-138. The number of clock cycles of the address information of the flash memory modules 131-138. The details are as follows:

The method realized when the processor 210 loads and executes the program code of the self-adjusting recognition module 272 can refer to the flowcharts shown in FIG. 3A and FIG. 3B , and the details are as follows:

Step S312: Initially, the storage product 100 is powered on and reset. The processor 210 uses a preset identification mode to identify the type of the flash memory.

Step S314: Existence detection of the NAND flash memory module is performed. The processor 210 can drive the flash memory interface 250 to detect the status of each connected memory bank. For example, the flash memory interface 250 can apply a voltage to a specific pin of each memory bank, and observe whether there is a response (Response). Once a response is found on the specific memory bank, it is determined that the memory bank is provided with a NAND flash memory module. For example, assuming that the flash memory interface 250 is connected to 8 memory banks, but a response is only found in 4 memory banks, the processor 210 determines that there are NAND flash memory modules on these 4 memory banks .

Step S316: Determine whether there is a NAND flash memory module in the storage product 100. If yes, proceed to step S322. Otherwise, proceed to step S318. When the flash memory interface 250 finds a response in any memory bank, the processor 210 determines that there is a NAND flash memory module in the storage product 100 .

Step S318 : Feed back the information that the NAND flash memory does not exist, for launching further detection and error removal operations. For example, when there is no NAND flash memory module in the storage product 100 , no subsequent identification of the flash memory type is required. For another example, if there is a NAND flash memory module in the storage product 100, but the feedback information that the NAND flash memory does not exist indicates that the storage product 100 needs further testing.

Step S322 : The drive flash memory interface 250 sends a command to read the NAND flash memory ID to the NAND flash memory module, such as one of the NAND flash memory modules 131 - 138 , using the SDR protocol. At this time, the flash memory interface 250 is in the state of default configurations (Default configurations), for example, the VCCQ supplied to the NAND flash memory module is 1.8V, and the address information output to the NAND flash memory module for 5 clock cycles and so on.

Step S324: Determine whether the reading is successful. If yes, proceed to step S360. Otherwise, proceed to step S332. If the processor 210 receives the correct NAND flash memory ID from the designated NAND flash memory module after sending the command, it means that the reading is successful. When the reading is successful, not only the NAND flash memory ID is obtained, but also the processor 210 knows that the default configuration of the flash memory interface 250 can use the SDR protocol to normally access the data in the NAND flash memory module. In other words, the processor 210 also obtains the type of the flash memory interface 250 . On the contrary, if the processor 210 receives an unrecognizable reply from the specified NAND flash memory module after sending the command or still does not get a reply after a timeout, it means that the reading fails.

Step S332 : The processor 210 switches to the next identification mode to identify the type of the flash memory, and powers off the NAND flash memory modules 131 - 138 and restarts them. There can be a preset time interval between power off and power on again.

Step S334: The drive flash memory interface 250 uses DDR2 to issue a command to read the NAND flash memory ID to the NAND flash memory module, such as one of the NAND flash memory modules 131-138. At this time, the flash memory interface 250 is in a default configuration state.

Step S336: Determine whether the reading is successful. If yes, proceed to step S360. Otherwise, proceed to step S342. When the reading is successful, not only the NAND flash memory ID is obtained, but also the processor 210 knows that the default configuration of the flash memory interface 250 can use DDR2 to normally access the data in the NAND flash memory module. The technical details of the judgment in this step are similar to step S324, and will not be repeated for simplicity.

Step S342: The processor 210 switches to the next identification mode to identify the type of flash memory, and powers off the NAND flash memory modules 131-138 and provides settings for the NAND flash memory modules 131-138. The VCCQ of 138 is 1.2V. There can be a preset time interval between power off and power on again.

Step S344: The drive flash memory interface 250 uses DDR2 to issue a command to read the NAND flash memory ID to the NAND flash memory module, such as one of the NAND flash memory modules 131-138. At this time, the flash memory interface 250 is in an adjusted state.

Step S346: Determine whether the reading is successful. If yes, proceed to step S360. Otherwise, proceed to step S352. When the reading is successful, not only the NAND flash memory ID is obtained, but also the processor 210 knows that the adjusted configuration of the flash memory interface 250 can use DDR2 to normally access the data in the NAND flash memory module. The technical details of the judgment in this step are similar to step S324, and will not be repeated for simplicity.

Step S352: The processor 210 switches to the next identification mode to identify the flash memory type, so that the NAND flash memory modules 131-138 are powered off and then powered on and set to use 6 clock cycles to transmit address information to NAND flash memory modules 131-138. There can be a preset time interval between power off and power on again.

Step S354 : The drive flash memory interface 250 uses the SDR protocol to issue a command to read the NAND flash memory ID to the NAND flash memory module, such as one of the NAND flash memory modules 131 - 138 . At this time, the flash memory interface 250 is in an adjusted state.

Step S356: Determine whether the reading is successful. If yes, proceed to step S360. Otherwise, proceed to step S358. When the reading is successful, not only the NAND flash memory ID is obtained, but also the processor 210 knows that the adjusted configuration of the flash memory interface 250 can use the SDR protocol to normally access the data in the NAND flash memory module. The technical details of the judgment in this step are similar to step S324, and will not be repeated for simplicity.

Step S358 : Feedback the information that the NAND flash memory cannot be identified, for launching further detection and error removal operations. For example, check that the NAND flash memory module is correctly soldered on the memory bank.

Step S360: store the identification result 274 to the non-volatile memory 270, for example, may include the read NAND flash memory ID, the configuration parameters of the current flash memory interface 250, etc., so that the host can then restart the main control After the IC110, according to the NAND flash memory ID in the non-volatile memory 270 of the main control IC110, the firmware corresponding to the NAND flash memory modules 131-138 is written into the non-volatile memory in the main control IC110 Or specify the specified address of the physical block in the NAND flash memory modules 131-138 to complete the card opening operation.

All or part of the steps in the method of the present invention can be implemented by computer programs, such as computer operating systems, drivers or software programs for specific hardware in the computer. In addition, other types of programs as shown above may also be implemented. Those with ordinary knowledge in the technical field can write the method of the embodiment of the present invention into a computer program, and the description is omitted for the sake of brevity. The computer program implemented according to the method of the embodiment of the present invention can be stored in an appropriate computer-readable medium, such as DVD, CD-ROM, USB, hard disk, and can also be placed on a network (such as the Internet or other appropriate carriers) Accessed web server.

Although the components described above are included in FIG. 1 and FIG. 2 , it is not excluded to use more other additional components to achieve better technical effects without violating the spirit of the invention. In addition, although the flow charts in FIG. 3A and FIG. 3B are executed in a specified order, those skilled in the art can modify the order of these steps on the premise of achieving the same effect without violating the spirit of the invention. Therefore, the present invention is not limited to using only the sequence described above. In addition, those skilled in the art may also integrate several steps into one step, or perform more steps sequentially or in parallel in addition to these steps, and the present invention is not limited thereby.

In summary, according to some embodiments of the method and device for self-adjusting and identifying the type of the flash memory of the present invention, the type of the NAND flash memory can be automatically identified, and the identified NAND flash memory identification code can be automatically stored in the Non-volatile memory, so that the electronic device writes the corresponding firmware into the non-volatile memory in the main control integrated circuit or/and the specified bit in the NAND flash memory module according to the NAND flash memory identification code address, and can solve the shortcomings of high cost and low manufacturing flexibility caused by traditional manual identification and reprogramming of electronic fuses.

While the invention has been described using the above examples, it should be noted that these descriptions are not intended to limit the invention. On the contrary, this invention covers modifications and similar arrangements obvious to those skilled in the art. Therefore, the claims must be construed in the broadest possible manner to include all obvious modifications and similar arrangements.

100: store product 110: Main control integrated circuit 131～138: NAND flash memory module 210: Processor 230: host interface 250: Flash memory interface 270: Non-volatile memory 272: Self-adjustment recognition module 274: Recognition result S312: step S314: step S316: step S318: step S322: step S324: step S332: step S334: step S336: step S342: step S344: step S346: step S352: Step S354: step S356: Step S358: step S360: Steps

[Fig. 1] is a block diagram of an embodiment of the storage device according to the present case. [Fig. 2] is a block diagram of an embodiment of the main control integrated circuit according to this case. [FIG. 3A] is a flow chart of the method according to one embodiment of self-adjustment and identification of flash memory type in this case. [FIG. 3B] is a flow chart of another embodiment of the self-adjustment and identification of flash memory type according to the present case.

100: store product

110: Main control integrated circuit

131~138: NAND flash memory module

Claims (10)

A method of identifying a type of flash memory, performed by a processor when loading and executing code, comprising: driving a flash memory interface in a specific setting state to send a read command for reading a flash memory identification code to a flash memory module using a specific communication protocol; If the read fails, change the setting state of the flash memory interface, the communication protocol, or both, and perform a read operation again until all preset adjustments have been tried; and If the reading is successful, the read flash memory identification code is stored in a non-volatile memory, so that the electronic device writes the corresponding firmware into a main control integrated circuit according to the flash memory identification code the specified address in the non-volatile memory or/and the flash memory module; Wherein, the adjustable settings of the flash memory interface include a digital voltage provided to the flash memory module and a clock cycle number of address information sent to the flash memory module. The method for identifying the type of flash memory according to Claim 1, wherein the digital voltage is 1.8 V or 1.2 V. The method for identifying the type of flash memory according to claim 1, wherein the number of clock cycles is 5 or 6. The method for identifying the type of the flash memory according to claim 1, wherein the method is executed before the card is activated successfully. The method for identifying the type of flash memory according to claim 1, wherein the communication protocol includes a single data rate protocol and a second-generation double data rate protocol. The method for identifying the type of flash memory as described in claim 1, wherein the main control integrated circuit includes the processor, the non-volatile memory and the flash memory interface, and the flash memory interface coupling Connect the flash memory module. A device for identifying the type of flash memory, comprising: a flash memory interface coupled to a flash memory module; a non-volatile memory; and A processor, coupled to the flash memory interface and the non-volatile memory, is used to drive the flash memory interface in a specific setting state and use a specific communication protocol to read a flash memory A read command of the identification code is given to the flash memory module; if the read fails, change the setting state of the flash memory interface, the communication protocol, or both, and perform a read operation again until and if the reading is successful, store the read out flash memory identification code in the non-volatile memory, so that the electronic device can use the flash memory identification code to update the corresponding firmware write to a non-volatile memory in a master integrated circuit or/and a specified address in the flash memory module; Wherein, the settings that can be adjusted by the flash memory interface include a digital voltage provided to the flash memory module and the number of clock cycles of address information sent to the flash memory module. The device for identifying flash memory type as claimed in claim 7, wherein the digital voltage is 1.8V or 1.2V. In the device for identifying flash memory type according to claim 7, the number of clock cycles is 5 or 6. In the device for identifying flash memory type according to claim 7, wherein the communication protocol includes a single data rate protocol and a second-generation double data rate protocol.

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