TWI779145B - Method of treating a single crystal silicon ingot to improve the lls ring/core pattern - Google Patents

Abstract

A method is disclosed for reducing the size and density of defects in a single crystal silicon wafer. The method involves subjected a single crystal silicon ingot to an anneal prior to wafer slicing.

Description

Method for processing single crystal silicon ingots to improve laser light scattering ring/nuclei patterns

The field of the invention relates generally to a method of processing a monocrystalline silicon ingot to reduce the size and density of defects in monocrystalline silicon wafers cut from the processed ingot.

Single crystal materials, which are the starting materials for the manufacture of many electronic components such as semiconductor devices and solar cells, are commonly prepared using the Czochralski ("CZ") method. Briefly, the Chowklarski method involves melting a polycrystalline source material, such as polycrystalline silicon ("polysilicon"), in a crucible to form a silicon melt, and then pulling a single crystal from the melt. Ingot.

Semiconductor wafers are typically made from single crystal ingots (eg, silicon ingots) that are processed to remove the seed and end cones and then trimmed, optionally sheared and ground to have one or more flat surfaces or notches to properly orient the wafer in subsequent procedures. The ingot is then diced into individual wafers. Although reference will be made herein to semiconductor wafers composed of silicon, other materials can be used to make semiconductor wafers, such as germanium, silicon carbide, silicon germanium, gallium arsenide, and other alloys of group III and V elements such as gallium nitride or indium phosphide) or alloys of Group II and VI components (such as cadmium sulfide or zinc oxide).

The ever-shrinking size of modern electronic devices imposes challenging constraints on the quality of silicon substrates, as determined at least in part by the size and distribution of microdefects grown therein. Most of the microdefects that form in silicon crystals grown by the Chowklarski process are clusters of point defects (ie, vacancies and self-interstitials) inherent in silicon or oxide precipitates.

Attempts to produce substantially defect-free single crystal silicon generally involve controlling the ratio of the crystal pull rate (v) to the magnitude (G) of the axial temperature gradient near the melt/crystal interface. For example, some known methods involve controlling the v/G ratio around a critical v/G value, in which case vacancies and interstitials are incorporated into the growing crystal ingot at very low and comparable concentrations, thereby interacting with each other. Annihilates and thus inhibits any possible formation of microdefects at lower temperatures. However, as described in U.S. Patent No. 8,673,248 to Kulkarni, controlling the v/G ratio around this critical v/G value can form an annular ring or "belt" of relatively large and/or concentrated condensation defects, which from The lateral surface or peripheral edge of the silicon crystal ingot extends radially inward a distance, referred to herein as a "defect edge zone" or simply "defect zone".

Such a defect zone is typically of lower quality than the rest of the silicon crystal ingot located radially inward from the defect zone, and can significantly reduce the yield of the crystal ingot. For example, increasingly stringent wafer quality requirements for memory devices have increased the required breakdown voltage for gate oxide integrity (GOI) tests used to evaluate memory devices (e.g., SRAM, DRAM) in silicon or the quality of semiconductor wafers. As a result, more GOI failures occur near or within the defect edge zone of substantially defect-free silicon wafers, thereby reducing yield.

This prior art section is intended to introduce the reader to various aspects of the present technology, which may be related to various aspects of the present invention, which are described and/or claimed below. It is believed that this discussion helps to provide the reader with background information to facilitate a better understanding of the various aspects of the invention. Accordingly, it should be understood that these statements are to be read in light of this teaching, and not as admissions of prior art.

In one aspect, the invention relates to a method of processing a silicon monocrystalline ingot, the method comprising: grinding the silicon monocrystalline ingot, wherein the silicon monocrystalline ingot includes an end, an end opposite the end tail end and a body between the seed end and the tail end, wherein the body is ground to a constant diameter; annealing the ground monocrystalline silicon ingot is sufficient to reduce the The size or number of localized laser scattering defects, temperature and duration; and cutting the annealed single crystal silicon ingot into at least two single crystal silicon wafers.

The invention further relates to a method of processing a silicon monocrystalline ingot, the method comprising: removing a cone and an end cone from the silicon monocrystalline ingot, wherein the silicon monocrystalline ingot comprises the cone, and the The end cone opposite the cone and a body between the seed cone and the end cone; the body of the monocrystalline silicon ingot is sheared such that the body of the monocrystalline silicon ingot comprises one or more monocrystalline silicon Segments, one of which has a thickness of at least about 1 cm, at least about 10 cm, or at least about 20 cm; annealing one or more of the sheared monocrystalline silicon segments is sufficient to reduce one of the sheared monocrystalline silicon segments The size or number of localized laser scattering defects on the wafer, temperature and duration; and dicing the annealed single crystal silicon segment into at least two single crystal silicon wafers.

There are various refinements on the features mentioned in the above aspects. Further features may also be incorporated into the above described aspects. These refinements and additional features may exist individually or in any combination. For example, various features discussed below in relation to any of the illustrated embodiments may be incorporated into any of the above-described aspects alone or in any combination.

Cross References to Related Applications

This application claims priority to U.S. Provisional Application No. 62/608,624, filed December 21, 2017, the disclosure of which is incorporated herein by reference as if set forth in its entirety.

The methods described herein facilitate reducing the size and concentration of defects formed in single crystal ingots, such as single crystal silicon ingots, grown by the Chowklarski method. Therefore, the method of the present invention is sufficient to remove defect patterns that affect device yield. Without being bound to a particular theory, wafers cut from an ingot can have a laser light scattering (LLS) ring/nucleation pattern, the source of which has been identified as defects formed during crystal pull Or etch pits formed by polished slicing procedures. LLS ring/nuclei patterns can only be detected after the wafer has been diced and during LLS ring/nuclei pattern measurement, which is one of the last procedural steps in the dicing technique. Conventionally, a heat treatment is performed on the diced wafer to remove defects associated with the LLS ring/nuclei pattern. According to the method of the invention, an ingot in the rod state is subjected to an annealing before wafer dicing. This anneal has several advantages, including reduced size and density of defects making up the LLS ring/nuclei pattern, time and cost savings compared to thermally treating individual wafers, reduced contamination due to rod state thermal processing and heating a Uniformity resulting from an entire ingot or section of an ingot rather than individual wafers.

The monocrystalline silicon ingots used in the method of the present invention can be of any length and diameter obtainable by the Chowklarski method. In some embodiments, the ingot may have a diameter of at least about 100 mm, at least about 200 mm, such as at least about 300 mm, at least about 400 mm, or even at least about 450 mm, such as between about 150 mm and about 450 mm. between. In some embodiments, the length of the ingot is at least 25 cm, such as at least about 50 cm, at least about 75 cm, at least about 100 cm, at least about 150 cm or even at least about 200 cm, such as between about 100 cm and about Between 300 cm. In some embodiments, the mass of an ingot having such length and diameter may be at least about 15 kg or at least about 100 kg, such as at least about 200 kg, at least about 300 kg, at least about 400 kg, at least about 500 kg, At least about 600 kg, at least about 700 kg, or even at least about 800 kg, such as between about 15 kilograms (kg) and about 450 kg, such as between about 150 kg and about 450 kg. A single crystal silicon ingot grown by the Chowklarski method includes a cone at the seed end and an end cone at a tail end opposite the seed end. The ingot also includes a body portion between the seed end and the tail end. After the ingot is grown, the monocrystalline silicon ingot can be cooled to a temperature that allows for handling. Although the method of the present invention can be applied to an as-grown ingot, generally speaking, the seed and end cones will be removed from the ingot prior to the method of the present invention.

In some embodiments, the monocrystalline silicon ingot with the seed cone and tail cone removed may be sheared into one or more monocrystalline silicon segments. Single crystal silicon ingots can also be trimmed to have an orientation flat or a notch at a portion of the perimeter to indicate crystal orientation. Any of the one or more monocrystalline silicon segments may have a thickness of at least about 1 cm, at least about 10 cm, at least about 20 cm, or at least about 50 cm. Generally, a segment is less than about 1 m thick, less than about 50 cm thick, or less than about 40 cm thick, or less than 30 cm thick. In some embodiments, a segment is between about 10 cm and about 30 cm thick.

In some embodiments, the ingot may be subjected to grinding sufficient to produce an ingot having a body with a region of constant diameter. Grinding can occur across the entire monocrystalline silicon ingot (ie, prior to shearing). The length of an unsheared ingot can be at least about 1 cm, at least about 10 cm, at least about 20 cm, or at least about 1 m, such as between about 1 m and about 3 m. The ingots may weigh between about 15 kilograms (kg) and about 450 kg, such as between about 150 kg and about 450 kg. The systems and methods disclosed herein can also be used to grow the diameter of less than 150 mm or greater than 450 mm or between about 15 kilograms (kg) and about 450 kg (such as between about 150 kg and about 450 kg) ) ingots of loading sizes other than . Alternatively, a sheared segment can be ground to a constant diameter region. Any of the one or more monocrystalline silicon segments may have a thickness of at least about 1 cm, at least about 10 cm, at least about 20 cm, or at least about 50 cm. Generally, a segment is less than about 1 m thick, less than about 50 cm thick, or less than about 40 cm thick, or less than about 30 cm thick. In some embodiments, a segment is between about 10 cm and about 30 cm thick. A machine using a grinding wheel shapes the ingot to the precision required for wafer diameter control. Other grinding wheels are then used to engrave a characteristic notch or a plane to define the proper orientation of the future wafer with respect to a particular crystallographic axis. The constant diameter region may have a diameter of at least about 150 mm, at least about 200 mm, at least about 300 mm, or at least about 450 mm, such as between about 150 mm to about 450 mm.

During the growth procedure, the crucible slowly dissolves oxygen into the melt for incorporation into the final crystal ingot. In some embodiments, the ingot, or any single crystal silicon wafer cut therefrom, may include interstitial oxygen at a concentration generally achievable by the Chowklarski method. In some embodiments, the ingot or any single crystal silicon wafer cut therefrom includes oxygen at a concentration between about 4 PPMA (about 2×10 ¹⁷ atoms/cm ³ ) and about 18 PPMA (about 9×10 ¹⁷ atoms/cm 3 ). ³ ) between. In some embodiments, the semiconductor wafer includes oxygen at a concentration between about 4 PPMA (about 2×10 ¹⁷ atoms/cm ³ ) and about 45 PPMA (about 2.2× ^{10 18} atoms/cm ³ ), such as between about Between 10 PPMA (about 5x10 ¹⁷ atoms/cm ³ ) and about 35 PPMA (about 1.7x10 ¹⁸ atoms/cm ³ ). Preferably, the ingot or any single crystal silicon wafer cut therefrom includes oxygen at a concentration not greater than about 12 PPMA (about 6×10 ¹⁷ atoms/cm ³ ), such as less than about 10 PPMA (about 5×10 ¹⁷ atoms/cm ³ ). Interstitial oxygen can be measured according to SEMI MF 1188-1105.

Typical carbon concentrations in ingots grown by the Chowklarski method may be less than about ^1.0x1016 atoms/ ^cm3 , such as between about ^2x1015 atoms/ ^cm3 and about ^1.0x1016 atoms/ ^cm3 or between Between about 5x10 ¹⁵ atoms/cm ³ and about 1.0x10 ¹⁶ atoms/cm ³ .

The intentional addition of dopants controls the resistivity profile of the final crystal. In general, there is no limit to the resistivity of an ingot or any single crystal silicon wafer cut from it. Instead, the resistivity of ingots, segments, and wafers cut therefrom are determined by the end use of the wafers. An ingot, segment, or any monocrystalline silicon wafer cut therefrom may have any resistivity obtainable by the Chowklarski or Float Zone method. Therefore, the resistivity of the ingot, segment, or any monocrystalline silicon wafer cut therefrom is based on the requirements of the end use/application of the structures of the present invention. Accordingly, resistivity can vary from milliohms or less to megaohms or greater. In some embodiments, the ingot or any single crystal silicon wafer cut therefrom includes a p-type or an n-type dopant. Suitable dopants include p-type dopants such as boron, aluminum, gallium, and indium, and n-type dopants such as phosphorus, arsenic, and antimony. The dopant concentration is selected based on the desired resistivity. In some embodiments, the ingot, segment, or any single crystal silicon wafer cut therefrom includes a p-type dopant, such as boron. In some embodiments, the ingot, segment, or any single crystal silicon wafer cut therefrom includes an n-type dopant, such as arsenic or phosphorous.

In some embodiments, the ingot, segment, or any single crystal silicon wafer cut therefrom has a relatively low minimum volume resistivity, such as less than about 100 ohm-cm, less than about 50 ohm-cm, less than about 1 ohm-cm, below about 0.1 ohm-cm, or even below about 0.01 ohm-cm. In some embodiments, the ingot, segment, or any single crystal silicon wafer cut therefrom has a relatively low minimum volume resistivity, such as below about 100 ohm-cm or between about 1 ohm-cm and about 100 ohm -cm, such as between about 0.01 ohm-cm and about 100 ohm-cm. Low-resistivity wafers may include electrically active dopants, such as p-type dopants such as boron, aluminum, gallium and indium and/or n-type dopants such as phosphorus, arsenic and antimony.

In some embodiments, the ingot, segment, or any single crystal silicon wafer cut therefrom has a relatively high minimum volume resistivity. High resistivity ingots, segments or wafers may include electrically active dopants, such as p-type dopants (such as boron, aluminum, gallium, and indium) and/or n-type dopants (such as phosphorus, arsenic, and antimony) , etc. usually have very low concentrations. In some embodiments, the ingot, segment, or any monocrystalline silicon wafer cut therefrom has a minimum volume resistivity of at least 100 Ohm-cm, at least about 500 Ohm-cm, at least about 1000 Ohm-cm, or Even at least about 3000 Ohm-cm, such as between about 100 Ohm-cm and about 100,000 Ohm-cm or between about 500 Ohm-cm and about 100,000 Ohm-cm or between about 1000 Ohm-cm and about Between 100,000 Ohm-cm or between about 500 Ohm-cm and about 10,000 Ohm-cm or between about 750 Ohm-cm and about 10,000 Ohm-cm, between about 1000 Ohm-cm and about 10,000 Ohm -cm, between about 2000 Ohm-cm and about 10,000 Ohm-cm, between about 3000 Ohm-cm and about 10,000 Ohm-cm, or between about 3000 Ohm-cm and about 5,000 Ohm-cm between.

An ingot, segment, or any monocrystalline silicon wafer cut therefrom may have any of a (100), (110), or (111) crystallographic orientation, and the choice of crystallographic orientation may be dictated by the end use of the structure.

The monocrystalline silicon ingot or one of its sheared sections is subjected to an annealing prior to wafer dicing. Annealing can take place on the ingot with the seed cone and end cone still in place so that the seed cone and end cone are removed, or one of the sheared segments can be annealed. Anneal at a temperature and for a duration sufficient to reduce defects found in LLS ring/nuclei patterns from annealed ingots or sliced wafers. Advantageously, other defects may also be reduced. Annealing can occur in a furnace such as a chamber furnace suitable for industrial or laboratory use. The annealing ambient atmosphere is typically inert, ie, non-hydrogenating and/or non-oxidizing. In some embodiments, the atmosphere may include argon, nitrogen, or a combination of one of argon and nitrogen. In some embodiments, the ambient atmosphere includes argon. In some embodiments, the ambient atmosphere consists essentially of high purity argon, such as at least about 99 vol%, at least about 99.9 vol%, at least about 99.99 vol%, or even at least about 99.999 vol%. In some embodiments, the ambient atmosphere includes nitrogen. In some embodiments, the ambient atmosphere consists essentially of high purity nitrogen, such as at least about 99% by volume, at least about 99.9% by volume, at least about 99.99% by volume, or even at least about 99.999% by volume. In some embodiments, the ambient atmosphere includes a combination of argon and nitrogen, wherein the nitrogen content can vary between about 1% by volume and about 99% by volume, such as between about 10% by volume and about 90% by volume or between Between about 20% by volume and about 80% by volume, it is in equilibrium with argon. In some embodiments, the annealing temperature is at least about 600°C, such as between about 600°C and about 1200°C or between about 600°C and about 1000°C or between about 600°C and about 900°C or between about 700°C and about 900°C. In some embodiments, the monocrystalline silicon ingot or fragment thereof is annealed for a duration of at least about 1 hour, such as between about 1 hour and about 6 hours, such as between about 1 hour and about 4 hours Or a duration of one of between about 1 hour and about 3 hours or about 2 hours.

After annealing and cooling to a temperature sufficient to allow handling, individual wafers are cut from the heat-treated ingot. Wafer shaping involves the series of precise mechanical and chemical process steps required to turn an ingot fragment into a functional wafer. During these steps, the wafer surface and dimensions are refined to exacting detail. Each step is designed to make the wafer meet user specifications. The first of these critical steps is multi-wiring cutting. The main state-of-the-art cutting technology is multi-wire sawing (MWS). Here, a thin wire is positioned over a cylindrical reel so that hundreds of parallel wire segments run simultaneously through the ingot. While the saw as a whole moves slowly through the ingot, the individual wire segments perform a translational motion to keep the new wire in contact with the silicon. The sawing effect is actually achieved by SiC or other abrasives running along the line of rotation. After MWS, the wafers are cleaned and consolidated into process batches and transported to the next operation. Lateral deflection of the wire saw can cause marks or "waviness" on the wafer surface and line-to-line thickness variations result in wafer thickness variations no higher than a few microns. The wafer is thus exposed to a complex polishing procedure. Cut at least two wafers from annealed ingots or segments, each wafer comprising: two main substantially parallel surfaces, one of which is a front surface of a monocrystalline silicon wafer and the other of which is a monocrystalline silicon wafer. A rear surface of the crystalline silicon wafer; a circumferential edge connecting the front surface and the rear surface of the monocrystalline silicon wafer; a central plane between the front surface and the rear surface of the monocrystalline silicon wafer and parallel to these surfaces ; a central axis, which is perpendicular to the central plane; and a block-shaped region, which is between the front surface and the rear surface of the single crystal silicon wafer. Each wafer had a thickness, as measured between the front and rear surfaces of the monocrystalline silicon wafer and along the central axis, of less than about 1500 microns. A typical segment (eg, a segment having a length between about 10 cm and about 30 cm) can be diced into between about 2 wafers and about 400 wafers, such as between about 2 Between about 10 wafers and about 300 wafers or between about 50 wafers and about 300 wafers or between about 50 wafers and about 300 wafers.

Front surface polishing is usually performed in a two-step procedure. A mechanical polishing step (thinning) produces flatness, followed by a chemical etch to produce smoothness. After polishing, the wafer undergoes a final cleaning. Wafer thinning removes saw marks and surface defects from the front and back sides of the wafer, thins the wafer to gauge and relieves most of the stress that builds up in the wafer during the sawing process. The purpose of thinning includes removing subsurface damage in the diced wafer, thinning the wafer to a target thickness, and achieving a high degree of parallelism and flatness of the wafer surface. Both single-side and double-side thinning procedures can be used to thin the substrate wafer. In double-sided thinning (DSL), loose abrasive particles are suspended in a colloidal slurry to abrade material from the wafer surface. The wafer is held in a gear carrier driven by planetary motion. After manually loading a batch of wafers into the holes of the carrier, the upper wafers will be forced by a certain pressure (or weight) (for example, from about 1 kg to about 30 kg or from about 5 kg to about 20 kg, such as about 10 kg). board down. Both plates start to rotate in the same direction or in opposite directions. During double-sided thinning, both sides of the wafer are thinned simultaneously. The gel-like slurry is continuously filled into the thinning machine, and there is usually a thin film of slurry between the wafer and the two plates. The slurry performs material removal through the abrasive grit as it slides or rolls between the wafer surface and the two plates. Thinning may occur for at least 1 minute, at least 5 minutes, at least 10 minutes, at least 15 minutes, at least 20 minutes, at least 25 minutes, such as about 10 minutes. Thinning parameters including thinning pressure, plate rotation speed, plate material, abrasive material and grain size, slurry concentration, slurry flow rate, and carrier design can be based on known techniques. For example, the particle size in the thinning slurry may range from about 1 micron to about 250 microns, such as between about 1 micron and about 50 microns, such as between about 5 microns and about 20 microns. The spin rate may range from about 10 rpm to about 150 rpm or from about 25 rpm to about 150 rpm, such as about 50 rpm, about 75 rpm or about 100 rpm. In some embodiments, the wafer may be contacted with an aluminum oxide (Al ₂ O ₃ ) slurry. In some embodiments, the wafer may be contacted with a slurry comprising single crystal diamond particles. In some embodiments, the wafer may be contacted with a slurry including boron carbide particles. In some embodiments, the wafer may be contacted with a slurry including silicon carbide particles.

Edge grinding is usually performed before or after thinning and is very important to the structural integrity of the wafer. The edge grinding step is critical to the safety of the wafer edge. Single crystal silicon is very brittle and may peel off during handling if the edges are not profiled or rounded. Edge peeling not only adversely affects individual wafers, but can also affect other wafers being processed as edge peeling contaminates processing equipment or nearby wafers. The edges of 200 mm and 300 mm wafers are rounded, even in the notch area. Grind this edge with a diamond disc to remove damage and relieve peripheral stress. Adjust the final diameter of the wafer (with an accuracy of up to 0.02 mm) by edge grinding.

After a final cleaning and polishing, the wafer is ready for a final inspection before delivery. Use specially designed inspection tools to measure the flatness and surface particles of individual wafers to ensure wafer quality. The method of the present invention can reduce the defect characteristics of the LLS ring/nuclei pattern. In some embodiments, the number of defects in LLS ring/nuclei patterns can be reduced by at least about 50%, such as at least about 60%, at least about 70%, or even at least about 80%, using the 37 nm LLS size criterion. Example 1 .

A single crystal silicon ingot grown by the Chowklarski method is cut into segments by a shear saw. Silicon ingots were grown under conditions meeting the standards of Perfect Silicon ^TM (SunEdison Semiconductor, Ltd.). These criteria include ingots free of agglomeration defects, DSOD (Direct Surface Oxidation Defects), COP (Pit Originating from Crystal), D Defects, and I Defects. The oxygen concentration is less than 6.0x10 ¹⁷ atoms/cm ³ (approximately 12 PPMA).

Shear segments can be ground to have a constant diameter body. Alternatively, sheared fragments can be annealed prior to milling. The fragments were loaded into a chamber furnace (TCM, STC80K-CT). In some instances, the fragments were annealed at 500°C for one hour in a nitrogen atmosphere. In some instances, fragments were annealed at 900°C for up to two hours. The annealed segments were then diced into individual wafers by wire saw and analyzed for LLS ring/nuclear defect patterns.

The heat treatment at 500°C for 1 hour did not remove the 37 nm (LLS grid size) and 47 nm (LLS grid size) LLS patterns. See the second and third row in Figure 1. The rows depict the wafer defect pattern for an average of wafers cut from a segment before annealing and an average of 25 wafers cut from an annealed segment. As shown in Figure 1, the low temperature, short duration anneal did not significantly reduce the defect density. Each 25 wafer LLS images stacked on top of each other were investigated after the polishing and cleaning steps and it turned out that each 25 images before and after were also sister cassettes, meaning that each cassette image was the same image and quality before heat treatment. Longer duration anneals at higher temperatures reduced defect numbers and resulted in pattern disappearance, and LLS loop/nuclei patterns were completely removed under rod heat treatment conditions at 900°C for 2 hours. See the fourth and fifth rows of Figure 1. For these wafers, the LLS defect count was reduced from an average of 157 defects per wafer to 24 defects per wafer based on the 37 nm LLS size guidelines.

When introducing elements of the invention or its embodiment(s), the articles "a", "an", "the" and "these" are intended to mean that there are one or more of the elements. The terms "comprising", "including" and "having" are intended to be inclusive and mean that there may be additional elements other than the listed elements.

As various changes could be made in the above constructions and methods without departing from the scope of the invention, it is intended that all matter contained in the above description and shown in the accompanying drawings shall be interpreted as illustrative and not not a limiting meaning.

Figure 1 is a table depicting reduced LLS ring/nucleation patterns in single crystal silicon fragments before and after annealing at two temperatures and for two durations. Defects were measured under 37 nm and 47 nm test conditions.

Claims (27)

A method of processing a single crystal silicon ingot, the method comprising: grinding the single crystal silicon ingot, wherein the single crystal silicon ingot comprises an end, a tail end opposite the seed end, and the seed end and the tail end between a body, wherein the body is ground to a constant diameter, wherein the diameter of the body of the monocrystalline silicon ingot is at least about 150 mm; annealing the ground monocrystalline silicon ingot is sufficient to reduce the A temperature and duration of the size or number of localized laser scattering defects on a wafer cut from an ingot, wherein the monocrystalline silicon ingot is annealed at a temperature between about 600°C and about 900°C, and the annealed for a duration of at least about 1 hour, and further wherein the single crystal silicon ingot is annealed in an ambient atmosphere consisting of argon, nitrogen, or a combination of argon and nitrogen, so that the 37nm laser light scattering size criterion is used , reducing the number of defects in the laser light scattering ring/nuclei pattern by at least 80%; and cutting the annealed monocrystalline silicon ingot into at least two monocrystalline silicon wafers. The method of claim 1, wherein the monocrystalline silicon ingot is grown by the Chowklarski procedure, and the monocrystalline silicon ingot is cooled prior to grinding, and further wherein the monocrystalline silicon ingot comprises a concentration between about 4 PPMA ( Between about 2x10 ¹⁷ atoms/cm ³ ) and about 18 PPMA (about 9x10 ¹⁷ atoms/cm ³ ) of oxygen. The method of claim 1, wherein the diameter of the body of the silicon monocrystalline ingot is at least about 300 mm. The method according to claim 1, which further comprises cutting the monocrystalline silicon ingot into one or more slices The step of segments, wherein a segment has a thickness of at least about 1 cm. The method according to claim 1, further comprising the step of cutting the single crystal silicon ingot into one or more segments, wherein the thickness of one segment is less than about 1 m. The method according to claim 1, further comprising the step of cutting the single crystal silicon ingot into one or more segments, wherein the thickness of one segment is between about 10 cm and about 30 cm. The method of claim 1, wherein each monocrystalline silicon wafer cut from the annealed ingot comprises: two main substantially parallel surfaces, one of which is a front surface of the monocrystalline silicon wafer and which The other is a rear surface of the single crystal silicon wafer; a peripheral edge, which connects the front surface and the rear surface of the single crystal silicon wafer; a central plane, which is on the Between and parallel to the front surface and the rear surface; a central axis perpendicular to the central plane; and a block-like region between the front surface and the rear surface of the single crystal silicon wafer wherein each wafer has a thickness, as measured between the front surface and the back surface of the single crystal silicon wafer and along the central axis, of less than about 1500 microns. The method of claim 1, wherein the annealed single crystal silicon ingot is cut into between about two single crystal silicon wafers and about 300 single crystal silicon wafers. The method of claim 1, wherein the annealed single crystal silicon ingot is cut into about 300 single crystal silicon wafers. The method of claim 1, wherein the single crystal silicon ingot is annealed in an ambient atmosphere comprising nitrogen. The method of claim 1, wherein the single crystal silicon ingot is annealed in an ambient atmosphere consisting essentially of nitrogen. The method of claim 1, wherein the single crystal silicon ingot is annealed at a temperature between about 700°C and about 900°C. The method of claim 1, wherein the single crystal silicon ingot is annealed for a duration between about 1 hour and about 4 hours. The method of claim 1, wherein the single crystal silicon ingot is annealed for a duration of about 2 hours. A method of processing a silicon monocrystalline ingot, the method comprising: removing a cone and a tail cone from the silicon monocrystalline ingot, wherein the silicon monocrystalline ingot includes the seed cone, the tail opposite the seed cone cone and a main body between the seed cone and the end cone, wherein the diameter of the main body of the monocrystalline silicon ingot is at least about 150 mm; shearing the main body of the monocrystalline silicon ingot such that the monocrystalline silicon ingot The body of the ingot comprises one or more monocrystalline silicon segments, one of which has a thickness of at least about 1 cm; annealing one or more of the sheared monocrystalline silicon segments is sufficient to reduce cutting from the monocrystalline silicon segment The size or number of local laser scattering defects on a wafer, the temperature and duration, which One or more of the sheared single crystal silicon segments are annealed at a temperature between about 600°C and about 900°C for a duration of at least about 1 hour, and further wherein the Nitrogen or a combination of argon and nitrogen anneal one or more of the sheared single crystal silicon fragments in an ambient atmosphere to thereby scatter the laser light ring/nuclei using the 37nm laser light scattering size criterion reducing the number of defects in the pattern by at least 80%; and dicing the annealed single crystal silicon segment into at least two single crystal silicon wafers. The method of claim 15, wherein the monocrystalline silicon ingot is grown by Chowklarski procedure, and further wherein the monocrystalline silicon ingot comprises a concentration between about 4PPMA (about 2×10 ¹⁷ atoms/cm ³ ) and about 18PPMA ( Oxygen between about 9x10 ¹⁷ atoms/cm ³ ). The method of claim 15, further comprising grinding the body of the monocrystalline silicon segment, wherein the body is ground to a constant diameter of at least about 300 mm. The method of claim 15, wherein the thickness of one single crystal silicon segment is less than about 1 m. The method of claim 15, wherein the thickness of a single crystal silicon segment is between about 10 cm and about 30 cm. The method of claim 15, wherein each monocrystalline silicon wafer cut from the annealed monocrystalline silicon segment comprises: two main substantially parallel surfaces, one of which is a front surface of the monocrystalline silicon wafer and The other of them is a rear surface of the silicon monocrystalline wafer; a peripheral edge connecting the front surface and the rear surface of the silicon monocrystalline wafer; a central plane on the surface of the silicon monocrystalline wafer round front table between and parallel to the rear surface; a central axis perpendicular to the central plane; and a block-like region between the front surface and the rear surface of the single crystal silicon wafer, Wherein each wafer has a thickness, as measured between the front surface and the back surface of the single crystal silicon wafer and along the central axis, of less than about 1500 microns. The method of claim 15, wherein the annealed single crystal silicon segment is cut into between about two single crystal silicon wafers and about 300 single crystal silicon wafers. The method of claim 15, wherein the annealed single crystal silicon segment is cut into about 300 single crystal silicon wafers. The method of claim 15, wherein the single crystal silicon fragment is annealed in an ambient atmosphere comprising nitrogen. The method of claim 15, wherein the single crystal silicon segment is annealed in an ambient atmosphere consisting essentially of nitrogen. The method of claim 15, wherein the single crystal silicon segment is annealed at a temperature between about 700°C and about 900°C. The method of claim 15, wherein the single crystal silicon segment is annealed for a duration between about 1 hour and about 4 hours. The method of claim 15, wherein the single crystal silicon segment is annealed for a duration of about 2 hours.

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