TWI778105B - Printed circuit board - Google Patents

Abstract

A printed circuit board according to an example includes: an insulating layer of which a metal pad is embedded in the bottom surface; a metal via penetrating the insulating layer and formed on the metal pad, and a low-melting-point metal layer formed on an upper part of the metal via and having a melting point lower than that of the metal via, wherein the bottom surface of the metal pad is recessed more than the bottom surface of the insulating layer.

Description

A printed circuit board

The following description is about a printed circuit board.

With the implementation of long term evolution (LTE) services, a complex communication is being developed that modularizes an application processor (AP), a duplex (duplex), and a radio frequency (RF) switch module. In addition, with the development of Internet of Things (Internet of Things, IoT) technology, complex communication modules are combined with sensors. The substrates used in complex communication modules may be coreless substrates. In the case of a coreless substrate, the substrate may be formed as a multilayer substrate by a sequential lamination method using a carrier. Alternatively, the individual substrates can be fabricated separately and then all of the individual substrates compressed together.

Korean Patent No. 10-0734234 describes an example of a printed circuit board.

An object of the present invention is to provide a printed circuit board with excellent interlayer bonding strength.

According to an aspect of the present invention, there is provided a printed circuit board, the printed circuit board comprising: an insulating layer, metal pads are embedded in the bottom surface of the insulating layer; gold a metal through hole penetrates the insulating layer and is formed on the metal pad, and a low melting point metal layer is formed on the upper part of the metal through hole and has a melting point lower than that of the metal through hole, wherein the bottom surface of the metal pad is recessed beyond the bottom surface of the insulating layer.

According to another aspect of the present invention, a printed circuit board is provided, the printed circuit board includes: a first insulating layer, a bottom surface of the first insulating layer is embedded with a first metal pad; a metal bump, penetrate the first insulating layer and be formed on the upper portion of the first metal pad; a second insulating layer is formed on the first insulating layer and embedded in the bottom surface of the second insulating layer A second metal pad is disposed, wherein the bottom surface of the second metal pad is recessed beyond the bottom surface of the second insulating layer, and wherein the upper surface of the metal bump contacts the second metal pad the bottom surface of the pad.

According to another aspect of the present invention, there is provided a printed circuit board, the printed circuit board includes: a first insulating layer, in which a first metal pad is embedded; and a metal bump penetrating all the the first insulating layer is formed on the upper portion of the first metal pad; and the second insulating layer is formed on the first insulating layer, and a second metal is embedded in the second insulating layer A pad, wherein the metal bump penetrates the second insulating layer, and the upper surface of the metal bump contacts the bottom surface of the second metal pad.

Other features and aspects will be apparent from a reading of the following detailed description, drawings and claims.

100: insulating layer/first insulating layer

100': opening

110: Metal Pad/First Metal Pad

111, 131, 211: Recessed space/recessed part

120, 220: Metal bumps

121, 221: metal through hole

122, 222: low melting point metal layer

130, 230: Circuits

200: insulating layer/second insulating layer

210: Second metal pad

300: insulating layer/third insulating layer

310: Third metal pad

C: carrier

C1: Carrier component

C2: carrier metal foil/seed metal layer

P: circuit pattern layer

FIG. 1 shows an example of a printed circuit board.

FIG. 2 shows another example of a printed circuit board.

3 to 10 are cross-sectional views illustrating exemplary processes used in a method of manufacturing a printed circuit board.

Throughout the drawings and the detailed description, the same drawing numbers refer to the same elements. The figures may not be drawn to scale and the relative sizes, proportions, and depiction of elements in the figures may be exaggerated for clarity, illustration, and convenience.

The following detailed description is provided to assist the reader in gaining a comprehensive understanding of the methods, apparatus and/or systems described herein. However, various changes, modifications and equivalents of the methods, apparatus and/or systems described herein will be apparent to those skilled in the art. The sequences of operations described herein are examples only, and are not limited to those mentioned herein, but, as will be apparent to those of ordinary skill in the art, except that operations necessarily occur in a particular order Other than that, it can be changed. Also, descriptions of functions and constructions that are well known to those skilled in the art may be omitted for increased clarity and clarity.

Features described herein may be implemented in different forms and should not be construed as limited to the examples described herein. Rather, the examples described herein are provided so that this disclosure will be thorough and complete, and will convey the full scope of the invention to those skilled in the art.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Any term defined in a commonly used dictionary should be interpreted as having the same meaning as in the context of the related art, and unless explicitly defined otherwise, it should not be interpreted as having an idealized or overly formal meaning.

Regardless of the figure numbers, the same or corresponding components will be given the same reference numbers, and the same or corresponding components will not be repeatedly described. Throughout the description of the present invention, when the description of a specific related conventional art is determined to be irrelevant to the viewpoint of the present invention, the detailed description thereof will be omitted. Terms such as "first" and "second" may be used when describing various components, but the above components should not be limited to the above terms. The above terms are only used to distinguish the various components. In the accompanying drawings, some components may be exaggerated, omitted, or briefly shown, and the dimensions of the components do not necessarily reflect the actual dimensions of the components.

Hereinafter, specific embodiments of the present invention will be explained in detail with reference to the accompanying drawings.

FIG. 1 shows an example of a printed circuit board. FIG. 2 shows another example of a printed circuit board. 3 to 10 are cross-sectional views illustrating exemplary processes used in a method of manufacturing a printed circuit board.

Referring to FIG. 9 , a printed circuit board according to an embodiment of the present invention includes an insulating layer 100 , metal pads 110 and metal bumps 120 . As shown in FIG. 1 or FIG. 2, the individual printed circuit boards are laminated together to form a multilayer printed circuit board (mutlilayer printed circuit board).

The insulating layer 100 is formed of an insulating material such as resin and has a plate type. The resin of the insulating layer 100 may be various materials such as thermosetting resin and thermoplastic resin, and specifically may be epoxy resin or polyimide. Examples of the epoxy resin include naphthalene epoxy resin, bisphenol A type epoxy resin, bisphenol F type epoxy resin, novolak epoxy resin resin (novolac epoxy resin), cresol novolak epoxy resin (cresol novolak epoxy resin), rubber modified epoxy resin (rubber modified epoxy resin), cycloaliphatic epoxy resin (cycloaliphatic epoxy resin), silicon epoxy resin Resin (silicon-based epoxy resin), nitrogen-based epoxy resin (nitrogen-based epoxy resin), phosphorus-based epoxy resin (phosphorus-based epoxy resin) and the like. However, it is not limited to this.

The insulating layer 100 may include a reinforcing material, and the reinforcing material may be an inorganic filler such as glass cloth and silicon dioxide. The insulating layer 100 may be a prepreg (PPG) containing glass fibers or a build-up film containing inorganic fillers. As such a build-up film, Ajinomoto Build-up Film (ABF) or the like can be used.

The insulating layer 100 may be formed of a material having a low dielectric constant Dk and a low dielectric tangent (Df), such as liquid crystal polymer (LCP), polytetrafluoroethylene (PTFE), Polyphenylene ether (PPE), cycloolefin polymer (COP), perfluoroalkoxy (perfluoroalkoxy, PFA) etc.

The insulating layer 100 can also be formed of a photosensitive material such as a photoimageable dielectric (PID) or the like.

The metal pads 110 are embedded in the bottom surface of the insulating layer 100 and are connected to the circuit 130 to be described later. Here, “embedded in the bottom surface” means that the bottom surface of the metal pad 110 is inserted into the insulating layer 100 to be exposed to the bottom surface of the insulating layer 100 . That is, the metal pads 110 are inserted into the insulating layer 100, but the bottom surfaces of the metal pads 110 are exposed.

The metal pads 110 may be formed of metals such as copper (Cu), palladium (Pd), aluminum (Al), nickel (Ni), titanium (Ti), gold (Au), platinum or alloys thereof.

The bottom surface of the metal pad 110 is recessed beyond the bottom surface of the insulating layer 100 . That is, the bottom surface of the metal pad 110 is more inside the insulating layer 100 than the bottom surface of the insulating layer 100 . A step-height is formed between the bottom surface of the metal pad 110 and the bottom surface of the insulating layer 100 . A predetermined space surrounded by the bottom surface of the metal pad 110 and the insulating layer 100 is provided. Such spaces may be referred to as recessed spaces or recesses.

The bottom surface of the metal pad 110 may be in a low-roughness or no-roughness state in which the roughness Ra is almost zero. For example, the roughness Ra of the bottom surface of the metal pad 110 may be less than 0.1.

The circuit 130 is physically and electrically connected to the metal pads 110 and is patterned according to design to transmit electrical signals. The circuit 130 becomes a line for transmitting electrical signals, and the metal pads 110 become the terminals of the line. metal pad The width (area) of the 110 may be formed to be larger than the width (area) of the circuit 130 .

The circuit 130 is also embedded in the bottom surface of the insulating layer 100 and the bottom surface of the circuit 130 is recessed beyond the bottom surface of the insulating layer 100 so that a recessed space or recess 131 is formed in the bottom surface of the circuit 130 .

The circuit 130 may also be formed of metals such as copper (Cu), palladium (Pd), aluminum (Al), nickel (Ni), titanium (Ti), gold (Au), platinum (Pt), or alloys thereof.

The metal bumps 120 penetrate the insulating layer 100 and are formed on upper portions of the metal pads 110 . The metal bumps 120 may be formed by filling the openings formed in the insulating layer 100 with a metal material to be located over the metal pads 110 . The metal bumps 120 may be formed in a columnar shape such as a column or a polygonal column. The bottom surface of the metal bump 120 may contact the upper surface of the metal pad 110 , and the upper end of the metal bump 120 may protrude beyond the upper surface of the insulating layer 100 .

The metal bumps 120 may be formed in two layers. That is, the metal bumps 120 may be formed by the metal vias 121 and the low melting point metal layer 122 . The melting point of the metal through hole 121 is higher than the melting point of the low melting point metal layer 122 .

The metal via 121 is made of a metal having a relatively high melting point (compared to the low melting point metal layer 122 ), and is formed of a metal such as copper (Cu). The metal vias 121 may occupy most of the metal bumps 120 . The metal through hole 121 may be formed by plating or the like.

The low melting point metal layer 122 is formed on the upper portion of the metal through hole 121 and is made of a metal having a relatively low melting point such as tin (Sn). The low melting point metal layer 122 may be formed by plating or the like.

The metal vias 121 may occupy most of the metal bumps 120 , and the low melting point metal layer 122 may be formed on the upper portion of the metal vias 121 in a relatively small volume. In this case, the thickness of the low melting point metal layer 122 may be smaller than the thickness of the metal through hole 121 .

The low melting point metal layer 122 may protrude beyond the upper surface of the insulating layer 100 . The upper surface of the metal via 121 may be positionally coincident with the upper surface of the insulating layer 100 , or may be located below the upper surface of the insulating layer 100 . However, it is not limited to this.

The upper surface of the metal bump 120 (especially the upper surface of the low melting point metal layer 122 ) may be in a low-roughness or no-roughness state in which the roughness Ra is almost zero. For example, the roughness Ra of the upper surface of the low melting point metal layer 122 may be less than 0.1.

As shown in FIG. 9 , in a single printed circuit board before lamination, the cross-sectional area of the low melting point metal layer 122 and the cross-sectional area of the metal via 121 may be substantially the same.

1, a printed circuit board according to an embodiment of the present invention includes a plurality of insulating layers 100, 200, 300, . . . stacked on top of each other. The insulating layers 100 and 200 adjacent to each other among the plurality of insulating layers will now be described. The features described below may apply to all insulating layers or to a portion of the insulating layers in a printed circuit board composed of multiple insulating layers.

The printed circuit board according to the embodiment of the present invention includes a first insulating layer 100 , a first metal pad 110 , a metal bump 120 , a second insulating layer 200 and a second metal pad 210 .

The first insulating layer 100 and the second insulating layer 200 are insulated by, for example, resin The material is formed and is in the form of a plate. The resin of the first insulating layer 100 and the second insulating layer 200 may be various materials such as thermosetting resin and thermoplastic resin, and specifically may be epoxy resin or polyimide. Examples of the epoxy resin include naphthalene epoxy resin, bisphenol A type epoxy resin, bisphenol F type epoxy resin, novolak epoxy resin, cresol novolac epoxy resin, rubber modified epoxy resin, alicyclic epoxy resin Group epoxy resin, silicon epoxy resin, nitrogen epoxy resin, phosphorus epoxy resin, etc. However, it is not limited to this.

The first insulating layer 100 and the second insulating layer 200 may include reinforcing materials, and the reinforcing materials may be inorganic fillers such as glass cloth and silicon dioxide.

The first insulating layer 100 and the second insulating layer 200 may be formed of materials with low dielectric constant Dk and low dielectric tangent Df, such as liquid crystal polymer (LCP), polytetrafluoroethylene (PTFE), polyphenylene Ether (PPE), Cyclic Olefin Polymer (COP), Perfluoroalkoxy (PFA), etc.

The first insulating layer 100 and the second insulating layer 200 may also be formed of a photosensitive material such as a photosensitive imaging dielectric (PID).

The first insulating layer 100 and the second insulating layer 200 may be formed of the same material or different materials.

The first metal pad 110 is embedded in the bottom surface of the first insulating layer 100 , and the second metal pad 210 is embedded in the bottom surface of the second insulating layer 200 .

The bottom surface of the first metal pad 110 is recessed more than the bottom surface of the first insulating layer 100 is recessed. That is, the bottom surface of the first metal pad 110 is more inside the first insulating layer 100 than the bottom surface of the first insulating layer 100 . A mesa is formed between the bottom surface of the first metal pad 110 and the bottom surface of the first insulating layer 100 step height. A recessed space or recess 111 surrounded by the bottom surface of the metal pad 110 and the insulating layer 100 is provided.

The bottom surface of the second metal pad 210 is recessed beyond the bottom surface of the second insulating layer 200 . That is, the bottom surface of the second metal pad 210 is more inside the second insulating layer 200 than the bottom surface of the second insulating layer 200 . A step height is formed between the bottom surface of the second metal pad 210 and the bottom surface of the second insulating layer 200 . A recessed space or recessed portion 211 surrounded by the bottom surface of the second metal pad 210 and the second insulating layer 200 is provided.

The first metal pad 110 and the second metal pad 210 can be made of, for example, copper (Cu), palladium (Pd), aluminum (Al), nickel (Ni), titanium (Ti), gold (Au), platinum (Pt) or Its alloys and other metals are formed.

The bottom surface of the first metal pad 110 and the bottom surface of the second metal pad 210 may be in a low-roughness or no-roughness state in which the roughness Ra is almost zero. For example, the roughness Ra of the bottom surface of the first metal pad 110 and the bottom surface of the second metal pad 210 may be less than 0.1.

The metal bumps 120 penetrate the first insulating layer 100 and are formed on the first metal pads 110 . The metal bumps 120 may be formed by filling the openings formed in the first insulating layer 100 with a metal material to be located over the first metal pads 110 . The metal bumps 120 may be formed in a columnar shape such as a column or a polygonal column.

The metal bumps 120 may be formed in two layers. That is, the metal bumps 120 may be formed by the metal vias 121 and the low melting point metal layer 122 . The melting point of the metal through hole 121 is higher than the melting point of the low melting point metal layer 122 .

The metal via 121 is made of a metal having a relatively high melting point (compared to the low melting point metal layer 122 ), such as copper (Cu). The metal vias 121 may occupy most of the metal bumps 120 . The metal through hole 121 may be formed by plating or the like.

The low melting point metal layer 122 is formed on the upper portion of the metal through hole 121 and is made of a metal having a relatively low melting point such as tin (Sn). The low melting point metal layer 122 may be formed by plating or the like.

The metal vias 121 may occupy most of the metal bumps 120 , and the low melting point metal layer 122 may be formed on the upper portion of the metal vias 121 in a relatively small volume. In this case, the thickness of the low melting point metal layer 122 may be smaller than the thickness of the metal through hole 121 .

The upper surface of the metal bump 120 contacts the bottom surface of the second metal pad 210 . Since the bottom surface of the second metal pad 210 is recessed beyond the bottom surface of the second insulating layer 200 , the upper surface of the metal bump 120 is located above the bottom surface of the second insulating layer 200 . In this case, the upper surface of the metal bump 120 contacts the bottom surface of the second metal pad 210 , and specifically, the upper surface of the low melting point metal layer 122 contacts the bottom surface of the second metal pad 210 .

The contact area between the metal bump 120 and the second metal pad 210 is smaller than the area of the bottom surface of the second metal pad 210 . Specifically, the contact area between the low melting point metal layer 122 and the second metal pad 210 is smaller than the area of the bottom surface of the second metal pad 210 . In this case, the region of the bottom surface of the second metal pad 210 that does not contact the low melting point metal layer 122 contacts the first insulating layer 100 . This may be the flow of the lower first insulating layer 100 to the recessed space or recess when the individual substrates are laminated together The result in the trap 211.

The low melting point metal layer 122 may flow in the lateral direction during the lamination, and the area after the lamination is larger than the area before the lamination. As shown in FIG. 9 , even though the cross-sectional area of the low-melting metal layer 122 and the cross-sectional area of the metal through hole 121 in a single printed circuit board before lamination are substantially the same, the cross-sectional area of the low-melting metal layer 122 after lamination is still It may be larger than the cross-sectional area of the metal through hole 121 .

The low melting point metal layer 122 does not cover the entire bottom surface of the second metal pad 210 , but covers only a part of the bottom surface of the second metal pad 210 . The rest of the bottom surface of the second metal pad 210 may be covered by the first insulating layer 100 .

When a plurality of layers are stacked together in a state in which the second metal pad 210 contacts the low melting point metal layer 122 in a high temperature environment, intermetallic compounds (intermetallic compounds) are formed between the second metal pad 210 and the low melting point metal layer 122 . compound, IMC), thus a layer of Cu ₃ Sn or Cu ₆ Sn may be formed between the second metal pad 210 and the low melting point metal layer 122 . Specifically, when the lamination of a plurality of layers is performed under pressure at a temperature higher than the melting point of the low melting point metal layer 122, in a state in which the low melting point metal layer 122 is melted and the metal through hole 121 is not melted, the second An IMC is formed between the metal pads 210 and the low melting point metal layer 122 . When the lamination is performed at a temperature lower than the melting point of the low melting point metal layer 122 by appropriately supplying a high voltage, in a state in which the low melting point metal layer 122 is melted and the metal through hole 121 is not melted, the second metal pad 210 and the An IMC may be formed between the low melting point metal layers 122 . In the latter case, voids may not occur.

In addition, the upper surfaces of the metal bumps 120 (especially the low melting point metal layer 122 ) may be in a low-roughness or no-roughness state in which the roughness Ra is almost zero. For example, the roughness (Ra) of the upper surface of the low melting point metal layer 122 may be less than 0.1. When the roughness of the bottom surface of the second metal pad 210 and the upper surface of the low melting point metal layer 122 is low, a precise IMC is formed between the second metal pad 210 and the low melting point metal layer 122 during the build-up and the first The formation of voids between the two metal pads 210 and the low melting point metal layer 122 can be reduced. As a result, the interlayer adhesion strength and reliability can be improved.

The metal bumps 220 including the metal vias 221 and the low melting point metal layer 222 are also formed in the second insulating layer 200 on the second metal pads 210 and thus can be connected to the third insulating layer formed on the second insulating layer 200 Third metal pad 310 of layer 300 . That is, the close bonding relationship between the metal bumps and the metal pads can be repeatedly formed on the plurality of insulating layers.

A circuit pattern layer P may be formed on the insulating layer on the uppermost layer. A surface treatment layer made of metal such as gold or nickel may be formed on a portion of the surface of the circuit pattern layer P. As shown in FIG. Although not shown in the drawings, a solder resist may also be applied to the insulating layers at the uppermost and lowermost layers.

2, a printed circuit board according to an embodiment of the present invention includes a plurality of insulating layers 100, 200, 300, . . . stacked on top of each other. The insulating layers 100 and 200 adjacent to each other among the plurality of insulating layers will now be described. The features described below may apply to all of the insulating layers or to a portion of the plurality of insulating layers in a printed circuit board composed of the plurality of insulating layers.

The printed circuit board according to the embodiment of the present invention includes the first insulating layer 100, The first metal pads 110 , the metal bumps 120 , the second insulating layer 200 and the second metal pads 210 .

The first insulating layer 100 and the second insulating layer 200 are formed of insulating material such as resin, and are plate-shaped. The resin of the first insulating layer 100 and the second insulating layer 200 may be various materials such as thermosetting resin and thermoplastic resin, and specifically may be epoxy resin or polyimide. Examples of the epoxy resin include naphthalene epoxy resin, bisphenol A type epoxy resin, bisphenol F type epoxy resin, novolak epoxy resin, cresol novolac epoxy resin, rubber modified epoxy resin, alicyclic epoxy resin Group epoxy resin, silicon epoxy resin, nitrogen epoxy resin, phosphorus epoxy resin, etc. However, it is not limited to this.

The first insulating layer 100 and the second insulating layer 200 may include reinforcing materials, and the reinforcing materials may be inorganic fillers such as glass cloth and silicon dioxide.

The first insulating layer 100 and the second insulating layer 200 may be formed of materials with low dielectric constant Dk and low dielectric tangent Df, such as liquid crystal polymer (LCP), polytetrafluoroethylene (PTFE), polyphenylene Ether (PPE), Cyclic Olefin Polymer (COP), Perfluoroalkoxy (PFA), etc.

The first insulating layer 100 and the second insulating layer 200 may be formed of a photosensitive material such as a photosensitive imaging dielectric (PID).

The first insulating layer 100 and the second insulating layer 200 may be formed of the same material or different materials.

A first metal pad 110 is embedded in the first insulating layer 100 , and a second metal pad 210 is embedded in the second insulating layer 200 .

Since the metal pads 110 are embedded "inside" the insulating layer 100, the metal The top and bottom surfaces of the pads 110 are not exposed through the top and bottom surfaces of the insulating layer 100 . In the previous embodiment (see FIG. 1 ), the bottom surface of the metal pad 110 is exposed through the bottom surface of the insulating layer 100 because the metal pad 110 is embedded in the bottom surface of the insulating layer 100 . In this embodiment, the top and bottom surfaces of the metal pads 110 are not exposed because they are located inside the insulating layer 100 .

The first metal pad 110 and the second metal pad 210 can be made of, for example, copper (Cu), palladium (Pd), aluminum (Al), nickel (Ni), titanium (Ti), gold (Au), platinum (Pt) or Its alloys and other metals are formed.

The bottom surface of the first metal pad 110 and the bottom surface of the second metal pad 210 may be in a low-roughness or no-roughness state in which the roughness Ra is almost zero. For example, the roughness of the bottom surface of the first metal pad 110 and the bottom surface of the second metal pad 210 may be less than 0.1.

The metal bumps 120 penetrate the first insulating layer 100 and are formed on the first metal pads 110 . The metal bumps 120 may be formed by filling the openings formed in the first insulating layer 100 with a metal material to be located over the first metal pads 110 . The metal bumps 120 may be formed in a columnar shape such as a column or a polygonal column.

The bottom surface of the metal bump 120 may contact the upper surface of the first metal pad 110 , and the upper surface of the metal bump 120 may protrude beyond the upper surface of the first insulating layer 100 .

The upper surface of the metal bump 120 penetrates the second insulating layer 200 , and the upper surface of the metal bump 120 contacts the bottom surface of the second metal pad 210 .

The metal bumps 120 may be formed in two layers. That is, the metal bumps 120 may be It is formed by the metal through hole 121 and the low melting point metal layer 122 . The melting point of the metal through hole 121 is higher than the melting point of the low melting point metal layer 122 .

The metal via 121 may be made of a metal having a relatively high melting point (compared to the low melting point metal layer 122 ), such as copper (Cu). The metal vias 121 may occupy most of the metal bumps 120 . The metal through hole 121 may be formed by plating or the like.

The low melting point metal layer 122 is formed on the upper portion of the metal through hole 121 and is made of a metal having a relatively low melting point such as tin (Sn). The low melting point metal layer 122 may be formed by plating or the like.

The metal vias 121 may occupy most of the metal bumps 120 , and the low melting point metal layer 122 may be formed on the upper portion of the metal vias 121 in a relatively small volume. In this case, the thickness of the low melting point metal layer 122 may be smaller than the thickness of the metal through hole 121 .

The contact area between the metal bump 120 and the second metal pad 210 is smaller than the area of the bottom surface of the second metal pad 210 . Specifically, the contact area between the low melting point metal layer 122 and the second metal pad 210 is smaller than the area of the bottom surface of the second metal pad 210 . In this case, a region of the bottom surface of the second metal pad 210 that does not contact the low melting point metal layer 122 contacts the second insulating layer 200 . This may be a result of the second insulating layer 200 on the underside flowing into the recessed spaces or recesses when the individual substrates are laminated together.

The low melting point metal layer 122 may flow in the lateral direction during the lamination, and the area after the lamination is larger than the area before the lamination. As shown in FIG. 9, the cross-sectional area of the low melting point metal layer 122 and the metal vias in a single printed circuit board even before lamination The cross-sectional areas of the 121 are substantially the same, and the cross-sectional area of the low-melting metal layer 122 can still be larger than the cross-sectional area of the metal through hole 121 after lamination.

The low melting point metal layer 122 does not cover the entire bottom surface of the second metal pad 210 , but covers only a part of the bottom surface of the second metal pad 210 . The rest of the bottom surface of the second metal pad 210 may be covered by the second insulating layer 200 .

When a plurality of layers are stacked together in a state in which the second metal pad 210 contacts the low melting point metal layer 122 in a high temperature environment, since the intermetallic compound (IMC) is formed between the second metal pad 210 and the low melting point metal layer 122 ), thus a layer of Cu ₃ Sn or Cu ₆ Sn may be formed between the second metal pad 210 and the low melting point metal layer 122 . Specifically, when the lamination of a plurality of layers is performed under pressure at a temperature higher than the melting point of the low melting point metal layer 122, in a state in which the low melting point metal layer 122 is melted and the metal through hole 121 is not melted, the second An IMC is formed between the metal pads 210 and the low melting point metal layer 122 . When the lamination is performed at a temperature lower than the melting point of the low melting point metal layer 122 by appropriately supplying a high voltage, in a state in which the low melting point metal layer 122 is melted and the metal through hole 121 is not melted, the second metal pad 210 and the An IMC may be formed between the low melting point metal layers 122 . In the latter case, voids may not occur.

In addition, the upper surface of the metal bump 120 (especially the upper surface of the low melting point metal layer 122 ) may be in a low-roughness or no-roughness state in which the roughness Ra is almost zero. For example, the roughness (Ra) of the upper surface of the low melting point metal layer 122 may be less than 0.1. When the roughness of the bottom surface of the second metal pad 210 and the upper surface of the low melting point metal layer 122 is low, a precise IMC is formed between the second metal pad 210 and the low melting point metal layer 122 during the build-up and the first Two metal pads 210 and low melting point gold The formation of voids between the metal layers 122 can be reduced. As a result, the interlayer adhesion strength and reliability can be improved.

The metal bumps 220 are also formed in the second insulating layer 200 on the second metal pads 210 and thus can be connected to the third metal pads 310 of the third insulating layer 300 formed on the second insulating layer 200 . That is, the close bonding relationship between the metal bumps and the metal pads can be repeatedly formed on the plurality of insulating layers.

A circuit pattern layer P may be formed on the insulating layer on the uppermost layer. A surface treatment layer made of metal such as gold or nickel may be formed on a portion of the surface of the circuit pattern layer P. As shown in FIG. Although not shown in the drawings, a solder resist may also be applied to the insulating layers at the uppermost and lowermost layers.

A method of manufacturing the above printed circuit board will be explained with reference to accompanying drawings 3 to 10 .

Referring to Figure 3, a carrier C was prepared. The carrier C is composed of a carrier member C1 and a carrier metal foil C2. The carrier metal foil C2 includes a seed metal layer.

Referring to FIG. 4 , the circuit 130 and the metal pads 110 are formed on the carrier C. As shown in FIG. The circuit 130 and the metal pads 110 are formed on the seed metal layer C2 of the carrier C by an electrolytic plating method. The circuit 130 and the metal pads 110 may be formed of the same metal as the seed metal layer C2.

5, an insulating layer 100 is formed, and an opening 100' is formed in the insulating layer 100. When the insulating layer 100 is photosensitive, the opening 100' can be formed by a lithography process, but is not limited thereto.

Referring to FIG. 6, a metal via 121 is formed in the opening 100'. by plating The metal vias 121 are formed by a cladding method.

Referring to FIG. 7 , a low melting point metal layer 122 is formed on the metal vias 121 to provide metal bumps 120 . The low melting point metal layer 122 may be formed by a plating method and protrude beyond the insulating layer 100 .

Referring to FIG. 8 , the insulating layer 100 is separated from the carrier C, and the seed metal layer C2 of the carrier C is left on the insulating layer 100 .

9, the seed metal layer C2 is removed, and the seed metal layer C2 may be removed by etching or the like. Specifically, when the seed metal layer C2, the circuit 130 and the metal pads 110 are formed of the same material, as the seed metal layer C2 is removed by etching, a portion of the bottom surface of the circuit 130 and the metal pads A portion of the bottom surface of the pad 110 may be removed. In this way, recessed spaces or recesses 111 and 131 are provided in the bottom surface of the circuit 130 and the bottom surface of the metal pad 110 . Multiple single-layer printed circuit boards formed by a series of processes can be provided.

Referring to FIG. 10 , a multilayer printed circuit board may be formed by a batch lamination method in which a plurality of single-layer printed circuit boards are laminated and pressed in a high temperature environment. Here, when the insulating layer 100 located under the two adjacent insulating layers 100 and 200 flows into the recessed space or the recessed portion 211 , a multilayer printed circuit board is provided as described with reference to FIG. 1 . On the other hand, when the insulating layer 200 located above the two adjacent insulating layers 100 and 200 flows into the recessed space or the recessed portion 211 , a multilayer printed circuit board is provided as described with reference to FIG. 2 .

As shown in FIG. 10 , a single circuit pattern layer P may be formed on the insulating layer on the uppermost layer and the single circuit pattern layers P can be laminated together. exist In this case, a method of removing unnecessary portions of the metal layer other than the circuit pattern layer P after forming the metal layer including the circuit pattern layer P may be used.

In addition, the high temperature environment provided in the batch build-up may be a temperature higher than the melting point of the low melting point metal layer 122 of the metal bump 120 or a low temperature. Specifically, when a suitable high pressure environment is provided at a temperature lower than the melting point of the low melting point metal layer 122 , the IMC is sufficiently formed between the low melting point metal layer 122 and the metal pad 110 , and voids may not appear.

While this disclosure includes specific examples, it will be apparent to those skilled in the art that various forms can be made in these examples without departing from the spirit and scope of the claims and their equivalents and changes in details. The examples described herein should be regarded as illustrative only and not restrictive. Descriptions of features or aspects in each example should be considered applicable to similar features or aspects in other examples. If the techniques are performed in a different order and/or if the components in the described systems, architectures, devices, or circuits are combined in a different manner and/or substituted or supplemented with other components or their equivalents, the achieve suitable results. Therefore, the scope of the present invention is defined not by the detailed description but by the scope of the patent application and its equivalents, and all changes within the scope of the patent application and its equivalents should be construed as being included in the present invention middle.

100‧‧‧Insulating layer/First insulating layer

110‧‧‧Metal Pad/First Metal Pad

111, 131‧‧‧Depressed space/depressed part

120, 220‧‧‧Metal bump

121, 221‧‧‧Metal through hole

122, 222‧‧‧low melting point metal layer

130, 230‧‧‧ circuit

200‧‧‧Insulating layer/Second insulating layer

210‧‧‧Second metal pad

300‧‧‧Insulating layer/Third insulating layer

310‧‧‧Third metal pad

P‧‧‧circuit layer

Claims (19)

A printed circuit board comprising: an insulating layer including metal pads, wherein the metal pads are embedded in a bottom surface of the insulating layer; and metal vias penetrating the insulating layer and formed in the metal pads A pad, and a low-melting metal layer, are formed on the upper portion of the metal via and have a lower melting point than the metal via, wherein the bottom surface of the metal pad is recessed beyond all of the insulating layer. the bottom surface, wherein the bottom surface of the metal pad is exposed from the bottom surface of the insulating layer, and wherein the bottom surface of the metal pad is further inward of the insulating layer than the bottom surface of the insulating layer direction depression. The printed circuit board of claim 1, wherein the low melting point metal layer protrudes beyond the upper surface of the insulating layer. The printed circuit board of claim 1, wherein a circuit connected to the metal pad is embedded in the bottom surface of the insulating layer, and the bottom surface of the circuit is recessed beyond the insulating layer the bottom surface of the layer. The printed circuit board of claim 1, wherein the insulating layer is photosensitive. The printed circuit board of claim 1, wherein the roughness (Ra) of the bottom surface of the metal pad and the upper surface of the low melting point metal layer The surface roughness (Ra) is less than 0.1. A printed circuit board, comprising: a first insulating layer with a first metal pad embedded in the bottom surface of the first insulating layer; metal bumps penetrating the first insulating layer and formed on the first insulating layer on the upper part of the metal pad; a second insulating layer is formed on the first insulating layer, and a second metal pad is embedded in the bottom surface of the second insulating layer, wherein the second metal pad is The bottom surface of the pad is recessed beyond the bottom surface of the second insulating layer, and wherein the top surface of the metal bump contacts the bottom surface of the second metal pad. The printed circuit board of claim 6, wherein a contact area between the metal bump and the second metal pad is smaller than a bottom area of the second metal pad, and wherein the first Regions of the bottom surfaces of the two metal pads that are not in contact with the metal bumps contact the first insulating layer. The printed circuit board of claim 6, wherein the metal bumps comprise: metal through holes formed on the first metal pads; and a low melting point metal layer formed on the metal through holes , wherein the low melting point metal layer contacts the bottom surface of the second metal pad. The printed circuit board of claim 8, wherein the thickness of the low melting point metal layer is smaller than the thickness of the metal through hole. The printed circuit board of claim 8, wherein a cross-sectional area of the low-melting metal layer is larger than a cross-sectional area of the metal through hole. The printed circuit board of claim 6, wherein the first insulating layer and the second insulating layer are photosensitive. The printed circuit board of claim 6, wherein roughness (Ra) of the bottom surface of the second metal pad and roughness (Ra) of the upper surface of the metal bump less than 0.1. A printed circuit board, comprising: a first insulating layer in which a first metal pad is embedded; and a metal bump that penetrates the first insulating layer and is formed on the first metal pad and a second insulating layer formed on the first insulating layer, and a second metal pad is embedded in the second insulating layer, wherein the metal bump penetrates the second insulating layer an insulating layer, and the upper surface of the metal bump contacts the bottom surface of the second metal pad. The printed circuit board of claim 13, wherein a contact area between the metal bump and the second metal pad is smaller than a bottom area of the second metal pad. The printed circuit board of claim 13, wherein the metal bumps comprise: metal vias formed on the first metal pads; and A low melting point metal layer formed on the metal through hole, wherein the low melting point metal layer contacts the bottom surface of the second metal pad. The printed circuit board of claim 15, wherein the thickness of the low melting point metal layer is smaller than the thickness of the metal through hole. The printed circuit board of claim 15, wherein a cross-sectional area of the low melting point metal layer is larger than a cross-sectional area of the metal through hole. The printed circuit board of claim 13, wherein the first insulating layer and the second insulating layer are photosensitive. The printed circuit board of claim 13, wherein roughness (Ra) of the bottom surface of the second metal pad and roughness (Ra) of the upper surface of the metal bump less than 0.1.

Images