TWI776488B - Counting device - Google Patents

Abstract

A counting device includes a plurality of counting circuit stages and a first logic operation circuit. The counting circuit stages are connected in sequence. A first counting circuit stage performs a counting action according to a first clock signal and generates a first counting result. The second to Nth counting circuit stages perform a counting operation according to a second clock signal, where N is a positive integer larger than 2. The first logic operation circuit provides the first counting result to be the second clock signal according to an indication signal.

Description

counting device

The present invention relates to a counting device, and in particular, to a counting device that can increase the working speed.

In the application of the counting device, an initial value can be set for the counting device, and then during the counting operation, the counting device can operate according to a clock signal and output the counting results of multiple bits.

In the prior art, when the counting device is in operation, a calculation target value can be set as the counting end point. In addition, the logic operation circuit in the counting device will be activated. When the clock signal is oscillating, the logic operation circuit will perform operations on the gradually decreasing count result, and when the counting node reaches the calculation target value, the logic operation circuit can output. A count termination signal. In such an application, when the frequency of the clock signal is too high (the period is too small), and the calculation speed of the logic operation circuit is too late to generate the count termination signal, the counting action of the counting device will generate errors.

The invention provides a counting device, which can effectively increase the working frequency.

The counting device of the present invention includes a plurality of counting circuit stages and a first logic operation circuit. The counting circuit stages are connected in sequence, wherein the counting circuit stage of the first stage performs the counting action according to the first clock signal, and generates the counting result of the first stage. The counting circuit stage of the second stage to the counting circuit stage of the Nth stage performs the counting operation according to the second clock signal, and N is a positive integer greater than 2. The first logic operation circuit is coupled to the counting circuit stages, and provides the first stage counting result as the second clock signal according to the indication signal.

Based on the above, the present invention makes the counter circuit stage of the first stage work according to the relatively high-frequency first clock signal, and reduces the frequency of the first clock signal to generate the second clock signal, and then makes the second clock signal of the subsequent stage work. The counter circuit stage of the second stage to the counter circuit stage of the Nth stage work according to the second clock signal of the low frequency. In this way, the counting device of the embodiment of the present invention can generate the counting result performed by the first clock signal, and avoid errors due to the operation circuit being too late, thereby effectively increasing the speed of the counting device.

100: Counting device

111~11N, 211~217: Counting circuit level

120, 400, 500: logic operation circuit

CK: clock terminal

CK1: The first clock signal

CK2: The second clock signal

CNT<0>~CNT<N-1>: count result

CNTB<1>~CNTB<6>: Reverse count result

D: data terminal

DEL: Delayer

FF1~FF7, FFx, DFF1, DFF51, DFF52: flip-flop

i0~i6: initial value

Ini: Initiator

IV1~IV9, IV41~IV45, IV51: Inverter

ND1~ND4, ND41, ND42, ND51, ND52: reverse and gate

NO1, NO2, NO3, NO51: reverse or gate

OR1, OR41: OR gate

Q: output terminal

R: reset terminal

RST: reset signal

RUN: Indication signal

RUNX: Indication signal receiver

SRUN: synchronization indication signal

STP: count stop signal

T1~T4: Time point

X1~X6: anti-mutual exclusion or gate

FIG. 1 is a schematic diagram of a counting device according to an embodiment of the present invention.

FIG. 2 is a schematic circuit diagram of a plurality of counting circuit stages of a counting device according to an embodiment of the present invention.

FIG. 3 is a schematic diagram of components of a flip-flop in a counting circuit stage according to an embodiment of the present invention.

4 is a schematic diagram of a logic operation circuit of the counting device according to the embodiment of the present invention picture.

FIG. 5 is a schematic circuit diagram of a logic operation circuit for generating a counting termination signal in the counting device according to an embodiment of the present invention.

FIG. 6A and FIG. 6B respectively illustrate waveform diagrams of counting operations performed by the counting device according to the embodiment of the present invention according to different initial values.

Please refer to FIG. 1 , which is a schematic diagram of a counting device according to an embodiment of the present invention. The counting device 100 includes a plurality of counting circuit stages 111 - 11N and a logic operation circuit 120 . The counting circuit stages 111 to 11N are connected in sequence, wherein the counting circuit stage 111 of the first stage receives the first clock signal CK1 and performs a counting operation according to the first clock signal CK1 to generate the first stage counting result CNT<0 >. The logic operation circuit 120 is coupled to the counting circuit stages 111 - 11N. The first-stage counting circuit stage 111 transmits the generated first-stage counting result CNT<0> to the logic operation circuit 120 . The logic operation circuit 120 generates the second clock signal CK2 according to the first-stage counting result CNT<0> and the instruction signal RUN to provide the first-stage counting result CNT<0>.

Among the counting circuit stages 111 to 11N, the counting circuit stage 112 of the second stage to the counting circuit stage 11N of the Nth stage all receive the second clock signal CK2 . The counting circuit stage 112 of the second stage to the counting circuit stage 11N of the Nth stage perform the counting operation according to the second clock signal CK2, and respectively generate the second counting result to the Nth counting result CNT<1>~CNT<N- 1>. The frequency of the second clock signal CK2 is lower than the frequency of the first clock signal CK1.

In this embodiment, the logic operation circuit 120 can decide to make the second clock signal CK2 equal to the first stage count result CNT<0> or the first clock signal CK1 according to the instruction signal RUN first stage count result CNT<0> . Wherein, when the indication signal RUN is at the first logic level, the logic operation circuit 120 can provide the first-stage counting result CNT<0> as the second clock signal CK2. On the other hand, when the indication signal RUN is at the second logic level, the logic operation circuit 120 can provide the first clock signal CK1 as the second clock signal CK2. In addition, the counting circuit stages 111 to 11N receive the instruction signal RUN, and when the instruction signal RUN is at the first logic level, are activated to perform the accelerated counting action. In this embodiment, the first logic level may be logic 1 or logic 0, and the second logic level may be logic 0 or logic 1.

In this embodiment, the counting circuit stages 111 ˜ 11N can be constructed as a synchronous counter. The counting circuit stages 111 ˜ 11N can respectively receive a plurality of initial values at an initial time point. These initial values are used to set a counting starting point of the counting device 100 . The counting circuit stages 111 to 11N perform a down counting operation from the starting point of the counting during the counting operation. The counting operations of the counting circuit stages 111 ˜ 11N may end when the first stage count result to the Nth stage count result CNT<0>˜CNT<N−1> are equal to a preset value.

It is worth noting that, in this embodiment, only the first-stage counting circuit stage 111 corresponding to the least significant bit among the counting circuit stages 111 to 11N performs the counting operation according to the first clock signal CK1 having a relatively high frequency. The counting operations of the remaining second-stage counting circuit stages 112 to N-th counting circuit stages 11N are all performed according to the first clock signal CK2 having a relatively low frequency. Therefore, because the frequency of the clock signal used as the basis for counting is too high, the surrounding operation circuit sound is too late for the calculation. Raw mistakes can be effectively avoided. Therefore, on the premise that the counting device 100 can generate correct counting results CNT<0>~CNT<N-1>, the speed of the counting operation can be effectively increased.

Please refer to FIG. 2 and FIG. 3 , wherein FIG. 2 is a schematic circuit diagram of a plurality of counting circuit stages of the counting device according to the embodiment of the present invention, and FIG. 3 is a schematic diagram showing the elements of the flip-flops in the counting circuit stage according to the embodiment of the present invention. Symbol diagram. In FIG. 2 , the counting device 200 includes counting circuit stages 211 to 217 . The counting circuit stage 211 of the first stage receives the first clock signal CK1, and performs the counting operation according to the first clock signal CK1. In this embodiment, the counter circuit stage 211 of the first stage includes a flip-flop FF1 and an inverter IV1. Referring to FIG. 3 first, the circuit symbols of the flip-flops FF1 to FF7 in the embodiment of FIG. 2 may be the flip-flop FFx shown in FIG. 3 . The flip-flop FFx has a clock terminal CK, a reset terminal R, an initial terminal ini, an indication signal receiving terminal RUNX, a data terminal D and an output terminal Q. The flip-flop FFx can receive the working clock through the clock terminal CK; through the initial terminal ini to receive the initial value for initialization; through the indication signal receiving terminal RUNX to receive the indication signal RUN; through the reset terminal R to receive the reset signal ; And generate the count result through the output terminal Q.

Please refer to FIG. 2 again, in the first stage of the counting circuit stage 211, the initial end of the flip-flop FF1 receives the initial value i0; the clock end of the flip-flop FF1 receives the first clock signal CK1; The indication signal receiving end receives the indication signal RUN; the data end of the flip-flop FF1 is coupled to the output end of the inverter IV1; the output end of the flip-flop FF1 generates the first-stage counting result CNT<0>. In this embodiment, the flip-flop FF1 can be constructed as a frequency divider and used to divide the frequency of the first clock signal CK1 by 2, to generate the first stage count result CNT<0>.

In addition, the counter circuit stage 212 of the second stage includes a flip-flop FF2, an anti-mutex OR gate X1, and inverters IV2, IV3. The anti-mutually exclusive OR gate X1 has a first input terminal for receiving the second-stage counting result CNT<1>, and a second input terminal for receiving a logic operation result generated according to the previous-stage counting result. Wherein, in the counting circuit stage 212 of the second stage, the second input terminal of the anti-mutual exclusive OR gate X1 receives the inversion signal of the first stage counting result CNT<0> generated by the inverter IV2. The output terminal of the anti-mutual exclusion OR gate X1 is coupled to the data terminal of the flip-flop FF2.

In addition, the initial end of the flip-flop FF2 receives the initial value i1; the clock terminal of the flip-flop FF2 receives the second clock signal CK2; the indication signal receiving end of the flip-flop FF2 receives the indication signal RUN; the output of the flip-flop FF2 The second-level count result CNT<1> is generated at the terminal. In addition, the inverter IV3 is coupled to the output end of the flip-flop FF2 for generating the second-stage reverse counting result CNTB<1>.

In this embodiment, the counting circuit stage 213 of the third stage includes a flip-flop FF3, an anti-mutual exclusion OR gate X2, and inverters IV4 and IV5. The anti-mutual exclusive OR gate X2 has a first input terminal for receiving the second-stage counting result CNT<2>, and a second input terminal for receiving a logic operation result generated according to the previous-stage counting result. Among them, in the counting circuit stage 213 of the third stage, the second input terminal of the anti-mutual exclusive OR gate X2 receives the first stage counting result CNT<0> generated by the inverter IV4 and the anti-OR gate NO1 and the second stage The OR operation result of the count result CNT<1>. The output terminal of the anti-mutual exclusion OR gate X2 is coupled to the data terminal of the flip-flop FF3.

In addition, the initial end of the flip-flop FF3 receives the initial value i2; the flip-flop FF3 The clock terminal of the flip-flop FF3 receives the second clock signal CK2; the indicator signal receiving terminal of the flip-flop FF3 receives the indicator signal RUN; the output terminal of the flip-flop FF3 generates the third-level counting result CNT<2>. The inverter IV5 is coupled to the output end of the flip-flop FF3 for generating the second-stage reverse counting result CNTB<2>.

The circuit structure of the counting circuit stage 214 of the fourth stage to the counting circuit stage 217 of the seventh stage is similar to that of the counting circuit stage 213 of the fourth stage, and the relevant details are not repeated here. The counting circuit stage 214 of the fourth stage to the counting circuit stage 217 of the seventh stage respectively include flip-flops FF4 ˜ FF7 , anti-mutual exclusive OR gates X3 ˜ X6 , and inverters IV6 ˜ IV9 . In addition, the anti-mutual exclusive OR gate X3 receives the logic operation of a plurality of previous-stage counting results (the first-stage counting result CNT<0> to the third-stage counting result CNT<2>) through the anti-AND gate ND1 and the anti-OR gate NO1 Result: the anti-mutual exclusive OR gate X4 receives multiple previous-stage counting results (the first-stage counting result CNT<0> to the fourth-stage counting result CNT<3) through the anti-AND gate ND2, the anti-OR gate NO2, and the anti-OR gate NO1 >) logic operation result; anti-mutual exclusive OR gate X5 receives multiple previous stage count results (first stage count result CNT<0> to fifth stage count result) through anti-AND gate ND3, anti-OR gate NO1 and anti-OR gate NO2 The logic operation result of the counting result CNT<4>); the anti-mutual exclusive OR gate X6 receives multiple previous-stage counting results (the first-stage counting result CNT<0> through the anti-AND gate ND4, the anti-OR gates NO1, NO2 and NO3). to the logical operation result of the sixth-level count result CNT<5>).

Incidentally, the inverters IV6 to IV9 generate the fourth-stage reverse count result CNTB<3> to the seventh-stage reverse count result CNTB<6>, respectively. The flip-flops FF4 to FF7 perform initialization actions according to the initial values i3 to i6 respectively.

In this embodiment, the flip-flops FF1 to FF7 may be J-K type flip-flops.

The counting circuit stages 211 ˜ 217 can perform a synchronous counting operation, and obtain the counting starting point according to the initial values i0 ˜ i6 respectively at the initial time point. The flip-flop FF1 starts counting according to the first clock signal CK1, and the flip-flops FF2-FF7 start counting down according to the second clock signal CK2.

Please refer to FIG. 4 below. FIG. 4 is a schematic diagram of a logic operation circuit of the counting device according to an embodiment of the present invention. The logic operation circuit 400 is used for providing the second clock signal CK2 according to the indication signal RUN. The logic operation circuit 400 includes a flip-flop DFF1, inverters IV41-IV45, inversion gates ND41, ND42, OR gate OR41, and a delay device DEL. The flip-flop DFF1 is a D-type flip-flop, receives the instruction signal RUN, synchronizes with the instruction signal RUN according to the first clock signal CK1, and generates the synchronization instruction signal SRUN. In addition, the flip-flop DFF1 can perform a reset operation according to the reset signal RST. The inverters IV41 and IV42 are serially connected between the output end of the flip-flop DFF1 and an input end of the inverter gate ND41 in sequence. The other input terminal of the inversion gate ND41 receives the first stage count result CNT<0>. The inversion gate ND41 performs inversion operation on the synchronization indication signal SRUN and the first-stage counting result CNT<0>, and transmits the result to the AND gate ND42 through the serially connected inverters IV43, IV44 and the delay device DEL. Specifically, when the synchronization indication signal SRUN is at the logic level 1, the first-stage counting result CNT<0> can be transmitted to an input terminal of the AND gate ND42 after being delayed. Conversely, when the synchronization indication signal SRUN is at the logic level 0, the delay device DEL transmits the logic level 1 to the inversion gate ND42.

On the other hand, the OR gate OR41 receives the first clock signal CK1 and the synchronization instruction signal SRUN. When the synchronization indication signal SRUN is logic level 1, The first clock signal CK1 can be masked from being transmitted to the inversion gate ND42. Conversely, if the synchronization indication signal SRUN is at logic level 0, the first clock signal CK1 can be transmitted to the inverting gate ND42.

Continuing the above description, when the synchronization indication signal SRUN is at logic level 1, the inversion gate ND42 can output the inversion signal of the first-stage counting result CNT<0>, and through the inverter IV45, the second The clock signal CK2 is substantially the same as the first stage count result CNT<0>. On the contrary, when the synchronization indication signal SRUN is at logic level 0, the inversion gate ND42 outputs the inversion signal of the first clock signal CK1, and through the inverter IV45, the second clock signal CK2 can be substantially Same as the first clock signal.

Please refer to FIG. 5 below. FIG. 5 is a schematic circuit diagram of a logic operation circuit for generating a counting termination signal in the counting device according to an embodiment of the present invention. In the embodiment of the present invention, the counting device can set the logic operation circuit 500 to generate the counting termination signal STP. The counting termination signal STP is used to indicate that the counting action of the counting device has been completed. The application circuit behind the counting device can perform various required operations according to the counting termination signal.

Corresponding to the counting device 200 of the embodiment of FIG. 2 , in this embodiment, the counting termination point of the counting device 200 is set, for example, at the second level counting result CNT<1> to the seventh level counting result CNT<6>, which are respectively logic levels 1, 0, 0, 0, 0, 0 hours. The logic operation circuit 500 includes an inverter IV51 , inverting gates ND51 and ND52 , an inverting OR gate NO51 , and flip-flops DFF51 and DFF52 . Inverter IV51, inverting gates ND51, ND52, and inverting OR gate NO51 are used to perform logical operations based on the second-stage reverse counting result CNTB<1> to the seventh-stage reverse counting result CNTB<6>, and when the secondary meter When the counting result CNT<1> to the seventh-level counting result CNT<6> are logic levels 1, 0, 0, 0, 0, and 0, respectively, an output signal of logic level 1 is generated by the inverse OR gate NO51. The output signal of the logic level 1 can be synchronized according to the first clock signal CK1 through the flip-flops DFF51 and DFF52 to generate the count termination signal STP. In addition, the flip-flops DFF51 and DFF52 can perform a reset operation according to the reset signal RST.

It is worth mentioning that in this embodiment, the designer can set the required counting termination point, and change the inverter IV51 and the inverter gate ND51 according to the logic operation formula required for the set counting termination point. , ND52 and anti-OR gate NO51. The related logic operation formulas and the corresponding logic gate setting methods are well known to those skilled in the art, and will not be repeated here.

Please refer to FIG. 6A and FIG. 6B . FIG. 6A and FIG. 6B respectively illustrate waveform diagrams of counting operations performed by the counting device according to the embodiment of the present invention according to different initial values. In FIG. 6A , corresponding to the counting device 200 of the embodiment of FIG. 2 , the counting device 200 receives an initial value i6-i0 with a hexadecimal value of 38 as the starting point of counting, and starts the counting action at time point T1. At the time point T1, the hexadecimal value of the seventh stage count result CNT<6> to the second stage count result CNT<1> is 1c, and the seventh stage count result CNTB<6> to the second stage count result CNTB<6> The hexadecimal value of the reverse counting result CNT<1> is 23, and the first-level counting result CNT<0> is the logic level 0 at this time.

After the time point T1, the first-level counting result CNT<0> changes state according to the first clock signal CK1, and the second-level counting result CNT<1> to the seventh-level counting result CNT<6> are based on the first-level counting As a result, CNT<0> changes state. The digital values of the first-level counting result CNT<0> to the seventh-level counting result CNT<6> can follow the first clock signal CK1 decreases sequentially. At the time point T2, the first-stage counting result CNT<0> to the seventh-stage counting result CNT<6> are equal to the set termination time point, therefore, the counting termination signal STP is pulled up to the logic level 1, and the counting device The counting action of 200 can be stopped.

In FIG. 6B , also corresponding to the counting device 200 of the embodiment of FIG. 2 , the counting device 200 receives the initial value i6-i0 with a hexadecimal value of 39 as the starting point of counting, and starts the counting operation at the time point T3. At time point T3, the hexadecimal value of the seventh stage count result CNT<6> to the second stage count result CNT<1> is 1c, and the seventh stage count result CNTB<6> to the second stage count result CNTB<6> The hexadecimal value of the reverse counting result CNT<1> is 23, and the first-level counting result CNT<0> is the logic level 1 at this time.

After the time point T3, the first-level counting result CNT<0> changes state according to the first clock signal CK1, and the second-level counting result CNT<1> to the seventh-level counting result CNT<6> are based on the first-level counting As a result, CNT<0> changes state. The digital values of the first-level counting result CNT<0> to the seventh-level counting result CNT<6> can be sequentially decremented with the first clock signal CK1. At the time point T4, the first-stage counting result CNT<0> to the seventh-stage counting result CNT<6> are equal to the set termination time point. Therefore, the counting termination signal STP is pulled up to the logic level 1, and the counting device The counting action of 200 can be stopped.

It can be seen from the waveforms in FIG. 6A and FIG. 6B that the counting device of the embodiment of the present invention can complete the counting operation under the relatively high-speed first clock signal CK1, and will not generate errors due to the logic operation circuit being too late to perform operations.

It is worth mentioning that in the waveforms of FIG. 6A and FIG. 6B , the counting devices are both Execute the countdown action. However, within the scope of implementation of the present invention, it is not limited that the counting device must perform the down counting action. According to the prompts of various embodiments and implementation manners of the present invention, it is not difficult for those skilled in the art to implement a counting device for performing an incrementing counting action with the same concept.

To sum up, the present invention maintains the normal counting behavior of the counting device by making the counting circuit stage of the first stage work according to the relatively high-frequency first clock signal. The present invention reduces the frequency of the first clock signal to generate the second clock signal, and then makes the counting circuit stage of the second stage of the subsequent stage to the counting circuit stage of the Nth stage according to the second clock signal of low frequency. Work. In this way, the counting device according to the embodiment of the present invention will not generate errors due to the operation circuit being too late to operate, thereby effectively increasing the speed of the counting device.

100: Counting device

111~11N: Counting circuit level

120: Logic Operation Circuit

CK1: The first clock signal

CNT<0>~CNT<N-1>: count result

CK2: The second clock signal

RUN: Indication signal

Claims (10)

A counting device, comprising: a plurality of counting circuit stages, the counting circuit stages are connected in sequence, wherein the counting circuit stage of the first stage performs a counting action according to a first clock signal, and generates a first-stage counting result; The second-stage counting circuit stage to the N-th counting circuit stage perform counting operations according to a second clock signal, where N is a positive integer greater than 2; and a first logic operation circuit, coupled to the counting circuit stages, According to an indication signal, the first-stage counting result is provided as the second clock signal. The counting device of claim 1, wherein the frequency of the second clock signal is lower than the frequency of the first clock signal. The counting device of claim 1, wherein the counting circuit stages form a synchronous counter. The counting device as claimed in claim 1, wherein when the indication signal is at a first logic level, the first logic operation circuit makes the first-stage counting result be the second clock signal, and when the indication signal is When a second logic level is used, the first clock signal is the second clock signal. The counting device of claim 1, wherein the counting circuit stages respectively receive a plurality of initial values at an initial time point, and set a counting starting point of the counting device according to the initial values. The counting device according to claim 1, further comprising: a second logic operation circuit, receiving the first-stage counting result and a first-stage counting circuit stage respectively generated by the second-stage counting circuit stage to the N-th counting circuit stage Two count results To an Nth count result, the second logic operation circuit performs a logic operation according to the first stage count result to the Nth count result to generate a count termination signal. The counting device according to claim 1, wherein the first logic operation circuit comprises: a flip-flop, receiving the indication signal, and synchronizing the indication signal according to the first clock signal to generate a synchronization indication signal; a first An inversion gate, performing an inversion operation on the synchronization indication signal and the first-stage counting result to generate a first signal; a delay device, delaying the first signal to generate a second signal; an OR gate, for the The synchronization indication signal and the first clock signal perform an OR operation to generate a third signal; and a second inversion gate performs an inversion operation on the second signal and the third signal to generate the second clock Signal. The counting device of claim 1, wherein the counting circuit stage of the first stage comprises: an inverter; and a flip-flop having a data terminal coupled to the output terminal of the inverter, the flip-flop The output terminal of the inverter generates the first-stage counting result and is coupled to the input terminal of the inverter, the clock terminal of the flip-flop receives the first clock signal, and the flip-flop is activated according to the indication signal to Counting is performed, and the initial signal terminal of the flip-flop receives an initial value. The counting device of claim 1, wherein each of the counting circuit stage of the second stage to the counting circuit stage of the Nth stage comprises: an anti-mutually exclusive OR gate, having an input terminal for receiving a current-stage counting result, and having another input terminal for receiving a logic operation result generated according to a plurality of previous-stage counting results; and a flip-flop having a data terminal coupled to to the output terminal of the anti-mutual exclusive OR gate, the output terminal of the flip-flop generates the current stage count result and is coupled to the input terminal of the anti-mutual exclusive OR gate, and the clock terminal of the flip-flop receives the second clock a pulse signal, the flip-flop is activated to perform the counting operation according to the indication signal, the initial signal terminal of the flip-flop receives an initial value; and an inverter is coupled to the output terminal of the flip-flop, according to The current stage count result is used to generate an inverse current stage count result. The counting device as claimed in claim 1, wherein the counting circuit stages perform a down counting action according to the indication signal.

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