TWI773616B - Semiconductor memory device - Google Patents

Abstract

A semiconductor memory device includes a transmission circuit and a control circuit. The transmission circuit is configured to obtain write data and transmit that into a memory cell array according to the external clock signal when the chip selection signal is asserted. The control circuit is configured to control the transmission circuit to transmit first write data into the memory cell array when the chip selection signal changes from assertion to negation during an input period of the first write data of the write data, according to the external clock signal.

Description

semiconductor memory device

The present invention relates to a semiconductor memory device, in particular to a semiconductor memory device that operates asynchronously with an external clock signal.

Existing semiconductor memory devices include Synchronous Dynamic Random Access Memory (SDRAM) and Pseudo-Static Random Access Memory (pSRAM). For example, the SDRAM disclosed in US Patent Publication No. 5594704 operates in synchronization with an external clock signal.

In addition, pSRAM operates asynchronously with an external clock signal, and uses a dynamic random access memory (DRAM) as a memory cell array to store data, and has the same function as a static random access memory (SRAM) Compatible interface. pSRAM adopts Double Data Rate (DDR) method as data transmission method, and can use Expanded Serial Peripheral Interface (xSPI), HyperBus ^TM interface, or Xccella ^TM interface as access interface.

FIG. 1(a) and FIG. 1(b) are timing charts of each signal in response to the input of a write command in a conventional semiconductor memory device. Here, a pSRAM using the HyperBus ^TM interface is used as an example. In this example, the pSRAM is configured to perform a write operation when the chip select signal CS# is active (low level); when the chip select signal CS# is inactive (high level), stop the input of the external clock signal CK to the receiver. operation to stop generating the internal clock signal. In this way, the validity of the chip select signal CS# is asynchronous with the external clock signal CK.

In the write command sequence of FIG. 1, a case where the delay count is 3 and the burst length of the write data is 4 is taken as an example. In this example, since the chip select signal CS# becomes inactive (high level), the time tRWR (the time required for the semiconductor memory device to return to the read/write operation) has elapsed, and then three delay counts of the external clock signal CK have elapsed. , input the write data at the rising edge of the sixth clock of the external clock signal CK. Although the delay count is 3 as an example, the value of the delay count depends on the frequency of the external clock signal CK. For example, when the frequency of the external clock signal CK is higher, the delay count is larger.

In the example of FIG. 1, after the chip selection signal CS# is changed from inactive (high level) to active (low level), commands (CMD) are sequentially input according to the first to third clocks of the external clock signal CK, Row Address (RA), and Column Address (CA). Then, according to the sixth clock of the external clock signal CK, the input write data (DE6, DO6) are written into the designated memory unit. Next, according to the seventh clock of the external clock signal CK, the input write data (DE7, DO7) are written into the designated memory cells.

Then, when all the write data in the write command is input, the chip selection signal CS# changes from valid to invalid to end the write operation.

However, as shown in Figure 1(b), if the chip select signal CS# changes from active to inactive during the input period of the write data (DE7, DO7), some circuits in the semiconductor memory device will be terminated immediately, As a result, the input write data (DE7, DO7) cannot be transferred to the memory cell array, and as a result, it may be difficult to write the write data (DE7, DO7) to the designated memory cell.

In view of the above problems, the purpose of the present invention is to solve the problem that the semiconductor memory device is deactivated during data writing, resulting in that data cannot be completely written into the semiconductor memory device.

In order to solve the above problems, the present invention provides a semiconductor memory device that performs a write operation in response to a chip select signal in an active state. The semiconductor memory device includes a memory cell array, a transmission circuit and a control circuit. When the chip selection signal is in an active state, the transmission circuit obtains the written data according to the external clock signal and transmits it to the memory cell array. According to the external clock signal, the control circuit maintains the operation of the transmission circuit when the chip selection signal changes from an active state to an inactive state during the period of inputting the first written data of the written data, so as to transmit the first written data to the memory cell array.

According to the present invention, during the period when the first write data is input according to the external clock signal, even when the chip selection signal is changed from valid to invalid, the first write data can be transmitted to the memory cell array, so that the first write data can be transferred to the memory cell array. Data is written to the memory cells in the memory cell array. Therefore, even when deactivation of the semiconductor memory device is performed during data writing, data can be appropriately written to the semiconductor memory device.

Hereinafter, the semiconductor memory device related to the embodiment of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to these Examples. Furthermore, in this specification, the notations such as "first", "second" and "third" are used to distinguish a certain element from other elements, and are not limited to the number, order, priority, etc. of the elements.

FIG. 2 is a block diagram showing the configuration of the semiconductor memory device according to the first embodiment of the present invention. The semiconductor memory device related to the present embodiment is a semiconductor memory device that asynchronously performs inactivation by the chip select signal CS# with respect to the external clock signal CK: wherein the semiconductor memory device includes an input-output interface (I/O) part 10. A control logic unit 20, and a memory cell array having a plurality of memory cells arranged in a matrix (not shown).

The I/O section 10 is configured to perform reception and transmission of signals (eg, chip select signal CS#, data signal DQ, external clock signal CK, etc.) with an external device (eg, memory controller). In addition, the control logic unit 20 is configured to control operations such as reading or writing of data in the memory unit based on an instruction received from an external device. Further, the I/O section 10, the control logic section 20, and the memory cell array may be configured by dedicated hardware devices or logic circuits.

The semiconductor memory device related to this embodiment may be any semiconductor memory device (eg, DRAM, pSRAM, SRAM, etc.) that is deactivated by the chip select signal CS# asynchronously to the external clock signal CK. In this embodiment, the semiconductor memory device is described by taking the HyperBus ^TM interface pSRAM as an example. In addition, in this embodiment, as in the example of FIG. 1, the delay count in the write command sequence is 3 and the burst length of the write data is 4. In this embodiment, the same signals as those shown in FIG. 1 are appropriately used and described.

The I/O section 10 includes a receiver 11 connected to a data terminal (DQ terminal), a data clock (DCK) buffer 12, a delay flip-flop (DFF) 13, and a receiver connected to a chip select terminal (CS# terminal) 14. A wafer select (CS) buffer 15, a receiver 16 connected to an external clock terminal (CK terminal), and a clock (CK) buffer 17. To simplify the description, other known configurations in the I/O section 10 (eg, circuits for sending or receiving other signals (data strobe signals, reset signals, etc.)) are not shown here.

The CS buffer 15 is configured to output the signal CSADQX, and the signal CSADQX is configured to activate the receiver 11 in an active state. The receiver 11 is configured to receive the data signal DQ from the external device through the DQ terminal when receiving the signal CSADQX in the active state from the CS buffer 15 . Here, the data signal DQ is input according to the external clock signal CK, and includes commands, addresses (column address, column address, etc.) and write commands of a specific length (in this embodiment, 8 bits). Enter data. In addition, the receiver 11 outputs the input data signal DQ to the DFF 13 as a signal ADQINX.

The DCK buffer 12 is configured to be activated according to the active state of the signal ENCADRV and the signal ENDQDRV, which are provided by the command decoder 21 (described later).

In addition, during the period when the signal ENCADRV is in the active state, in response to each rising edge of the clock of the internal clock signal CLK1 provided by the CK buffer 17, in the rising edge of the external clock signal CK corresponding to the above clock, the DCK buffer 12 Generates and outputs to DFF 13 a signal ACLKE for fetching the input command, address, and writing data (including signal ADQINX). In this case, the signal ACLKE may also be a signal having the same phase as the clock of the internal clock signal CLK1.

Furthermore, when the signal ENCADRV is valid, in response to each falling edge of the clock of the internal clock signal CLK1 input to the CK buffer 17, in the falling edge of the external clock signal CK corresponding to the above clock, the DCK buffer 12 generates and outputs to DFF 13 the signal ACLKO for fetching the input command, address, and writing data (including signal ADQINX). In this case, the signal ACLKO may also be a signal having an opposite phase to the clock of the internal clock signal CLK1.

Furthermore, when the signal ENDQDRV is valid, in response to each falling edge of the clock of the internal clock signal CLK1 input to the CK buffer 17, the DCK buffer 12 generates a signal for The input write data (including the signal ADQINX) is transmitted to the data clock signal DCLK of the memory cell array and output to the DFF 13 . In this case, the clock width of the data clock signal DCLK may be the same as or different from that of the internal clock signal CLK1.

When the chip selection signal CS# is enabled, the DFF 13 obtains the input write data according to the external clock signal CK, and transmits it to the memory cell array. In addition, the DFF 13 is configured to operate when the signal ENCADRV or the signal ENDQDRV is asserted even when the chip select signal CS# is deasserted (high level). In addition, the DFF 13 is an example of a "transmission circuit" in the present invention.

Specifically, when the signal ENCADRV is enabled, the DFF 13 obtains the signal ADQINX output from the receiver 11 every time the signal ACLKE and the signal ACLKO are received from the DCK buffer 12 . Then, the DFF 13 outputs the signal ADD representing the instruction and the address included in the signal ADQINX to the instruction decoder 21 and the memory array control circuit 22 (described later). In addition, when the signal ENDQDRV is enabled, whenever the signal ACLKE and the signal ACLKO are received from the DCK buffer 12 , the DFF 13 obtains the signal ADQINX output from the receiver 11 and the DFF 13 inputs the data clock from the DCK buffer 12 at the same time. When the signal DCLK is used, the write data including the acquired signal ADQINX is converted and stored in parallel. Then, the DFF 13 outputs (transmits) the signal DQ representing the written data including the signal ADQINX to the memory cell array according to the data clock signal DCLK.

The receiver 14 outputs the chip select signal CS# input from the external device via the CS# terminal to the CS buffer 15 as the internal chip select signal CSINX.

The CS buffer 15 operates when the internal chip select signal CSINX is asserted (low level), or when the first control signal CSACTB provided by the CK buffer 17 is asserted (high level). Specifically, the CS buffer 15 logically inverts the internal chip select signal CSINX from the receiver 14 and outputs the inverted chip select signal CSACT to the CK buffer 17 . In addition, the CS buffer 15 outputs the signal CSADQX in the active (high level) state to the receiver 11 , and outputs the signal CSCLKX in the active (high level) state for activating the receiver 16 to the receiver 16 .

When the valid signal CSCLKX is input from the CS buffer 15, the receiver 16 outputs the external clock signal CK input from the external device via the CK terminal to the CK buffer 17 as the signal CLKX. In addition, regardless of whether the chip selection signal CS# is enabled or not, the external clock signal CK can be input at a fixed frequency.

When a valid (high level) inverted chip select signal CSACT is input from the CS buffer 15 , the CK buffer 17 makes the first control signal CSACTB valid (high level) and outputs it to the CS buffer 15 and the command decoder 21 . In addition, the CK buffer 17 takes the signal CLKX input from the receiver 16 as the internal clock signal CLK1 and outputs it to the DCK buffer 12 and the command decoder 21 . The frequency of the internal clock signal CLK1 may be the same as or different from the frequency of the external clock signal CK. In addition, the frequency of the internal clock signal CLK1 can vary over time, for example, to temporarily speed up data read or write operations.

In addition, according to the external clock signal CK, during the input period of the first write data (here, the write data (DE7, DO7)), when the chip select signal CS# changes from valid (low level) to invalid (high level), The CK buffer 17 operates the DFF 13 (transfer circuit) to transfer the write data (DE7, DO7) to the memory cell array. Here, the CK buffer 17 is an example of a "control circuit" in the present invention.

In addition, the above-mentioned first write data may be the last write data in the write command (in this embodiment, write data (DE7, DO7)). Therefore, according to the external clock signal CK, during the input period of the write data (DE7, DO7), even if the chip select signal CS# changes from valid (low level) to invalid (high level), the write data (DE7 , DO7) are transmitted to the memory cell array, so the write data (DE7, DO7) can be written to the memory cells in the memory cell array. Thus, all the write data input in the write command can be appropriately written to the semiconductor memory device.

In addition, even after the chip selection signal CS# becomes inactive (high level), the CK buffer 17 can maintain the active (high level) state by maintaining the first control signal CSACTB for operating the DFF 13 (transmission circuit) To make the DFF 13 operate, the first control signal CSACTB (control signal) is generated based on the chip selection signal CS#. Thus, even when the chip selection signal CS# is changed from active to inactive, since the first control signal CSACTB is made active (high level), the DFF 13 can be operated based on the active first control signal CSACTB.

In addition, the internal clock signal CLK1 is generated based on the external clock signal CK, and the CK buffer 17 can maintain the first control signal CSACTB ( The control signal) is in an active (high level) state; the data clock signal DCLK is a signal for transmitting the first write data (here, write data (DE7, DO7)) to the memory cell array. Thus, based on the internal clock signal CLK1, the DFF 13 can be operated when the data clock signal DCLK for transferring the write data (DE7, DO7) to the memory cell array is generated. According to the generated internal clock signal CLK1, the write data (DE7, DO7) can be transmitted to the memory cell array.

In addition, the CK buffer 17 ends the operation of the DFF 13 (transfer circuit) during the period after the chip select signal CS# is changed from active (low level) to inactive (high level) until the next time it is active. Thus, the DFF 13 can be reset before the chip select signal CS# is next active (ie, the next read or write operation starts).

Next, the configuration of the control logic section 20 will be described. The control logic unit 20 includes an instruction decoder 21 and a memory array control circuit 22 . In addition, to simplify the description, other known configurations in the control logic 20 (eg, circuits that control the refresh operation of the memory cells) are not shown here.

When the valid (high level) first control signal CSACTB is input from the CK buffer 17, the rise of a specific clock (in the example of FIG. 4, the first clock) of the internal clock signal CLK1 input from the CK buffer 17 The instruction decoder 21 outputs a valid (high level) signal ENCADRV to the DCK buffer 12 during the edge to the falling edge of a particular clock (in the example of FIG. 4 , the third clock). In addition, when the valid first control signal CSACTB is input from the CK buffer 17, the rising edge of the specific clock (in the example of FIG. 4, the sixth clock) of the internal clock signal CLK1 to the specific clock (in the fourth In the example in the figure, during the falling edge of the seventh clock), the instruction decoder 21 outputs the valid (high level) signal ENDQDRV to the DCK buffer 12 .

In addition, after recognizing all the input column addresses based on the signal ADD input from the DFF 13, when the clock of the internal clock signal CLK1 (in the example of FIG. 4, the third clock) is input, the command decoder 21 borrows the From the inputted column address, the column control signal RAS for activating the selected word line is activated (high level), and output to the memory array control circuit 22 .

In addition, in the falling edge of a specific clock of the internal clock signal CLK1 (in the example of FIG. 4, the sixth clock and the seventh clock, respectively), the instruction decoder 21 according to the external clock signal CK corresponding to the above clock, The column control signal CASP for selecting the input write data to be written to the bit line of the memory array is active (high level), and is output to the memory array control circuit 22 . Here, the bit line of the memory cell is selected based on the column address including the signal ADD input from the DFF 13 .

In addition, when the invalid (low level) first control signal CSACTB is input from the CK buffer 17, in the falling edge of the clock (in the example of FIG. 4, the seventh clock) of the column control signal CASP, the instruction decoder 21 is used for the precharge signal PRE to be active (high level), and output to the memory array control circuit 22, while the column control signal RAS is inactive (low level). The above-mentioned column control signal CASP is a signal for selecting the last write data (in the example of FIG. 4, write data (DE7, DO7)) to be written to the bit line of the memory cell.

Further, when a specific precharge time elapses, the command decoder 21 deactivates the signal PRE (low level), ends the operation, and transitions to the standby state.

Based on the signal ADD input from the DFF 13, the column control signal RAS, the column control signal CASP, and the signal PRE input from the command decoder 21, the memory array control circuit 22 controls commands, addresses, and data to the memory cell array. . Further, since the control details of the instructions, addresses and data for the memory cell array are the same as those of the known technology, the description thereof will be omitted in this embodiment.

Next, the configuration and operation of a part of the CK buffer 17 will be described with reference to FIG. 3 . Referring to (a) of FIG. 3 , a CK buffer 17 according to an embodiment of the present invention includes a P-channel MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor, MOSFET) 100 , an N-channel MOSFET 101 , and four inverters 102 , 103 , 104 , 105 and delay circuit 106 .

The source of the P-channel type MOSFET 100 is connected to the high-voltage power supply, and the drain of the MOSFET 100 is connected to the high-voltage power supply side of the inverter 103 . The internal clock signal CLK1 is input to the gate of the MOSFET 100 .

The drain of the N-channel type MOSFET 101 is connected to the low-voltage power supply side of the inverter 103 . The source of MOSFET 101 is connected to a low voltage power supply. The gate of the MOSFET 101 is connected to the output terminal of the inverter 102 .

The internal clock signal CLK1 is input to the input terminal of the inverter 102 . The inverter 102 logically inverts the input internal clock signal CLK1 and outputs the logically inverted signal to the gate of the MOSFET 101 .

The inverting chip select signal CSACT is input to the input terminal of the inverter 103 . The output terminal of the inverter 103 is connected to the input terminal of the inverter 104 . When the respective MOSFET 100 and MOSFET 101 are in an on state, the inverter 103 is operated. Specifically, the inverter 103 logically inverts the inverted chip select signal CSACT, and outputs the logically inverted signal to the inverter 104 .

The input terminal of the inverter 104 is connected to the output terminal of the inverter 103 . The output terminal of the inverter 104 is connected to the delay circuit 106 . The inverter 104 logically inverts the signal output from the inverter 103 , and outputs the logically inverted signal to the delay circuit 106 .

The input terminal of the inverter 105 is connected to the node n01 between the inverter 104 and the delay circuit 106 . In addition, the output terminal of the inverter 105 is connected to the node between the inverter 103 and the inverter 104 . The inverter 105 logically inverts the signal output from the inverter 104 , and outputs the logically inverted signal to the inverter 104 .

The delay circuit 106 delays the signal output from the inverter 104 by a specific time, and outputs the delayed signal to the CS buffer 15 and the command decoder 21 as the first control signal CSACTB.

Next, the operation of a part of the CK buffer 17 shown in (a) of FIG. 3 will be described with reference to (b) of FIG. 3 . In this embodiment, during the period when the clock (the seventh clock) of the external clock signal CK for inputting the write data (DE7, DO7) as shown in FIG. 4 is valid, the chip select signal CS# is changed from valid ( low level) becomes invalid (high level). First, when the inverted chip select signal CSACT is asserted (high level) and the internal clock signal CLK1 is deactivated (low level), the inverted chip select signal CSACT is input to the delay circuit 106 via the inverters 103 and 104 . Then, the signal input from the delay circuit 106 is delayed, and the effective (high level) first control signal CSACTB is output from the delay circuit 106 .

Next, when the seventh clock of the external clock signal CK is enabled (high level), at time t1, the seventh clock of the internal clock signal CLK1 is enabled (high level). In this case, since the respective MOSFETs 100 and 101 are turned off, the operation of the inverter 103 is stopped, and the potential of the output terminal of the inverter 103 is maintained at a low level. Thus, the first control signal CSACTB output from the delay circuit 106 is maintained in an active (high level) state.

Then, at time t2, when the seventh clock of the external clock signal CK is active, when the chip select signal CS# changes from active (low level) to inactive (high level), the inverting chip select signal CSACT changes from active becomes invalid (low level). Here, since the seventh clock of the internal clock signal CLK1 is kept active (high level), the respective MOSFETs 100 and 101 are kept in the OFF state. Therefore, the first control signal CSACTB that remains active is output from the delay circuit 106 .

In this way, the internal clock signal CLK1 is generated based on the external clock signal CK. During the period when the internal clock signal CLK1 for generating the data clock signal DCLK is valid, the CK buffer 17 maintains the first control signal CSACTB in the valid state; the above-mentioned The data clock signal DCLK is used to transmit write data (DE7, DO7) to the memory cell array.

Further, based on the first control signal CSACTB output from the delay circuit 106, the command decoder 21 outputs a valid signal ENDQDRV. In addition, the DCK buffer 12 generates a data clock signal DCLK for transferring the write data ( DE7 , DO7 ) to the memory cell array, and outputs it to the DFF 13 . In addition, the DFF 13 obtains the signal ADQINX according to the input of the signal ACLKE, the signal ACLKO, and the data clock signal DCLK, and outputs (transmits) the signal DQ representing the written data including the signal ADQINX to the memory cell array.

In this way, even if the chip select signal CS# becomes inactive (high level), the CK buffer 17 can still enable the DFF 13 by maintaining the first control signal CSACTB for operating the DFF 13 in the active (high level) state In operation, the first control signal CSACTB is generated based on the chip selection signal CS#.

In addition, in this way, according to the external clock signal CK, during the input period of the write data (DE7, DO7), when the chip select signal CS# changes from valid (low level) to invalid (high level), the CK buffer 17 operates DFF 13 to transfer the write data (DE7, DO7) to the memory cell array.

Next, at time t3, when the seventh clock of the internal clock signal CLK1 is changed from active (high level) to inactive (low level), the respective MOSFETs 100 and 101 become on-state. In this case, the inverter 103 logically inverts the invalid (low level) inverting chip select signal CSACT, and outputs the logically inverted signal. Then, the signal output from the inverter 103 is input to the delay circuit 106 via the inverter 104 . Then, the signal input from the delay circuit 106 is delayed, and at time t4, the first control signal CSACTB inactive (low level) is output from the delay circuit 106 . At this time, based on the first control signal CSACTB output from the delay circuit 106, the command decoder 21 outputs an invalid (low level) signal ENDQDRV. Thereby, the operation of the DCK buffer 12 is terminated, and further, the operation of the DFF 13 is terminated.

In one embodiment, the delay time in the delay circuit 106 can be arbitrarily set, eg, can be set to be less than the inactive duration of the chip select signal CS# between read or write operations in the semiconductor memory device (eg, in HyperBus tCSHI in the ^TM interface specification). In this case, the CK buffer 17 may end the operation of the DFF 13 after the chip selection signal CS# is changed from valid to invalid and until the next valid time.

FIG. 4 is a timing chart of signal changes in the semiconductor memory device when a write command is input. First, when the chip select signal CS# changes from inactive (high level) to active (low level), the CS buffer 15 starts to operate by making the internal chip select signal CSINX active (low level). At this time, the CK buffer 17 starts to operate (ie, enabled or activated) by asserting the inverting chip select signal CSACT (high level). In addition, when the signal CSADQX and the signal CSCLKX are asserted (high level), the receiver 11 and the receiver 16 start to operate. In addition, when the first control signal CSACTB is active (high level), the command decoder 21 starts to operate. According to the above-mentioned operations, the DCK buffer 12, the DFF 13 and the memory array control circuit 22 start to operate.

Next, a command (CMD), a column address (RA), and a column address (CA) are input between the rising edge of the first clock of the external clock signal CK and the falling edge of the third clock. Then, in the falling edge of the second clock of the external clock signal CK, when all the column addresses are input, in response to the rising edge of the third clock of the internal clock signal CLK1 generated according to the external clock signal CK, the column control The signal RAS is valid, and the row control signal RAS is a signal for activating the word line selected by the input row address. Thus, the selected word line is activated by the column address.

Next, in the rising edge and the falling edge of the sixth clock of the external clock signal CK, write data (DE6, DO6) are input. Then, in response to the falling edge of the sixth clock of the internal clock signal CLK1, the clock (sixth clock) of the data clock signal DCLK, which is used to input the sixth clock of the external clock signal CK, is valid. The data (DE6, DO6) are transmitted to the signal of the memory cell array. According to the above clock, the written data (DE6, DO6) are transferred to the memory cell array.

Then, after the sixth clock of the internal clock signal CLK1 is disabled (low level), the clock (sixth clock) of the column control signal CASP is enabled (high level), and the column control signal CASP is used for selecting write data ( DE6, DO6) write the signal to the bit line of the memory cell and activate the bit line selected by the field address. Thus, the input write data (DE6, DO6) are written into the memory cells by the sixth clock of the external clock signal CK.

Next, in the rising edge and the falling edge of the seventh clock of the external clock signal CK, write data (DE7, DO7) are input. Here, during the valid (high level) period of the seventh clock of the external clock signal CK, when the chip selection signal CS# changes from valid (low level) to inactive (high level), the internal chip selection signal CSINX is deactivated (high level). ), and further, the inverting chip select signal CSACT is disabled (low level).

On the other hand, as described in (b) of FIG. 3, after the chip selection signal CS# is changed from active (low level) to inactive (high level), the first control signal CSACTB can still be maintained at active (high level) state, so that the signal CSADQX and the signal CSCLKX are also maintained in the active (high level) state. In this case, the receiver 11 and the receiver 16, the DCK buffer 12, the DFF 13, the CS buffer 15, the CK buffer 17, the instruction decoder 21 and the memory array control circuit 22 continue to operate. Therefore, in the falling edge of the seventh clock of the internal clock signal CLK1, the clock (the seventh clock) of the data clock signal DCLK is enabled (high level), and the above-mentioned data clock signal DCLK is used for the second clock of the external clock signal CK. The data (DE7, DO7) input by the seven clocks are transmitted to the signal of the memory cell array. With the above-mentioned valid data clock signal DCLK, the input data (DE7, DO7) are transmitted to the memory cell array.

Then, after the seventh clock of the internal clock signal CLK1 is disabled (low level), the clock (the seventh clock) of the column control signal CASP is enabled (high level), and the column control signal CASP is used to select the write data ( DE7, DO7) Write the signal to the bit line of the memory cell, and activate the bit line selected by the field address. Thus, the write data (DE7, DO7) input by the seventh clock of the external clock signal CK are written into the memory cells.

Further, after a certain time elapses from the invalidation (low level) of the seventh clock of the internal clock signal CLK1, the first control signal CSACTB is invalidated (low level), so that the signals CSADQX and CSCLKX are invalid (low level). Thereby, the operation of the receiver 11, the receiver 16, the DCK buffer 12, the DFF 13, the CS buffer 15, and the CK buffer 17 ends.

In addition, during the falling edge of the seventh clock of the column control signal CASP, the precharge signal PRE is active (high level), while the column control signal RAS is inactive (low level). Then, when a specific precharge period has elapsed, the signal PRE is deactivated (low level). At this point, the command decoder 21 and the memory array control circuit 22 end their operations.

In this way, according to the external clock signal CK, during the input period of the write data (DE7, DO7), when the chip select signal CS# changes from valid (low level) to inactive (high level), the write data (DE7, DO7) can be written ) is transmitted to the memory cell array, and write data (DE7, DO7) can be written to the memory cells in the memory cell array.

As described above, according to the semiconductor memory device related to this embodiment, according to the external clock signal CK, during the input period of the write data (DE7, DO7) (first write data), even if the chip select signal CS# is changed from the active (low-order) When the standard) becomes invalid (high level), the write data (DE7, DO7) can still be transferred to the memory cell array, and the write data (DE7, DO7) can be written to the memory in the memory cell array body unit. Thus, even when deactivation of the semiconductor memory device is performed during a data writing operation, data can be properly written to the semiconductor memory device.

In addition, according to the semiconductor memory device related to the present embodiment, regardless of whether the chip selection signal CS# is active (low level), even when the external clock signal CK is input at a fixed frequency, the data (DE7, DO7) can be written (the first A write data) is transmitted to the memory cell array, and the write data (DE7, DO7) can be written to the memory cells in the memory cell array. In addition, according to the semiconductor memory device related to this embodiment, the supply timing of the external clock signal from the external device to the semiconductor memory device is not limited (eg, the interval between two consecutive clocks of the external clock signal is enlarged or narrowed, etc.). Since an external clock signal can be supplied to the semiconductor memory device at a fixed frequency, a semiconductor memory device with improved operability can be realized.

Hereinafter, Embodiment 2 concerning the present invention will be explained. The semiconductor memory device of this embodiment is different from Embodiment 1 in that the CK buffer 17 (control circuit) operates the DFF 13 (transfer circuit) until the write data (DE7, DO7) (first write data) is written into any memory cell in the memory cell array. Hereinafter, a configuration different from that of Embodiment 1 will be explained.

FIG. 5 is a block diagram showing the configuration of the I/O section and the control logic section 20 of the semiconductor memory device according to the present embodiment. In the example of FIG. 5, the second control signal CSACTC (control signal) is generated based on the chip select signal CS#, and the second control signal CSACTC for operating the DFF 13 is input from the CK buffer 17 to the command decoder twenty one.

When a valid (high level) inverting chip select signal CSACT is input from the CS buffer 15, the CK buffer 17 makes the first control signal CSACTB valid (high level) and outputs it to the CS buffer 15 and the command decoder twenty one. In addition, in this embodiment, when a valid (high level) inverting chip select signal CSACT is input from the CS buffer 15, the CK buffer 17 makes the second control signal CSACTC valid (high level), and outputs it to Instruction decoder 21 .

In addition, in this embodiment, the column control signal CASP for selecting write data (DE7, DO7) (the first write data) to be written to the bit line of the memory cell is active (high level) during the period , the CK buffer 17 operates the DFF 13 (transmission circuit). Therefore, the DFF 13 can be operated while the column control signal CASP for selecting the write data (DE7, DO7) to be written to the bit line of the memory cell is active (high level). (DE7, DO7) can be more reliably transferred to the memory cell array.

In this embodiment, when the valid (high level) first control signal CSACTB or the valid (high level) second control signal CSACTC is input from the CK buffer 17, the internal clock signal CLK1 input from the CK buffer 17 During the period from the rising edge of the specific clock (here the first clock) to the falling edge of the specific clock (here the third clock), the instruction decoder 21 outputs the valid (high level) signal ENCADRV to the DCK buffer 12 . In addition, when the valid (high level) first control signal CSACTB or the valid (high level) second control signal CSACTC is input from the CK buffer 17 , at the specific clock ( The instruction decoder 21 outputs a valid (high level) signal ENDQDRV to the DCK buffer 12 during the period from the rising edge of the sixth clock (here the sixth clock) to the falling edge of the specific clock (here the seventh clock).

Next, referring to FIG. 6(a), the CK buffer 17 includes a delay circuit 200 connected in series to three inverters 201, 202, 203, and a NAND circuit 204 connected in series to three inverters 205, 206 , 207, NOR circuit 208, inverter 209, RS flip-flop composed of two NAND circuits 210, 211, two inverters 212, 213, P-channel MOSFET 214, N-channel MOSFET 215, and Three inverters 216, 217, 218.

The internal clock signal CLK1 is input to the delay circuit 200 . The delay circuit 200 delays the input internal clock signal CLK1 by a specific time, and outputs the delayed signal CLK1D to the NAND circuit 204 and the inverter 201 .

The input terminal of the inverter 201 is connected to the node between the delay circuit 200 and the NAND circuit 204 . In addition, the inverter 203 logically inverts the signals input through the inverters 201 and 202 , and outputs the logically inverted signal to the NAND circuit 204 .

The signal CLK1D output from the delay circuit 200 is input to one input terminal of the NAND circuit 204 . In addition, the signal output from the inverter 203 is input to the other input terminal of the NAND circuit 204 . In addition, the NAND circuit 204 performs NAND calculation based on the input signal, and outputs the signal CLKDRP to the NAND circuit 210 as the calculation result.

The column control signal CASP is input to the input terminal of the inverter 205 . In addition, the inverter 207 logically inverts the input signal via the inverters 205 and 206 , and outputs the logically inverted signal to the NOR circuit 208 .

The column control signal CASP is input to an input terminal of the NOR circuit 208 . In addition, the signal output from the inverter 207 is input to the other input terminal of the NOR circuit 208 . In addition, the NOR circuit 208 performs NOR calculation based on the input signal, and outputs the calculation result to the inverter 209 .

The inverter 209 logically inverts the signal input from the NOR circuit 208, and outputs the logically inverted signal to the NAND circuit 211 as the signal CASPFP.

The signal CLK1DRP output from the NAND circuit 204 is input to one input terminal of the NAND circuit 210 of the RS flip-flop. In addition, the other input terminal of the NAND circuit 210 is connected to the output terminal of the NAND circuit 211 . In addition, the output terminal of the NAND circuit 210 is connected to the input terminal of the inverter 212 and one input terminal of the NAND circuit 211 . In addition, the signal CASPFP output from the inverter 209 is input to the other input terminal of the NAND circuit 211 .

The inverter 212 logically inverts the signal output from the NAND circuit 210 , and outputs the logically inverted signal to the inverter 213 and the MOSFET 215 as a signal MASK2 .

The inverter 213 logically inverts the signal MASK2 output from the inverter 212, and outputs the logically inverted signal to the MOSFET 214 as the signal MASK1.

Further, the MOSFETs 214, 215 and the three inverters 216, 217, 218 are configured such that the signal MASK1 is input to the gate of the MOSFET 214, and the signal MASK2 is input to the gate of the MOSFET 215, except as shown in (a) of FIG. 6 The signal of the node n01 shown is input to the inverter 216, and the second control signal CSACTC is output from the inverter 217, and the MOSFETs 100, 101 and the three inverters shown in (a) of FIG. 3 The configurations of 103, 104, and 105 are the same.

Referring to (b) of FIG. 6, first, when the inverting chip select signal CSACT is made active (high level), the internal clock signal CLK1 is inactive (low level), and the column control signal CASP is inactive (low level), the signal MASK1 goes low and the signal MASK2 goes high. Thus, the inverter 216 logically inverts the signal input from the node n01 , and outputs the logically inverted signal to the inverter 217 . In addition, the inverter 217 logically inverts the input signal, and outputs the logically inverted signal as the valid (high level) second control signal CSACTC.

Next, when the sixth clock of the external clock signal CK is enabled (high level), at time t11, the sixth clock of the internal clock signal CLK1 is enabled (high level). After that, the signal CLK1D is enabled (high level), and the signal CLK1DRP is changed to a low level. At this time, by setting the RS flip-flop, the signal MASK1 becomes a high level, and the signal MASK2 becomes a low level. In this case, since the respective MOSFETs 214 and 215 are turned off, the operation of the inverter 216 is stopped, and the potential of the output terminal of the inverter 216 is maintained at a low level. Thus, the second control signal CSACTC is maintained in an active (high level) state.

Next, after a certain time has elapsed from the falling edge of the sixth clock of the internal clock signal CLK1, the clock of the column control signal CASP (the sixth clock) is made active (high level). Thus, the write data (DE6, DO6) input by the sixth clock of the external clock signal CK are written into the memory cells. Then, when the clock (sixth clock) of the column control signal CASP is deactivated (low level), in time t12, the signal CASPFP becomes the low level. At this time, by resetting the RS flip-flop, the signal MASK1 becomes a low level, and the signal MASK2 becomes a high level. In this case, the respective MOSFETs 214 and 215 are turned on, and the inverter 216 logically inverts the input signal of the node n01 and outputs the logically inverted signal to the inverter 217 . Here, since the logic level of the signal of the node n01 is the same as the logic level of the first control signal CSACTB (the high level at this time), the second control signal CSACTC is maintained in the active (high level) state.

Next, at time t13, based on validating (high level) the seventh clock of the internal clock signal CLK1, the signal CLK1DRP becomes a low level. In this case, as described above, based on the reset RS flip-flop, the respective MOSFETs 214 and 215 become off-states. Thus, the second control signal CSACTC is maintained in an active (high level) state.

Next, when the inverting chip select signal CSACT changes from active (high level) to inactive (low level) during the period when the seventh clock of the internal clock signal CLK1 is active (high level), the clock from the internal clock signal CLK1 is active (high level). The first control signal CSACTB is deactivated (low level) after a certain time has elapsed since the seventh clock is valid (high level).

Then, after a specific time has elapsed from the falling edge of the seventh clock of the internal clock signal CLK1, the clock (the seventh clock) of the column control signal CASP is enabled (high level). Thus, the write data (DE7, DO7) input by the seventh clock of the external clock signal CK are written into the memory cells. Then, when the clock (the seventh clock) of the column control signal CASP is deactivated (low level), the signal CASPFP becomes low level at time t14. At this time, by resetting the RS flip-flop, the signal MASK1 becomes a low level, and the signal MASK2 becomes a high level. In this case, the respective MOSFETs 214 and 215 are turned on, and the inverter 216 logically inverts the input signal of the node n01 and outputs the logically inverted signal to the inverter 217 . Here, since the logic level of the signal of the node n01 is the same as the logic level of the first control signal CSACTB (the low level at this time), the second control signal CSACTC is invalid (the low level).

At this time, since the respective first control signal CSACTB and the second control signal CSACTC are invalid (low level), the command decoder 21 outputs the invalid (low level) signal ENDQDRV. Thereby, the operation of the DCK buffer 12 is ended, and further, the operation of the DFF 13 is ended.

In this way, the CK buffer 17 can operate the DFF 13 during the period when the column control signal CASP for selecting the write data (DE7, DO7) to be written to the bit line of the memory cell is active.

In addition, according to the external clock signal CK, during the writing data (DE7, DO7) input period, even if the chip select signal CS# is changed from active (low level) to inactive (high level), the CK buffer 17 can operate the DFF 13, Until write data (DE7, DO7) is written to any memory cell in the memory cell array.

Further, in the present embodiment, it should be noted that the delay time of the delay circuit 200 must be set so that the RS flip-flops are alternately set and reset (ie, the next time the internal clock signal CLK1 is delayed by the clock of the signal CLK1D ( For example, before the seventh clock) is valid (high level), the clock (for example, the sixth clock) of the column control signal CASP generated based on the clock of the internal clock signal CLK1 (for example, the sixth clock) is invalid (low level)) .

FIG. 7 is a timing chart of temporal changes of signals in the semiconductor memory device in this embodiment when a write command is input. Here, different parts from the timing chart shown in FIG. 4 will be described.

First, when the chip select signal CS# changes from inactive (high level) to active (low level), the internal chip select signal CSINX is enabled (low level), and the inverted chip select signal CSACT is enabled (high level). Thus, the first control signal CSACTB and the second control signal CSACTC are enabled (high level).

Here, as described in (b) of FIG. 6, until the clock (seventh clock) of the column control signal CASP for writing the selection write data (DE7, DO7) to the bit lines of the memory cell is invalid During the period up to (low level), the second control signal CSACTC is maintained in an active (high level) state. In this case, as shown in FIG. 7, because the active (high level) state of the second control signal CSACTC is longer than the active (high level) state of the first control signal CSACTB, based on the active second control signal CSACTC, so that the DCK buffer 12 and the DFF 13 operate for a long time. Therefore, compared with the first embodiment, since the width of the seventh clock of the data clock signal DCLK can be enlarged, the write data (DE7, DO7) can be transmitted to the memory cell array more reliably.

As described above, according to the semiconductor memory device according to the present embodiment, since the DFF 13 (transfer circuit) can be operated until the write data (DE7, DO7) (first write data) is written in the memory cell, it is possible to The write data (DE7, DO7) (the first write data) are more reliably transferred to the memory cell array.

Hereinafter, a modification of the above-described Embodiment 2 will be described. In this modification, the difference from Embodiment 2 is that by writing the write data (DE7, DO7) (first write data) to any memory cell, the CK buffer 17 (control circuit) can The DFF 13 (transfer circuit) is operated until the number of write data written to any memory cell in the write command reaches the number of write data input in the write command. Hereinafter, a configuration different from that of Embodiment 2 will be explained.

FIG. 8 is a configuration diagram of the I/O unit 10 and the control logic unit 20 of the semiconductor memory device according to the modification of the present invention. In the example of FIG. 8 , the CK buffer 17 is configured to output the second control signal CSACTC based on the signal MASK1 input from the command decoder 21 .

Next, with reference to FIG. 9, description will be given regarding the configuration of the instruction decoder 21 and the CK buffer 17 in the present modification. Referring to (a) of FIG. 9 , the instruction decoder 21 includes a first counter 300 , a second counter 301 , a comparator 30 , an inverter 303 , and a NAND circuit 304 .

During the period in which the signal WRSTA indicating the state of the write operation is input in the active (high level) state, in the write data of the clock of the internal clock signal CLK1 input from the CK buffer 17, in each write data corresponding to the above write data At the falling edge of the clock, the first counter 300 counts the number of write data input in the write data. Then, the first counter 300 outputs the signal CNTDIN representing the count value to the comparator 302 .

Here, the signal WRSTA can be generated by the command decoder 21 . According to the external clock signal CK, when the input command (CMD) represents a write command, the command decoder 21 can generate a valid (high level) signal WRSTA.

During the period when the signal WRSTA is input in the active (high level) state, at each falling edge of the clock of the column control signal CASP input from the command decoder 21, the second counter 301 writes to any memory in the write command. The number of written data of the body cell is counted. Then, the second counter 301 outputs a signal CNTWR representing the count value to the comparator 302 .

The comparator 302 compares the signal CNTDIN input from the first counter 300 with the signal CNTWR input from the second counter 301 . Then, when the values indicated by the respective signals CNTDIN and CNTWR are consistent, the comparator 302 outputs the high-level signal WRMTC to the NAND circuit 304 . In addition, when the values indicated by the respective signals CNTDIN and CNTWR are inconsistent, the comparator 302 outputs the low-level signal WRMTC to the NAND circuit 304 .

The inverter 303 logically inverts the internal clock signal CLK1 input from the CK buffer 17 , and outputs the logically inverted signal to the NAND circuit 304 .

The signal WRMTC output from the comparator 302 is input to one input terminal of the NAND circuit 304 . In addition, the signal output from the inverter 303 is input to the other input terminal of the NAND circuit 304 . In addition, the NAND circuit 304 performs NAND calculation based on the input signal, and outputs the calculation result signal MASK1 to the CK buffer 17 .

Next, with reference to FIG. 9(b), the configuration of a part of the CK buffer 17 will be described. The CK buffer 17 includes a P-channel type MOSFET 400 , an N-channel type MOSFET 401 and four inverters 402 , 403 , 404 and 405 .

Further, the MOSFETs 400, 401 and the four inverters 402, 403, 404, 405 are configured such that, in addition to the signal MASK1 input to the gate of the MOSFET 400, the signal MASK2 is input to the gate of the MOSFET 401, and from the inverter 404 The configurations of the MOSFETs 100, 101 and the four inverters 102, 103, 104, and 105 shown in FIG. 3(a) are the same as those of the output control signal CSACTC.

Referring to Fig. 10, the operation of the part of the instruction decoder 21 shown in Fig. 9(a) and the operation of the part of the CK buffer 17 shown in Fig. 9(b) will be described. Here, (a) of FIG. 10 shows that the clock based on the internal clock signal CLK1 (for example, the sixth clock) is enabled before the next clock (for example, the seventh clock) of the internal clock signal CLK1 is enabled (high level). The clock (eg, the sixth clock) generated by the column control signal CASP is invalid (low level). In addition, (b) of FIG. 10 shows that the clock based on the internal clock signal CLK1 (for example, the sixth clock) is enabled before the next clock (for example, the seventh clock) of the internal clock signal CLK1 is enabled (high level). ) generated by the column control signal CASP clock (eg, the sixth clock) is not invalid (low level).

First, referring to (a) of FIG. 10, when the inverting chip select signal CSACT is active (high level), the internal clock signal CLK1 is inactive (low level), and the count values from the first counter 300 and the second counter 301 When consistent (ie, the signal WRMTC is at a high level), the signal MASK1 is at a low level, and the signal MASK2 is at a high level. Accordingly, the inverter 403 logically inverts the input inverting chip select signal CSACT, and outputs the logically inverted signal to the inverter 404 . In addition, the inverter 404 logically inverts the input signal, and outputs the logically inverted signal as the valid (high level) second control signal CSACTC.

Next, when the sixth clock of the external clock signal CK is enabled (high level), at time t21, the sixth clock of the internal clock signal CLK1 is enabled (high level). At this time, the signal MASK1 becomes a high level, and the signal MASK2 becomes a low level. In this case, since the respective MOSFETs 400 and 403 are turned off, the operation of the inverter 403 is stopped, and the potential of the output terminal of the inverter 403 is maintained at a low level. Thus, the second control signal CSACTC is maintained in an active (high level) state.

Next, at time t22, the sixth clock of the internal clock signal CLK1 is deactivated (low level). At this time, as the count value of the first counter 300 increases, the signal WRMTC becomes low level because the values of the respective signals CNTDIN and CNTWR are different. In this case, since the signal MASK2 is at a low level, the second control signal CSACTC is maintained in an active (high level) state.

Then, after a certain time elapses from the falling edge of the sixth clock of the internal clock signal CLK1, the clock of the column control signal CASP (the sixth clock) is enabled (high level). Thus, the write data (DE6, DO6) input by the sixth clock of the external clock signal CK are written into the memory cells. Then, at time t23, when the clock (sixth clock) of the column control signal CASP is deactivated (low level), the count value of the second counter 301 is increased. Therefore, since the values of the respective signals CNTDIN and CNTWR are equal, the signal WRMTC becomes a high level. In addition, when the signal MASK1 goes low and the signal MASK2 goes high, the inverter 403 starts to operate. Furthermore, at this time, the second control signal CSACTC is maintained in an active (high level) state.

In addition, during the period when the seventh clock of the internal clock signal CLK1 is active (high level), when the chip select signal CS# changes from active (low level) to inactive (high level), the inverted chip select signal CSACT changes from active (high level). standard) becomes invalid (low level).

Next, at time t24, the seventh clock of the internal clock signal CLK1 is deactivated (low level). At this time, as the count value of the first counter 300 increases, the signal WRMTC becomes a low level because the values of the respective signals CNTDIN and CNTWR are different. Here, because the signal MASK2 is at a low level, the second control signal CSACTC is maintained in an active (high level) state.

Then, after a specific time has elapsed from the falling edge of the seventh clock of the internal clock signal CLK1, the clock (the seventh clock) of the column control signal CASP is enabled (high level). Thus, the write data (DE7, DO7) input by the seventh clock of the external clock signal CK are written into the memory cells. Then, at time t25, when the clock (seventh clock) of the column control signal CASP is deactivated (low level), the count value of the second counter 301 is increased. Therefore, since the values of the respective signals CNTDIN and CNTWR are equal, the signal WRMTC becomes a high level. In addition, when the signal MASK1 goes low and the signal MASK2 goes high, the inverter 403 starts to operate. The inverter 403 logically inverts the input inverting chip select signal CSACT, and outputs the logically inverted signal to the inverter 404 . Here, because the logic level of the first control signal CSACTB is the same as the logic level of the inverted chip select signal CSACT (the low level at this time), the second control signal CSACTC is invalid (the low level).

At this time, since the respective first control signal CSACTB and the second control signal CSACTC are invalidated (low level), the command decoder 21 outputs the invalid (low level) signal ENDQDRV. Thereby, the operation of the DCK buffer 12 is ended, and further, the operation of the DFF 13 is ended.

In this way, by writing write data (DE7, DO7) to any memory cell, CK buffer 17 can operate DFF 13 until the number of write data written to any memory cell in the write command reaches Up to the number of write data entered in the above write command.

Next, the case shown in FIG. 10(b) will be described. Here, the states of the respective signals at the time t31 and the time t32 are the same as the states of the respective signals at the time t21 and the time t22 in FIG. 10(a).

At time t33, when the clock (the seventh clock) of the column control signal CASP is active (high level), when the seventh clock of the internal clock signal CLK1 is active (high level), because of the respective signals CNTDIN, The value of CNTWR is still different, so the signal WRMTC goes low. In addition, since the signal MASK2 is at a low level, the second control signal CSACTC is maintained in an active (high level) state.

Next, at time t34, when the clock (sixth clock) of the column control signal CASP is deactivated (low level), the count value of the second counter 301 is increased. Therefore, since the values of the respective signals CNTDIN and CNTWR are equal, the signal WRMTC becomes a high level. Here, since the seventh clock of the internal clock signal CLK1 is enabled (high level), the signal MASK2 is still at the low level. Therefore, the second control signal CSACTC is maintained in an active (high level) state.

Then, at time t35, the seventh clock of the internal clock signal CLK1 is deactivated (low level). At this time, as the count value of the first counter 300 increases, the signal WRMTC becomes a low level because the values of the respective signals CNTDIN and CNTWR are different. In this case, since the signal MASK2 is at a low level, the second control signal CSACTC is maintained in an active (high level) state.

The states of the respective signals at time t36 are the same as the states of the respective signals at time t25 in FIG. 10(a).

As described above, according to the present modification, the same effect as the above-described second embodiment can be obtained without adjusting the effective timing between the internal clock signal CLK1 and the column control signal CASP. Further, since the time change of the signal in the semiconductor memory device of this modification when the write command is input is the same as the time change of the signal of the above-mentioned second embodiment, the description thereof will be omitted.

As described above, according to the semiconductor memory device of the present modification, until the number of write data written to the memory cell in the write command reaches the number of write data input in the write command (ie, write data (DE7, DO7) (the first written data) is written to the memory unit), since the operation of DFF13 (transmission circuit) is maintained, the written data (DE7, DO7) can be more reliably transmitted to the memory unit array.

Further, in each of the above-described embodiments and modifications, the semiconductor memory device has been described by taking the case of pSRAM using the HyperBus ^™ interface as an example, but in this case, further effects described below are exhibited.

(a) of FIG. 11 is a diagram illustrating an example of the input timing of the chip select signal CS# based on the existing semiconductor memory device specification. In the HyperBus ^TM interface specification, the dynamic characteristics (AC characteristics) of the chip select signal CS# are defined. . (a) of FIG. 11 shows an example of the minimum value of each parameter when the external clock signal CK is 200Mhz. Here, tCSS is the setting time of the chip select signal CS# until the next rising edge of the external clock signal CK, and tCSH is the holding time of the chip select signal CS# after the falling edge of the external clock signal CK. In addition, tCK is the clock period, and tCKHP is the half period of the clock.

As shown in (a) of FIG. 11, based on individual parameters, when adjusting the input timing of the chip selection signal CS#, the interval between the zeroth clock and the first clock of the external clock signal CK, and the seventh clock Since the interval between eight clocks is different from the interval between other clocks, it is difficult to input the external clock signal CK at a fixed frequency.

Therefore, as shown in (b) of FIG. 11, regardless of whether the chip selection signal CS# is enabled (low level), when the respective parameters are redefined so that the external clock signal CK can be input at a fixed frequency, due to tCSH The range of the timing margin is as narrow as about 0.7 ns, so it is still difficult to input a fixed frequency, for example, a high-frequency external clock signal CK such as 200Mhz. In addition, in the conventional semiconductor memory device, when the clock of the external clock signal CK (here, the seventh clock) is active (high level), when the chip selection signal CS# is inactive (high level), the above-mentioned The write data input by the clock is not transferred to the memory cell array, and as a result, it may be difficult to write the write data to the memory cells in the memory cell array.

On the other hand, as shown in (c) of FIG. 11, according to the semiconductor memory devices of the above-described embodiments and modifications, during the input of write data, even if the chip select signal CS# is changed from active (low level) to inactive (high level), the written data can also be transmitted to the memory cell array. Further, since the written data can be written to the memory cells in the memory cell array, the value of tCSH can be negative. direction increases (for example, -1.5 ns). As a result, the timing margin of tCSH can be expanded to about 1.85 (= 1.5 + 0.35) ns. Therefore, according to the semiconductor memory devices of the above-mentioned embodiments and modifications, while maintaining the compatibility with the HyperBus ^TM interface specification, regardless of whether the chip select signal CS# is enabled or not, it is possible to continue to input high-frequency external signals such as 200 Mhz. clock signal CK. Therefore, the performance of a system combining an external device (eg, a memory controller) and a semiconductor memory device can be improved.

The above-described respective embodiments and modified examples are for the simple understanding of the present invention, and are not described to limit the present invention. Therefore, each feature shown in each of the above-described embodiments and modified examples is intended to include all design changes and equivalents that belong to the technical scope of the present invention.

For example, in each of the above-mentioned embodiments and modifications, the case where the HyperBus ^TM interface is used is described as an example, but the present invention is not limited to this. For example, even in the case of using the Xccella ^™ interface, the same effects as those of the above-described embodiments and modifications can be obtained.

In addition, in each of the above-mentioned embodiments and modifications, the signal valid at the low level can be changed to be valid at the high level. In addition, the signal that is valid at high level can be changed to be valid at low level.

In addition, in each of the above-described embodiments and modifications, the case where the CK buffer 17 is used as the control circuit has been described as an example, but the present invention is not limited to this. For example, other circuits having the configurations shown in Fig. 3(a), Fig. 6(a), and/or Fig. 9(b) may be provided as control circuits.

In addition, in each of the above-described embodiments and modifications, the case where the command decoder 21 has the configuration shown in FIG. 9( a ) has been described as an example, but the present invention is not limited to this. For example, the configuration shown in (a) of FIG. 9 may be provided in the CK buffer 17, or may be provided in another circuit.

In addition, in each of the above-mentioned embodiments and modifications, although the last write data (write data (DE7, DO7)) in the write command is input, the chip selection signal CS# is changed from valid to invalid. An example is shown. However, the present invention is not limited to this. For example, even when the chip selection signal CS# is changed from valid to invalid during the input of other write data (for example, write data (DE6, DO6)), the above-mentioned respective embodiments and modifications can obtain the same effect as the above-mentioned and effects.

In addition, the arrangement shown in Fig. 3(a), Fig. 6(a), Fig. 9(a), and Fig. 9(b) are examples, and may be changed as appropriate, and various other arrangements may be adopted. Configuration.

In addition, the configurations of the I/O unit 10 and the control logic unit 20 in each of the above-described embodiments and modifications are examples, and may be changed as appropriate, and other various configurations may be employed.

10: I/O department 11: Receiver 12: DCK buffer 13: DFF 14: Receiver 15: CS buffer 16: Receiver 17: CK buffer 20: Control Logic Department 21: Instruction Decoder 22: Memory array control circuit 100:P channel MOSFET 101: N-channel MOSFET 102: Inverter 103: Inverter 104: Inverter 105: Inverter 106: Delay circuit 200: Delay circuit 201: Inverter 202: Inverter 203: Inverter 204: NAND circuit 205: Inverter 206: Inverter 207: Inverter 208:NOR circuit 209: Inverter 210: NAND circuit 211: NAND circuit 212: Inverter 213: Inverter 214: P-channel MOSFET 215: N-channel MOSFET 216: Inverter 217: Inverter 218: Inverter 300: First counter 300 301: Second counter 301 302: Comparator 303: Inverter 304: NAND circuit 400:P channel MOSFET 401: N-channel MOSFET 402: Inverter 403: Inverter 404: Inverter 405: Inverter n01: Node between inverter 104 and delay circuit 106 ACLKE: Signal input from DCK buffer 12 ACLKO: Signal input from DCK buffer 12 ADD: Signal input from DFF 13 ADQINX: Signal output from receiver 11 CASP: Column Control Signal CASPFP: Signal output from inverter 209 CK: External clock signal CLK1: Internal clock signal CLK1D: Delay signal CLK1DRP: Signal output from NAND circuit 204 CLKX: CK buffer 17 input signal from receiver 16 CMD: command CS#: Chip Select Signal CSACT: Inverting chip select signal CSACTB: The first control signal CSACTC: The second control signal CSADQX: Signal for activating receiver 11 CSCLKX: Signal used to activate receiver 16 CSINX: Internal Chip Select Signal DCLK: data clock signal DQ: data signal ENCADRV: Signal for activating DCK buffer 12 ENDQDRV: Signal for activating DCK buffer 12 MASK1:MASK2 logic inverted signal MASK2: Signal output from inverter 212 (Fig. 6), signal output from inverter 402 (Fig. 9) RA: column address RAS: row control signal CA: field address DE6,DO6: write data DE7,DO7: write data PRE: Precharge signal WRSTA: Signal indicating write operation status WRMTC: the signal output from the comparator 302 CNTDIN: The first counter 300 represents the signal of the count value CNTWR: The signal of the second counter 301 representing the count value

(a) to (b) of FIG. 1 are timing charts showing temporal changes of signals in a conventional semiconductor memory device when a write command is input. FIG. 2 is a block diagram showing the configuration of the input/output interface (I/O) part and the control logic part of the semiconductor memory device according to the first embodiment of the present invention. (a) of FIG. 3 is a diagram showing an example of the arrangement of a part of the clock (CK) buffer, and (b) of FIG. 3 is a timing chart of a time change of a signal in a part of the CK buffer. FIG. 4 is a timing chart of signal changes in the semiconductor memory device when a write command is input. FIG. 5 is a block diagram showing the configuration of the I/O part and the control logic part of the semiconductor memory device according to the second embodiment of the present invention. (a) of FIG. 6 is a diagram showing an example of the arrangement of a part of the clock (CK) buffer, and (b) of FIG. 6 is a timing chart of a time change of a signal in a part of the CK buffer. FIG. 7 is a timing chart of temporal changes of signals in the semiconductor memory device when a write command is input. FIG. 8 is a block diagram showing the arrangement of the I/O section and the control logic section of the semiconductor memory device according to the modification of the present invention. (a) of FIG. 9 is a diagram showing an example of the arrangement of a part of the command decoder, and (b) of FIG. 9 is a diagram of an example of the arrangement of a part of the CK buffer. (a) to (b) of FIG. 10 are timing charts showing time changes of signals in a part of the command decoder and a part of the CK buffer. (a) of FIG. 11 is a diagram illustrating an example of the input timing of the chip selection signal based on the specifications of the conventional semiconductor memory device, and (b) of FIG. 11 is based on the conventional semiconductor memory device for inputting a fixed frequency Figure 11 (c) is an illustration of the input timing of the chip selection signal in the semiconductor memory device related to the embodiment and modification of the present invention. sample graph.

10: I/O department 11: Receiver 12: DCK buffer 13: DFF 14: Receiver 15: CS buffer 16: Receiver 17: CK buffer 20: Control Logic Department 21: Instruction Decoder 22: Memory array control circuit DQ: data signal CS#: Chip Select Signal CK: External clock signal ENCADRV: Signal for activating DCK buffer 12 ENDQDRV: Signal for activating DCK buffer 12 CLK1: Internal clock signal ADQINX: Signal output from receiver 11 CSADQX: Signal for activating receiver 11 CSINX: Internal Chip Select Signal CSACTB: The first control signal CSCLKX: Signal used to activate receiver 16 CSACT: Inverting chip select signal CLKX: CK buffer 17 input signal from receiver 16 ADD: Signal input from DFF 13 ACLKE: Signal input from DCK buffer 12 ACLKO: Signal input from DCK buffer 12 DCLK: data clock signal RAS: row control signal CASP: Column Control Signal PRE: Precharge signal

Claims (17)

A semiconductor memory device that performs a write operation in response to a chip select signal in an active state, comprising: an array of memory cells, including a plurality of memory cells; a transmission circuit, when the chip selection signal is in the valid state, obtains write data according to an external clock signal, and transmits it to the memory cell array; and The control circuit, according to the external clock signal, maintains the operation of the transmission circuit after the chip selection signal changes from the active state to the inactive state during the first write data input period of the write data, so as to make the first write data input Write data is transferred to the array of memory cells. The semiconductor memory device of claim 1; Wherein, the first written data is the last written data in the write command. The semiconductor memory device of claim 1; Wherein, the control circuit is configured to generate a first control signal according to the reversed chip select signal, and the control circuit is configured to activate the transmission even after the chip select signal becomes the inactive state The first control signal of the circuit is maintained in an active state, so that the transmission circuit maintains operation. The semiconductor memory device of claim 3; Wherein, the control circuit is further configured to generate an internal clock signal according to the external clock signal, and when the internal clock signal for generating the data clock signal is in a valid state, the control circuit maintains the first control signal in the valid state state; the data clock signal is a signal used to transmit the first write data to the memory cell array. The semiconductor memory device of claim 1; Wherein, the control circuit operates the transmission circuit until the first write data is written to any memory cell in the memory cell array. The semiconductor memory device of claim 5; Wherein, the control circuit is configured to receive a column control signal, and when the column control signal is in an active state, the control circuit operates the transmission circuit; the column control signal is used to select the first write data to be written The signal of the bit line of the memory cell. The semiconductor memory device of claim 5 or 6; Wherein, by writing the first write data to any of the memory cells, the control circuit operates the transmission circuit until the number of write data written to any of the memory cells in the write command reaches Up to the number of write data entered in the write command. The semiconductor memory device of claim 1; Wherein, after the chip selection signal changes from the valid state to the invalid state; and during the next time the chip selection signal becomes the valid state, the control circuit ends the operation of the transmission circuit. The semiconductor memory device of claim 1; Wherein, the external clock signal is input at a fixed frequency. As claimed in claim 4, the semiconductor memory device further includes: an instruction decoder, coupled to the control circuit to receive the internal clock signal and the first control signal, and configured to generate a data clock buffer control signal; and a data clock buffer, coupled to the transmission circuit, the data clock buffer is configured to be activated according to the data clock buffer control signal of the active state, during the period when the data clock buffer is activated, in response to the internal clock The signal generates a signal for obtaining the written data and the data clock signal. As claimed in claim 10, the semiconductor memory device further includes: a chip select signal receiver configured to generate an internal chip select signal according to the chip select signal; a chip select buffer, coupled to the chip select signal receiver, and configured to output the data receiver control signal and the external clock signal receiver control signal; a data receiver, coupled to the transmission circuit and the chip select buffer, the data receiver configured to be activated according to the data receiver control signal in a valid state to receive the write data from an external device; and The external clock signal receiver is coupled to the control circuit and the chip selection buffer; and is configured to be activated according to the external clock signal receiver control signal to output the external clock signal to the control circuit. The semiconductor memory device of claim 10; Wherein, when the data clock buffer control signal is in the active state, the transmission circuit obtains the write data from the data receiver whenever the signal for obtaining the write data is received from the data clock buffer , and then output the obtained address signal in the written data to the instruction decoder. The semiconductor memory device of claim 10; Wherein, when the transmission circuit obtains the written data from the data receiver; every time the data clock signal is received from the data clock buffer, the written data is converted and stored in parallel, and then according to the data clock signal The write data is transmitted to the memory cell array. The semiconductor memory device of claim 10; Wherein, the control circuit generates a second control signal in a valid state according to the inverted chip selection signal, and outputs the second control signal to the command decoder, when the command decoder receives the first control signal Either one of the second control signals is in the active state, and the instruction decoder generates the data clock buffer control signal in the active state. The semiconductor memory device of claim 1; Wherein, the control circuit includes a delay circuit, the chip selection signal is provided to the delay circuit according to the internal clock signal, and the delay circuit is configured to delay the received chip selection signal to generate a first control signal, and automatically The delay circuit maintains the first control signal in an active state while the internal clock signal is maintained in an active state from the active state into the inactive state, so that the transmission circuit maintains operation. The semiconductor memory device of claim 15; Wherein, after the chip selection signal and the internal clock signal become the inactive state, during the delay period of the delay circuit, the delay circuit maintains the first control signal in an active state, so that the transmission circuit maintains operation. The semiconductor memory device of claim 10; The instruction decoder is further configured to generate a calculation result signal according to the internal clock signal and the column control signal, and the control circuit is configured to generate a second control signal according to the calculation result signal, wherein the control circuit controls the second control signal. The period during which the signal maintains the valid state is configured to be longer than the period during which the first control signal maintains the valid state.

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