TWI773457B - Method of calculating error compensation for phase adjustment circuit - Google Patents

Abstract

A method of calculating error compensation for a phase adjustment circuit includes: starting initializing a field programmable gate array (FPGA); performing a self-test by the FPGA, if the self-test indicates a normal state, performing a next step, and if the self-test indicates an error state, sending an error message; acquiring information about operating time of the FPGA; calculating a circuit drift coefficient; determining a phase compensation value according to the circuit drift coefficient ; calculating a voltage value required to be output to a comparator in the phase adjustment circuit; outputting the voltage value to a digital to analog converter in the phase adjustment circuit; and finishing performing the compensation of the phase adjustment circuit.

Description

Error Compensation Calculation Method Applied to Phase Adjustment Circuit

The invention relates to the technical field of semiconductor testing, in particular to an error compensation calculation method applied to a phase adjustment circuit.

In the field of automatic chip testing machines, it is often necessary to adjust the output waveform phase of certain signals. For high-speed signals, the precise phase control circuit represents the design level of the testing machine, which directly affects the testing effect of the testing factory on the chip. The industry traditionally uses FPGA to count the high-frequency clock to adjust the signal phase. This method has two disadvantages: one is that the phase adjustment can only be an integer multiple of the high-frequency clock cycle, and it cannot achieve stepless adjustment; The signal frequency is fast, and high-level programmable logic array (FPGA) needs to be selected, which is a challenge to cost and FPGA design. In particular, when the chips, resistors and capacitors used in the actual circuit increase with the use of time, their characteristics will shift with time. Most testing opportunities require testing machine users to calibrate the testing machine every 3 to 6 months. , Usually the DC calibration is easier, just use the corresponding calibration instrument, but the calibration of the phase adjustment circuit will require the use of a high-order oscilloscope, which is difficult to meet the conditions at the user's site. If the calibration of the phase adjustment circuit is not performed for a long time, the phase adjustment result will be shifted over time.

In order to overcome the deficiencies of the prior art, the present invention provides an error compensation calculation method applied to a phase adjustment circuit, which adopts the actual measurement to model the phase offset error and time, thereby predicting that the phase adjustment circuit generates errors with time, and realizes low-cost and convenient Compensate for errors caused by time.

In order to achieve the above purpose, an error compensation calculation method applied to the phase adjustment circuit is designed. The specific process is as follows:

S1: Start to initialize the programmable logic array (FPGA);

S2: Make the FPGA perform self-checking, if the self-checking display is normal, proceed to step S3; if the self-checking display is wrong, report the error;

S3: Read the length of the FPGA usage time;

)，且Ｋ為電路漂移係數； S4: Calculate the circuit drift coefficient, where the circuit drift coefficient satisfies the following formula, K=(1+αt) * (1-βt) * (1- γ

), and K is the circuit drift coefficient;

)，且T為相位補償值； S5: Calculate the phase compensation value according to the circuit drift coefficient, where the phase compensation value satisfies the following formula, T = RC*Ln[U _VG1 /(U _VG1 -U _C )] * K= RC*Ln[U _VG1 /(U _VG1 -U _C )] * (1+αt) * (1-βt) * (1- γ

), and T is the phase compensation value;

S6: Calculate the voltage value that needs to be output to the comparator of the phase adjustment circuit;

S7: a digital-to-analog converter that supplies the output voltage value to the phase adjustment circuit; and

S8: Complete the phase adjustment circuit compensation configuration.

)，FPGA的使用時間對於電阻的影響公式為 R=R0 *（1＋αt），其中R0是初始時的精確阻值，α為電阻的電阻時間係數，通過具體實驗可以測出電路中採用電阻的係數；FPGA的使用時間對於電容的影響公式為C = C0 * (1-βt)，經實驗得出電容量每年的損耗大概在1%~2%，運算增益隨時間的變化多在10mV/年，變化因數考慮為 1- γ

。 The phase compensation coefficient K=(1+αt)*(1-βt)*(1-γ

), the formula for the influence of FPGA usage time on the resistance is R=R0 * (1+αt), where R0 is the precise initial resistance value, α is the resistance time coefficient of the resistance, and the coefficient of the resistance used in the circuit can be measured through specific experiments. ; The influence formula of FPGA usage time on capacitance is C = C0 * (1-βt). It is found by experiments that the annual loss of capacitance is about 1%~2%, and the change of operation gain with time is mostly 10mV/year. The variation factor is considered as 1- γ

.

The FPGA self-check is to generate a finely adjustable voltage through the digital-to-analog converter of the FPGA and the phase adjustment circuit, which is input to the negative terminal of the comparator of the phase adjustment circuit, and inputs a high-speed signal for phase adjustment to the comparator of the phase adjustment circuit. On the positive end, two voltages are input to the two ends of the comparator. By adjusting the voltage on the negative end of the comparator, waveforms of different phases can be obtained at the output end of the comparator.

Compared with the prior art, the present invention provides an error compensation calculation method applied to the phase adjustment circuit, which adopts the actual measurement to model the phase offset error and time, thereby predicting the error of the phase adjustment circuit over time, and realizes the low-cost and convenient implementation for the use of Compensate for errors caused by time.

The present invention will be further described below according to the accompanying drawings.

As shown in FIG. 1, an error compensation calculation method 100 applied to a phase adjustment circuit. A programmable logic array (FPGA) is connected to the phase adjustment circuit, and the phase adjustment circuit includes a digital-to-analog converter and a comparator. The specific process is as follows:

S1: FPGA initialization starts;

S2: FPGA self-checking (ie self-checking), if the self-checking display is normal, go to step S3; if the self-checking display is wrong, the system will report an error;

S3: Read the length of the FPGA usage time;

)，其中K為電路漂移係數，且t為FPGA使用時間長度； S4: Calculate the circuit drift coefficient. For example, it can be calculated using the following formula, K=(1+αt)*(1-βt)*(1-γ

), where K is the circuit drift coefficient, and t is the length of time used by the FPGA;

)，其中T為相位補償值，R為相位調整電路中的一電阻（例如為圖2的電阻R1）之阻值，且C為相位調整電路中的一電容（例如為圖2的電容C1）之容值； S5: Calculate the phase compensation value according to the circuit drift coefficient. For example, it can be calculated using the following formula, T = RC*Ln[U _VG1 /(U _VG1 -U _C )] * K= RC*Ln[U _VG1 /(U _VG1 -U _C )] * (1+αt) * (1 -βt) * (1- γ

), where T is the phase compensation value, R is the resistance of a resistor in the phase adjustment circuit (eg, resistor R1 in Figure 2), and C is a capacitor in the phase adjustment circuit (eg, capacitor C1 in Figure 2) capacity value;

S6: Calculate the voltage value that needs to be output to the comparator of the phase adjustment circuit;

S7: give the output voltage value to the digital-to-analog converter of the phase adjustment circuit;

S8: Compensation configuration of the phase adjustment circuit is completed.

)，FPGA的使用時間對於電阻的影響公式為 R=R0 *（1＋αt），其中R0是初始時的精確阻值，α為電阻的電阻時間係數，通過具體實驗可以測出電路中採用電阻的係數；FPGA的使用時間對於電容的影響公式為 C = C0 * (1-βt)，經實驗得出電容量每年的損耗大概在1%~2%；運算增益隨時間的變化多在10mV/年，變化因數考慮為 1- γ

。 Phase compensation coefficient K=(1+αt) * (1-βt) * (1- γ

), the formula for the influence of FPGA usage time on the resistance is R=R0 * (1+αt), where R0 is the precise initial resistance value, α is the resistance time coefficient of the resistance, and the coefficient of the resistance used in the circuit can be measured through specific experiments. ; The influence formula of FPGA usage time on capacitance is C = C0 * (1-βt), the annual loss of capacitance is about 1%~2% through experiments; the change of operation gain with time is mostly 10mV/year, The variation factor is considered as 1- γ

.

The FPGA self-check generates a finely adjustable voltage for the digital-to-analog converter through the FPGA and the phase adjustment circuit, and inputs this voltage to the negative terminal of the comparator of the phase adjustment circuit. Input the high-speed signal of phase adjustment to the positive terminal of the comparator of the phase adjustment circuit. The above two voltages are input to both ends of the comparator, and by adjusting the voltage of the negative terminal of the comparator, waveforms of different phases can be obtained at the output terminal of the comparator.

The length of use time can be recorded and read through the FPGA, and then the time and phase drift can be modeled through the actual measurement of the oscilloscope. In the subsequent use of the tester, the FPGA will calculate the set value of the negative terminal voltage of the comparator according to the compensation model and the actual use time.

As shown in Figure 2, where the resistor R1 and the capacitor C1 are used for the adjustment of the RC rise time delay, the voltage on the capacitor C1 is derived from the RC charging time formula, U _C =U _VG1 *(1-e ^-t/rc ), so Delay error t=RC*Ln[U _VG1 /(U _VG1 -U _C )], where U _C is the voltage of capacitor C1, and the voltage U _C on capacitor C1 will gradually increase with the charging of resistor R1, and also That is, the voltage of the input positive terminal of the digital analog converter IOP1 will gradually increase, and the resistance R5 and the resistance R2 constitute an operational amplifier circuit. The actual application can be adjusted to the desired amplification factor according to the specific voltage requirements. The resistance R5, the resistance R2 and the digital The analog converter IOP1 receives the voltage VF1.

LMV393 is the type of comparator U1, and its positive terminal is the output voltage U _O = U _C * (1+ R2/R1) of the previous stage digital-analog converter IOP1 (that is, the amplified Uc). The negative terminal input voltage U _VS1 of the comparator U1 (ie, the voltage VS1 in FIG. 2 ) is adjusted by the FPGA through a digital-to-analog converter (DAC), and is a programmable terminal, which is connected to the resistor R3. With the rise of the output voltage U _O of the positive terminal of the comparator U1, when the output voltage U _O is higher than the input voltage U _VS1 of the negative terminal, the output terminal of the comparator U1 is reversed and a rising edge is issued. The delay of this rising edge can be passed through It is adjusted by adjusting the voltage VS1 on the negative input of the comparator. In this example, the output end of the comparator U1 is further connected to the resistor R6, one end of the resistor R6 receives the voltage VF2, and the other end of the resistor R6 receives the voltage VS2.

The resistor R1, capacitor C1, digital-to-analog converter IOP1, voltage VS1 and comparator U1 in the circuit all drift with time. When the use time changes, its operational gain, resistance value, capacitance value, output voltage and other parameters may all be change. This circuit may change the output of the phase adjustment circuit due to the use of the automatic testing machine over time, so a mathematical model is established to establish the phase change with time T=RC*Ln[U _VG1 /(U _VG1 -U _C )] Mathematical model for more accurate error compensation.

The formula for the influence of the use time on the resistance is R=R0 * (1+αt), where R0 is the precise initial resistance value, and α is the resistance time coefficient of the resistance. Through specific experiments, the coefficient of the resistance used in the circuit can be measured, and the measured α very small.

The use time has a great influence on the capacitance of the X7R capacitor, showing a linear aging characteristic C=C0 * (1-βt). After experiments, the annual loss of capacitance is about 1%~2%.

。 The change of operational gain over time is small, mostly at 10 millivolts (mV)/year, and the change factor is considered as 1- γ

.

)。 Therefore, the circuit drift coefficient K = (1+αt) * (1-βt) * (1-γ

).

)。 The compensation formula for the final calculation delay is as follows: T=RC*Ln[U _VG1 /(U _VG1 -U _C )]*K; T=RC*Ln[U _VG1 /(U _VG1 -U _C )]*(1＋αt)* (1-βt) * (1-γ

).

Example:

Based on Sandtek's Astar series automatic testing machine, after actual measurement, the α, β and γ parameter values are shown in Table 1. Table I alpha <0.0001 (resistance aging) beta 1.1% γ 0.003

Bring-in delay calculation formula: Assuming that the step size (also known as unit step) signal source voltage U _VG1 = 2V, U _C is set to 50% of U _VG1 , that is, when U _C reaches 50% of the input step signal , the comparator flips, and the delayed signal is output, that is, the phase is adjusted. When time compensation is not considered, the calculation is as follows:

Let U _VG1 = 2V, U _C = 1; bring in T = RC*Ln[U _VG1 /(U _VG1 -U _C )] = Ln[2/(2-1)] = 6.931 microseconds (us); add Time compensation factor, assuming time t=1 year, recalculate T:

) = 6.931 * (1+0.0001) * (1- 0.011) * (1 – 0.003) = 6.931 * 0.986 = 6.835 us。 T= RC*Ln[U _VG1 /( U _VG1 - U _C )] * (1+αt) * (1-βt) * (1- γ

) = 6.931 * (1+0.0001) * (1- 0.011) * (1 – 0.003) = 6.931 * 0.986 = 6.835 us.

Calculate the adjusted U _C according to T= 6.835 brought into the previous formula T = RC*Ln[U _VG1 /( U _VG1 - U _C )].

100: Error compensation calculation method R1~R3, R5~R6: Resistors VG1, VS1, VS2, VF2: Voltage U1: Comparator LMV393: Model IOP1: Digital to Analog Converter

[Fig. 1] is a flow chart of the present invention; and [Figure 2] is a circuit diagram of phase adjustment.

100: Error compensation calculation method

Claims (2)

An error compensation calculation method, which is applied to a phase adjustment circuit, the error compensation calculation method includes: S1: start to initialize a programmable logic array; S2: make the programmable logic array perform self-check, if the self-check shows normal , perform step S3, if the self-check shows an error, report the error; S3: read the length of the use time of the programmable logic array; S4: calculate a circuit drift coefficient, wherein the circuit drift coefficient satisfies the following formula, K =(1+αt) * (1-βt) * (1-γ√ t ), and K is the drift coefficient of the circuit, t is the length of the use time of the programmable logic array, and α is the resistance of the phase adjustment circuit The resistance time coefficient, β is the capacitance time coefficient of the capacitance of the phase adjustment circuit, γ is the gain change time coefficient of the operation gain of the phase adjustment circuit; S5: Calculate a phase compensation value according to the circuit drift coefficient, where the phase The compensation value satisfies the following formula, T=RC*Ln[U _VG1 /(U _VG1 -U _C )] * K=RC*Ln[U _VG1 /(U _VG1 -U _C )] * (1+αt) * (1 -βt) * (1-γ√ t ), T is the phase compensation value, R is the resistance value of the resistor of the phase adjustment circuit, C is the capacitance value of the capacitor of the phase adjustment circuit, U _VG1 is the step signal source voltage value of the voltage, and U _C is the voltage value on the capacitor of the phase adjustment circuit; S6: calculate a voltage value that needs to be output to a comparator of the phase adjustment circuit; S7: output the voltage value to the phase adjustment circuit a digital-to-analog converter of the circuit; and S8: complete the compensation configuration of the phase adjustment circuit. The error compensation calculation method of claim 1, wherein the programmable logic array performs self-checking by generating a finely adjustable voltage through the programmable logic array and the digital-to-analog converter of the phase adjustment circuit, and inputting the Finely adjust the voltage to a negative terminal of the comparator of the phase adjustment circuit, and input a high-speed signal for phase adjustment to a positive terminal of the comparator of the phase adjustment circuit, by adjusting the voltage of the negative terminal, Waveforms of different phases are obtained at an output end of the comparator.

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