TWI773289B - Data access adjustment method of display data latch, display driver chip and information processing device - Google Patents

Abstract

The present invention mainly discloses a data access adjustment method of a display data latch, which enables a display driver chip to adjust the bit writing/reading method of its internal display data latch according to different scanning modes, so that The display driving chip can be equipped with a display data latch with a storage bit width of only 12 bits, which reduces the manufacturing cost of the display driving chip. When operating at a maximum scan number, the display data latch directly performs data latching on a first display grayscale data based on a storage bit width, and directly outputs the first display grayscale during a grayscale data output period data. And, when operating at a minimum number of scans, the display data latch cuts and latches a second display grayscale data into a plurality of sub-display grayscale data according to the one-bit storage rule during the data receiving period, and the The display data latch outputs the second display grayscale data as a third display grayscale data with a specified bit width during the grayscale data output period; the specified bit width is, for example, 16 bits, 15 bits bits or 14 bits.

Description

Data access adjustment method of display data latch, display driver chip and information processing device

The present invention relates to the related field of display technology, and more particularly to a display data latch for enabling a display driver chip to adjust the bit writing/reading of its internal display data latch according to different scanning modes. Data access adjustment method.

Light-emitting diodes (LEDs) have many advantages such as small size, light weight, long service life and high luminous efficiency, and have been widely used in lighting devices and display devices. The LED display device is a self-luminous flat display device, which has the advantages of bright colors, wide dynamic range, high brightness, long life and high reliability. Therefore, the LED display device with large screen has been widely used in large squares, commercial advertisements, Sports venues, information dissemination, news releases, stock exchanges, as a public display medium.

FIG. 1 shows a structure diagram of a conventional LED display device. As shown in FIG. 1, the conventional LED display device 1a includes: an LED display panel 11a including X×Y LED sub-pixels, a column driving unit 12a, a row driving unit 13a including K display driving chips 131a, and A display control unit 14a, wherein the display control unit 14a is used to control the actions of the column driving unit 12a and the row driving unit 13a. Electronic engineers who are familiar with the design and manufacture of LED displays must know that since each display driver chip 131a has a fixed number of drive channels, the value of K above is Y/O, where O is the number of drive channels of the display driver chip 131a .

It is known that the display driving modes of the display driving wafer 131a for the LED display panel 11a are divided into two types: static scanning and dynamic scanning. It is worth noting that, with more and more applications of the LED display device 1a, users have higher and higher requirements for its appearance and performance. Therefore, the LED display panel 11a with ultra-small dot pitch is widely used in LED display devices 11a. Fabrication of the display device 1a. However, the LED display panel 11a with the ultra-small dot pitch can only be driven by dynamic scanning. According to the ratio of the number of lines lit at the same time to the number of lines of the entire LED display panel 11a, the dynamic scanning mode can be divided into For 8 sweeps, 16 sweeps and 32 sweeps. It is added that in the 8-scan mode, the same output channel of the display driver chip 131a is time-multiplexed to drive 8 LED sub-pixels, and so on.

FIG. 2 shows an internal block diagram of the display driver chip 131a of FIG. 1 . As shown in FIG. 2, the conventional display driving chip 131a basically includes: a shift register 1311a, a display data latch 1312a, a grayscale comparison unit 1313a, a driving current generating unit 1314a, and a current setting unit 1316a , and a plurality of digital buffers U1a~U4a. The shift register 1311a is coupled to a data clock signal DCLK and a serial display data signal SDI. On the other hand, the display data latch 1312a and the grayscale comparison unit 1313a are respectively coupled to an enable signal LE and a grayscale clock signal GCLK. It should be noted that, according to the current display data latched in the display data latch 1312a and the grayscale clock signal GCLK, the grayscale comparison unit 1313a generates a frame of display signal in the form of PWM and transmits it to the drive current generation unit 1314a , thereby adjusting the driving current of each output channel of the driving current generating unit 1314a by adjusting the duty ratio of the PWM signal, thereby adjusting the brightness (ie, displaying grayscale) of the specified LED sub-pixel.

For the LED display device 1a using dynamic scan driving, the refresh rate is an important indicator. Under the same gray level (or the number of gray levels), the higher the refresh rate is, the more stable the LED display device 1a can show the screen display without flickering. Electronic engineers who are familiar with the design and manufacture of the LED display device 1a should know that under normal circumstances, the refresh rate, grayscale level and frame period can be calculated using the following formulas (1)~(3) : Refresh rate = number of refresh groups × frame rate. . . . . . . . . . . . . . ． ． ． ． ． . . . ． ． . ． . . . . . ． . . . ． . . . . . . (1)

Gray level = number of refresh groups × number of gray clocks displayed per scan. ． ． . . . . . . . . . . . . . . . . . . . . . (2)

Frame period = number of refresh groups × number of scans × number of grayscale clocks displayed per scan × Tgclk. . . . . . . . . . . . . . . . . ． ． ． ． . ． . (3)

However, practical experience shows that the grayscale clock signal GCLK and the display clock signal DCLK are limited by the wiring frequency of the PCB board, so that the signal frequency cannot be increased. In this case, when the number of refresh groups is fixed, the maximum gray level (or the number of gray levels) that the LED display device 1a can support will vary with the change of the dynamic scanning mode. For example, when the scan number is 32 scans (high scan), the LED display device 1a can only support a maximum number of gray scales of 14 bits, but cannot support 16 bits.

As can be seen from the above description, there is a need in the art for a novel method for performing data access adjustment to the display data latch according to the scan number.

The main purpose of the present invention is to provide a data access adjustment method of a display data latch, so that a display driver chip can adjust the bit writing/reading of its internal display data latch according to different scanning modes In this way, the display driving chip can be equipped with a display data latch with a storage bit width of only 12 bits, thereby reducing the manufacturing cost of the display driving chip.

In order to achieve the above object, the present invention provides an embodiment of the data access adjustment method of the display data latch, which is applied to a display driver chip included in an LED display device, and the display driver chip includes a display driver chip. a data latch, and the display data latch has a storage bit width; the data access adjustment method of the display data latch includes the following steps: when operating a maximum scan number, the display data latch directly perform data latching on a first display grayscale data based on the storage bit width during a data reception period, and the display data latch directly outputs the first display grayscale data during a grayscale data output period; and when operating at a minimum scan number, the display data latch cuts and latches a second display grayscale data into a plurality of sub-display grayscale data based on the storage bit width during the data reception, and The display data latch outputs the second display grayscale data as a third display grayscale data having a specified bit width during the grayscale data output period.

In one embodiment, the display driver chip includes a control unit for executing the bit storage rules and for controlling the display data latch to realize data storage, data division, data splicing or data output. .

In one embodiment, the bit storage rule is M+((4M/12)+1), M is an address length, and 12 is the value of the storage bit width of the display data latch.

In one embodiment, when the specified bit width is 16 bits, the control unit controls the display data latch to splicing a plurality of the sub-display grayscale data into the third display grayscale. output after the data.

The present invention also provides a display driver chip, which is used in an LED display device and has a display data latch, and the display data latch has a storage bit width; it is characterized in that the LED display chip has a control The unit is used to implement a data access adjustment method of a display data latch, the method comprising the steps of: when operating at a maximum scan number, the display data latch is based on the storage bit width during a data reception period A first display grayscale data is directly data latched, and the display data latch directly outputs the first display grayscale data during a grayscale data output period; and when operating at a minimum scan number, the display The data latch cuts and latches a second display grayscale data into a plurality of sub-display grayscale data based on the storage bit width during the data reception, and the display data latch is in the grayscale data. During the output period, the second display grayscale data is outputted as a third display grayscale data with a specified bit width.

In one embodiment, the display driver chip includes a control unit for executing the bit storage rules and for controlling the display data latch to realize data storage, data division, data splicing or data output. .

In one embodiment, the bit storage rule is M+((4M/12)+1), M is an address length, and 12 is the value of the storage bit width of the display data latch.

In one embodiment, when the specified bit width is 16 bits, the control unit controls the display data latch to splicing a plurality of the sub-display grayscale data into the third display grayscale. output after the data.

In one embodiment, the LED display device has a display panel, and the display panel is selected from a light-emitting diode display panel, a quantum dot light-emitting diode display panel, a micro-light-emitting diode display panel, and a sub-millimeter light-emitting An LED display panel in the group consisting of a diode display panel and a perovskite-based LED (Perovskite LED, PVSK LED) display panel.

In one embodiment, the display panel has X×Y sub-pixels, the display driving chip has Y/L driving channels, and both X and Y are positive integers.

The present invention also provides an information processing device having an LED display device and at least one display driving chip of the present invention as described above.

In one embodiment, the information processing device is selected from the group consisting of a video wall, a smart TV, a smart phone, a tablet computer, a notebook computer, a smart watch, a door phone, a smart bracelet, an all-in-one computer, and a desk. An electronic device in the group consisting of upper computer and industrial computer.

1a: LED display device

11a: LED display panel

12a: Column driver unit

13a: Row drive unit

131a: Display driver chip

1311a: Shift register

1312a: Display data latch

1313a: Grayscale comparison unit

1314a: drive current generation unit

1316a: Current setting unit

14a: Display Control Unit

U1a: digital buffer

U2a: digital buffer

U3a: digital buffer

U4a: digital buffer

1: LED display device

11: LED display panel

12: Column drive unit

13: Row drive unit

131: Display driver chip

1311: Shift register

1312: Display data latch

1313: Grayscale comparison unit

1314: drive current generation unit

1315: Control Unit

1316: Current setting unit

14: Display control unit

U1: digital buffer

U2: digital buffer

U3: digital buffer

U4: digital buffer

S1: When operating at a maximum scan number, the display data latch directly performs data latching on a first display grayscale data based on the storage bit width during a data reception period, and the display data latch Directly output the first display grayscale data during a grayscale data output

S2: when operating at a minimum scan number, the display data latch cuts and latches a second display grayscale data into a plurality of sub-display grayscale data based on the storage bit width during the data receiving period, And the display data latch outputs the second display grayscale data as a third display grayscale data with a specified bit width during the grayscale data output period

1 is a structural diagram of a conventional LED display device; FIG. 2 is an internal block diagram of the display driver chip of FIG. 1; Schematic diagram of the display device; FIG. 4 is an internal block diagram of the display driver chip of FIG. 3 ; and FIG. 5 is a flowchart of a data access adjustment method of a display data latch according to the present invention.

In order to enable your examiners to further understand the structure, features, objectives, and advantages of the present invention, drawings and detailed descriptions of preferred embodiments are attached as follows.

FIG. 3 shows a structural diagram of an LED display device applying a data access adjustment method of a display data latch according to the present invention. As shown in FIG. 3 , the LED display device 1 includes: an LED display panel 11 including X×Y LED sub-pixels, a column driving unit 12 , a row driving unit 13 including K display driving chips 131 , and a display control unit 14. Electronic engineers who are familiar with the design and manufacture of LED displays must know that since each display driver chip 131 has a fixed number of driving channels, the aforementioned K value can be calculated as Y/O, where O is the value of the display driver chip 131. The number of drive channels. FIG. 4 shows an internal block diagram of the display driver chip 131 of FIG. 3 . As shown in FIG. 2 , the conventional display driving chip 131 basically includes: a shift register 1311 , a display data latch 1312 , a grayscale comparison unit 1313 , a driving current generating unit 1314 , and a current setting unit 1316 , and a plurality of digital buffers U1~U4. It should be noted that, as shown in FIG. 4 , the display driving chip 131 further has a control unit 1315 , and the control unit 1315 can implement the data access adjustment method of the display data latch of the present invention.

Specifically, the display data latch 1312 has a storage bit width (eg, 12 bits). FIG. 5 is a flow chart showing a data access adjustment method of a display data latch according to the present invention. As shown in FIG. 5 , the data access adjustment method includes the following steps: S1 : when operating at a maximum scan number, the display data latch 1312 adjusts a first value based on the storage bit width during a data reception period The display grayscale data is directly latched, and the display data latch 1312 directly outputs the first display grayscale data during a grayscale data output period; and S2: when operating at a minimum scan number, the display data During the data receiving period, the latch 1312 cuts and latches a second display grayscale data into a plurality of sub-display grayscale data according to the one-bit storage rule, and the display data latch 1312 is in the grayscale data. During the output period, the second display grayscale data is outputted as a third display grayscale data with a specified bit width.

The bit width of the display grayscale data (ie, the serial display data signal SDI) received by the display driving chip 131 generally varies between 12 bits and 16 bits. After the control unit 1315 and the shift register 1311 receive a serial display data signal SDI, the shift register 1311 performs a shift register process on the serial display data signal SDI, and the control unit 1315 performs a shift register on the serial display data signal SDI. Display data signal SDI for data identification. It is worth noting that when the scan number adopted in the scan mode is 32 scans (ie, the highest scan number), the display driving chip 131 corresponding to 32 scans can support a maximum grayscale number of 14 bits, and cannot support 16 bits. At this time, according to the design of the present invention, when the storage bit width of the display data latch 1312 is 12 bits, the control unit 1315 will execute step S1, so as to make the display data latch 1312 a During data reception, data latch processing is directly performed on a first display grayscale data obtained from the serial display data signal SDI based on the storage bit width (ie, 12 bits), and the display data latch 1312 directly outputs the first display grayscale data during a grayscale data output period.

On the other hand, in the case where the scan number is 8 scans (ie, the lowest scan number), the control unit 1315 will execute step S2: when the operation is at a lowest scan number, the display data latch 1312 is in the data During reception, a second display grayscale data obtained from the serial display data signal SDI is divided and latched into a plurality of sub-display grayscale data according to the one-bit storage rule, and the display data The latch 1312 outputs the second display grayscale data as a third display grayscale data having a specified bit width during the grayscale data output period.

For example, if the storage bit width of the display data latch 1312 is 12 bits, the bit storage rule is M+((4M/12)+1); where M is an address length, and 12 is an address length. The value of the storage bit width of the display data latch. Therefore, when the operation is at the lowest scan number, the display data latch 1312 realizes the syntax reference of the second display grayscale data according to the bit storage rule as follows: data_1={sram[M+1][3:0 ],sram[0]}; data_2={sram[M+1][7:4],sram[0]};data_3={sram[M+1][11:8],sram[0]}; data_4={sram[M+2][3:0],sram[0]};. . . . . . . . ．

Thus, the above has completely and clearly described a data access adjustment method for a display data latch of the present invention; and, from the above, it can be known that the present invention has the following advantages:

(1) The present invention discloses a data access method for adjusting the display data latch according to the scan number, so that a display driver chip can adjust the bit writing/writing of the internal display data latch according to different scanning modes. The readout method enables the display driving chip to be equipped with a display data latch with a storage bit width of only 12 bits, which reduces the manufacturing cost of the display driving chip. When operating at a maximum scan number, the display data latch directly performs data latching on a first display grayscale data based on a storage bit width, and directly outputs the first display grayscale during a grayscale data output period data. And, when operating at a minimum number of scans, the display data latch cuts and latches a second display grayscale data into a plurality of sub-display grayscale data according to the one-bit storage rule during the data receiving period, and the The display data latch outputs the second display grayscale data as having a specified bit during the grayscale data output period One of the element widths thirdly displays grayscale data; the specified element width is, for example, 16bits, 15bits or 14bits.

(2) The present invention also provides an information processing device having an LED display device and at least one display driver chip applying the data access method for adjusting the display data latch according to the scan number of the present invention. Wherein, the information processing device is selected from the group consisting of video walls, smart TVs, smart phones, tablet computers, notebook computers, smart watches, door phones, smart bracelets, all-in-one computers, desktop computers, An electronic device in the group consisting of an industrial computer.

It must be emphasized that the above-mentioned disclosure in this case is a preferred embodiment, and any partial changes or modifications originating from the technical ideas of this case and easily inferred by those who are familiar with the art are within the scope of the patent of this case. category of rights.

To sum up, regardless of the purpose, means and effect of this case, it shows that it is completely different from the conventional technology, and its first invention is suitable for practical use, and indeed meets the patent requirements of the invention. Society is to pray for the best.

S1: When operating at a maximum scan number, the display data latch directly performs data latching on a first display grayscale data based on the storage bit width during a data reception period, and the display data latch Directly output the first display grayscale data during a grayscale data output

S2: when operating at a minimum scan number, the display data latch cuts and latches a second display grayscale data into a plurality of sub-display grayscale data based on the storage bit width during the data receiving period, And the display data latch outputs the second display grayscale data as a third display grayscale data with a specified bit width during the grayscale data output period

Claims (10)

A data access adjustment method for a display data latch, which is applied to a display driver chip included in an LED display device, the display driver chip includes a display data latch, and the display data latch has a storage bit width; the data access adjustment method of the display data latch includes the following steps: when operating at a maximum scan number, the display data latch is adjusted based on the storage bit width during a data reception period A first display grayscale data is directly data latched, and the display data latch directly outputs the first display grayscale data during a grayscale data output period; and when operating at a minimum scan number, the display data The latch cuts and latches a second display grayscale data into a plurality of sub-display grayscale data according to the one-bit storage rule during the data receiving period, and the display data latch is during the grayscale data output period The second display grayscale data is output as a third display grayscale data with a specified bit width. The data access adjustment method for a display data latch as claimed in claim 1, wherein the display driver chip includes a control unit for executing the bit storage rule and for controlling the display data latch In order to realize the work of data storage, data segmentation, data splicing or data output. The data access adjustment method of the display data latch according to claim 2, wherein the bit storage rule is M+((4M/12)+1), M is an address length, and 12 is the display The value of the storage bit width of the data latch. The data access adjustment method for a display data latch according to claim 2, wherein, in the case that the specified bit width is 16 bits, the control unit controls the display data latch to store a plurality of all The sub-display grayscale data is spliced into the third display grayscale data and then output. A display driving chip is applied in an LED display device and has a display data latch, the display data latch has a storage bit width; it is characterized in that the display driving chip has a control unit for realizing A data access adjustment method for a display data latch, the method includes the following steps: When operating at a maximum scan number, the display data latch directly performs data latching on a first display grayscale data based on the storage bit width during a data reception period, and the display data latch is in a The first display grayscale data is directly output during grayscale data output; and when operating at a minimum scan number, the display data latch stores a second display grayscale according to a bit-byte storage rule during the data receiving period The data is cut and latched into a plurality of sub-display grayscale data, and the display data latch outputs the second display grayscale data as a third display grayscale with a specified bit width during the grayscale data output period degree data. The display driver chip according to claim 5, wherein the display driver chip includes a control unit for executing the bit storage rule and for controlling the display data latch to realize data storage, data division, Data splicing or data output work. The display driver chip of claim 6, wherein the bit storage rule is M+((4M/12)+1), M is an address length, and 12 is the storage of the display data latch The value of the width in bits. The display driving chip according to claim 6, wherein, when the specified bit width is 16 bits, the control unit controls the display data latch to splicing a plurality of the sub-display grayscale data into a The third display grayscale data is output. An information processing device has an LED display device and at least one display driving chip according to any one of claim 5 to claim 8. The information processing device according to claim 9, wherein the information processing device is selected from the group consisting of video walls, smart TVs, smart phones, tablet computers, notebook computers, smart watches, door phones, smart phones An electronic device in the group consisting of rings, all-in-one computers, desktop computers, and industrial computers.

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