TWI772982B - Memory device and manufacturing method thereof - Google Patents

Abstract

A memory device includes: a substrate, and a stacked structure including first dielectric layers and electrode layers alternately arranged. In a first lateral direction, the memory device includes a middle region and an array region. In a second lateral direction, the stacked structure includes a first block storage region and a second block storage region each including a wall structure region. In the middle region, the wall structure regions of the first block storage region and the second block storage region are separated by a stepped structure. The memory device further includes a bundle structure located in the middle region and including at least a plurality of discrete first bundle structures each extending along the second lateral direction and connecting the wall structure regions of the first block storage region and the second block storage region; and a plurality of second dielectric layers located in the bundle structure. In the first bundle structure, the second dielectric layers alternate with the first dielectric layers.

Description

Memory storage device and method of making the same

In general, the present disclosure relates to the technical field of semiconductor manufacturing, and in particular, to a memory storage device and a method for manufacturing the same.

Scale planar memory cells to smaller sizes by improving process technology, circuit design, programming algorithms and manufacturing processes. However, as memory cell feature sizes approach lower limits, planar processes and fabrication techniques become challenging and costly. Therefore, the storage density of planar memory cells approaches an upper limit.

The three-dimensional storage architecture can address the density limit in planar storage cells. A three-dimensional storage architecture includes a storage array and peripheral components for controlling signals accessing the storage array.

With the development of planar flash memory, tremendous progress has been made in the production process of semiconductor electronic components. However, in recent years, the continued development of planar flash memory has encountered many challenges, such as physical limitations, limitations of existing lithography technology, limitations of stored electron density, and so on. In order to solve the difficulties encountered by planar flash memory and pursue lower production cost per storage unit, various three-dimensional (3D) flash memory structures including 3D or not (NOR) and 3D and not (NAND) have appeared .

In the 3D flash memory of the NOR type structure, storage cells are arranged in parallel between the bit line and the ground line, while in the 3D flash memory of the NAND type structure, the bit line and the ground line are connected in series Arrange storage units. NAND flash memory with a tandem structure has lower read speed, but higher write speed and erase speed. Therefore, NAND flash memory is suitable for storing data. In addition, for data storage, NAND flash memory also exhibits many advantages, such as smaller cell size and larger storage capacity.

A 3D NAND flash memory includes a plurality of storage array structures, wherein each storage array structure includes a plurality of storage cells arranged in a 3D array. The 3D NAND flash memory further includes a plurality of ladder structures for accessing and electrically connecting the memory cells at different layers. In many designs, each stepped structure corresponds to and is located at one side of a storage array structure. The electrical connections from the stepped structures all extend in the same direction to connect the storage array structures. As the number of stacked layers in the memory array structure increases, the resistance of the wiring from the ladder structure to the memory array structure increases, causing resistance-capacitance (RC) delay problems. Therefore, the performance of 3D NAND flash memory may be affected.

In order to reduce the length of the connection between the stepped structure and the corresponding storage unit, in some designs, the stepped structure is arranged between two storage array structures, and the electrical connection from the stepped structure can be between the two storage array structures. Extend in different directions to connect the storage array structure. Therefore, the total resistance of the wiring can be reduced, and thus the RC delay problem can be suppressed. When a stepped structure is formed between two storage array structures, some electrical connections formed on the stepped structure need to pass through the wall structure in order to be electrically connected to the two storage structures. However, as the number of stacked layers in 3D NAND flash memory increases, the height of the wall structure may increase, and thus collapse of the wall structure may become a problem for 3D NAND flash memory.

The disclosed memory storage elements and methods of manufacture address one or more of the problems set forth above, as well as others in the art.

One aspect of the present disclosure provides a memory storage element. The memory storage element includes: a substrate; and a stack structure including a plurality of first dielectric layers and a plurality of electrode layers alternately arranged on the substrate. In a first lateral direction relative to the substrate, the memory storage element includes array regions and intermediate regions disposed between the array regions. In a second lateral direction relative to the substrate, the stack structure includes a first block of storage areas and a second block of storage areas each including a wall structure area. In the intermediate area, the wall structure areas of the first block storage area and the second block storage area are separated by a stepped structure. The memory storage element further includes: a bundle structure located in the intermediate region and including all of the storage regions each extending in the second lateral direction and connecting the first storage region and the second storage region. at least a plurality of discrete first bundle structures of the wall structure region; and a plurality of second dielectric layers in the bundle structures. In the plurality of discrete first bundle structures, the plurality of second dielectric layers alternate with the plurality of first dielectric layers.

Another aspect of the present disclosure provides a method for forming a memory storage element. The method includes forming a stack including a plurality of first dielectric layers and a plurality of second dielectric layers alternately arranged on a substrate. In a first lateral direction with respect to the substrate, the stacked structure is formed in an array region and an intermediate region disposed between the array regions. The method includes forming a stepped structure and a plurality of discrete first beam structures in the intermediate region. Each first bundle structure of the plurality of discrete first bundle structures extends in a second lateral direction relative to the substrate. The method further includes forming vertically through the stack and into the substrate, and along the A plurality of gate line slots (GLS) extending in the first lateral direction. In the second lateral direction, the plurality of gate line slits define at least a first block storage area and a second block storage area. The plurality of gate line slits include gate line slits formed in respective array regions at a boundary between the first block storage region and the second block storage region. The method further includes removing the plurality of second dielectric layers from the array region and partially from the intermediate region. Portions of the plurality of second dielectric layers remain in the plurality of discrete first bundle structures after removing the plurality of second dielectric layers from the array region and partially from the intermediate region middle.

Those skilled in the art can understand other aspects of the present disclosure from the description of the disclosure, the scope of the application and the accompanying drawings.

100:3D memory storage element

102: slice storage area

104: Ladder Structure

106: Storage Array Structure

200: 3D memory storage element

202: slice storage area

204: Ladder Structure

206-1: Storage array structure (first storage array structure)

206-2: Storage Array Structure (Second Storage Array Structure)

300:3D memory storage element

301: Intermediate Zone

302: block storage area

303: Array area

304: refers to the storage area

306: Wall Structure Area

308: Gate line gap

310: Cut

312: word line contact

314: Dummy channel structure

318: Channel Structure

321: Dielectric layer

322: Sacrificial Layer

350: Base

400: Middle Zone

401: Stacked Structure

402: The first step area

404: Wall Structure

406-1: The first pair of stairs

406-2: The first pair of stairs

408-1: Partition

408-2: Partition

408-3: Partition

410-1: Second pair of stairs

410-2: Second pair of stairs

412: Second step area

414-1: Third pair of stairs

414-2: Third Pair of Ladders

416-1: Fourth Pair of Ladders

416-2: Fourth Pair of Ladders

501: Middle Zone

502: block storage area

5021: block storage area

5022: block storage area

5023: block storage area

5024: block storage area

503: Array area

504: refers to the storage area

506: Wall Structure Area

508: Gate line gap

512: word line contact

516: First isolation structure

518: First Bundle Structure

519: Second bundle structure

520: Sub-ladder structure

521: first dielectric layer

522: Second Dielectric Layer

530: Second isolation structure

531: Electrode layer

550: Base

S601: Steps

S602: Step

S603: Steps

S604: Step

S605: Steps

S701: Steps

S702: Steps

S703: Steps

S704: Step

S705: Steps

E: point

F: point

L0: width (distance)

L0': width (distance)

L1: Distance

L2: Distance

The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments of the present disclosure and together with the description further serve to explain the principles of the present disclosure and to enable others skilled in the relevant art to make and use the present invention content.

Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. Note that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

The following drawings are merely examples for illustrative purposes, and are not intended to limit the scope of the present disclosure, in accordance with the various disclosed embodiments.

Figure 1 illustrates a 3D memory storage element with a stepped structure located at the edge of the slice storage area. Schematic diagram; FIG. 2 illustrates a schematic diagram of another 3D memory storage element with a stepped structure located in the middle area of the slice storage area; FIG. 3 illustrates a 3D memory storage element with a stepped structure located in the center of the slice storage area A plan view of the element; FIG. 4 illustrates a cross-sectional view of the 3D memory storage element shown in FIG. 3 along line AA'; FIG. 5 illustrates a front top perspective view of the stepped structure of a 3D memory storage element; FIG. 6-23 illustrate schematic diagrams of semiconductor structures at particular stages of an exemplary method according to various embodiments of this disclosure; FIG. 24 illustrates a method for forming memory storage elements according to various embodiments of this disclosure. Flow charts of exemplary methods; FIGS. 25-38 illustrate schematic diagrams of semiconductor structures at particular stages of an exemplary method in accordance with various embodiments of the present disclosure; FIG. 39 illustrates methods for forming various implementations in accordance with the present disclosure. Figure 40 illustrates a schematic top view of an exemplary semiconductor structure in accordance with various embodiments of this disclosure; and Figure 41 illustrates various implementations in accordance with this disclosure A schematic top view of another exemplary semiconductor structure of the present invention.

The features and advantages of the present disclosure will become more apparent from the detailed description set forth below, when read in conjunction with the accompanying drawings, wherein like reference characters identify corresponding elements. In the drawings, like reference numerals generally identify identical, functionally similar, and/or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit(s) in the corresponding reference number.

Embodiments of the present disclosure will be described with reference to the accompanying drawings.

Reference will now be made in detail to exemplary embodiments of the present invention which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts.

The technical solutions in the embodiments of the present invention will be described below with reference to the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts. Obviously, the described embodiments are only some, but not all, embodiments of the invention. Features in the various embodiments may be exchanged and/or combined. Other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative efforts will fall within the scope of the present invention.

Reference will now be made in detail to the exemplary embodiments of the present invention illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like elements.

The following disclosure provides many different embodiments or examples for implementing different features of the presented subject matter. To simplify this disclosure, specific examples of components and arrangements are described below. Of course, these are only examples and are not intended to be limiting. For example, in the following description, the formation of a first feature on or over a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include embodiments in which additional features may be formed Embodiments between the first and second features such that the first and second features may not be in direct contact. Furthermore, this summary may repeat reference numerals and/or letters in various instances. This repetition is for the purpose of simplicity and clarity and does not in itself determine the relationship between the various embodiments and/or configurations discussed.

Furthermore, for ease of description, spatially relative terms, such as "below,""under,""lower,""over,""over," and the like, may be used herein to describe one element or feature as illustrated in the figures with respect to another element or feature. feature relationship. Spatially relative terms are intended to encompass different orientations of elements in use or steps of operation (in addition to the orientation shown in the figures). The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

While specific configurations and arrangements are discussed, it should be understood that this has been done for illustrative purposes only. Those skilled in the relevant art will recognize that other configurations and arrangements may be used without departing from the spirit and scope of the present disclosure. It will be apparent to those skilled in the relevant art that the present teachings may also be used in various other applications.

Note that references in this specification to "one embodiment," "an embodiment," "an example embodiment," "some embodiments," etc. indicate that the described embodiment may include the particular feature, structure, or characteristic, but each Implementations may not necessarily include a particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Furthermore, when a particular feature, structure or characteristic is described in conjunction with an embodiment, it will be within the knowledge of one skilled in the relevant art to affect such feature, structure or characteristic in conjunction with other embodiments, whether explicitly described or not.

Generally, terms can be understood, at least in part, from their usage in the context. For example, the term "one or more" as used herein may be used to describe any feature, structure or characteristic in the singular or may be used to describe the feature, structure or characteristic in the plural depending at least in part on context combination. Similarly, terms such as "a", "an", and "the" may again be understood to convey a singular usage or to convey a plural usage, depending at least in part on context. Furthermore, again The term "based on" may be understood as not necessarily intended to convey an exclusive set of factors, and may instead allow for the presence of additional factors not necessarily explicitly described, at least in part on context.

It should be readily understood that the meanings of "on", "on" and "over" in this summary are to be taken in the broadest sense is interpreted in such a way that "on" means not only "directly on something", but also includes the meaning of "on something" with intervening features or layers, and " On" or "over" not only means "over something" or "over something," but can also include its "over something" The meaning of "on" or "over something" without intervening features or layers (ie, directly on something).

Additionally, spatially relative terms such as "below", "below", "lower", "above", "upper", etc. may For ease of description, the description herein of one element or feature is used to describe the relationship of one element or feature to other elements or features as illustrated in the accompanying drawings. In addition to the orientations depicted in the figures, the spatially relative terms are intended to include different orientations of the device during use or processing steps. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

As used herein, the term "substrate" refers to a material to which subsequent layers of material are added. The substrate includes a "top" surface and a "bottom" surface. The top surface of the substrate is generally where the semiconductor devices are formed, and thus the semiconductor devices are formed at the top side of the substrate, unless otherwise specified. The bottom surface is opposite the top surface, and thus the bottom side of the substrate is opposite the top side of the substrate. The substrate itself can be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Additionally, the substrate may include a number of semiconductor materials (eg, silicon, germanium, gallium arsenide, indium phosphide, etc.). Alternatively, the substrate may be made of a non-conductive material such as glass, plastic or sapphire wafer.

As used herein, the term "layer" refers to a portion of a material that includes a region of thickness. The layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate and the top side is relatively remote from the substrate. A layer may extend over the entire underlying or overlying structure, or may have a width that is less than the width of the underlying or overlying structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of the continuous structure or between any set of levels thereon. The layers may extend horizontally, vertically and/or along a tapered surface. A substrate can be a layer, can include one or more layers therein, and/or can have one or more layers thereon, over it, and/or under it. Layers may include multiple layers. For example, the interconnect layers may include one or more conductive and contact layers (wherein contacts, interconnect lines and/or vertical interconnect access (VIA) are formed) and one or more dielectric layers.

In this summary, for ease of description, "row" is used to refer to elements of substantially the same height along a vertical direction. For example, wordlines and underlying gate dielectric layers may be referred to as "rows," wordlines and underlying insulating layers may be collectively referred to as "rows," and wordlines of substantially the same height may be referred to as "rows" A line of word lines" or similar terms, etc.

As used herein, the term "nominal (nominal)/nominal (nominal)" refers to a desired or target value of a characteristic or parameter of an element or process step set during the design phase of a product or process, Along with a range of values above and/or below the desired value. The range of values may be due to slight variations in manufacturing process or tolerances. As used herein, the term "about" indicates a given amount of value that may vary based on the particular technology node associated with the subject semiconductor device. Based on the particular technology node, the term "about" may indicate a given amount of value that varies, eg, within 10-30% of the value (eg, ±10%, ±20%, or ±30% of the value).

As used herein, the term "nominal/nominal" refers to a desired or target value for a characteristic or parameter of a component or process step set during the design phase of a product or process, and higher and/or lower The range of values to expect. The range of values may be due to slight variations in the manufacturing process or tolerances. As used herein, the term "about" indicates a given amount of value that may vary based on the particular technology node associated with the subject semiconductor element. Based on a particular technology node, the term "about" may indicate a given amount of value, which varies, for example, within 10%-30% of the value (eg, ±10%, ±20%, or ±30% of the value).

In this context, the term "horizontal/horizontal/lateral/laterally" means nominally parallel to the lateral surface of the substrate, and the term "vertical" or "vertically" means nominally perpendicular to the lateral surface of the base.

As used herein, the term "3D memory" refers to a solid (referred to herein as a "memory string", eg, a NAND string) of vertically oriented strings of memory cell transistors (referred to herein as "memory strings", eg, NAND strings) on a laterally oriented substrate. 3D) semiconductor device such that the memory strings extend in a vertical direction relative to the substrate.

The following disclosure provides various embodiments or examples for implementing various features of the presented subject matter. Specific examples of elements and arrangements are described below to simplify the disclosure. Of course, these are examples only and are not intended to be limiting. For example, appearances in the description below that a first feature is formed on or over a second feature may include embodiments in which the first and second features are directly contactable features, and may also include Embodiments in which additional features are formed between the first and second features such that the first and second features are not in direct contact. Furthermore, the present invention may reuse digits and/or letters as reference numerals in the various examples. This repetition is for the purpose of simplicity and clarity, and does not in itself indicate the relationship between the various embodiments and/or configurations discussed.

In some 3D memory storage devices, a stacked storage structure (eg, storage stack layers) is passed through, ie, storage cells for storing data are stacked vertically. 3D memory storage elements typically include stepped structures formed on one or more sides (edges) of the stacked storage structure for purposes such as word line fan-out. Since a staircase structure is usually formed at the edge of each slice storage area, word lines and corresponding The stepped structure drives the storage unit on one side.

FIG. 1 illustrates a schematic diagram of a 3D memory storage element with a stepped structure at the edge of a slice storage area. Referring to FIG. 1 , a 3D memory storage element 100 (eg, a 3D NAND memory storage element) includes two slice storage regions 102 each having an array of storage cells in a storage array structure 106 . It should be noted that the X and Y axes are included in Figure 1 to illustrate two orthogonal (perpendicular) directions in the wafer plane. The X direction is the word line direction of the 3D memory storage device 100 , and the Y direction is the bit line direction of the 3D memory storage device 100 . The 3D memory storage element 100 also includes two stepped structures 104 at opposite sides in the X direction of each storage array structure 106 . Each word line of the slice storage area 102 extends laterally in the X direction, across the entire slice storage area 102 to a respective step (level) in the stepped structure 104 . Row decoders (not shown) are formed just above, below, or near the respective ladder structures 104 to reduce interconnect length. That is, each row decoder drives half of the memory cell unilaterally (in either the positive or negative X direction, but not in both directions) through half of the word lines, each of which Across the entire slice store 102 .

The load of the single-sided row word line drive scheme, which includes the resistance of the entire word line across the chip storage area 102 . Furthermore, as the demand for higher storage capacity continues to grow, the number of vertical levels of stacked storage structures increases and the thickness of the stacked layers, including individual word line films, decreases. therefore, High resistance may be introduced into the load, thus causing significant resistance-capacitance (RC) delays. Accordingly, the performance (eg, read and write speed) of the 3D memory storage device 100 may be affected by the single-sided word line driving scheme with the side stepped structure 104 .

In order to reduce the RC delay, in some other 3D memory storage devices, a ladder structure is arranged between the slice storage areas to realize a double-sided word line driving scheme. By replacing the conventional side ladder structure with, for example, a center ladder structure, each row decoder can start from the middle of the slice storage area and drive the word lines bilaterally in opposite directions so that the resistance in the load will be affected by the row decoding. The length of the word line driven by the driver can be reduced by, for example, half. In some 3D memory storage devices, a portion of the staircase structure is introduced into the wall structure to connect the word lines separated by the center/transition staircase structure. In addition, a multi-partition ladder structure in which each step of the ladder structure includes a plurality of partitions of a plurality of word lines for fan-out is used to improve the utilization rate of the ladder structure and reduce the manufacturing complexity. Additionally, multiple cutting processes are used to form multiple steps at different depths to reduce the number of trim etch processes, thus further reducing fabrication complexity and increasing yield. Further, after the steps are formed, partitions are formed to reduce the number of material layer pairs (eg, silicon nitride and silicon dioxide pairs) in the stack to be etched, thereby reducing the need to cover areas outside the step regions (eg, , wall structure) thickness requirements of the hard mask.

FIG. 2 illustrates a schematic diagram of another 3D memory storage element having a stepped structure located in the middle area of the slice storage area. Referring to FIG. 2 , the 3D memory storage element 200 includes two slice storage areas 202 . Each slice storage area 202 includes a storage array structure 206-1/storage array structure 206-2 and an intermediate area. The stepped structure 204 formed in the middle area laterally divides the storage array structure 206-1/storage array structure 206-2 into the first storage array structure 206-1 and the second storage array in the X direction (word line direction) Structure 206-2. That is, the stepped structure 204 is formed between the first storage array structure 206-1 and the second storage array structure 206-2. Unlike the 3D memory storage device 100 shown in FIG. 1 , the ladder structure in FIG. 1 has 104 bits At opposite sides of each storage array structure 106, each stepped structure 204 of the 3D memory storage device 200 in this embodiment is located between the first storage array structure 206-1 and the second storage array structure 206-2. As shown in FIG. 2, in some examples, for each slice storage area 202, the stepped structure 204 is located in the center of the storage array structure 206-1/storage array structure 206-2. That is, the ladder structure 204 may be one that equally divides the storage array structure 206-1/storage array structure 206-2 into the first storage array structure 206-1 and the second storage array structure 206-2 having the same number of storage cells Center ladder structure. For example, the first storage array structure 206 - 1 and the second storage array structure 206 - 2 may be symmetrical in the X direction corresponding to the central stepped structure 204 . It should be understood that in some other examples, the stepped structure 204 may not be centrally located (ie, at the exact center) of the storage array structure 206-1/206-2, such that the first storage array structure 206-1 and the second storage array structure 206-2 may have different sizes and/or different numbers of storage cells. In some examples, 3D memory storage element 200 is a NAND flash memory element in which NAND is stored in first storage array structure 206-1 and second storage array structure 206-2 The storage cells are provided in the form of an array of strings (not shown). The first storage array structure 206-1 and the second storage array structure 206-2 may include any other suitable elements including, but not limited to, gate line slots (GLS), through-array contacts (TACs), array common source (ACS), etc.

Each word line (not shown) of the slice storage area 202 extending laterally in the X direction is separated into two parts by the corresponding staircase structure 204: the first word line spanning the first storage array structure 206-1 portion, and a second word line portion across the second storage array structure 206-2. As described in detail below, the two portions of each word line are electrically connected by wall structures (not shown) in the ladder structure 204 at each step of the ladder structure 204 . A row decoder (not shown) is formed directly above, below, or near each ladder structure 204 to reduce interconnect length. Therefore, instead of the row decoders of the 3D memory storage element 100 shown in FIG. 1, each row decoder of the 3D memory storage element 200 drives the first storage bilaterally (in both the positive and negative X directions) Memory cells in the array structure 206-1 and the second memory array structure 206-2 Yuan. That is, by replacing the conventional side stair structure (eg, the stair structure 104 shown in FIG. 1 ) with, for example, the stair structure 204 in the middle of the storage array structures 206-1/206-2, each row decoder can Starting in the middle of the storage area 202, the word lines are driven bilaterally in opposite directions so that the resistance in the load is reduced by, for example, half the length of the portion of each word line to be driven by the row decoder (in the The stepped structure 204 can be reduced when arranged in the central portion of the storage array structure 206-1/206-2). That is, the row decoder of the 3D memory storage device 200 only needs to drive either the first word line part or the second word line part of each word line.

3 illustrates a plan view of a 3D memory storage element having a stepped structure at the center of a slice storage area, and FIG. 4 illustrates a cross-sectional view of the 3D memory storage element shown in FIG. 3 along line AA'. 3-4, the X, Y, and Z axes are used to illustrate the spatial relationship of elements in 3D memory storage element 300. The 3D memory storage device 300 includes a substrate 350 and a stacked structure including a plurality of dielectric layers 321 and a plurality of sacrificial layers 322 . The plurality of dielectric layers 321 and the plurality of sacrificial layers 322 are alternately arranged. In the X direction, the 3D memory storage element 300 includes a middle area 301 located at the center of a slice storage area (not shown). The 3D memory storage element 200 may be a stepped structure including a middle area formed in the slice storage area 202 . 204 is one example of the slice storage area 202 shown in FIG. 2 , and the middle area 301 of the 3D memory storage element 300 may be an example corresponding to the middle area in the slice storage area 202 . As shown in FIG. 3 , the 3D memory storage element 300 is divided in the Y direction (bit line direction) into a plurality of block storage regions 302 separated by a plurality of parallel gate line slits 308 . In some examples, 3D memory storage element 300 is a NAND flash memory element, and accordingly, each block storage area 202 is the smallest erasable unit of a NAND flash memory element. Each block storage area 302 further includes a plurality of finger storage areas 304 separated in the Y direction by gate line slits 308 having "H" cutouts 310 . Each block storage area 302 also includes a wall structure area 306 that separates the block storage area 302 from adjacent block storage areas 302 .

Referring to FIG. 3 , the 3D memory storage element 300 further includes two array regions 303 separated by a middle region 301 . A plurality of top select gates (TSGs) can be formed in the array region 303 and can be electrically connected to interconnects in the middle region 301 . As described in detail below, the intermediate region 301 includes a plurality of stepped regions, each corresponding to a respective finger storage region 304 , and also includes a plurality of wall structures (not labeled) corresponding to the wall structure regions 306 . That is, each wall structure is formed in a region overlapped by the intermediate region 301 and the corresponding wall structure region 306 . Therefore, the wall structure does not extend into any array region 303 in the X direction. The 3D memory storage element 300 includes a plurality of dummy channel structures 314 located in the intermediate region 301 including stepped regions and wall structures in order to provide mechanical support and/or load balancing. The 3D memory storage element 300 further includes a plurality of word line contacts 312 located in the stepped regions of the middle region 301, and each word line contact 312 reaches each word line (not shown) at each step in the middle region 301. ) for word line driving. The 3D memory storage element 300 may further include a plurality of channel structures 318 formed in the two array regions 303 .

To implement the double-sided word line driving scheme, each wall structure connects (physically and electrically) the first and second memory array structures (not shown) formed in the two array regions 303, respectively. In the memory storage element, word lines contact 312 from each word line in the stepped region of the middle region 301 at the middle of the 3D memory storage element 300 through the wall structure, bilaterally (in both the positive and negative x-directions) ) drives each word line. FIG. 3 further schematically illustrates the current paths of a double-sided word line drive scheme with a wall structure. The first current path, indicated by the solid arrows, and the second current path, indicated by the dashed arrows, respectively represent current through two separate word lines at different levels.

FIG. 5 illustrates a front top perspective view of the middle region 400 of a 3D memory storage element. The middle area 400 may be an example of the middle area of the 3D memory storage element 200 shown in FIG. 2 , or may correspond to the middle area 301 of the 3D memory storage element 300 shown in FIG. 3 . The intermediate region 400 includes a stacked structure 401 formed on a substrate (not shown).

In FIG. 5 , the X, Y, and Z axes are used to illustrate the spatial relationship of elements in the intermediate region 400 . The substrate of the 3D memory storage element includes two lateral surfaces extending laterally in the X-Y plane: a top surface on which the stepped structure is formed, on the front side of the wafer, and on the back side opposite to the front side of the wafer the bottom surface. The Z axis is perpendicular to both the X and Y axes. As used herein, one element (eg, a layer or element) of a 3D memory storage element is located on another element (eg, a layer or element) when the substrate is in the lowest plane of the 3D memory storage element in the Z-direction "Above", "above" or "below" is determined in the Z direction (the vertical direction perpendicular to the X-Y plane) with respect to the base of the 3D memory storage element.

The stacked structure 401 includes a plurality of first material layers (not shown) and a plurality of second material layers (not shown) alternately stacked in the Z direction. The material used to form the plurality of first material layers is different from the material used to form the plurality of second material layers. That is, the stacked structure 401 includes a plurality of material layer pairs vertically stacked in the Z direction, wherein each material layer pair includes one first material layer and one second material layer. The number of material layer pairs in stack 401 (eg, 32, 64, 96, 128, 160, 192, 224, or 256) determines the number of memory cells stacked in the Z-direction.

For example, the 3D memory storage device is a NAND flash memory device, and the stack structure 401 is a stacked storage structure through which NAND storage strings are formed. Each of the first material layers includes a conductor layer, and each of the second material layers includes a dielectric layer. That is, the stacked structure 401 includes interwoven conductor layers and dielectric layers (not shown). Further, the respective conductor layers serve as gate lines and word lines of the NAND strings, and the word lines extend from the gate lines in the lateral direction and are formed in the middle region 400 in a stepped structure for word line fan-out. stop there.

Each step (eg, shown as a "level") of the stepped structure formed in the intermediate region 400 includes one or more pairs of material layers. Referring to Figure 5, the top material layer of each step is a conductor layer for interconnection in the vertical direction (Z direction), and every two adjacent steps of the stepped structure are offset in the Z direction by nominally the same distance , and are offset in the X direction by the nominally same distance. The respective offsets thus form "landing areas" for interconnects in the Z-direction with corresponding word line contacts (not shown) of the 3D memory storage element.

As shown in FIG. 5, the middle region 400 includes a first stepped region 402, a second stepped region 412, and a space between the first stepped region 402 and the second stepped region 412 in the Y direction (bit line direction) Wall structure 404 . Each of the first stepped region 402 and the second stepped region 412 includes a stepped structure. The stepped structure of the first stepped area 402 includes multiple pairs of steps located in the X direction (word line direction), and the multiple pairs of steps include a first pair of steps 406-1, a first pair of steps 406-2, and a second pair of steps 410. -1 and the second pair of steps 410-2, the third pair of steps 414-1 and the third pair of steps 414-2, and the fourth pair of steps 416-1 and the fourth pair of steps 416-2. Each step (eg, 406-1, 406-2, 410-1, 410-2, 414-1, 414-2, 416-1, or 416-2) includes a plurality of steps in the X direction. Also, each step is a step used for contacts to reach interconnects (eg, word line via contacts), as opposed to dummy steps.

Further, the first stepped area 402 includes three finger storage areas located in the Y direction, and correspondingly, 406-1, 406-2, 410-1, 410-2, 414-1, 414-2, 416- Each step in 1 and 416-2 includes three partitions 408-1, partition 408-2, and partition 408-3 in the Y direction. In step 406-2, each step in zone 408-2 is below any step in zone 408-1 and above any step in zone 408-3.

Further, at least one of the steps in the first step area 402 or the second step area 412 The stepped through-wall structures 404 are electrically connected to each of the first storage array structure and the second storage array structure. For example, as shown in FIG. 5, the steps in steps 410-2 may pass through wall structure 404 and communicate with each other via wordline portions extending in the negative and positive X directions, respectively, as indicated by the current paths (represented by arrows). The first storage array structure and the second storage array structure are electrically connected.

Referring to FIG. 5 , as the number of material layer pairs in the stacked structure 401 increases, the steps exposing the bottom material layer pairs have a greater depth relative to the top of the wall structure 404 . That is, the aspect ratio (height in the Z direction to width in the Y direction) of the wall structure is larger. In addition, the increase in the number of material layer pairs in the stacked structure 401 also results in an increase in the length of the wall structure 404 along the X direction. Further, referring to FIGS. 3-4 , in the process of fabricating the 3D memory storage device, after the steps are formed, a plurality of gate line slits may be fabricated. For example, referring to FIG. 3, it is necessary to go all the way through the wall structure in the X direction to form gate line slits and separate adjacent stepped regions. With the larger aspect ratio and larger length of the wall structure, the wall structure may easily collapse when forming gate line slits through the entire length of the wall structure. Therefore, the performance of 3D memory storage devices may need to be improved.

SUMMARY OF THE INVENTION A method for forming a memory storage element is provided. According to the disclosed method, the formed stepped structure includes a plurality of sub-staircase structures, and the adjacent sub-staircase structures are separated from each other along the length direction of the wall structure by the first bundle of structures connected to the wall structure. The first bundle structure can provide mechanical support for the wall structure, thus preventing the wall structure from collapsing when forming gate line slits through the wall structure. In addition, for the adjacent block storage regions in which the finger storage regions are arranged between the wall structure regions, the gate line gaps formed between the two block storage regions are respectively formed at both sides of the intermediate region at the intermediate region The two first isolation structures are truncated. In the middle region spanning the two block storage regions, the second bundle structures connect the first isolation structures formed at each side of the middle region. In the second beam structure, after the second dielectric layer is removed from the array region, a portion of the second dielectric layer remains between adjacent first dielectric layers. therefore, The second dielectric layer and the first dielectric layer in the second bundle structure not only provide mechanical support for subsequent fabrication processes, but also provide electrical isolation for the two bulk storage regions. Additionally, after the second dielectric layer is removed from the array region, at least a portion of the second dielectric layer remains in each of the first bundle structures, which also provides mechanical support for subsequent fabrication processes.

24 illustrates a flowchart of an exemplary method for forming a memory storage element in accordance with various embodiments of this disclosure. 6-23 illustrate schematic diagrams of semiconductor structures at certain stages of the exemplary method.

Referring to FIG. 24 , a stacked structure including a plurality of first dielectric layers and a plurality of second dielectric layers alternately arranged on a substrate may be formed; in a first lateral direction with respect to the substrate, the stacked structure may include two an array area, and an intermediate area arranged between the array areas; in a second lateral direction relative to the substrate, the stacked structure can be divided into a plurality of block storage areas, wherein each block storage area includes a wall structure area, and an arrangement A plurality of finger storage areas at one side of the wall structure area, and adjacent block storage areas, so that the wall structure area can be arranged between the finger storage area of one block storage area and the finger storage area of another block storage area between the two block storage areas, or the finger storage areas of both block storage areas are arranged between the wall structure areas (S601). 6-7 illustrate schematic diagrams of an exemplary semiconductor structure in accordance with various embodiments of this disclosure. Specifically, FIG. 6 illustrates a schematic plan view of the semiconductor structure, and FIG. 7 illustrates a schematic cross-sectional view of the semiconductor structure shown in FIG. 6 along the line B-B'.

Referring to FIGS. 6-7 , a stack structure including a plurality of first dielectric layers 521 and a plurality of second dielectric layers 522 may be formed on a substrate 550 . A plurality of second dielectric layers 522 and a plurality of first dielectric layers 521 may be alternately arranged on the substrate 550 . In Figures 6-7, the X, Y, and Z axes are used to illustrate the spatial relationship of elements in a semiconductor structure. This summary applies the same concepts used to describe spatial relationships. in the first horizontal In the direction (eg, the X direction), the stacked structure may include two array regions 503 and an intermediate region 501 disposed between the two array regions 503 . In the second lateral direction (Y direction), the stacked structure may be divided into a plurality of block storage areas 502 . In one embodiment, each block storage area 502 may be used to form one erase unit of 3D NAND flash memory. Further, in the Y direction, each block storage area 502 may include a plurality of finger storage areas 504 and a wall structure area 506 .

Further, among the plurality of block storage areas 502 , adjacent block storage areas 502 may have the wall structure areas 506 of the two block storage areas 502 next to each other so as to span between the two block storage areas 502 A wall structure is formed in the middle region 501 of the boundary, or the finger storage region 504 of the two block storage regions 502 is arranged between the wall structure regions 506 . For example, in the Y direction, the plurality of block storage areas 502 may include a block storage area 5021, a block storage area 5022, a block storage area 5023, and a block storage area 5024 that are sequentially arranged in the Y direction. The multiple finger storage areas 504 of the block storage area 5022 and the multiple finger storage areas 504 of the adjacent block storage area 5021 can be used to connect the block storage area 5021 and the block storage area 5022 to each other. The wall structure area 506, and the wall structure area 506 of the adjacent block storage area 5022, connect the block storage area 5022 and the block storage area 5023 to each other. The block storage area 5023 and the block storage area 5024 may be connected to each other using the plurality of finger storage areas 504 of the block storage area 5024 and the plurality of finger storage areas 504 of the adjacent block storage area 5023 . It should be noted that, for illustration, four block storage areas 502 (block storage area 5021, block storage area 5022, block storage area 5023, and block storage area 5024) are shown in FIG. 6, while in practical application, the semiconductor structure At least two block storage areas may be included such that the finger storage areas of the block storage area are arranged between the wall structure areas. It should also be noted that only the portion of each array region 503 adjacent to the middle region 501 is shown in FIG. 6 .

In subsequent fabrication processes, a plurality of memory cells (eg, memory array structures) may be formed in each of the array regions 503 . In addition, a stepped structure may be formed in the finger storage areas 504 (arranged in the middle area 501 of the adjacent block storage areas 502 between the wall structure areas 506 ) spanning the two block storage areas 502 . Mutually Accordingly, the wall structures may be simultaneously formed in the intermediate regions 501 of the adjacent block storage regions 502 that span the wall structure regions 506 next to each other.

In one embodiment, the substrate 550 may be made of silicon, germanium, silicon germanium, or any other suitable semiconductor material. In other embodiments, the substrate may be made of silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable semiconductor composite material.

In one embodiment, the plurality of first dielectric layers 521 may be made of oxide (eg, silicon dioxide), and the plurality of second dielectric layers 522 may be made of nitride (eg, silicon nitride) . Therefore, the stacked structure may be a nitroxide (NO) stacked structure including a plurality of NO stacked layers.

Further, returning to FIG. 24, a first isolation structure through the stack structure may be formed at each side of the intermediate region between the two block storage regions between the wall structure regions; A stepped structure is formed from the stacked structure in the middle area of the plurality of finger storage areas; along the first lateral direction, the stepped structure may include a plurality of sub-staircase structures spaced apart from each other through the first bundle structure, the first bundle structure is along the second lateral direction extending in the direction and connected with the wall structure areas of the two block storage areas; in each block storage area, along the second lateral direction, the sub-step structure may include a plurality of rows of sub-steps formed in the plurality of finger storage areas ( S602 ) . 8-11 illustrate schematic diagrams of an exemplary semiconductor structure in accordance with various embodiments of this disclosure. Specifically, FIG. 8 illustrates a schematic plan view of the semiconductor structure, FIG. 9 illustrates a schematic cross-sectional view of the semiconductor structure shown in FIG. 8 along the line DD', and FIG. 10 illustrates a schematic view along the line CC' A schematic cross-sectional view of the semiconductor structure shown in FIG. 8 along line BB', and FIG. 11 illustrates a schematic cross-sectional view of the semiconductor structure shown in FIG. 8 along line BB'.

8-11, between the plurality of finger storage areas 504 and the two block storage areas 502 in contact with each other (eg, between block storage area 5021 and block storage area 5022, between block storage area 5023 and block storage area 5024, respectively), a first isolation through the stack structure may be formed at each side of intermediate area 501 Structure 516. In addition, a stepped structure (not labeled) may be formed from the stacked structure in the middle region 501 of the plurality of finger storage regions 504 of the two block storage regions 502; along the X direction, the stepped structure may include a plurality of sub-staircase structures 520, and phase Adjacent sub-staircase structures 520 may be separated from each other by the first bundle structures 518 extending in the Y direction. The first bundle structures 518 may be connected to the wall structure regions 506 of the respective block storage regions 520 . In one embodiment, the width of each first bundle structure 518 may be L0 in the X direction.

In one embodiment, within each block storage area 502, the sub-staircase structure 520 may include a plurality of rows of sub-steps (not shown) extending in the Y direction. In a subsequent process, word line contacts 512 may be formed on sub-steps formed in the stepped structure. For example, word line contacts 512 may be formed in each finger storage area 504 to electrically connect the sub-steps formed in the finger storage area 504 . It should be noted that wordline contacts 512 may be formed in a subsequent process, and that the circles in FIG. 8 and the dashed plugs in FIG. 10 are for illustrative purposes only for forming wordline contacts in subsequent processes 512's predetermined location. It should also be noted that a portion of the second dielectric layer 522 longitudinally below each intended wordline contact 512 may be replaced with an electrode layer in a subsequent process in order to establish electrical properties with the corresponding wordline contact 512 connect.

8-9, along the D-D' line in the array region 503 near the middle region 501, the first isolation structure 516 formed between the plurality of finger storage regions 504 and the block storage region 502 may penetrate the stack structure. Referring to FIGS. 8 and 10, along the C-C' lines parallel to the Y direction and in the cross-sectional direction cutting the sub-staircase structure 520, word line contacts 512 may be formed in the respective finger storage regions 504 in a subsequent process for electrically Sexual connection corresponding steps. In addition, after the stepped structure including the plurality of sub-staircase structures 520 is formed, the intermediate region 501 between the wall structure region 506 and the adjacent block storage regions 502 in contact with each other may be simultaneously formed along the X direction Extended wall structure (not marked). Therefore, the width of the wall structure (refer to FIG. 10 ) in the Y direction is approximately the total width of two adjacent wall structure regions 506 . 8 and 11 , the BB' line of the first bundle structure 518 between adjacent sub-staircase structures 520 is cut along the Y direction and in the cross-sectional direction, after the first isolation structure 516 and the stepped structure are formed , the stacking structure can remain unchanged. Therefore, the first bundle structure 518 extending in the Y direction can prevent the width of the wall structure from narrowing on the path from one side of the middle region 501 to the other side of the middle region 501 (about the total of the two wall structure regions 506 ). width). Therefore, when making gate line slits passing through the wall structure in the X direction, the wall structure may not easily collapse.

For each pair of the plurality of finger storage areas 504 and the block storage areas 502 in contact with each other, the first isolation structure 516 formed at each side of the middle area 501 can be used to be a stepped structure between the two block storage areas 502 The central portion of the second dielectric layer 522 in the middle provides protection so that when the second dielectric layer 522 is replaced with a metal electrode layer in a subsequent process, the stepped structure between the two bulk storage regions 502 may not be removed. the central portion of the second dielectric layer 522. The remaining central portion of the second dielectric layer 522 (which may be made of nitride) and the first dielectric layer 521 (which may be made of oxide) in the stepped structure between the two bulk storage regions 502 may Not only does it provide mechanical support for subsequent manufacturing processes, it also provides electrical isolation for the two bulk storage regions 502 formed in the memory storage element.

In one embodiment, the first isolation structure 516 may have a rectangular shape. The size of the first isolation structure 516 in the X direction may be larger than the size of the first isolation structure 516 in the Y direction. For example, the size of the first isolation structure 516 in the Y direction may be in the range of about 10 nm to 40 nm. The size of the first isolation structure 516 in the Y direction can be controlled. If the size is too small, it may take more time and use more materials in the process of filling the corresponding gap to form the first isolation structure 516 . The size of the first isolation structure 516 in the Y direction should not be too large, otherwise the first isolation structure 516 may not be able to be the second intermediate in the stepped structure between the two block storage regions 502 during the subsequent etching process. The central portion of the electrical layer 522 provides adequate protection. In addition, the size of the first isolation structure 516 in the X direction may be larger than half of the size of the finger storage area 504 in the Y direction. In addition, the dimension of each finger storage region 504 in the Y direction may be approximately the same as the dimension of the wall structure region 506 in the Y direction. In other embodiments, the first isolation structure may have any other suitable shape.

In one embodiment, the portion of the first isolation structure 516 formed in the array region 503 may be larger than the portion of the first isolation structure 516 formed in the middle region 501 . For example, the entire first isolation structure 516 may be formed in the array region 503 with an edge overlapping the boundary between the array region 503 and the intermediate region 501 , or a portion of the first isolation structure 516 formed in the array region 503 , may be twice as large as the portion of the first isolation structure 516 formed in the middle region 501 . In other embodiments, the portion of the first isolation structure formed in the array region may be equal to or smaller than the portion of the first isolation structure formed in the wall structure region.

The first isolation structure 516 may be made of insulating material (eg, silicon dioxide). It should be noted that the etch rate of the material used to form the first isolation structures 516 may be less than the etch rate of the material used to form the second dielectric layer 522 when the second dielectric layer 522 is removed in a subsequent etching process.

Referring to FIG. 8 (and FIG. 40 ), in a stepped structure formed across a plurality of finger storage areas and adjacent block storage areas 502 in contact with each other, an area close to the boundary between two block storage areas 502 is referred to as the first Two-beam structure 519. In a subsequent process, after partially replacing the second dielectric layer 522 in the stepped structure with an electrode layer, a portion of the second dielectric layer 522 (refer to FIG. 10 ) may remain in the second bundle structure 519 so that Mechanical support is provided for the material layers and electrical isolation is provided for the two bulk storage regions 502 . It should be noted that, in FIG. 8 , the rectangular area connecting the first isolation structures 516 formed at each side of the intermediate region 501 is used to schematically represent the position of the second bundle structure 519 , while in practical applications, in from the middle After the plurality of second dielectric layers 522 are partially removed, the remaining portions of the second dielectric layers in each sub-staircase structure 520 may have a different shape from the rectangle shown in FIG. 8 . In addition, as shown in FIG. 10 , since the sub-steps are formed in the respective sub-staircase structures 520 , the space between the block storage area 5021 and the block storage area 5022 or between the block storage area 5023 and the block storage area 5024 is formed. The top layer of the first dielectric layer 521 at the boundary may be lower than the top surface of the initially formed stack structure. Therefore, the top surface of the second bundle structure 519 may be lower than the top surface of the first bundle structure 518 . In the schematic top views shown in FIGS. 8 and 40 , since the first bundle structures 518 and the second bundle structures 519 have different heights, the second bundle structures 519 are shown as being cut by a plurality of first bundle structures 518 of discrete parts.

Further, returning to FIG. 24 , the stack structure may be vertically penetrated, and at the boundaries of the respective finger storage regions and the respective wall structure regions of the block storage region, a plurality of gate line slits ( GLS), wherein respective gate line gaps formed between a plurality of finger storage regions and adjacent block storage regions may be truncated by two first isolation structures formed at both sides of the middle region (S603). 12-15 illustrate schematic diagrams of an exemplary semiconductor structure in accordance with various embodiments of this disclosure. Specifically, FIG. 12 illustrates a schematic plan view of the semiconductor structure, FIG. 13 illustrates a schematic cross-sectional view of the semiconductor structure shown in FIG. 12 along the line DD', and FIG. 14 illustrates a schematic view along the line CC' A schematic cross-sectional view of the semiconductor structure shown in FIG. 12 along line BB', and FIG. 15 illustrates a schematic cross-sectional view of the semiconductor structure shown in FIG. 12 along line BB'.

Referring to FIGS. 12-15 , a plurality of gate line slits extending in the X direction may be formed vertically through the stack structure, and at the boundaries of the respective finger storage regions 504 and the respective wall structure regions 506 of the plurality of block storage regions 502 508. Gate line gaps 508 (also referred to as second spacer structures) formed between the wall structure region 506 and the adjacent block storage regions 502 in contact with each other, may extend through the array region 503 and the middle region 501, and thus may Two adjacent block storage areas 502 are electrically separated. For example, referring to Figure 12, the second block formed in The gate line gap 508 between the storage area 5022 and the third storage area 5023 may extend through the entire stack structure along the X direction.

Gate line gaps 508 (also referred to as first separation structures) formed between the plurality of finger storage regions 504 and adjacent block storage regions 502 in contact with each other may be confined in the two array regions 503 . That is, at each side of the middle region 501, the gate line gaps 508 formed between the plurality of finger storage regions 504 and the two block storage regions 502 in contact with each other may be connected to the corresponding first isolation structures 516 , and thus, gate line slits 508 (eg, first separation structures) may not extend into intermediate region 501 . For example, referring to FIG. 12, between the first block storage area 5021 and the second block storage area 5022, or between the third block storage area 5023 and the fourth block storage area 5024, each gate line gap 508 may only be in the middle The array region 503 at one side of the region 501 is formed in and may be connected to (or terminated by) a first isolation structure 516 formed at the same side of the middle region 501 .

In addition, within each block storage area 502 (including the first block storage area 5021, the second block storage area 5022, the third block storage area 5023, and the fourth block storage area 5024), the adjacent finger storage area 504 A gate line gap 508 is formed therebetween, or between the wall structure region 506 and the adjacent finger storage region 504 . For example, each gate line gap 508 formed between the wall structure region 506 and the adjacent finger storage region 504 may also be referred to as a third separation structure, while each gate line gap 508 formed between the adjacent finger storage regions 504 The gate line slot 508 may also be referred to as a fourth separation structure. It should be noted that in each block storage area 502, the gate line gap 508 formed in the middle area 501 may not be exactly located between the adjacent finger storage areas 504, or between the wall structure area 506 and the adjacent finger storage areas at the boundary between zones 504. Additionally, the gate line slits 508 may be formed that do not extend into the first bundle structure 518 in the X direction. For example, the gate line slits 508 may be formed at the edges of the sub-staircase structure 520, and the length of the gate line slits 508 may be smaller than the width of the sub-staircase structure 520 in the X direction. Similarly, sub-levels between adjacent finger storage areas 504 may be Gate line slits 508 are formed in the ladder structure 520 , and the length of the gate line slits 508 may be smaller than the width of the sub-staircase structure 520 in the X direction. It should also be noted that within each block storage area 502, gate line slits 508 formed in the array area 503 may extend through the entire array area 503 in the X direction.

12-13, along the line D-D' in the array region 503 close to the middle region 501, a through-stack structure may be formed at the boundary between the wall structure region 506 and the adjacent block storage regions 502 in contact with each other gate line slot 508. 12 and 14, the CC' line parallel to the Y direction and truncating the sub-staircase structure 520 in the cross-sectional direction, except that it is formed at the boundary between the wall structure region 506 and the two block storage regions 502 in contact with each other In addition to the gate line slits 508 , gate line slits 508 may also be formed in each block storage area 502 to separate the plurality of finger storage areas 504 and the wall structure areas 506 . It should be noted that, in the middle region 501, the gate line gap 508 may not be formed at the boundary between the plurality of finger storage regions 504 and the adjacent block storage regions 502 that are in contact with each other. Referring to FIGS. 12 and 15 , along the BB′ line parallel to the Y direction and cutting the first bundle structure 518 between adjacent sub-staircase structures 520 in the cross-sectional direction, the adjacent sub-staircase structures 506 may be in contact with each other in the wall structure region 506 . At the boundaries between the block storage regions 502, gate line gaps 508 are formed through the stacked structure.

The plurality of gate line slits 508 may serve as a reference for replacing the plurality of second dielectric layers 522 in the array region 503 and the stepped structure during subsequent processing. In one embodiment, gate line slits 508 may be formed in only two array regions 503 at the boundaries between the plurality of finger storage regions 504 and adjacent block storage regions 502 in contact with each other (refer to FIG. 12 and FIG. 14). In addition, in a subsequent process, when the plurality of second dielectric layers 522 are removed from the array region 503 , the first isolation structures 516 formed at both sides of the middle region 501 may be the second dielectric layers in the middle region 501 . A central portion of electrical layer 522 provides protection. Therefore, after the second dielectric layer 522 is removed from the array region 503, the central portion of the second dielectric layer 522 (in the second bundle structure 519) may remain between the plurality of finger storage regions and the two contacts in contact with each other. In the middle area 501 between the block storage areas 502 . Therefore, the remaining center of the second dielectric layer 522 in the intermediate region 501 between the two bulk storage regions 502 In part, the necessary mechanical support and electrical isolation can be provided for the subsequently formed memory storage element. Additionally, the etch process may also remove portions of the second dielectric layer 522 that lie longitudinally below the intended word line contacts 512 .

For example, referring to FIG. 12 , from two block storage areas 502 (eg, the third block storage area 5023 and the fourth block storage area 5024 ) located in the middle area 501 and located in the plurality of finger storage areas 504 and in contact with each other Point E at the boundary between, the distance to the closest gate line slot 508 may be L1, and the distance from the location of the word line contact 512 to the closest gate line slot 508 may be L3. To ensure that the central portion of the second dielectric layer 522 in the middle region 501 remains after the portion of the second dielectric layer 522 below the intended wordline contact 512 is removed in the longitudinal direction, L1 may always be greater than L3 . That is, the shortest distance to the closest gate line gap 508 from a point located in the middle region 501 and located in the plurality of finger storage regions 504 and located at the boundary between two block storage regions 502 in contact with each other, can be Greater than the longest distance from the location of the word line contact 512 to the closest gate line slot 508 . Similarly, to ensure that after the portion of the second dielectric layer 522 in the array region 503 is removed, the central portion of the second dielectric layer 522 in the intermediate region 501 between the two bulk storage regions 502 remains, from The shortest distance to the closest gate line slot 508 from a point in the middle region 501 and located in the plurality of finger storage regions 504 and at the boundary between two block storage regions 502 that are in contact with each other may be greater than that from the point located in the array The point in region 503, the longest distance to the closest gate line slot 508.

Further, at least a portion of the second dielectric layer 522 in the first bundle structure 518 may remain after removing the portion of the second dielectric layer 522 longitudinally below the intended wordline contact 512 . Therefore, the removed portion of the second dielectric layer 522 and the plurality of first dielectric layers 521 may provide mechanical support for the material structure in the intermediate region 501 . For example, referring to FIG. 12, the distance from point F in the first bundle structure 518 to the closest gate line slot 508 may be L2, and in order to ensure that in the removal longitudinal direction it is at the intended After the word line contacts the portion of the second dielectric layer 522 under 512, at least a portion of the second dielectric layer 522 in the first bundle structure 518 remains, and the maximum value of L2 may be greater than the maximum value of L3. That is, the longest distance from a point located in the first bundle structure 518 to the closest gate line slot 508 may be longer than the longest distance from the location where the word line contact 512 to be formed to the closest gate line slot 508 long distance. Thus, by properly selecting the etch time, at least a portion of the second dielectric layer 522 in the first bundle structure 518 remains after removing the portion of the second dielectric layer 522 longitudinally below the intended word line contact 512 part. Similarly, to ensure that at least a portion of the second dielectric layer 522 in the first bundle structure 518 remains after the portion of the second dielectric layer 522 in the array region 503 is removed, from the The longest distance from a point to the closest gate line slot 508 may be longer than the longest distance from a point located in the array region 503 to the closest gate line slot 508 .

In addition, referring to FIG. 12 , in the X direction, the gate line slits 508 are formed in the respective sub-staircase structures 520 between adjacent finger storage regions 504 or between the wall structure regions 506 and the finger storage regions 504, It may be equal to or shorter than the size of the sub-staircase structure 520 . Therefore, in the X direction, the distance L0' between the gate line slits 508 may be equal to or greater than the distance L0 between the sub-staircase structures 520. That is, in the X direction, the length of each gate line slit 508 formed in the sub-staircase structure 520 may be equal to or smaller than the width of the sub-staircase structure 520 . Therefore, when the second dielectric layer 522 is removed, the second dielectric layer 522 in the first beam structure 518 may allow less portion to be removed, thus helping to preserve the first beam structure 518 after the etching process At least a portion of the second dielectric layer 522 in the .

Further, returning to FIG. 24, the plurality of second dielectric layers may be removed from the array region and partially from the intermediate region, and after removing the plurality of second dielectric layers from the array region and partially from the intermediate region, A central portion of the second dielectric layer located in the intermediate region across the plurality of finger storage regions and adjacent block storage regions in contact with each other may be retained, and the second dielectric layer located in each of the first bundle structures may also be retained at least a part of (S604). 16-19 illustrate schematic cross-sectional views of semiconductor structures consistent with various embodiments of this disclosure. Specifically, the cross-sectional view shown in FIG. 16 is developed from the cross-sectional view shown in FIG. 13 , and the cross-sectional view shown in FIG. 17 is developed from the cross-sectional view shown in FIG. 14 , and the cross-sectional views shown in FIGS. 18-19 are two examples developed from the cross-sectional view shown in FIG. 15 . It should be noted that since the second dielectric layer is initially located between adjacent first dielectric layers, after removing the second dielectric layer from the array region and partially from the intermediate region, the plan view of the semiconductor structure remains the same as that of FIG. 12 The same as the floor plan shown in . That is, FIG. 12 also provides a schematic plan view of the semiconductor structure after removing the second dielectric layer from the array region and the stepped structure.

Referring to FIGS. 12 and 16-19 , the plurality of second dielectric layers 522 may be removed from the array region 503 and partially from the intermediate region 501 . Since FIG. 16 illustrates a schematic cross-sectional view of the semiconductor structure along the line D-D' in the array region 503, the plurality of second dielectric layers 522 at the cross-sectional view are completely removed. As shown in FIG. 17, central portions of the plurality of second dielectric layers 522, which span the boundaries between the plurality of finger storage regions 504 and the two bulk storage regions 502 in contact with each other, may remain in the semiconductor structure. As shown in FIG. 18, in one embodiment, portions of the plurality of second dielectric layers 522 may remain in the first bundle structure 518, and each second dielectric layer 522 may continue to span the plurality of fingers The storage area 504 extends from the two block storage areas 502 in contact with each other. As shown in FIG. 19, in other embodiments, the remainder of each second dielectric layer 522 may include a plurality of discrete subsections, and a plurality of second dielectric layers 522 and a plurality of first dielectric layers Layer 521 can form a plurality of vertical struts that can further provide mechanical support for subsequent manufacturing processes. It should be noted that whether the remaining portion of each second dielectric layer 522 is a continuous thin film layer between the two first dielectric layers 521 or a discrete structure depends on the designed pattern of the gate line slot 508, the present invention The content merely requires that at least a portion of the second dielectric layer 522 be retained in each of the first bundle structures 518 in order to provide sufficient mechanical support for the semiconductor structures.

Further, returning to FIG. 24 , a plurality of electrode layers may be formed in the spaces between adjacent first dielectric layers ( S605 ). 20-23 illustrate schematic cross-sectional views of semiconductor structures consistent with various embodiments of this disclosure. Specifically, the cross-sectional view shown in FIG. 20 is developed from the cross-sectional view shown in FIG. 16 , and the cross-sectional view shown in FIG. 21 is developed from the cross-sectional view shown in FIG. 17 . , and the cross-sectional views shown in Figures 22 and 23 are two examples developed from the cross-sectional views shown in Figures 18 and 19, respectively. It should be noted that since the electrode layers are formed between adjacent first dielectric layers, the plan view of the semiconductor structure is still the same as that shown in FIG. 12 after the formation of the plurality of electrode layers. That is, FIG. 12 also provides a schematic plan view of the semiconductor structure after forming a plurality of electrode layers in the spaces between adjacent first dielectric layers.

Referring to FIGS. 12 and 20-23 , a plurality of electrode layers 531 may be formed in empty spaces between adjacent first dielectric layers 521 . Therefore, the plurality of second dielectric layers 522 (refer to FIG. 13 ) formed in the array region 503 may be replaced with a plurality of electrode layers 531, and a portion of the second dielectric layer 522 may be replaced with a plurality of electrode layers 531 (refer to FIG. 13 ). Figure 14-15). In one embodiment, the plurality of electrode layers 531 may be made of tungsten.

In one embodiment, for the wall structure region 506 and the two bulk storage regions 502 in contact with each other (eg, the second bulk storage region 5022 and the third bulk storage region 5023 ), gate lines formed through the stack structure can be passed through A slit 508, a part of the electrode layer 531 formed in one block storage area 502 (eg, the second block storage area 5022), and a part of the electrode layer 531 formed in the other block storage area 502 (eg, the third block storage area 5023) Another part of the electrode layer 531 is isolated. For a plurality of finger storage areas 504 and adjacent block storage areas 502 in contact with each other (eg, first block storage area 5021 and second block storage area 5022, or third block storage area 5023 and fourth block storage area 5024), A first isolation structure 516 is formed at each side of the middle region 501 , and gate line slits 508 are formed in the array region 503 and connected to the first isolation structure 516 and across the middle region of the two block storage regions 502 The remaining central portion of the second dielectric layer 522 in 501 may be formed in A part of the electrode layer 531 in one block storage area 502 (for example, the first block storage area 5021 or the third block storage area 5023 ) is different from that formed in the other block storage area 502 (for example, the second block storage area 5022 or the third block storage area 5023 ). Another part of the electrode layer 531 in the four storage regions 5024) is electrically isolated.

Further, after forming the plurality of electrode layers 531, a plurality of word line contacts 512 may be formed in the middle region 501 to electrically connect the sub-steps formed in the sub-step structure. Additionally, multiple channel structures (not shown) may be formed in the array region.

According to the disclosed method, the formed stepped structure includes a plurality of sub-staircase structures, and the adjacent sub-staircase structures are separated from each other along the length direction of the wall structure by the first bundle of structures connected to the wall structure. The first bundle structure can provide mechanical support for the wall structure, thus preventing the wall structure from collapsing when gate line slits through the wall structure are formed. In addition, for adjacent block storage regions having finger storage regions disposed between their wall structure regions, gate line gaps formed between two block storage regions are formed in the intermediate regions, respectively, in the intermediate regions. The two first isolation structures at both sides are truncated. In the middle region spanning the two bulk storage regions, the second bundle structures connect the first isolation structures formed at each side of the middle region. In the second beam structure, after removing the second dielectric layer from the array region, portions of the second dielectric layer are left between adjacent first dielectric layers. Therefore, the second dielectric layer and the first dielectric layer in the second bundle structure not only provide mechanical support for the subsequent fabrication process, but also provide electrical isolation for the two bulk storage regions. Additionally, after the second dielectric layer is removed from the array region, at least a portion of the second dielectric layer remains in each of the first bundle structures, which also provides mechanical support for subsequent fabrication processes.

The present disclosure also provides another method for forming a memory storage element. 39 illustrates a flowchart of an exemplary method for forming a memory storage element in accordance with various embodiments of this disclosure. 25-38 illustrate schematic diagrams of semiconductor structures at certain stages of the exemplary method.

Referring to FIG. 39 , a stacked structure including a plurality of first dielectric layers and a plurality of second dielectric layers alternately arranged on a substrate may be formed; in a first lateral direction with respect to the substrate, the stacked structure may include two an array area, and an intermediate area arranged between the two array areas; in a second lateral direction relative to the substrate, the stacked structure can be divided into a plurality of block storage areas, wherein each block storage area includes a plurality of finger storage areas area, and a wall structure area that separates the block storage area from an adjacent block storage area, and the adjacent block storage area may have the wall structure areas of the two block storage areas in contact with each other, or the two block storage areas. The plurality of finger storage areas of the block storage area are in contact with each other (S701).

The formation of the stacked structure on the substrate can be substantially the same as the formation of the stacked structure on the substrate described in the embodiments provided above. For the details of the formation of the stacked structure and the definition of the plurality of block storage areas, array areas and intermediate areas, Reference may be made to the corresponding descriptions in the embodiments provided above.

Further, returning to Figure 39, a first isolation structure may be formed across the stack structure at each side of the intermediate region between the two block storage regions between the wall structure regions; the two block storage regions may be The middle area of the plurality of finger storage areas forms a stepped structure from the stacked structure; along the first lateral direction, the stepped structure may include a first transverse bundle structure, and a plurality of sub-staircase structures spaced apart from each other; within each block storage region, and along the second lateral direction, the sub-staircase structure may include a single row of sub-staircases formed in finger storage regions adjacent to the wall structure region ( S702). 25-28 illustrate schematic diagrams of an exemplary semiconductor structure in accordance with various embodiments of this disclosure. Specifically, FIG. 25 illustrates a schematic plan view of the semiconductor structure, FIG. 26 illustrates a schematic cross-sectional view of the semiconductor structure shown in FIG. 25 along the line DD', and FIG. 27 illustrates a schematic view along the line CC' A schematic cross-sectional view of the semiconductor structure shown in FIG. 25 along line BB', and FIG. 28 illustrates a schematic cross-sectional view of the semiconductor structure shown in FIG. 25 along line BB'.

25-28, between a plurality of finger storage areas 504 and two block storage areas 502 in contact with each other (eg, between block storage area 5021 and block storage area 5022 and between block storage area 5023 and block storage area, respectively between regions 5024), a first isolation structure 516 may be formed at each side of the middle region 501 through the stack structure. Furthermore, a stepped structure (not labeled) may be formed from the stacked structure in the middle region 501 of the plurality of finger storage regions 504 of the two block storage regions 502 . Along the X direction, the stepped structure may include a plurality of sub-staircase structures 520, and adjacent sub-staircase structures 520 may be separated from each other by the first bundle structures 518 extending along the Y direction. The first bundle structures 518 may be connected to the wall structure regions 506 of the respective block storage regions 520 . In one embodiment, the width of each first bundle structure 518 may be L0 in the X direction.

In one embodiment, within each block storage area 502, the sub-staircase structure 520 may include a single row of sub-steps (not shown) extending in the Y direction. This single row of sub-steps may be formed in the finger storage region 504 adjacent to the wall structure region 506 . In a subsequent process, word line contacts 512 may be formed on sub-steps formed in the stepped structure. For example, word line contacts 512 may be formed in the finger storage region 504 adjacent to the wall structure region 506 to electrically connect the sub-steps formed in the finger storage region 504 . It should be noted that wordline contacts 512 may be formed in a subsequent process, and the circles in FIG. 25 and the dashed plugs in FIG. 27 are for illustrative purposes only for forming wordline contacts in subsequent processes The expected location of 512. It should also be noted that a portion of the second dielectric layer 522 longitudinally below each intended wordline contact 512 may be replaced with an electrode layer in a subsequent process in order to establish electrical properties with the corresponding wordline contact 512 connect.

25-26, along the D-D' line in the array region 503 close to the middle region 501, the first isolation structure 516 formed between the plurality of finger storage regions 504 and the block storage regions 502 in contact with each other can penetrate transparent stack structure. 25 and 27, the sub-staircase structure 520 is truncated along the direction parallel to the Y direction and in the cross-sectional direction. C-C' lines, word line contacts 512 can be formed in the finger storage region 504 adjacent to the wall structure region 506 in a subsequent process to electrically connect the corresponding steps. In addition, after the stepped structure including the plurality of sub-staircase structures 520 is formed, a wall structure (not shown) extending in the X direction may be simultaneously formed in the middle region 501 between the wall structure region 506 and the adjacent block storage regions 502 in contact with each other. mark). Therefore, the width of the wall structure in the Y direction (refer to FIG. 27 ) is approximately the total width of two adjacent wall structure regions 506 . Referring to FIGS. 25 and 28 , along the B-B' line parallel to the Y direction and cutting the first bundle structure 518 in the cross-sectional direction, the stacked structure may remain unchanged after the first isolation structure 516 and the stepped structure are formed. Therefore, the first bundle structures 518 extending in the Y direction can prevent the wall structures from having a narrow width (approximately the total of the two wall structure regions 506 ) all the way from one side of the middle region 501 to the other side of the middle region 501 . width). Therefore, the wall structure is less prone to collapse when making gate line slits that pass through the wall structure in the X direction.

For each pair of the plurality of finger storage areas 504 and the block storage areas 502 in contact with each other, the first isolation structures 516 formed at each side of the middle area 501 may be in a stepped structure between the two block storage areas 502 The central portion of the second dielectric layer 522 provides protection so that in subsequent processes, when the second dielectric layer 522 is replaced with a metal electrode layer, it is not necessary to remove the stair in the stepped structure between the two bulk storage regions 502. The central portion of the second dielectric layer 522 . The remaining central portion of the second dielectric layer 522 (which may be made of nitride) and the first dielectric layer 521 (which may be made of oxide) in the stepped structure between the two bulk storage regions 502 may Not only provides mechanical support for subsequent manufacturing processes, but also provides electrical isolation for the two bulk storage regions 502 formed in the memory storage element.

In one embodiment, the first isolation structure 516 may have a rectangular shape. The size of the first isolation structure 516 in the X direction may be larger than the size of the first isolation structure 516 in the Y direction. For example, the size of the first isolation structure 516 in the Y direction may be in the range of about 10 nm to 40 nm. The size of the first isolation structure 516 in the Y direction should not be too large, otherwise it is used to fill the corresponding gap to form the first isolation structure 516. The process of isolating structure 516 may take more time and use more material. The dimension of the first isolation structure 516 in the Y direction also cannot be too small, otherwise the first isolation structure 516 may not be able to be the second dielectric layer in the stepped structure between the two bulk storage regions 502 during the subsequent etching process The center section of the 522 provides adequate protection. In addition, the size of the first isolation structure 516 in the X direction may be greater than half of the size of the finger storage region 504 in the Y direction. In addition, the dimension of each finger storage region 504 in the Y direction may be approximately the same as the dimension of the wall structure region 506 in the Y direction. In other embodiments, the first isolation structure may have any other suitable shape.

In one embodiment, the portion of the first isolation structure 516 formed in the array region 503 may be larger than the portion of the first isolation structure 516 formed in the middle region 501 . For example, the entire first isolation structure 516 may be formed in the array region 503 with an edge overlapping the boundary between the array region 503 and the middle region 501 , or a portion of the first isolation structure 516 formed in the array region 503 , may be twice as large as the portion of the first isolation structure 516 formed in the middle region 501 . In other embodiments, the portion of the first isolation structure formed in the array region may be equal to or smaller than the portion of the first isolation structure formed in the wall structure region.

The first isolation structure 516 may be made of insulating material (eg, silicon dioxide). It should be noted that the etch rate of the material used to form the first isolation structures 516 may be less than the etch rate of the material used to form the second dielectric layer 522 when the second dielectric layer 522 is removed in a subsequent etch process.

Referring to FIG. 25 (as well as FIG. 40 ), in a stepped structure formed across a plurality of finger storage areas and adjacent block storage areas 502 in contact with each other, an area close to the boundary between the two block storage areas 502 is referred to as the second Bundle structure 519 . In a subsequent process, after partially replacing the second dielectric layer 522 in the stepped structure with an electrode layer, a part of the second dielectric layer 522 (refer to FIG. 27 ) may remain in the second bundle structure 519, In order to provide mechanical support for the material layers and to provide electrical isolation for the two bulk storage areas 502 . It should be noted that, in FIG. 25, the rectangular area connecting the first isolation structures 516 formed at each side of the intermediate area 501 is used to schematically represent the position of the second bundle structure 519, while in practical applications, in After the plurality of second dielectric layers 522 are partially removed from the intermediate region, the remaining portions of the second dielectric layers in each sub-staircase structure 520 may have a different shape from the rectangle shown in FIG. 25 . In addition, as shown in FIG. 27 , since the sub-steps are formed in the respective sub-staircase structures 520, the space between the block storage area 5021 and the block storage area 5022, or between the block storage area 5023 and the block storage area 5024 is formed. The top layer of the first dielectric layer 521 at the boundary may be lower than the top surface of the initially formed stack structure. Therefore, the top surface of the second bundle structure 519 may be lower than the top surface of the first bundle structure 518 . In the schematic top view shown in FIG. 25 , since the first bundle structures 518 and the second bundle structures 519 have different heights, the second bundle structures 519 are shown as discrete split by a plurality of first bundle structures 518 part.

Further, returning to FIG. 39 , the stack structure may be vertically penetrated, and at the boundaries of the respective finger storage regions and the respective wall structure regions of the block storage region, a plurality of gate line slits ( GLS), the respective gate line gaps formed between the plurality of finger storage areas and the adjacent block storage areas may be truncated by two first isolation structures formed at both sides of the intermediate area; and, in the block storage area Inside, the respective gate line slits formed between adjacent finger storage regions may be limited in the array region without extending into the intermediate region (S703). 29-32 illustrate schematic diagrams of an exemplary semiconductor structure in accordance with various embodiments of this disclosure. Specifically, Figure 29 illustrates a schematic plan view of the semiconductor structure, Figure 30 illustrates a schematic cross-sectional view of the semiconductor structure shown in Figure 29 along the line DD', and Figure 31 illustrates a schematic view along the line CC' A schematic cross-sectional view of the semiconductor structure shown in FIG. 29 along line BB', and FIG. 32 illustrates a schematic cross-sectional view of the semiconductor structure shown in FIG. 29 along line BB'.

Referring to Figures 29-32, the stack structure may be vertically traversed, and in multiple block storage areas 502 At the boundary between each finger storage area 504 and each wall structure area 506, a plurality of gate line slits 508 extending along the X direction are formed. The gate line gap 508 formed between the wall structure region 506 and the adjacent block storage region 502 in contact with each other can extend through the array region 503 and the intermediate region 501 and thus can electrically separate the two adjacent blocks Storage area 502 . For example, referring to FIG. 29 , the gate line gap 508 formed between the second block storage area 5022 and the third block storage area 5023 may extend through the entire stack structure in the X direction.

The gate line gaps 508 formed between the plurality of finger storage areas 504 and the adjacent block storage areas 502 in contact with each other may be limited in the two array areas 503 . That is, at each side of the middle region 501 , the gate line gaps 508 formed between the plurality of finger storage regions 504 and the two block storage regions 502 in contact with each other may be connected to the corresponding first isolation structures 516 , and thus, the gate line slit 508 may not extend into the middle region 501 . For example, referring to FIG. 29, between the first block storage area 5021 and the second block storage area 5022, or between the third block storage area 5023 and the fourth block storage area 5024, each gate line gap 508 may only be in the middle The array region 503 at one side of the region 501 is formed in and may be connected to (or terminated by) a first isolation structure 516 formed at the same side of the middle region 501 .

In addition, in the array area 503 of each block storage area 502 (including the first block storage area 5021, the second block storage area 5022, the third block storage area 5023, and the fourth block storage area 5024), adjacent fingers may be stored in the array area 503. Gate line gaps 508 are formed between the storage regions 504 and between the wall structure region 506 and the adjacent finger storage regions 504 . In the middle region 501 of each block storage region 502 , a gate line gap 508 may be formed between the wall structure region 506 and the adjacent finger storage region 504 . It should be noted that within each block storage area 502 , the gate line slits 508 formed in the intermediate area 501 may not be located exactly at the boundary between the wall structure area 506 and the adjacent finger storage area 504 . Additionally, the gate line slits 508 may be formed that do not extend into the first bundle structure 518 in the X direction. For example, the gate line slits 508 may be formed at the edges of the sub-staircase structure 520, and the length of the gate line slits 508 may be smaller than the width of the sub-staircase structure 520 in the X direction. return It should be noted that, within each block storage area 502, each gate line slot 508 formed in the array area 503 may extend through the entire array area 503 in the X direction.

29-30, along the line D-D' in the array region 503 close to the middle region 501, a through-stack structure may be formed at the boundary between the wall structure region 506 and the adjacent block storage regions 502 in contact with each other gate line slot 508. 29 and 31, the CC' line of the sub-staircase structure 520 is truncated along the direction parallel to the Y direction and in the cross-sectional direction, except for the line formed at the boundary between the wall structure region 506 and the two block storage regions 502 in contact with each other In addition to gate line slits 508 , gate line slits 508 may also be formed within each block storage region 502 to separate wall structure regions 506 from adjacent finger storage regions 504 . It should be noted that in the middle region 501 , the gate line gap 508 may not be formed at the boundary between adjacent finger storage regions 504 . Referring to FIGS. 29 and 32 , along the BB' line that cuts the first bundle structure 518 between adjacent sub-staircase structures 520 parallel to the Y direction and in the cross-sectional direction, adjacent blocks that may be in contact with each other in the wall structure region 506 Gate line gaps 508 through the stacked structure are formed at the boundaries between the storage regions 502 .

The plurality of gate line slits 508 may be used to replace the process fiducials of the plurality of second dielectric layers 522 in the array region 503 and the stepped structure during subsequent processing. In one embodiment, at the boundary between the plurality of finger storage areas 504 and the adjacent block storage areas 502 in contact with each other, gate line slits 508 may be formed in only two array areas 503 (refer to FIG. 29 and FIG. 31). In addition, when the plurality of second dielectric layers 522 are removed from the array region 503 in a subsequent process, the first isolation structures 516 formed at both sides of the middle region 501 may be between the two block storage regions 502 The central portion of the second dielectric layer 522 in the border adjacent to the middle region 501 provides protection. Therefore, after the second dielectric layer 522 is removed from the array region 503, the central portion of the second dielectric layer 522 (in the second bundle structure 519) may remain between the plurality of finger storage regions and the two contacts in contact with each other. In the middle area 501 between the block storage areas 502 . Therefore, the remaining central portion of the second dielectric layer 522 in the intermediate region 501 between the two bulk storage regions 502 may be a subsequently formed memory storage element Provide the necessary mechanical support and electrical isolation. In addition, the etching process may also be capable of removing the portion of the second dielectric layer 522 in the finger storage region 504 adjacent to the wall structure region 506 that is longitudinally below the predetermined word line contact 512 .

For example, referring to FIG. 29 , from between two block storage areas 502 (eg, the third block storage area 5023 and the fourth block storage area 5024 ) located in the middle area 501 and located in the plurality of finger storage areas 504 and located in contact with each other At point E at the boundary between the two, the distance to the closest gate line slot 508 may be L1, and the distance from the location where the word line contact 512 to be formed to the closest gate line slot 508 may be L3 . In order to ensure that after removing the portion of the second dielectric layer 522 located longitudinally below the predetermined word line contact 512, the second dielectric layer 522 in the intermediate region 501 between the two block storage regions 502 remains. In the central part, L1 can always be larger than L3. That is, the shortest distance to the closest gate line gap 508 from a point located in the middle region 501 and located in the plurality of finger storage regions 504 and located at the boundary between two block storage regions 502 in contact with each other, can be Greater than the longest distance from the location of the word line contact 512 to be formed to the closest gate line slot 508 . Similarly, to ensure that after the portion of the second dielectric layer 522 in the array region 503 is removed, the central portion of the second dielectric layer 522 in the intermediate region 501 between the two bulk storage regions 502 remains, from The shortest distance to the closest gate line slot 508 from a point in the middle region 501 and located in the plurality of finger storage regions 504 and at the boundary between two block storage regions 502 that are in contact with each other may be greater than that from the point located in the array The longest distance from a point in region 503 to the closest gate line slot 508.

Further, at least a portion of the second dielectric layer 522 in the first bundle structure 518 may remain after removing the portion of the second dielectric layer 522 longitudinally below the intended wordline contact 512 . Accordingly, the removed portion of the second dielectric layer 522 and the plurality of first dielectric layers 521 may provide mechanical support for the material structure in the intermediate region 501 . For example, referring to FIG. 29, the distance from point F in the first bundle structure 518 to the closest gate line slot 508 may be L2, and in order to ensure that in the removal longitudinal direction the desired word is located After the element line contacts the portion of the second dielectric layer 522 under 512, at least a portion of the second dielectric layer 522 in the first bundle structure 518 remains, and the maximum value of L2 may be greater than the maximum value of L3. That is, the longest distance from a point located in the first bundle structure 518 to the closest gate line slot 508 may be longer than the longest distance from the location where the word line contact 512 is formed to the closest gate line slot 508 . Thus, by properly choosing the etch time, after removing the portion of the second dielectric layer 522 longitudinally below the intended word line contact 512, the second dielectric layer 522 in the first bundle structure 518 is preserved at least part of it. Similarly, to ensure that at least a portion of the second dielectric layer 522 in the first bundle structure 518 remains after the portion of the second dielectric layer 522 in the array region 503 is removed, from a point located in the first bundle structure 518 The longest distance to the closest gate line slot 508 may be longer than the longest distance from a point located in the array region 503 to the closest gate line slot 508 .

Since the gate line gaps 508 may not be formed between adjacent finger storage areas 504 in the middle areas 501 of the respective block storage areas 502, during the subsequent process of removing the plurality of second dielectric layers 522, the gate line gaps 508 may not be formed. Removing a larger portion of the second dielectric layer 522 in the stepped structure, and the remaining portion of the second dielectric layer 522 , and the plurality of first dielectric layers 521 , may provide mechanical support for the material structure in the intermediate region 501 .

Further, returning to FIG. 39, the plurality of second dielectric layers may be removed from the array region and partially from the intermediate region, and after removing the plurality of second dielectric layers from the array region and partially from the stepped structure, A central portion of the second dielectric layer in the second bundle structure may be retained, and at least a portion of the second dielectric layer in each of the first bundle structures may also be retained (S704). 33-35 illustrate schematic cross-sectional views of semiconductor structures consistent with various embodiments of this disclosure. Specifically, the cross-sectional view shown in FIG. 33 is developed from the cross-sectional view shown in FIG. 30 , and the cross-sectional view shown in FIG. 34 is developed from the cross-sectional view shown in FIG. 31 . , and the cross-sectional view shown in Figure 35 is from Figure 32 The cross-sectional diagram shown is developed. It should be noted that since the second dielectric layer is initially located between adjacent first dielectric layers, after the second dielectric layer is removed from the array region and partially from the intermediate region, the plan view of the semiconductor structure remains the same as in FIG. 29 The same as the floor plan shown in . That is, FIG. 29 also provides a schematic plan view of the semiconductor structure after removing the second dielectric layer from the array region and partially from the stepped structure.

Referring to FIGS. 29 and 33-35 , the plurality of second dielectric layers 522 may be removed from the array region 503 and partially from the intermediate region 501 . Since FIG. 33 illustrates a schematic cross-sectional view of the semiconductor structure along the line D-D' in the array region 503, the plurality of second dielectric layers 522 at the cross-sectional view are completely removed. As shown in FIG. 34, central portions of the plurality of second dielectric layers 522 that span the boundaries between the plurality of finger storage regions 504 and the two bulk storage regions 502 in contact with each other may remain in the semiconductor structure. As shown in FIG. 35 , portions of the plurality of second dielectric layers 522 may remain in the first bundle structure 518 and the respective second dielectric layers 522 may continue to contact each other across the plurality of finger storage regions 504 The two block storage areas 502 extend.

Further, returning to FIG. 39 , a plurality of electrode layers may be formed in the spaces between adjacent first dielectric layers ( S705 ). 36-38 illustrate schematic cross-sectional views of semiconductor structures consistent with various embodiments of this disclosure. Specifically, the cross-sectional view shown in FIG. 36 is developed from the cross-sectional view shown in FIG. 33 , and the cross-sectional view shown in FIG. 37 is developed from the cross-sectional view shown in FIG. 34 , and the cross-sectional view shown in FIG. 38 is developed from the cross-sectional view shown in FIG. 35 . It should be noted that since the electrode layers are formed between adjacent first dielectric layers, the plan view of the semiconductor structure remains the same as that shown in FIG. 29 after the formation of the plurality of electrode layers. That is, FIG. 29 also provides a schematic plan view of the semiconductor structure after forming a plurality of electrode layers in empty spaces between adjacent first dielectric layers.

Referring to FIGS. 29 and 36-38 , a plurality of electrode layers 531 may be formed in empty spaces between adjacent first dielectric layers 521 . Therefore, the plurality of second dielectric layers 522 formed in the array region 503 may be replaced with a plurality of electrode layers 531 (refer to FIG. 30 ), and a portion of the second dielectric layer 522 may be replaced with a plurality of electrode layers 531 (refer to FIG. 30 ). Figure 31-32). In one embodiment, the plurality of electrode layers 531 may be made of tungsten.

In one embodiment, for the two bulk storage regions 502 (eg, the second bulk storage region 5022 and the third bulk storage region 5023 ) that bring the wall structure region 506 into contact with each other, gates formed through the stack structure may be passed through The line slit 508 connects a portion of the electrode layer 531 formed in one block storage area 502 (eg, the second block storage area 5022 ) with the electrode layer 531 formed in the other block storage area 502 (eg, the third block storage area 5023 ) Another portion of the electrode layer 531 is isolated. For a plurality of finger storage areas 504 and adjacent block storage areas 502 in contact with each other (eg, first block storage area 5021 and second block storage area 5022, or third block storage area 5023 and fourth block storage area 5024), A first isolation structure 516 is formed at each side of the middle region 501 , and gate line slits 508 are formed in the array region 503 and connected to the first isolation structure 516 and across the middle region of the two block storage regions 502 The remaining central portion of the second dielectric layer 522 in 501 may be formed by combining a portion of the electrode layer 531 formed in one block storage area 502 (eg, the first block storage area 5021 or the third block storage area 5023 ) with the Another portion of the electrode layer 531 in another bulk storage region 502 (eg, the second bulk storage region 5022 or the fourth bulk storage region 5024) is electrically isolated.

Further, after forming the plurality of electrode layers 531 , a plurality of word line contacts 512 may be formed in the middle region 501 to electrically connect the steps formed in the finger storage region 504 adjacent to the wall structure region 506 . Additionally, multiple channel structures (not shown) may be formed in the array region.

According to the disclosed method, the formed stepped structure includes a plurality of sub-staircase structures, and along the length direction of the wall structure, adjacent sub-staircase structures are connected to each other through the first bundle of structures connected to the wall structure. This is separated. The first bundle structure can provide mechanical support for the wall structure, thus preventing the wall structure from collapsing when gate line slits through the wall structure are formed. In addition, for adjacent block storage regions having finger storage regions disposed between their wall structure regions, gate line gaps formed between two block storage regions are formed in the intermediate regions, respectively, in two of the intermediate regions. The two first isolation structures at the sides are truncated. In the middle region spanning the two bulk storage regions, the second bundle structures connect the first isolation structures formed at each side of the middle region. In the second beam structure, after removing the second dielectric layer from the array region, portions of the second dielectric layer are left between adjacent first dielectric layers. Therefore, the second dielectric layer and the first dielectric layer in the second bundle structure not only provide mechanical support for the subsequent fabrication process, but also provide electrical isolation for the two bulk storage regions. Additionally, after the second dielectric layer is removed from the array region, at least a portion of the second dielectric layer remains in each of the first bundle structures, which also provides mechanical support for subsequent fabrication processes.

The present disclosure also provides another method for forming a memory storage element. 40 illustrates a schematic top view of a semiconductor structure fabricated by an exemplary method in accordance with various embodiments of this disclosure. Compared with the semiconductor structure formed by the method described in the above embodiments, the method for forming the semiconductor structure shown in FIG. 40 may not include the first formation at each side of the intermediate region 501 in the Y direction Isolated structure. Instead, when the plurality of gate line slits 508 are formed, the gate line slits 508 (also referred to as first separation structures) formed may be located in the array region 503 . After further replacing the plurality of second dielectric layers with the plurality of electrode layers, since the plurality of electrode layers are inevitably formed at the boundary between the two bulk storage regions in the regions near the ends of the respective first separation structures, So the method may further include: extending each of the first separation structures in the X direction to completely remove the plurality of electrode layers formed at the boundary between the two bulk storage regions. Therefore, electrical isolation between two adjacent block storage areas can be achieved. In one embodiment, the first separation structure (eg, gate line gaps 508 formed between the plurality of finger storage regions 504 and adjacent block storage regions 502 in contact with each other) may be separated from the middle region 501 through a dry etching process. extension so that much of the an electrode layer.

The present disclosure also provides another method for forming a semiconductor structure. 41 illustrates a schematic top view of a semiconductor structure fabricated by an exemplary method in accordance with various embodiments of this disclosure. Compared to the semiconductor structure formed by the method described in the above embodiments, the method for forming the semiconductor structure shown in FIG. 41 may include adjacent blocks in contact with each other in the plurality of finger storage regions 504 in the Y direction. A plurality of discrete second isolation structures 530 are formed at the boundaries between the storage regions 502 . The plurality of second isolation structures 530 may be formed along with the first isolation structures 516 and thus may be made of the same material as the first isolation structures 516 . For example, when the first isolation structures 516 are formed at each side of the intermediate region 501 and between two adjacent block storage regions 502, the A plurality of discrete second isolation structures 530 are formed in the middle region 501 . Further, portions of the second dielectric layer 522 may remain in the stepped region 501 after removing the plurality of second dielectric layers. In the X-direction, the remainder of the second dielectric layer may connect adjacent second isolation structures 530 and also connect each of the first isolation structures 516 to the second isolation structures 530 . Thus, the gate line gap 508 (eg, the first spacer structure), the plurality of first isolation structures 516, the plurality of second isolation structures 530, and the remainder of the second dielectric layer can be stored together for two adjacent blocks Region 502 provides electrical isolation.

The present disclosure also provides a memory storage device. 12 and 20-23 illustrate schematic diagrams of an exemplary memory storage element consistent with various embodiments of this disclosure. Specifically, Figure 12 illustrates a schematic plan view of an exemplary memory storage element, Figure 20 illustrates a schematic cross-sectional view of the memory storage element along the line DD', and Figure 21 illustrates a schematic cross-sectional view of the memory storage element along the line CC' Schematic cross-sectional views of memory storage elements of line, and FIGS. 22-23 illustrate two schematic examples of cross-sectional views of memory storage elements along line BB'.

12 and 20-23, X, Y, and Z are used to illustrate the spatial relationship of elements in a memory storage element. The memory storage element may include a substrate 550 and a stacked structure formed on the substrate 550 . In a first lateral direction (X direction) with respect to the substrate 550 , the memory storage element may include two array regions 503 and an intermediate region 501 arranged between the two array regions 503 . In a second lateral direction (Y direction) with respect to the substrate 550 , the memory storage element may be divided into a plurality of block storage areas 502 . Further, in the Y direction, each block storage area 502 may include a plurality of finger storage areas 504 and a wall structure area 506 .

Further, adjacent block storage areas 502 of the plurality of block storage areas 502 may have the wall structure areas 506 of the two block storage areas 502 in contact with each other, or the plurality of finger storage areas 504 of the two block storage areas 502 may be in contact with each other. touch each other. For example, in the Y direction, the plurality of block storage areas 502 may include a block storage area 5021, a block storage area 5022, a block storage area 5023, and a block storage area 5024 that are sequentially arranged in the Y direction. The block store 5021 and the block store 5022 can be connected to each other using the multiple finger stores 504 of the block store 5021 adjacent to the multiple finger stores 504 of the block store 5022, and the block store 5023 can be connected to each other using the multiple fingers of the block store 5021. Wall structure area 506 of block storage area 5022 adjacent to wall structure area 506 connects block storage area 5022 and block storage area 5023 to each other, and blocks adjacent to the plurality of finger storage areas 504 of block storage area 5024 may be utilized The plurality of finger storage areas 504 of the storage area 5023 connect the block storage area 5023 and the block storage area 5024 to each other. It should be noted that, for illustration, four block storage areas 502 (block storage area 5021, block storage area 5022, block storage area 5023, and block storage area 5024) are shown in FIG. 12, while in practical application, the semiconductor structure At least two of the plurality of finger storage areas and the block storage areas in contact with each other may be included. It should also be noted that only the portion of each array region 503 adjacent to the middle region 501 is shown in FIG. 12 .

The stacked structure may include a plurality of first dielectric layers 521 and a plurality of electrode layers 531 . A plurality of first dielectric layers 521 and a plurality of electrode layers 531 may be alternately stacked on the substrate 550 . In one embodiment, Substrate 550 may be made of silicon, germanium, silicon germanium, or any other suitable semiconductor material. In other embodiments, the substrate may be made of SOI, GOI, or any other suitable semiconductor composite material. In one embodiment, the plurality of first dielectric layers 521 may be made of oxide (eg, silicon dioxide), and the plurality of electrode layers 531 may be made of conductive material (eg, tungsten).

In the intermediate region 501, the stacked structure may include a wall structure (not labeled) formed by the wall structure regions 506 of the adjacent block storage regions 502 that bring the wall structure regions 506 into contact with each other.

Further, the memory storage element may include a first isolation structure 516 formed through the stack structure at each side of the intermediate region 501 between the plurality of finger storage regions 504 and adjacent block storage regions 502 in contact with each other.

In one embodiment, the first isolation structure 516 may have a rectangular shape and may be made of an insulating material (eg, silicon dioxide). The size of the first isolation structure 516 in the X direction may be larger than the size of the first isolation structure 516 in the Y direction. For example, the size of the first isolation structure 516 in the Y direction may be in the range of about 10 nm to 40 nm. In addition, the size of the first isolation structure 516 in the X direction may be greater than half of the size of the finger storage region 504 in the Y direction. In other embodiments, the first isolation structure may have any other suitable shape.

In one embodiment, the portion of the first isolation structure 516 formed in the array region 503 may be larger than the portion of the first isolation structure 516 formed in the middle region 501 . For example, the entire first isolation structure 516 may be formed in the array region 503 with an edge overlapping the boundary between the array region 503 and the intermediate region 501, or a portion of the first isolation structure 516 formed in the array region 503 may be twice as large as the portion of the first isolation structure 516 formed in the intermediate region 501 . In other embodiments, formed in the array region The portion of the first isolation structure in the wall structure region may be equal to or smaller than the portion of the first isolation structure formed in the wall structure region.

Further, in the intermediate region 501, the stacked structure may further include a stepped structure (not labeled) formed in the plurality of finger storage regions 504 of the plurality of finger storage regions 504 and the adjacent block storage regions 502 in contact with each other. Along the X direction, the stepped structure may include a plurality of sub-staircase structures 520, and adjacent sub-staircase structures 520 may be separated from each other by the first bundle structure 518 extending along the Y direction. In the Y direction, the first bundle structures 518 may be connected to the wall structure regions 506 of the respective block storage regions 502 . In one embodiment, in the X direction, the width of each first bundle structure 518 may be L0, and within each block storage area 502, the sub-staircase structure 520 may include a plurality of rows of sub-steps (not shown) extending in the Y direction out). Each sub-step may include a plurality of pairs of the first dielectric layer 521 and the electrode layer 531 .

Additionally, at least a portion of each first bundle structure 518 may include a stacked structure formed of a plurality of first dielectric layers 521 alternating with a plurality of second dielectric layers 522 . That is, in each of the first bundle structures 518 , the second dielectric layer 522 and the electrode layer 531 may be connected to each other and located between the same pair of the first dielectric layers 521 . The plurality of second dielectric layers 522 may be made of nitride (eg, silicon nitride). In one embodiment, referring to FIG. 22, in the Y direction, each second dielectric layer 522 may continue to extend across the plurality of finger storage areas 504 and the two block storage areas 502 in contact with each other. In other embodiments, referring to FIG. 23 , along the Y direction, each second dielectric layer 522 may include a plurality of discrete subsections, and a plurality of second dielectric layers 522 may be formed along with a plurality of first dielectric layers 521 A plurality of vertical struts may further provide mechanical support for the memory storage element.

Further, in the intermediate region 501, the memory storage element may include a second bundle structure 519 located at adjacent block storage regions 502 across the plurality of finger storage regions 504 in contact with each other. Second bundle structure 519 may connect the first isolation structure 516 at one side of the middle region 501 to another first isolation structure 516 at the other side of the middle region 501 . Furthermore, in the second bundle structure 519 , the memory storage element may also include a plurality of second dielectric layers 522 alternating with the plurality of first dielectric layers 521 . It should be noted that the boundaries between the plurality of finger storage regions 504 and the adjacent block storage regions 502 in contact with each other may be in a stepped structure, and the top layers of the plurality of second dielectric layers 522 may be lower than the plurality of electrodes in the wall structure The top layer of layer 531. A plurality of second dielectric layers 522 may be connected to the first isolation structures 516 formed at each side of the middle region 501 .

The memory storage element may further include a plurality of gate line slits 508 formed vertically through the stack structure and extending in the X direction. The plurality of gate line slits 508 may include gate line slits 508 formed between the wall structure regions 506 and adjacent block storage regions 502 in contact with each other. Gate line gaps 508 formed between the wall structure regions 506 and adjacent block storage regions 502 in contact with each other may extend through the two array regions 503 and the intermediate region 501 to electrically separate the two adjacent block storage regions 502 separated.

The plurality of gate line slits 508 may further include gate line slits 508 formed between the plurality of finger storage regions 504 and adjacent block storage regions 502 in contact with each other. Gate line slits 508 each formed between the plurality of finger storage areas 504 and adjacent block storage areas 502 in contact with each other may be confined in the array area 503 and may be connected to the same side of the intermediate area 501. The corresponding first isolation structure. In one embodiment, a first isolation structure 516 formed at each side of the middle region 501, a gate line slot 508 formed in the array region 503 and connected to the first isolation structure 516, and storage across two blocks The plurality of first dielectric layers 521 and the plurality of second dielectric layers 522 in the middle region 501 of the region 502 may electrically isolate the plurality of finger storage regions 504 from adjacent block storage regions 502 in contact with each other.

Within each block storage area 502, the plurality of gate line slits 508 may further include forming adjacent between the finger storage regions 504 and gate line gaps 508 formed between the wall structure region 506 and the adjacent finger storage regions 504 . It should be noted that within each block storage area 502 , the gate line gap 508 formed in the intermediate area 501 may not be exactly located between adjacent finger storage areas 504 or between the wall structure area 506 and the adjacent finger storage area 504 In addition, the gate line slot 508 formed may not extend into the first bundle structure 518 in the X direction. It should also be noted that within each block storage area 502, each gate line slot 508 formed in the array area 503 may extend through the entire array area 503 in the X direction.

Further, referring to FIG. 12 , from the two block storage areas 502 (eg, the third block storage area 5023 and the fourth block storage area 5024 ) located in the middle area 501 and located in the plurality of finger storage areas 504 and in contact with each other The distance from point E at the boundary between to the closest gate line slot 508 may be L1, while the distance from the location where the word line contact 512 will be formed to the closest gate line slot 508 may be L3 . In one embodiment, L1 may always be greater than L3. That is, the shortest distance from a point located in the middle region 501 and located in the plurality of finger storage regions 504 and located at the boundary between two block storage regions 502 in contact with each other to the closest gate line slit 508 may be greater than from a point The longest distance from the location of the word line contact 512 to be formed to the closest gate line slot 508 . Similarly, the shortest distance from a point located in the middle region 501 and located in the plurality of finger storage regions 504 and at the boundary between two block storage regions 502 that are in contact with each other to the closest gate line gap 508 may be greater than The longest distance from a point located in the array region 503 to the closest gate line slot 508 .

Further, referring to FIG. 12, the distance from point F in the first bundle structure 518 to the closest gate line slot 508 may be L2. In one embodiment, the maximum value of L2 may be greater than the maximum value of L3. That is, the longest distance from a point located in the first bundle structure 518 to the closest gate line slot 508 may be longer than the longest distance from the location where the word line contact 512 to be formed to the closest gate line slot 508 long. Thus, by properly choosing the etch time, the intended word line contact 512 is located in the removal longitudinal direction At least a portion of the second dielectric layer 522 in the first bundle structure 518 remains after the portion of the second dielectric layer 522 below. Similarly, to ensure that at least a portion of the second dielectric layer 522 in the first bundle structure 518 remains after the portion of the second dielectric layer 522 in the array region 503 is removed, from a point located in the first bundle structure 518 The longest distance to the closest gate line slot 508 may be longer than the longest distance from a point located in the array region 503 to the closest gate line slot 508 .

In one embodiment, referring to FIG. 12 , in the X direction, gates are formed in respective sub-staircase structures 520 between adjacent finger storage regions 504 , or between the wall structure regions 506 and the finger storage regions 504 . The line slot 508 may be equal to or shorter than the size of the sub-staircase structure 520 . Therefore, in the X direction, the distance L0' between the gate line slits 508 may be equal to or greater than the distance L0 between the sub-staircase structures 520. That is, the length of each gate line slit 508 formed in the sub-staircase structure 520 may be equal to or smaller than the width of the sub-staircase structure 520 in the X direction.

Further, the memory storage element may include a plurality of word line contacts 512 formed in the middle region 501 for electrically connecting the rows of sub-steps. For example, word line contacts 512 may be formed in each finger storage area 504 to electrically connect the sub-steps formed in the finger storage area 504 .

According to the disclosed memory storage element, the formed stepped structure includes a plurality of sub-staircase structures, and along the length direction of the wall structure, adjacent sub-staircase structures are separated from each other by the first bundle structure connected to the wall structure. The first bundle structure may provide mechanical support for the wall structure, thus preventing the wall structure from collapsing when forming gate line gaps through the wall structure. In addition, for the adjacent block storage regions in which the finger storage regions are arranged between the wall structure regions thereof, gate line gaps formed between the two block storage regions are respectively formed on both sides of the intermediate region in the intermediate region The two first isolation structures at the truncation. In the middle region spanning the two bulk storage regions, the second bundle structures connect the first isolation structures formed at each side of the middle region. in the In the two-beam configuration, after the second dielectric layer is removed from the array region, portions of the second dielectric layer are left between adjacent first dielectric layers. Therefore, the second dielectric layer and the first dielectric layer in the second bundle structure not only provide mechanical support for the subsequent fabrication process, but also provide electrical isolation for the two bulk storage regions. Additionally, after the second dielectric layer is removed from the array region, at least a portion of the second dielectric layer remains in each of the first bundle structures, which also provides mechanical support for subsequent fabrication processes.

The present disclosure also provides another memory storage device. 29 and 36-38 illustrate schematic diagrams of an exemplary memory storage element consistent with various embodiments of this disclosure. Specifically, Figure 29 illustrates a schematic plan view of an exemplary memory storage element, Figure 36 illustrates a schematic cross-sectional view of the memory storage element along the line DD', and Figure 37 illustrates a schematic cross-sectional view of the memory storage element along the line CC' A schematic cross-sectional view of a memory storage element of line, and FIG. 38 illustrates a schematic cross-sectional view of a memory storage element along line BB'.

Referring to 29 and Figures 36-39, the memory storage elements are substantially the same as those described in the embodiments provided above. The following description will focus on the differences between these memory storage elements, and similar elements will not be described again herein. For details of similar elements, reference may be made to the corresponding descriptions in the embodiments provided above.

Referring to FIG. 29, within each block storage area 502 of the memory storage element, the sub-staircase structure 520 may include a single row of sub-stairs (not shown) extending in the Y direction. This single row of sub-steps may be formed in the finger storage region 504 adjacent to the wall structure region 506 . Each sub-step may include a plurality of pairs of the first dielectric layer 521 and the electrode layer 531 . Accordingly, word line contacts 512 may be formed in finger storage regions 504 adjacent to wall structure regions 506 . In addition, in the middle region 501 of each block storage region 502 , the gate line gap 508 may be formed only between the wall structure region 506 and the adjacent finger storage region 504 . Referring to Figures 37-38, in the non-intermediate zone 501 In the case where gate line gaps 508 are formed between adjacent finger storage regions 504 , the plurality of second dielectric layers 522 located in the middle region 501 spanning the plurality of finger storage regions and the adjacent block storage regions 502 in contact with each other The plurality of second dielectric layers 522 in the first bundle structure 518 may also be continuous and thus may have larger dimensions in the Y direction.

According to the manufacturing method of the memory storage element, the plurality of second dielectric layers 522 may initially occupy spaces between adjacent first dielectric layers 521 . Further, portions of the second dielectric layer 522 may be removed, and then a plurality of electrode layers 531 may be formed to fill the spaces created by removing the second dielectric layer 522 . Furthermore, since the etching process for removing the portion of the second dielectric layer 522 may be an isotropic wet etching process, and etching may be initiated from the plurality of gate line slits 508 . Therefore, by patterning the plurality of gate line slits 508 and selecting the etching time appropriately, the portion of the second dielectric layer 522 that remains after the etching process can be controllable. In one embodiment, since the sub-step structures 520 in each block storage area 502 may only include a single row of sub-steps formed in the finger storage area 504 adjacent to the wall structure area 506, it may not be necessary to remove the The portion of the second dielectric layer 522 in the middle region 501 of the storage region 504 that is not in contact with the wall structure region 506 is referred to. Therefore, it may not be necessary to form gate line gaps 508 between adjacent finger storage regions 504 in the intermediate region 501 . Therefore, the plurality of second dielectric layers located in the intermediate regions 501 of the adjacent block storage regions 502 that span the plurality of finger storage regions and contact each other may be wider in the Y direction, and the plurality of second dielectric layers located in the first bundle structure 518 The plurality of second dielectric layers 522 may not be disconnected in the Y direction.

In some of the embodiments of the present invention, there is provided a memory storage element including a substrate, a stack structure including a plurality of first dielectric layers and a plurality of electrode layers alternately arranged on the substrate, wherein In a first lateral direction relative to the substrate, the memory storage element includes an array region and an intermediate region disposed between the array regions, and in a second lateral direction relative to the substrate direction, the stacked structure includes a first block of storage areas each including a wall structure area and A second block storage area, wherein, in the middle area, the first block storage area and the wall structure area of the second block storage area are separated by a stepped structure, a bundle structure, which located in the intermediate region, wherein the bundle structure includes at least a plurality of discrete first bundle structures, wherein each first bundle structure includes a respective extension in the second lateral direction and connects the first block storage area and the the wall structure region of the second bulk storage region, and a plurality of second dielectric layers in the bundle structure, wherein, in the plurality of discrete first bundle structures, the plurality of The second dielectric layers alternate with the plurality of first dielectric layers.

In some of the embodiments of the present invention, the bundle structure further comprises a second bundle structure arranged to span the first storage block and the second storage block, and in The first lateral direction extends through the intermediate region, wherein the plurality of second dielectric layers alternate with the plurality of first dielectric layers in the second bundle structure.

In some of the embodiments of the present invention, further comprising: at least one first isolation structure vertically passing through the stack structure on each side of the intermediate region along the first lateral direction, and along the second lateral direction, formed between the first block storage area and the second block storage area, wherein the first isolation structure is made of silicon dioxide.

In some of the embodiments of the present invention, along the first lateral direction, the stepped structure includes a plurality of sub-staircase structures, wherein adjacent sub-staircase structures are separated by one of the plurality of discrete first bundle structures The first bundle structures are spaced apart.

In some of the embodiments of the present invention, it further comprises: a first separation structure formed vertically through the stacked structure and located along the first lateral direction, the first blocks in the respective array regions between the storage area and the second storage area, wherein the first storage area includes and a first edge opposite to the second block storage area, and the second block storage area includes a second edge opposite to the first block storage area, and a second partition structure is formed on the first block storage area on each of the edge and the second edge, and extending through the array region and the stepped region.

In some of the embodiments of the present invention, each of the first block storage area and the second block storage area further comprises: a plurality of finger storage areas extending along the first lateral direction, wherein: In the second lateral direction, the plurality of finger storage areas of the first block of storage areas and the plurality of finger storage areas of the second block of storage areas are alternately arranged, and the memory element Also included: a plurality of third partition structures formed in each of the first block storage areas and each of the second block storage areas and located between the wall structure area and an adjacent finger storage area, wherein: In each of the array areas of the first block storage area or the second block storage area, the third partition structure extends through the array area, and in the first block storage area or the second block storage area In the middle area of the block storage area, the third partition structure is arranged near the edge of each of the sub-step structures of the wall structure area, wherein a length of the third partition structure is shorter than or is equal to a width of the sub-staircase structure.

In some embodiments of the present invention, in the first block storage area or the second block storage area, each sub-staircase structure is formed in the finger storage area adjacent to the wall structure area and the memory storage element further includes: a plurality of word lines formed in the finger storage area adjacent to the wall structure area and used for electrically connecting the plurality of steps touch.

In some of the embodiments of the present invention, further comprising: a plurality of fourth partitions formed in each of the first block storage areas and each of the second block storage areas and located between adjacent finger storage areas structure, wherein: in each of the array areas of the first block storage area or the second block storage area, the fourth separation structure extends through the array area, and in the first block storage area storage area or the In the middle area of the two storage areas, and between the adjacent finger storage areas, the fourth partition structure is arranged in each of the sub-staircase structures, wherein the fourth partition structure is A length is shorter than or equal to a width of the sub-staircase structure.

In some embodiments of the present invention, in the first block storage area or the second block storage area, each of the sub-ladder structures includes each finger storage area formed in the plurality of finger storage areas A plurality of steps in the plurality of steps, and the memory storage element further includes: a plurality of word lines formed in each of the plurality of finger storage areas and used to electrically connect the plurality of steps touch.

In some of the embodiments of the present invention, along the second lateral direction, each second dielectric layer of the plurality of second dielectric layers in the first bundle structure includes a plurality of discrete sub-layers part.

In some embodiments of the present invention, a dimension of the first isolation structure in the first lateral direction is larger than that of each finger storage area of the plurality of finger storage areas in the second lateral direction One half of a dimension of , and the dimension of the first isolation structure in the second lateral direction is in the range of 10 nm to 40 nm.

In some of the embodiments of the present invention, further comprising: along the first lateral direction, a plurality of second isolation structures formed between the first block storage area and the second block storage area, wherein the The plurality of second dielectric layers connect adjacent second isolation structures and connect each of the first isolation structures to the second isolation structures.

In some of the embodiments of the present invention, there is provided a method for forming a memory storage element comprising forming a stack including a plurality of a first dielectric layer and a plurality of second dielectric layers, wherein: in a first lateral direction relative to the substrate, the stacked structure is an array region and disposed between the array regions formed in an intermediate region along a second lateral direction relative to the substrate, a stepped structure and a plurality of discrete first bundle structures are formed in the intermediate region, forming vertically through the stack structure and a plurality of gate line slots (GLS) entering the substrate and extending along the first lateral direction, wherein in the second lateral direction the plurality of gate line slots define at least a first block of storage area and a second block storage area, and the plurality of gate line slits include a gate in each array area formed at a boundary between the first block storage area and the second block storage area polar line slits, and removing the plurality of second dielectric layers from the array region and partially from the intermediate region, wherein the multiple second dielectric layers are removed from the array region and partially from the intermediate region After the plurality of second dielectric layers, a portion of the plurality of second dielectric layers remains in the plurality of discrete first bundle structures.

In some of the embodiments of the present invention, further comprising: forming a first block storage area across the first block storage area and the second block storage area and extending through the intermediate area in the first lateral direction A two-beam configuration, wherein a portion of the plurality of second dielectric layers remains in the second beam after removing the plurality of second dielectric layers from the array region and partially from the intermediate region In the structure, and between the first block storage area and the second block storage area, a first isolation structure vertically passing through the stack structure is formed, wherein the first isolation structure is located in each array area at a boundary between the intermediate regions, and the first isolation structure is connected with the gate line slits formed in the respective array regions and at the side adjacent to the intermediate regions, and the remaining portions of the plurality of second dielectric layers in the second bundle structure connecting the first isolation structures at each side of the intermediate region.

In some of the embodiments of the present invention, along the first lateral direction, the stepped structure includes a plurality of sub-staircase structures, wherein adjacent sub-staircase structures are separated by the plurality of discrete first bundle structures One of the first bundle structures is spaced apart.

In some of the embodiments of the present invention, each of the first block storage area and the second block storage area includes a wall structure area and a plurality of finger storage areas extending along the first lateral direction , wherein the plurality of finger storage areas of the first block storage area and the plurality of finger storage areas of the second block storage area are adjacent to each other, and the stepped structure is located in the first block storage area In the intermediate area between the area and the wall structure area of the second block storage area, in the second lateral direction, each first bundle structure extends through all the first block storage area. The plurality of finger storage areas, and the plurality of finger storage areas of the second block storage area are connected to the wall structure area of the first block storage area and the second block storage area.

In some of the embodiments of the present invention, it further comprises: after removing the plurality of second dielectric layers from the array region and partially from the intermediate region, in the adjacent first dielectric layers A plurality of electrode layers are formed between the layers, wherein the first isolation structure is made of insulating material.

In some of the embodiments of the present invention, when forming the first isolation structure vertically passing through the stack structure and located at the boundary between each array region and the intermediate region, the method further includes: forming a plurality of second isolation structures in the intermediate region, wherein each second isolation structure of the plurality of second isolation structures is aligned with the first isolation structure in the second lateral direction, The first isolation structure and the plurality of second isolation structures are made of insulating material, and the plurality of second dielectric layers are removed from the array region and partially from the intermediate region Afterwards, the remaining portions of the plurality of second dielectric layers in the second bundle structure connect adjacent second isolation structures, and also connect each of the first isolation structures to the first isolation structures. Two isolation structures.

In some of the embodiments of the present invention, the first block storage area includes a first edge opposite to the second block storage area, and the second block storage area includes an opposite side to the first block storage area Opposite a second edge, the plurality of gate line slits further include: a gate line slit formed on the first edge and extending through the array region and the intermediate region, and a gate line slit formed on the first edge and extending through the array region and the intermediate region. Another gate line slot on the second edge and extending through the array region and the intermediate region, and in each of the first block storage regions and each of the second block storage regions, along the The plurality of gate line slits extending in the first lateral direction further include: a gate line slit located in each of the array regions and between the wall structure region and the adjacent finger storage region, formed in the another gate line slot in each array area and between adjacent finger storage areas, wherein, along the first lateral direction, is formed in the array area and between adjacent finger storage areas Each of the gate line slits extends through the array region, and yet another gate line slit is located in the middle region and is located near the edge of each sub-staircase structure of the wall structure region, wherein the A length of the gate line slot in the middle region and located near the edge of each sub-staircase structure in the wall structure region is shorter than or equal to a width of the sub-staircase structure.

In some embodiments of the present invention, wherein in the first block storage area or the second block storage area, each of the sub-staircase structures includes the fingers formed adjacent to the wall structure area A plurality of steps in a storage area, and the memory storage element further includes: a plurality of steps formed in the finger storage area adjacent to the wall structure area and used for electrically connecting the plurality of steps word line contacts, and in each of the first block storage areas and each of the second block storage areas, the plurality of gate line slits extending in the first lateral direction further include forming in each of the gate line slits in the middle region and located between adjacent finger storage regions, wherein along the first lateral direction, gate lines formed in the middle region and located between adjacent finger storage regions A length of the line slot is shorter than or equal to the width of the sub-staircase structure.

According to the above paragraphs (please refer to the paragraphs and the drawings together), one of the features of the present invention is that the load of the single-side row word line driving scheme includes the entire word across the slice storage area 102 resistance of the line. Furthermore, as the demand for higher storage capacity continues to grow, the number of vertical levels of stacked storage structures increases and the thickness of the stacked layers, including individual word line films, decreases. Consequently, high resistance may be introduced into the load, thus causing significant resistance-capacitance (RC) delays. Accordingly, the performance (eg, read and write speed) of the 3D memory storage device 100 may be affected by the single-sided word line driving scheme with the side stepped structure 104 .

In order to reduce the RC delay, in some other 3D memory storage devices, a ladder structure is arranged between the slice storage areas to realize a double-sided word line driving scheme. By replacing the conventional side ladder structure with, for example, a center ladder structure, each row decoder can start from the middle of the slice storage area and drive the word lines bilaterally in opposite directions so that the resistance in the load will be affected by the row decoding. The length of the word line driven by the driver can be reduced by, for example, half. In some 3D memory storage devices, a portion of the staircase structure is introduced into the wall structure to connect the word lines separated by the center/transition staircase structure. In addition, a multi-partition ladder structure in which each step of the ladder structure includes a plurality of partitions of a plurality of word lines for fan-out is used to improve the utilization rate of the ladder structure and reduce the manufacturing complexity. Additionally, multiple cutting processes are used to form multiple steps at different depths to reduce the number of trim etch processes, thus further reducing fabrication complexity and increasing yield. Further, after the steps are formed, partitions are formed to reduce the number of material layer pairs (eg, silicon nitride and silicon dioxide pairs) in the stack to be etched, thereby reducing the need to cover areas outside the step regions (eg, , wall structure) thickness requirements of the hard mask.

Each word line (not shown) of the slice storage area 202 extending laterally in the X direction is separated into two parts by the corresponding staircase structure 204: the first word line spanning the first storage array structure 206-1 portion, and a second word line portion across the second storage array structure 206-2. As described in detail below, the two portions of each word line are electrically connected by wall structures (not shown) in the ladder structure 204 at each step of the ladder structure 204 . A row decoder (not shown) is formed directly above, below, or near each ladder structure 204 to reduce interconnect length. Therefore, instead of the row decoders of the 3D memory storage element 100 shown in FIG. 1, each row decoder of the 3D memory storage element 200 drives the first storage bilaterally (in both the positive and negative X directions) Array structure 206-1 and the memory cells in the second storage array structure 206-2. That is, by replacing the conventional side stair structure (eg, the stair structure 104 shown in FIG. 1 ) with, for example, the stair structure 204 in the middle of the storage array structures 206-1/206-2, each row decoder can Starting in the middle of the storage area 202, the word lines are driven bilaterally in opposite directions so that the resistance in the load is reduced by, for example, half the length of the portion of each word line to be driven by the row decoder (in the The stepped structure 204 can be reduced when arranged in the central portion of the storage array structure 206-1/206-2). That is, the row decoder of the 3D memory storage device 200 only needs to drive either the first word line part or the second word line part of each word line.

Referring to FIG. 5 , as the number of material layer pairs in the stacked structure 401 increases, the steps exposing the bottom material layer pairs have a greater depth relative to the top of the wall structure 404 . That is, the aspect ratio (height in the Z direction to width in the Y direction) of the wall structure is larger. In addition, the increase in the number of material layer pairs in the stacked structure 401 also results in an increase in the length of the wall structure 404 along the X direction. Further, referring to FIGS. 3-4 , in the process of fabricating the 3D memory storage device, after the steps are formed, a plurality of gate line slits may be fabricated. For example, referring to FIG. 3, it is necessary to go all the way through the wall structure in the X direction to form gate line slits and separate adjacent stepped regions. With the larger aspect ratio and larger length of the wall structure, the wall structure may easily collapse when forming gate line slits through the entire length of the wall structure. Therefore, the performance of 3D memory storage devices may need to be improved.

SUMMARY OF THE INVENTION A method for forming a memory storage element is provided. According to the disclosed method, the formed stepped structure includes a plurality of sub-staircase structures, and the adjacent sub-staircase structures are separated from each other along the length direction of the wall structure by the first bundle of structures connected to the wall structure. The first bundle structure can provide mechanical support for the wall structure, thus preventing the wall structure from collapsing when forming gate line slits through the wall structure. In addition, for the adjacent block storage regions in which the finger storage regions are arranged between the wall structure regions, the gate line gaps formed between the two block storage regions are respectively formed at both sides of the intermediate region at the intermediate region The two first isolation structures are truncated. In the middle region spanning the two block storage regions, the second bundle structures connect the first isolation structures formed at each side of the middle region. In the second beam structure, after the second dielectric layer is removed from the array region, a portion of the second dielectric layer remains between adjacent first dielectric layers. Therefore, the second dielectric layer and the first dielectric layer in the second bundle structure not only provide mechanical support for the subsequent fabrication process, but also provide electrical isolation for the two bulk storage regions. Additionally, after the second dielectric layer is removed from the array region, at least a portion of the second dielectric layer remains in each of the first bundle structures, which also provides mechanical support for subsequent fabrication processes.

The first bundle of structures 518 extending in the Y-direction prevents narrowing of the width of the wall structures along the path from one side of the intermediate region 501 to the other side of the intermediate region 501 (about the total width of the two wall structure regions 506 ) . Therefore, when making gate line slits passing through the wall structure in the X direction, the wall structure may not easily collapse.

For each pair of the plurality of finger storage areas 504 and the block storage areas 502 in contact with each other, the first isolation structure 516 formed at each side of the middle area 501 can be used to be a stepped structure between the two block storage areas 502 The central portion of the second dielectric layer 522 in the middle provides protection so that when the second dielectric layer 522 is replaced with a metal electrode layer in a subsequent process, the stepped structure between the two bulk storage regions 502 may not be removed. the central portion of the second dielectric layer 522. Second Dielectric in Ladder Structure Between Two Block Storage Areas 502 The remaining central portion of layer 522 (which may be made of nitride) and the first dielectric layer 521 (which may be made of oxide) may not only provide mechanical support for subsequent fabrication processes, but also provide mechanical support for forming in the memory. The two bulk storage regions 502 in the storage element provide electrical isolation.

According to the disclosed method, the formed stepped structure includes a plurality of sub-staircase structures, and the adjacent sub-staircase structures are separated from each other along the length direction of the wall structure by the first bundle of structures connected to the wall structure. The first bundle structure can provide mechanical support for the wall structure, thus preventing the wall structure from collapsing when gate line slits through the wall structure are formed. In addition, for adjacent block storage regions having finger storage regions disposed between their wall structure regions, gate line gaps formed between two block storage regions are formed in the intermediate regions, respectively, in the intermediate regions. The two first isolation structures at both sides are truncated. In the middle region spanning the two bulk storage regions, the second bundle structures connect the first isolation structures formed at each side of the middle region. In the second beam structure, after removing the second dielectric layer from the array region, portions of the second dielectric layer are left between adjacent first dielectric layers. Therefore, the second dielectric layer and the first dielectric layer in the second bundle structure not only provide mechanical support for the subsequent fabrication process, but also provide electrical isolation for the two bulk storage regions. Additionally, after the second dielectric layer is removed from the array region, at least a portion of the second dielectric layer remains in each of the first bundle structures, which also provides mechanical support for subsequent fabrication processes.

The foregoing description describes only specific exemplary embodiments of the invention, and is not intended to limit the scope of the invention. Those skilled in the art can understand the present specification as a whole, and technical features in various embodiments can be combined into other embodiments that are understandable to those skilled in the art. Without departing from the spirit and principle of the present invention, any equivalents or modifications fall within the applicable scope of the present invention. The above description is only the preferred embodiment of the present invention, and all the equivalent changes made according to the scope of the patent application of the present invention and modifications, all should fall within the scope of the present invention.

501: Middle Zone

502: block storage area

5021: block storage area

5022: block storage area

5023: block storage area

5024: block storage area

503: Array area

504: refers to the storage area

506: Wall Structure Area

508: Gate line gap

512: word line contact

516: First isolation structure

518: First Bundle Structure

520: Sub-ladder structure

Claims (20)

A memory storage element, comprising: a substrate; a stack structure including a plurality of first dielectric layers and a plurality of electrode layers alternately arranged on the substrate, wherein: a first dielectric layer relative to the substrate In a lateral direction, the memory storage element includes an array region and an intermediate region disposed between the array regions, and in a second lateral direction relative to the substrate, the stacked structure includes respective A first block storage area and a second block storage area including a wall structure area, wherein, in the intermediate area, the wall structure area of the first block storage area and the second block storage area , separated by a stepped structure; a bundle of structures located in the intermediate region, wherein the bundle structure comprises at least a plurality of discrete first bundle structures, wherein each first bundle structure comprises a extending in a direction and connecting the wall structure region of the first bulk storage region and the second bulk storage region; and a plurality of second dielectric layers located in the bundle structure, wherein in the plurality of In each of the discrete first bundle structures, the plurality of second dielectric layers alternate with the plurality of first dielectric layers. The memory storage element of claim 1, wherein: the bundle structure further comprises a second bundle structure arranged to span the first block of storage and the second block of storage region, and extending through the intermediate region in the first lateral direction, wherein: in the second bundle structure, the plurality of second dielectric layers are associated with the plurality of first dielectric layers alternately. The memory storage element of claim 2, further comprising: at least one first isolation structure vertically passing through the stack structure on each side of the intermediate region along the first lateral direction , and is formed between the first block storage area and the second block storage area along the second lateral direction, wherein: the first isolation structure is made of silicon dioxide. The memory storage device according to claim 3, wherein: a size of the first isolation structure in the first lateral direction is larger than that of each finger storage area in the plurality of finger storage areas in the first lateral direction. half of a dimension in two lateral directions; and the dimension of the first isolation structure in the second lateral direction, in the range of 10 nm to 40 nm. The memory storage element according to claim 3, further comprising: a plurality of second isolation structures formed between the first block storage area and the second block storage area along the first lateral direction, Wherein: the plurality of second dielectric layers are connected to the adjacent second isolation structures, and each of the first isolation structures is connected to the second isolation structures. The memory storage element of claim 1, wherein: along the first lateral direction, the stepped structure includes a plurality of sub-staircase structures, wherein adjacent sub-staircase structures are separated by the plurality of discrete first bundle structures One of the first bundle structures is spaced apart. The memory storage element of claim 6, further comprising: a first partition structure formed vertically through the stack structure and along the first lateral direction direction, located between the first block storage area and the second block storage area in each array area, wherein the first block storage area includes a first edge opposite to the second block storage area , and the second block storage area includes a second edge opposite the first block storage area; and a second partition structure formed on each of the first edge and the second edge , and extends through the array region and the stepped region. The memory storage element of claim 7, wherein each of the first block storage area and the second block storage area further comprises: a plurality of finger storage areas extending along the first lateral direction area, wherein: in the second lateral direction, the plurality of finger storage areas of the first block storage area and the plurality of finger storage areas of the second block storage area are alternately arranged; and The memory element further includes: a plurality of third partitions formed in each of the first block storage areas and each of the second block storage areas and located between the wall structure area and an adjacent finger storage area structure, wherein: in each array area of the first block storage area or the second block storage area, the third partition structure extends through the array area; and in the first block storage area or In the middle area of the second block storage area, the third partition structure is arranged near the edge of each of the sub-staircase structures in the wall structure area, wherein one of the third partition structures is The length is shorter than or equal to a width of the sub-staircase structure. The memory storage element according to claim 8, wherein: in the first block storage area or the second block storage area, each sub-staircase structure includes the a plurality of steps in a finger storage area; and the memory storage element further includes: the finger storage area formed adjacent to the wall structure area , and is used to electrically connect a plurality of word line contacts of the plurality of steps. The memory storage element according to claim 9, further comprising: a plurality of first block storage areas formed in each of the first block storage areas and each of the second block storage areas and located between adjacent finger storage areas Four partition structures, wherein: in each of the array areas of the first block of storage areas or the second block of storage areas, the fourth partition structure extends through the array areas; and in the first block of storage areas In one of the storage areas or the middle area of the second storage area, and between the adjacent finger storage areas, the fourth partition structure is arranged in each of the sub-staircase structures, wherein , a length of the fourth separation structure is shorter than or equal to a width of the sub-staircase structure. The memory storage element according to claim 10, wherein: in the first block storage area or the second block storage area, each of the sub-ladder structures includes a a plurality of steps in each finger storage area; and the memory storage element further includes: a plurality of steps formed in each of the plurality of finger storage areas and used for electrically connecting the plurality of steps character line contacts. The memory storage element of claim 8, wherein: along the second lateral direction, each second dielectric layer of the plurality of second dielectric layers in the first bundle structure comprises a plurality of a separate subsection. A method for forming a memory storage element, comprising: forming a stacked structure including a plurality of first intermediate layers alternately arranged on a substrate an electrical layer and a plurality of second dielectric layers, wherein: in a first lateral direction relative to the substrate, the stacked structure is an array region and an intermediate region disposed between the array regions forming; forming a stepped structure and a plurality of discrete first bundle structures in the intermediate region along a second lateral direction relative to the substrate; forming vertically through the stack and into the substrate , and a plurality of gate line slots (GLS) extending along the first lateral direction, wherein: in the second lateral direction, the plurality of gate line slots at least define a first block storage area and a a second block storage area; and the plurality of gate line slits include one gate line slit formed in each array area at a boundary between the first block storage area and the second block storage area ; and removing the plurality of second dielectric layers from the array region and partially from the intermediate region, wherein: after removing the plurality of first dielectric layers from the array region and partially from the intermediate region After the two dielectric layers, a portion of the plurality of second dielectric layers remains in the plurality of discrete first bundle structures. The method of claim 13, further comprising forming a second block across the first and second block storage areas and extending across the intermediate area in the first lateral direction beam structure, wherein: after removing the plurality of second dielectric layers from the array region and partially from the intermediate region, a portion of the plurality of second dielectric layers remains in the second beam In the structure; and between the first block storage area and the second block storage area, a first isolation structure vertically passing through the stack structure is formed, wherein: the first isolation structure is located in each array at a boundary between the zone and the intermediate zone; and the first isolation structures are connected together with the gate line slits formed in the respective array regions at the side adjacent to the intermediate region, and the plurality of the second bundle structures The remainder of the second dielectric layer connects the first isolation structures at each side of the intermediate region. The method according to claim 14, when forming the first isolation structure vertically passing through the stacked structure and located at the boundary between each array region and the intermediate region, further comprising: A plurality of second isolation structures are formed in the intermediate region, wherein: in the second lateral direction, each of the plurality of second isolation structures is aligned with the first isolation structure; the first isolation structure and the plurality of second isolation structures are made of insulating material; and the plurality of second dielectric layers are removed from the array region and partially from the intermediate region Afterwards, the remaining portions of the plurality of second dielectric layers in the second bundle structure connect adjacent second isolation structures, and also connect each of the first isolation structures to the first isolation structures. Two isolation structures. The method of claim 13, wherein: along the first lateral direction, the stepped structure includes a plurality of sub-staircase structures, wherein adjacent sub-staircase structures are separated by one of the plurality of discrete first bundle structures The first bundle structures are spaced apart. The method of claim 13, wherein each of the first block storage area and the second block storage area comprises: A wall structure area and a plurality of finger storage areas extending along the first lateral direction, wherein: the plurality of finger storage areas of the first block storage area, and the plurality of finger storage areas of the second block storage area Each finger storage area is adjacent to each other, the stepped structure is located in the middle area between the first block storage area and the wall structure area of the second block storage area, in the second lateral direction In the direction, each first bundle structure extends through the plurality of finger storage areas of the first block storage area and the plurality of finger storage areas of the second block storage area, and is connected to the first block storage area. One storage area and the wall structure area of the second storage area. The method of claim 17, wherein: the first block of storage includes a first edge opposite the second block of storage, and the second block of storage includes an edge opposite to the first block of storage a second edge opposite to the region; the plurality of gate line slits further include: a gate line slit formed on the first edge and extending through the array region and the intermediate region, and forming on said second edge and extending through another gate line slot of said array region and said intermediate region; and in each of said first block of storage regions and each of said second block of storage regions, The plurality of gate line slits extending along the first lateral direction further include: one gate line slit located in each array region and between the wall structure region and an adjacent finger storage region; forming In each array region and located between adjacent finger storage regions, another gate line slot, wherein, along the first lateral direction, is formed in the array region and located between adjacent finger storage regions each gate line slot between the two extends through the array region; and yet another gate line slot is located in the middle region and is located near the edge of each sub-staircase structure of the wall structure region, wherein, located in the intermediate zone and located close to the A length of the gate line slit at the edge of each sub-staircase structure in the wall structure region is shorter than or equal to a width of the sub-staircase structure. The method of claim 18, wherein: in the first block storage area or the second block storage area, each of the sub-staircase structures includes the fingers formed adjacent to the wall structure area a plurality of steps in a storage region; and the method further comprising: forming a plurality of word lines in the finger storage region adjacent to the wall structure region and for electrically connecting the plurality of steps contacting; and in each of the first block storage regions and each of the second block storage regions, the plurality of gate line slits extending in the first lateral direction further include being formed in each of the intermediate regions , and is located in the gate line gap between adjacent finger storage regions, wherein: along the first lateral direction, is formed in the middle region and is located in the gate line gap between adjacent finger storage regions A length of , which is shorter than or equal to the width of the sub-staircase structure. The method of claim 13, further comprising: after removing the plurality of second dielectric layers from the array region and partially from the intermediate region, inserting an adjacent first dielectric layer A plurality of electrode layers are formed therebetween, wherein: the first isolation structure is made of insulating material.

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