TWI772015B - Pixel structure and fabrication method thereof - Google Patents

Abstract

A pixel structure includes a substrate, an interlayer dielectric (ILD) layer, an active device, a plurality of conductive bumps, a planarization layer, a first electrode, a pixel defining layer (PDL), a light emitting layer and a second electrode. The ILD layer is on the substrate. The active device is on the substrate and includes a drain and a channel layer. The drain passes through the ILD layer to be electrically connected to the channel layer. The conductive bumps are on the ILD layer and separated from each other. The planarization layer is on the drain and the conductive bumps. The first electrode passes through the planarization layer and is electrically connected to the drain of the active device. The first electrode has a plurality of electrode protrusions. Each of the electrode protrusions overlaps each of the conductive bumps, respectively. The PDL has an opening overlapping the first electrode. The opening overlaps at least one of the conductive bumps. The light emitting layer is disposed in the opening and on the first electrode. The second electrode is disposed on the light emitting layer.

Description

Pixel structure and method of making the same

The present invention relates to a pixel structure and a manufacturing method thereof.

In today's electronic products, organic light emitting diode (OLED) display devices and micro light emitting diode (micro LED) display devices that provide active light emission have gradually become the mainstream of products.

The light output of the organic light emitting diode is affected by the difference in the refractive index and film thickness of the interface of each layer, resulting in the limitation of the waveguide. At present, most of the improvement methods are in the light-emitting diode process, by adding nanoparticles in the organic light-emitting layer to generate scattering, or fabricating a micro-lens array above it to solve this problem. However, the organic light-emitting layer is mostly fabricated by an inkjet printing process, which has severe limitations, such as surface flatness. Therefore, how to improve the confinement of the waveguide without affecting the process of the organic light-emitting layer is the focus of development in related fields.

The present invention provides a pixel structure and a manufacturing method thereof, which can improve light extraction efficiency.

A pixel structure according to an embodiment of the present invention includes a substrate, an interlayer dielectric layer, an active element, a plurality of conductive bumps, a flat layer, a first electrode, a pixel definition layer, a light-emitting layer, and a second electrode. An interlayer dielectric layer is on the substrate. The active element is located on the substrate and has a drain electrode and a channel layer, and the drain electrode penetrates the interlayer dielectric layer to be electrically connected with the channel layer. The conductive bumps are on the interlayer dielectric layer and are spaced apart from each other. The flat layer is located on the drain electrode and the conductive bump. The first electrode penetrates through the flat layer and is electrically connected to the drain electrode of the active element. The first electrode has a plurality of electrode protrusions, and each electrode protrusion is respectively overlapped with each conductive bump. The pixel definition layer has an opening overlapping the first electrode, and the opening overlapping at least one conductive bump. The light-emitting layer is disposed in the opening and on the first electrode. The second electrode is disposed on the light-emitting layer.

A pixel structure according to an embodiment of the present invention includes a substrate, an interlayer dielectric layer, an active element, a first planarization layer, a second planarization layer, a first electrode, a pixel definition layer, a light-emitting layer, and a second electrode. An interlayer dielectric layer is on the substrate. The active element is located on the substrate and has a drain electrode and a channel layer, and the drain electrode penetrates the interlayer dielectric layer to be electrically connected with the channel layer. The first planar layer is on the interlayer dielectric layer and has a plurality of insulating bumps spaced apart from each other. The second planar layer is located on the first planar layer, wherein the second planar layer has a plurality of insulating protrusions. The first electrode is electrically connected to the drain of the active element and has a plurality of electrode protrusions, and each electrode protrusion is respectively overlapped with each insulating protrusion and each insulating bump. The pixel definition layer has an opening overlapping the first electrode, and the opening overlapping at least one insulating bump. The light-emitting layer is disposed in the opening and on the first electrode. The second electrode is disposed on the light-emitting layer.

A method for fabricating a pixel structure according to an embodiment of the present invention includes the following steps. A channel layer is formed on the substrate. A gate insulating layer is formed on the channel layer. A gate is formed on the gate insulating layer. An interlayer dielectric layer is formed to cover the gate electrode and the channel layer, wherein the interlayer dielectric layer has a plurality of through holes. A conductive layer is formed on the entire surface on the interlayer dielectric layer, wherein the conductive layer is filled into the through holes. The conductive layer is patterned to form a source electrode, a drain electrode and a plurality of conductive bumps, wherein the source electrode, the drain electrode, the gate electrode and the channel layer constitute an active element, and the conductive bumps are separated from each other. A flat layer is formed on the source electrode, the drain electrode and the conductive bump. A first electrode is formed on the flat layer, the first electrode penetrates the flat layer and is electrically connected to the drain electrode. A pixel definition layer is formed on the first electrode, the pixel definition layer has an opening overlapping the first electrode, and the opening overlaps at least one conductive bump. A light-emitting layer is formed in the opening. A second electrode is formed on the light emitting layer.

Based on the above, in the pixel structure and the manufacturing method thereof according to an embodiment of the present invention, the conductive bumps are located on the interlayer dielectric layer and are separated from each other, the first electrode has a plurality of electrode protrusions, and the electrode protrusions are respectively overlapped on each conductive bump. The pixel definition layer has an opening overlapping the first electrode, and the opening overlapping at least one conductive bump. The light-emitting layer is disposed in the opening and located on the first electrode, which can effectively reduce the light-extraction loss caused by the limitation of the waveguide of the first electrode, thereby improving the light-extraction efficiency.

FIG. 1 is a schematic cross-sectional view of a pixel structure 10 according to an embodiment of the present invention. Referring to FIG. 1 , the pixel structure 10 includes a substrate 100 . In this embodiment, the material of the substrate 100 may be glass, quartz, organic polymer or other applicable materials.

The pixel structure 10 further includes a buffer layer 102 , a gate insulating layer 104 , an active element T and an interlayer dielectric layer 106 . The buffer layer 102 is disposed on the substrate 100 . The active element T is located on the substrate 100 and can be a low temperature polysilicon type thin film transistor (LTPS-TFT) and has a channel layer CH, a source electrode S, a drain electrode D and a gate electrode G. The channel layer CH is disposed on the buffer layer 102, and the material of the channel layer CH is polysilicon, but the invention is not limited to this. In other embodiments, the material of the channel layer CH is, for example, amorphous silicon, metal oxide semiconductor or other semiconductor materials. The gate insulating layer 104 is disposed between the channel layer CH and the gate electrode G. For example, in this embodiment, the gate G of the active element T is disposed above the channel layer CH to form a top-gate TFT, but the invention is not limited thereto. According to other embodiments, the gate G of the active element T can also be disposed below the channel layer CH, that is, the gate G is located between the channel layer CH and the substrate 100 to form a bottom-gate thin film transistor (bottom-gate thin film transistor). TFT).

The channel layer CH can be a single-layer or multi-layer structure, and its materials include amorphous silicon, microcrystalline silicon, nanocrystalline silicon, polycrystalline silicon, monocrystalline silicon, organic semiconductor materials, oxide semiconductor materials, carbon nanotubes/rods, Other suitable materials, or a combination of the foregoing. The buffer layer 102 and the gate insulating layer 104 can be inorganic thin films formed of inorganic materials, and the inorganic materials are insulating materials such as silicon nitride, silicon oxide, silicon oxynitride or other insulating materials, but the invention is not limited thereto.

The interlayer dielectric layer 106 is located on the gate insulating layer 104 and covers the gate electrode G of the active element T. As shown in FIG. The source electrode S and the drain electrode D of the active element T are disposed on the interlayer dielectric layer 106 and respectively overlap with two different regions of the channel layer CH. For example, the drain electrode D penetrates the interlayer dielectric layer 106 to be electrically connected to the channel layer CH, and the source electrode S penetrates the interlayer dielectric layer 106 to be electrically connected to the channel layer CH. The pixel structure 10 includes a plurality of conductive bumps 108 . The conductive bumps 108 are located on the interlayer dielectric layer 106 and are spaced apart from each other. The conductive bumps 108 and the source electrode S and the drain electrode D may be formed of the same film layer and may include the same material.

In this embodiment, the pixel structure 10 may further include an insulating layer 110 and a capacitor electrode 112 . The gate electrode G and the capacitor electrode 112 may be formed of the same film layer and may include the same material. The insulating layer 110 and the gate insulating layer 104 may be formed of the same film layer and may include the same material. The conductive bumps 108 and the capacitor electrodes 112 are located on opposite sides (eg, upper and lower sides) of the interlayer dielectric layer 106 and are separated by the interlayer dielectric layer 106 . Due to the separation between the capacitor electrodes 112 and the conductive bumps 108 , the capacitor electrodes 112 and the conductive bumps 108 may together form a storage capacitor in the form of a parallel plate capacitor.

The pixel structure 10 further includes a passivation layer 114 , a planarization layer 116 , a first electrode 118 , a pixel definition layer 120 , a light-emitting layer 122 and a second electrode 124 . The passivation layer 114 and the planarization layer 116 are located on the drain electrode D and the conductive bumps 108 . For example, the passivation layer 114 fills the space between the adjacent conductive bumps 108 . The conductive bumps 108 cause the passivation layer 114 to have topographical changes. For example, the passivation layer 114 has a plurality of recesses R1 and a plurality of protrusions P1. The top surface of the concave portion R1 is lower than the top surface of the protruding portion P1 , and each of the protruding portions P1 overlaps each of the conductive bumps 108 . The flat layer 116 is located on the passivation layer 114 and fills the recess R1 of the passivation layer 114 . The conductive bumps 108 indirectly cause the planarization layer 116 to have topographical changes. For example, the planarization layer 116 has a plurality of recesses R2 and a plurality of protrusions P2, and the top surface of the recesses R2 is lower than the top surface of the protrusions P2. Each protruding portion P2 of the flat layer 116 overlaps the protruding portion P1 of the passivation layer 114 , respectively, and the concave portion R2 of the flat layer 116 overlaps the concave portion R1 of the passivation layer 114 , respectively.

The pixel definition layer 120 is located on the first electrode 118 and the flat layer 116 , and has an opening OP overlapping the first electrode 118 , and the opening OP overlapping at least one conductive bump 108 . The light emitting layer 122 is disposed in the opening OP and on the first electrode 118 . The second electrode 124 is disposed on the light emitting layer 122 . The first electrode 118 penetrates through the planarization layer 116 and the passivation layer 114 and is electrically connected to the drain electrode D of the active element T. As shown in FIG. The first electrode 118 , the light-emitting layer 122 and the second electrode 124 together constitute the light-emitting element 126 . For example, the first electrode 118 serves as a reflective layer, so that the light-emitting layer 122 emits light upward, so the light-emitting element 126 is an upper light-emitting element. In some embodiments, the material of the pixel definition layer 120 may be a hydrophobic material, such as a fluorine-rich negative photoresist material. In some embodiments, the first electrode 118 may serve as an anode of the light emitting layer 122, but the invention is not limited thereto. In some embodiments, the second electrode 124 may serve as a cathode of the light emitting layer 122, but the invention is not limited thereto. The light emitting element 126 is, for example, an organic light emitting diode (organic light emitting diode, OLED).

The first electrode 118 is filled into the concave portion R2 of the flat layer 116, and the conductive bump 108 indirectly causes the first electrode 118 to have a topographical change. For example, the first electrode 118 has a plurality of electrode protrusions P3, and the electrode protrusions P3 overlap respectively. on each conductive bump 108 . In one embodiment, the first electrode 118 may have a plurality of concave portions R3 , and each concave portion R3 overlaps with the concave portion R2 of the flat layer 116 respectively. When a part of the light L1 emitted by the light emitting layer 122 travels toward the direction of the first electrode 118 , the first electrode 118 has an electrode protrusion P3 indirectly by disposing a plurality of conductive bumps 108 spaced apart from each other on the interlayer dielectric layer 106 . , the light L1 reflected by the first electrode 118 back to the light-emitting layer 122 can be prevented from being totally reflected at the interface between the first electrode 118 and the light-emitting layer 122 , so that the limitation of the waveguide of the first electrode 118 can be effectively reduced The resulting light output loss, thereby improving the light output efficiency.

In some embodiments, the material of the first electrode 118 is a conductor material, such as aluminum (Al), silver (Ag), chromium (Cr), copper (Cu), nickel (Ni), titanium (Ti), molybdenum (Mo) ), magnesium (Mg), platinum (Pt), gold (Au), or a combination thereof. In some embodiments, the material of the first electrode 118 may also include transparent or semi-transparent conductive materials, such as zinc oxide (ZnO), indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO) ), indium gallium oxide (IGO), zinc gallium oxide (ZGO), or other suitable materials. The first electrode 118 may be a single-layer, double-layer or multi-layer structure. In the embodiment in which the first electrode 118 has a three-layer structure, the first electrode 118 may include a first conductive layer 118a, a second conductive layer 118b, and a third conductive layer 118c. The following description will be given by taking the first electrode 118 as a three-layer structure.

In some embodiments, the first electrode 118 is, for example, a three-layer structure composed of ITO/Ag/ITO. In other words, the first conductive layer 118a is indium tin oxide (ITO), the second conductive layer 118b is silver (Ag), and the third conductive layer 118c is indium tin oxide (ITO). The refractive index of ITO is different from the refractive index of the light emitting layer 122 , for example, the refractive index of ITO is larger than that of the light emitting layer 122 . The electrode protrusion P3 can avoid total reflection of the light L1 reflected by the second conductive layer 118b back to the light emitting layer 122 at the interface between the third conductive layer 118c and the light emitting layer 122 . In this way, the light extraction loss caused by the limitation of the waveguide of the third conductive layer 118c can be effectively reduced, thereby improving the light extraction efficiency. In other embodiments, the first electrode 118 may also be Ti/Al/Ti or a three-layer structure composed of Mo/Al/Mo.

The material of the second electrode 124 can be a transparent conductive material, such as metal oxides such as indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, or indium germanium zinc oxide.

In one embodiment, the conductive bumps 108 and the drain electrodes D and the source electrodes S are in contact with the top surface of the interlayer dielectric layer 106 . The conductive bump 108, the drain electrode D and the source electrode S are formed of the same film layer and include the same material. In other words, the conductive bumps 108 and the drain electrodes D and the source electrodes S can be patterned by the same mask process, so the fabrication of the conductive bumps 108 is compatible with the existing process.

It should be noted that the gate electrode G, the source electrode S, the drain electrode D, the gate insulating layer 104 , the interlayer dielectric layer 106 and the planarization layer 116 can be selected from any of the methods known to those skilled in the art for display panels. Any gate, any source, any drain, any gate insulating layer, any interlayer dielectric layer and any flat layer are implemented, and the gate G, source S, drain D, gate insulation The layer 104 , the interlayer dielectric layer 106 and the planarization layer 116 can be formed by any method known to those skilled in the art, and thus will not be described in detail here. The material of the flat layer 116 is an organic material, such as photoresist or other suitable materials. The planarization layer 116 may be a single-layer, double-layer, or multi-layer structure, and may be the same material or different materials.

2 to 7 are schematic top views of the conductive bump 108 according to an embodiment of the present invention. Please refer to FIG. 2 first, the conductive bumps 108 are regularly arranged, for example, the conductive bumps 108 are distributed in point symmetry. In this way, the light guided back to the light emitting layer 122 by the conductive bumps 108 can be uniformly distributed, so that the brightness of the light emitting layer 122 can be uniform. For example, the conductive bumps 108 are arranged at equal intervals, for example, arranged in an array with a distance x1. In this embodiment, the top view shape of the conductive bump 108 is a rectangle, for example, a square. However, the present invention is not limited thereto. In other embodiments, the top-view shape of the conductive bump 108a (see FIG. 3 ) may be a circle or a triangle. Please refer to FIG. 4 for the top-view shape of the conductive bump 108b in this embodiment. It is a triangle, for example, an equilateral triangle, and the top-view shapes of the adjacent conductive bumps 108b are opposite up and down. Next, referring to FIG. 5, the conductive bumps 108c may have different sizes. For example, the conductive bumps 108c have a first group 1080 and a second group 1082, and the size of the first group 1080 is larger than that of the second group 1082 . In other embodiments, the pitch x2 of each conductive bump 108d (see FIG. 6 ) is greater than the pitch x1 of FIGS. 2 to 4 . The surface topography of the first electrode 118 (see FIG. 1 ) can be adjusted by designing the shape, size and spacing of the conductive bumps 108 to meet the requirements of different products. Next, referring to FIG. 7 , in other embodiments, the conductive bumps 108e may be arranged irregularly. In other words, the conductive bumps 108e are randomly distributed. And the conductive bumps 108e may have a first group 1084 and a second group 1086 , and the size of the first group 1084 is larger than that of the second group 1086 .

8A is a schematic cross-sectional view of a pixel structure 20 according to another embodiment of the present invention. Please refer to FIG. 8A. The difference between the pixel structure 20 of this embodiment and the pixel structure 10 of FIG. 1 lies in the pixel structure 20 The passivation layer 214 has a plurality of insulating bumps 214P separated from each other, and the insulating bumps 214P overlap and cover the conductive bumps 108 respectively. The passivation layer 214 is located between the planar layer 116 and the conductive bumps 108 , and the planar layer 116 is filled between adjacent conductive bumps 108 . By designing the insulating bumps 214P, the aspect ratio of the flat layer 116 filled between the adjacent conductive bumps 108 can be increased. Therefore, the flat layer 116 still has topographical changes. In other words, the concave portion R2 and the protrusion of the flat layer 116 Part P2 can be reserved. Therefore, when the thickness t1 of the flat layer 116 is relatively thick, the first electrode 118 still has a topographical change, in other words, the electrode protrusion P3 of the first electrode 118 will not be flattened and can be retained. For example, the thickness t1 of the flat layer 116 is 1 to 10 microns.

8B is a schematic cross-sectional view of a pixel structure 30 according to another embodiment of the present invention. Please refer to FIG. 8B. The pixel structure 30 includes a substrate 100, an interlayer dielectric layer 106, an active element T, a first planar layer 316, The second flat layer 318 , the first electrode 118 , the pixel definition layer 120 , the light emitting layer 122 and the second electrode 124 . The interlayer dielectric layer 106 is on the substrate 100 . The active device T is located on the substrate 100 and has a drain electrode D and a channel layer CH. The drain electrode D penetrates through the interlayer dielectric layer 106 to be electrically connected to the channel layer CH. The first planarization layer 316 is on the interlayer dielectric layer 106 and has a plurality of insulating bumps 316P spaced apart from each other.

The second planarization layer 318 is located on the first planarization layer 316 . The second planar layer 318 is filled between the adjacent insulating bumps 316P. The insulating bumps 316P cause the second planar layer 318 to have topographical variations, for example, the second planar layer 318 has a plurality of recesses R4 and a plurality of insulating protrusions P4. The top surface of the concave portion R4 is lower than the top surface of the insulating protruding portion P4, and the insulating protruding portion P4 overlaps the insulating bump 316P.

The first electrode 118 is electrically connected to the drain electrode D of the active element T, and the first electrode 118 is filled in the concave portion R4 of the second flat layer 318 , and the insulating bump 316P indirectly causes the first electrode 118 to have a topographical change. For example, The first electrode 118 has a plurality of electrode protrusions P3, and each of the electrode protrusions P3 overlaps each of the insulating bumps 316P, respectively. In one embodiment, the first electrode 118 may have a plurality of recesses R3 , and each of the recesses R3 overlaps with the recesses R4 of the second flat layer 318 respectively.

Each electrode protrusion P3 overlaps each insulating protrusion P4 and each insulating bump 316P, respectively. The pixel definition layer 120 has an opening OP overlapping the first electrode 118 , and the opening OP overlapping at least one insulating bump 316P. The light emitting layer 122 is disposed in the opening OP and on the first electrode 118 . The second electrode 124 is disposed on the light emitting layer 122 .

When a part of the light L1 emitted by the light emitting layer 122 travels toward the direction of the first electrode 118 , the first electrode 118 has an electrode protrusion P3 indirectly by disposing a plurality of insulating bumps 316P spaced apart from each other on the interlayer dielectric layer 106 . , the light L1 reflected by the first electrode 118 back to the light-emitting layer 122 can be prevented from being totally reflected at the interface between the first electrode 118 and the light-emitting layer 122 , so that the limitation of the waveguide of the first electrode 118 can be effectively reduced The resulting light output loss, thereby improving the light output efficiency.

In the case where the pixel structure 30 has multiple planar layers (eg, the first planar layer 316 and the second planar layer 318 ), the electrode protrusion P3 of the first electrode 118 will not be planarized and can be retained. In one embodiment, the thickness t2 of the first planarization layer 316 is 1 μm to 30 μm, and the thickness t3 of the second planarization layer 318 is 1 μm to 30 μm. In this embodiment, the insulating bumps 316P are point-symmetrically distributed. For example, the distribution of the insulating bumps 316P is the same as that in FIG. 2 to FIG. 6 , so it is not repeated here. Therefore, the surface topography of the first electrode 118 can be adjusted by designing the shape, size and spacing of the insulating bumps 316P to meet the requirements of different products.

8C is a schematic cross-sectional view of a pixel structure 40 according to another embodiment of the present invention. Please refer to FIG. 8C. The difference between the pixel structure 40 of this embodiment and the pixel structure 10 of FIG. 1 lies in the pixel structure 40 A part of the opening OP of the pixel definition layer 120a overlaps the capacitor electrode 112a and the insulating layer 110a, and another part of the opening OP does not overlap the capacitor electrode 112a and the insulating layer 110a. In other words, the sidewall sw of the opening OP is located directly above the capacitor electrode 112a, that is, the sidewall sw of the opening OP overlaps the capacitor electrode 112a. In other embodiments, the sidewall sw of the opening OP may overlap with other circuits (not shown), such as gate electrodes or any metal traces. By arranging the conductive bumps 108 on the interlayer dielectric layer 106 and separated from each other, the height difference of the stack structure below the opening OP caused by the capacitor electrode 112a or other circuits (not shown) can be reduced, thereby reducing the height difference. The vertical distance 128 between the electrode protruding portion P3 and the concave portion R3 of the third conductive layer 118c of the first electrode 118 is such that the surface flatness of the light-emitting layer 122 is improved. Furthermore, since the opening OP of the pixel definition layer 120a does not need to avoid the capacitor electrode 112a or other circuits (not shown), the size of the opening OP can be increased, and the opening ratio can be improved.

FIGS. 9 to 21 are schematic cross-sectional views of a method for fabricating a pixel structure 50 according to an embodiment of the present invention. Referring to FIG. 9 , first, a channel layer CH is formed on the substrate 100 . In one embodiment, the buffer layer 102 may be formed on the substrate 100 before the channel layer CH is formed. Next, referring to FIG. 10 , a gate insulating layer 104 is formed on the channel layer CH, and an insulating layer 110 is formed on the buffer layer 102 . The gate insulating layer 104 and the insulating layer 110 are formed by, for example, depositing an insulating material (not shown) on the channel layer CH and the buffer layer 102 over the entire surface, and then patterning the insulating material (not shown).

Referring to FIG. 11 , the gate electrode G is formed on the gate insulating layer 104 , and the capacitor electrode 112 is formed on the insulating layer 110 . The gate electrode G and the capacitor electrode 112 are formed by, for example, depositing a conductive material (not shown) on the buffer layer 102 , the channel layer CH, the gate insulating layer 104 and the insulating layer 110 on the entire surface, and then patterning the conductive material (not shown) formed. Next, referring to FIG. 12, an interlayer dielectric layer 106 is formed to cover the gate electrode G and the channel layer CH, and the interlayer dielectric layer 106 has a plurality of through holes V1, and the through holes V1 expose a part of the channel layer CH.

Referring to FIG. 13, a conductive layer 108A is formed over the entire surface on the interlayer dielectric layer 106, and the conductive layer 108A is filled into the via hole V1. A photoresist PR is coated on the conductive layer 108A, and the photoresist PR is exposed by a photomask MK. The mask MK has a plurality of patterns PN, and after exposure, the photoresist PR can have a plurality of exposure portions PR1 corresponding to the patterns PN. Referring to FIG. 14, the photoresist PR is developed to leave an exposed portion PR1.

Referring to FIG. 15, the conductive layer 108A is patterned by the exposure portion PR1 to form a source electrode S, a drain electrode D and a plurality of conductive bumps 108, which are composed of a source electrode S, a drain electrode D, a gate electrode G and a channel layer CH. The active element T, and the conductive bumps 108 are spaced apart from each other. The distribution and height of the conductive bumps 108 can be defined by the mask MK (see FIG. 13 ). For example, the distribution of the conductive bumps 108 can be as shown in FIGS. 2 to 6 . The patterning method is, for example, an etching method. Referring to FIG. 16 , the exposed portion PR1 of the photoresist PR is removed, for example, by using a stripper. Since the conductive bumps 108 are defined through the same mask process as the source S and the drain D, the conductive bumps 108 can be fabricated without changing the process of the light-emitting element 126 (eg, the light-emitting layer 122 ). Therefore, the manufacturing process of the light-emitting element 126 (eg, the light-emitting layer 122 ) will not be affected.

Due to the separation between the capacitor electrodes 112 and the conductive bumps 108 , the capacitor electrodes 112 and the conductive bumps 108 may together form a storage capacitor in the form of a parallel plate capacitor.

Next, referring to FIG. 17 , a passivation layer 114 and a flat layer 116 are formed on the source electrode S, the drain electrode D, and the conductive bump 108 . The conductive bumps 108 cause the passivation layer 114 to have topographical changes. For example, the passivation layer 114 has a plurality of recesses R1 and a plurality of protrusions P1. The flat layer 116 is located on the passivation layer 114 and fills the recess R1 of the passivation layer 114 . The conductive bumps 108 indirectly cause the planarization layer 116 to have topographical changes. For example, the planarization layer 116 has a plurality of recesses R2 and a plurality of protrusions P2.

Referring to FIG. 18 , a first electrode 118 is formed on the flat layer 116 , and the first electrode 118 penetrates through the flat layer 116 and is electrically connected to the drain electrode D. As shown in FIG. The first electrode 118 is filled into the concave portion R2 of the flat layer 116, and the conductive bump 108 indirectly causes the first electrode 118 to have a topographical change. For example, the first electrode 118 has a plurality of electrode protrusions P3, and the electrode protrusions P3 overlap respectively. on each conductive bump 108 . In one embodiment, the first electrode 118 may have a plurality of concave portions R3 , and each concave portion R3 overlaps with the concave portion R2 of the flat layer 116 . In one embodiment, in the embodiment in which the first electrode 118 has a three-layer structure, the first electrode 118 may include a first conductive layer 118a, a second conductive layer 118b and a third conductive layer 118c, which are the same as those shown in FIG. 1 . The description will not be repeated here for the sake of brevity. In some embodiments, the formation method of the first electrode 118 may be chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), evaporation (VTE), sputtering (SPT) or its combination.

Referring to FIG. 19 , next, a pixel definition layer 120 is formed on the first electrode 118 . The pixel definition layer 120 has an opening OP overlapping the first electrode 118 , and the opening OP overlapping at least one conductive bump 108 .

Referring to FIG. 20, the light emitting layer 122 is formed in the opening OP. In one embodiment, the light emitting layer 122 may be formed by ink jet printing (IJP). For example, a liquid organic light-emitting material (not shown) can be disposed on the first electrode 118 and located in the opening OP through an inkjet coating process, and then a thin-film light-emitting layer 122 can be formed by a drying process. In some embodiments, the light emitting layer 122 may be a multi-layer structure including a hole injection layer (HIL), a hole transfer layer (HTL), an emission layer (EL), and an electron transport layer. layer (electron transfer layer, ETL). Fig. 20 is only shown in a one-layer structure for convenience of description and clear representation. In this embodiment, the light emitting layer 122 with a desired thickness can be formed by repeating the inkjet coating process and the curing process, but the invention is not limited thereto.

When a part of the light L1 emitted by the light emitting layer 122 travels toward the direction of the first electrode 118 , the first electrode 118 has an electrode protrusion P3 indirectly by disposing a plurality of conductive bumps 108 spaced apart from each other on the interlayer dielectric layer 106 . , the light L1 reflected by the first electrode 118 back to the light-emitting layer 122 can be prevented from being totally reflected at the interface between the first electrode 118 and the light-emitting layer 122 , so that the limitation of the waveguide of the first electrode 118 can be effectively reduced The resulting light output loss, thereby improving the light output efficiency.

Referring to FIG. 21 , the second electrode 124 is formed on the light-emitting layer 122 , and the first electrode 118 , the light-emitting layer 122 and the second electrode 124 together constitute the light-emitting element 126 . Here, the pixel structure 50 is completed. In some embodiments, the formation method of the second electrode 124 may be chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), evaporation (VTE), sputtering (SPT) or its combination.

To sum up, in the pixel structure and the manufacturing method thereof according to an embodiment of the present invention, when a part of the light emitted by the light-emitting layer travels toward the direction of the first electrode, the interlayer dielectric layer is provided with a plurality of spaced apart A conductive bump indirectly makes the first electrode have an electrode protrusion, which can avoid total reflection of the light reflected by the first electrode back to the light-emitting layer at the interface between the first electrode and the light-emitting layer. The waveguide of an electrode limits the light-extraction loss caused by the light-extraction efficiency, thereby improving the light-extraction efficiency.

10, 20, 30, 40, 50: pixel structure 100: Substrate 102: Buffer layer 104: Gate insulating layer 106: Interlayer dielectric layer 108, 108b, 108c, 108d: Conductive bumps 108e: Conductive bumps 108A: Conductive layer 110,110a: Insulation layer 112, 112a: Capacitor electrodes 114: Passivation layer 116: flat layer 118: The first electrode 118a: first conductive layer 118b: second conductive layer 118c: the third conductive layer 120,120a: pixel definition layer 122: light-emitting layer 124: Second electrode 126: Light-emitting element 128: vertical distance 214: Passivation layer 214P: Insulation bump 316: First flat layer 316P: Insulation bump 318: Second flat layer 1080, 1084: Group 1 1082, 1086: The second group CH: channel layer D: drain G: gate L1: light MK: photomask OP: opening P1, P2: Protrusions P3: Electrode protrusion P4: Protrusion PN: Pattern PR: Photoresist PR1: Exposure Department R1, R2, R3, R4: Recess S: source sw: sidewall T: Active element t1, t2, t3: thickness V1: Through hole x1,x2: spacing

Various aspects of the present disclosure can be understood by reading the following detailed description and corresponding drawings. It should be noted that various features in the drawings are not drawn to scale according to standard practice in the industry. In fact, the dimensions of the described features may be arbitrarily increased or decreased to facilitate clarity of discussion. FIG. 1 is a schematic cross-sectional view of a pixel structure according to an embodiment of the present invention. 2 to 7 are schematic top views of a conductive bump according to an embodiment of the present invention. FIG. 8A is a schematic cross-sectional view of a pixel structure according to another embodiment of the present invention. FIG. 8B is a schematic cross-sectional view of a pixel structure according to another embodiment of the present invention. FIG. 8C is a schematic cross-sectional view of a pixel structure according to another embodiment of the present invention. 9 to 21 are schematic cross-sectional views of a method for fabricating a pixel structure according to an embodiment of the present invention.

Domestic storage information (please note in the order of storage institution, date and number) none Foreign deposit information (please note in the order of deposit country, institution, date and number) none

10: Pixel structure

100: Substrate

102: Buffer layer

104: Gate insulating layer

106: Interlayer dielectric layer

108: Conductive bumps

110: Insulation layer

112: Capacitor electrode

114: Passivation layer

116: flat layer

118: The first electrode

118a: first conductive layer

118b: second conductive layer

118c: the third conductive layer

120: Pixel Definition Layer

122: light-emitting layer

124: Second electrode

126: Light-emitting element

CH: channel layer

D: drain

G: gate

L1: light

OP: opening

P1, P2: Protrusions

P3: Electrode protrusion

R1, R2, R3: Recess

S: source

T: Active element

Claims (10)

A pixel structure, comprising: a substrate; an interlayer dielectric layer on the substrate; an active element on the substrate and having a drain electrode and a channel layer, the drain electrode penetrating the interlayer dielectric layer to communicate with The channel layer is electrically connected; a plurality of conductive bumps are located on the interlayer dielectric layer and are separated from each other; a flat layer is located on the drain electrode and the conductive bumps; a first electrode penetrates the flat layer and is electrically connected to the drain of the active element, the first electrode has a plurality of electrode protrusions, each of the electrode protrusions is respectively overlapped with each of the conductive bumps; a pixel definition layer has an opening overlapping the first an electrode, and the opening overlaps at least one of the conductive bumps; a light-emitting layer is disposed in the opening and on the first electrode; and a second electrode is disposed on the light-emitting layer. The pixel structure of claim 1, wherein the conductive bumps and the drain contact a top surface of the interlayer dielectric layer. The pixel structure of claim 1, wherein the conductive bumps are distributed in point symmetry. The pixel structure of claim 1, further comprising: a passivation layer located between the flat layer and the conductive bumps, wherein the The passivation layer has a plurality of insulating bumps separated from each other, and each of the insulating bumps respectively overlaps and covers each of the conductive bumps. The pixel structure of claim 1, wherein the thickness of the flat layer is 1 to 10 microns. A pixel structure includes a substrate; an interlayer dielectric layer on the substrate; an active element on the substrate and has a drain electrode and a channel layer, the drain electrode penetrates the interlayer dielectric layer to communicate with the The channel layer is electrically connected; a first flat layer is located on the interlayer dielectric layer and has a plurality of insulating bumps spaced apart from each other; a second flat layer is located on the first flat layer, wherein the second The flat layer has a plurality of insulating protrusions; a first electrode is electrically connected to the drain of the active element, and has a plurality of electrode protrusions, each of which is overlapped on each of the insulating protrusions and each of the insulating bumps; a pixel definition layer with an opening overlapping the first electrode, and the opening overlapping at least one of the insulating bumps; a light-emitting layer disposed in the opening and on the first electrode; and a second electrode disposed on the light-emitting layer. The pixel structure of claim 6, wherein the first level The thickness of the flat layer is 1 to 30 microns, and the thickness of the second flat layer is 1 to 30 microns. The pixel structure of claim 6, wherein the insulating bumps are distributed in point symmetry. A manufacturing method of a pixel structure, comprising forming a channel layer on a substrate; forming a gate insulating layer on the channel layer; forming a gate electrode on the gate insulating layer; forming an interlayer dielectric layer to cover the gate electrode and the channel layer, wherein the interlayer dielectric layer has a plurality of through holes; a conductive layer is formed on the entire surface of the interlayer dielectric layer, wherein the conductive layer is filled in the through holes; the conductive layer is patterned, to form a source electrode, a drain electrode and a plurality of conductive bumps, wherein the source electrode, the drain electrode, the gate electrode and the channel layer constitute an active element, and the conductive bumps are separated from each other; forming a flat layer on the source electrode, the drain electrode and the conductive bumps; form a first electrode on the flat layer, the first electrode penetrates the flat layer and is electrically connected to the drain electrode; forms a pixel definition layer on the first electrode, the pixel definition layer has an opening overlapping the first electrode, and the opening overlaps at least one of the conductive bumps; forming a light-emitting layer in the opening; and A second electrode is formed on the light emitting layer. The method of claim 9, wherein the conductive bumps are distributed point-symmetrically.

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