TWI771040B - Active stylus receiving circuit and touch panel system using active stylus pen - Google Patents

Active stylus receiving circuit and touch panel system using active stylus pen Download PDF

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TWI771040B
TWI771040B TW110120453A TW110120453A TWI771040B TW I771040 B TWI771040 B TW I771040B TW 110120453 A TW110120453 A TW 110120453A TW 110120453 A TW110120453 A TW 110120453A TW I771040 B TWI771040 B TW I771040B
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logic
sum unit
equivalent logic
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quadrature
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TW202248814A (en
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蘇芳毅
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敦泰電子股份有限公司
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Abstract

An active stylus pen receiving circuit receives a vector data signal sent by an active stylus pen. The vector data signal carries vector data. The vector data includes in-phase data and quadrature data. The active stylus pen receiving circuit includes: a delta-sigma analog-to-digital converter for performing delta-sigma operation to convert the vector data signal into a 1-bit bit-stream; and a first logic gate circuit and a second logic gate circuit. With the first logic gate circuit, the 1-bit bit-stream and in-phase modulation carrier signal are subject to logic AND quadrature operation to generate demodulated in-phase data and, with the second logic gate circuit, the 1-bit bit-stream and quadrature modulation carrier signal are subject to logic AND quadrature operation to generate demodulated quadrature data, thereby obtaining demodulated vector data.

Description

主動筆接收電路及使用主動筆的觸控面板系統Active pen receiving circuit and touch panel system using active pen

本發明係關於主動筆的技術領域,尤指一種主動筆接收電路及使用主動筆的觸控面板系統。The present invention relates to the technical field of active pens, in particular to an active pen receiving circuit and a touch panel system using the active pen.

主動筆(Active stylus)已廣泛被使用於與具有觸控面板的電子裝置搭配,以提供輸入效果,其中,主動筆內部具有發射電路可發射出經過調變(modulation)的向量資料訊號,以由觸控面板所接收來檢測主動筆的座標。而為正確接收並解調變(demodulation)主動筆所發出的向量資料訊號,觸控面板上設置有多數感應器以感應前述向量資料訊號,並以對應的接收電路接收此向量資料訊號來進行解調變以獲得向量資料。Active stylus has been widely used in combination with electronic devices with touch panels to provide input effects, wherein the active stylus has a transmitting circuit inside which can emit modulated vector data signals to The coordinates received by the touch panel to detect the active pen. In order to correctly receive and demodulate the vector data signal sent by the active pen, most sensors are arranged on the touch panel to sense the vector data signal, and the corresponding receiving circuit receives the vector data signal for decoding. Modulation to obtain vector data.

在前述向量資料的調變、發射、接收及解調變的過程中,主動筆係例如以載波對向量資料進行調變,其中向量資料包含同相資料及正交資料,經調變後的向量資料訊號由主動筆發出,以由對應的接收電路所接收,接收電路係以一循續漸近式類比數位轉換器(Successive-approximation register analog-to-digital converter, SAR ADC)將所接收的向量資料訊號轉換為N位元的數位訊號(N例如為10),再以兩乘法器(multiplier)分別以同相載波及正交載波對此N位元的數位訊號進行解調變,據以解調出同相資料及正交資料,俾獲得原始的向量資料。In the process of modulating, transmitting, receiving and demodulating the vector data, the active pen modulates the vector data, for example, with a carrier wave, wherein the vector data includes in-phase data and quadrature data, and the modulated vector data The signal is sent by the active pen to be received by the corresponding receiving circuit. The receiving circuit converts the received vector data signal with a successive-approximation register analog-to-digital converter (SAR ADC). Convert it into an N-bit digital signal (for example, N is 10), and then use two multipliers to demodulate the N-bit digital signal with an in-phase carrier and a quadrature carrier respectively, so as to demodulate the in-phase signal. data and orthogonal data to obtain the original vector data.

然而,在前述使用主動筆的觸控面板的架構中,觸控面板需具有大量的感應器以能正確感應主動筆所發出的向量資料訊號,因此,對應的接收電路的數量亦極其龐大,而每一接收電路需使用一類比數位轉換器及兩乘法器,導致需要使用大量的類比數位轉換器及乘法器,不但硬體成本過高且佔用過多的電路面積而難以實現,此外,由於類比數位轉換器的資料率(data rate)決定了主動筆所發出訊號的取樣率,在電路面積與功耗之考量下,使用循續漸近式類比數位轉換器的資料率一般為1.6MHz,因此,不易提高訊號的取樣率,而影響訊號接收的品質。However, in the aforementioned structure of the touch panel using the active pen, the touch panel needs to have a large number of sensors to correctly sense the vector data signal sent by the active pen. Therefore, the number of corresponding receiving circuits is also extremely large. Each receiving circuit needs to use an analog-to-digital converter and two multipliers, resulting in the need to use a large number of analog-to-digital converters and multipliers. The data rate of the converter determines the sampling rate of the signal sent by the active pen. Under the consideration of circuit area and power consumption, the data rate of using a progressive analog digital converter is generally 1.6MHz. Therefore, it is not easy to Increase the sampling rate of the signal and affect the quality of the signal reception.

因此,習知主動筆接收電路的設計上,實仍存在有諸多缺失而有予以改善之必要。Therefore, there are still many deficiencies in the design of the conventional active pen receiving circuit, and it is necessary to improve it.

本發明之目的主要係在提供一種主動筆接收電路及使用主動筆的觸控面板系統,藉由使用積分三角類比至數位轉換器及邏輯及閘來解調變出向量資料,不但可有效提升訊號接收的品質,且因無需使用硬體乘法器,而可大幅降低硬體成本及節省電路面積,進而有效減少功耗。The main purpose of the present invention is to provide an active pen receiving circuit and a touch panel system using an active pen. By using the sigma-delta analog-to-digital converter and logic sum gates to demodulate and transform vector data, not only can the signal be effectively improved The receiving quality is improved, and the hardware cost and circuit area can be greatly reduced because the hardware multiplier is not required, thereby effectively reducing the power consumption.

依據本發明之一特色,其提出一種主動筆接收電路,主動筆接收電路接收由一主動筆所發出的向量資料訊號,向量資料訊號載有向量資料,向量資料包含同相資料及正交資料,主動筆接收電路包含:一積分三角類比數位轉換器,將向量資料訊號以積分三角運算轉換為1位元的位元流;以及一第一邏輯閘電路與一第二邏輯閘電路,第一邏輯閘電路將1位元的位元流與同相調變載波訊號進行邏輯及正交運算,而產生解調變後的同相資料,第二邏輯閘電路將1位元的位元流與正交調變載波訊號進行邏輯及正交運算,而產生解調變後的正交資料,據以獲得解調變後的向量資料。According to a feature of the present invention, an active pen receiving circuit is provided. The active pen receiving circuit receives a vector data signal sent by an active pen. The vector data signal carries vector data, and the vector data includes in-phase data and quadrature data. The pen receiving circuit includes: a sigma-delta analog-to-digital converter, which converts the vector data signal into a 1-bit bit stream through sigma-delta operation; and a first logic gate circuit and a second logic gate circuit, the first logic gate The circuit performs logic and quadrature operations on the 1-bit bit stream and the in-phase modulated carrier signal to generate demodulated in-phase data. The second logic gate circuit converts the 1-bit bit stream and quadrature modulation. The carrier signal performs logic and quadrature operations to generate demodulated quadrature data, thereby obtaining demodulated vector data.

依據本發明之另一特色,其提出一種觸控面板系統,觸控面板系統包括:一主動筆,發出載有向量資料的向量資料訊號,其中向量資料包含同相資料及正交資料;一觸控面板,具有多數感應器,以感應由主動筆所發出的向量資料訊號;以及,一接收裝置,具有多數主動筆接收電路,每一主動筆接收電路連接至少一感應器,且包含:一積分三角類比數位轉換器,將向量資料訊號以積分三角運算轉換為1位元的位元流;以及一第一邏輯閘電路與一第二邏輯閘電路,第一邏輯閘電路將1位元的位元流與同相調變載波訊號進行邏輯及正交運算,而產生解調變後的同相資料,第二邏輯閘電路將1位元的位元流與正交調變載波訊號進行邏輯及正交運算,而產生解調變後的正交資料,據以獲得解調變後的向量資料。According to another feature of the present invention, a touch panel system is provided. The touch panel system includes: an active pen that sends out a vector data signal carrying vector data, wherein the vector data includes in-phase data and quadrature data; a touch The panel has a plurality of sensors to sense the vector data signal sent by the active pen; and a receiving device has a plurality of active pen receiving circuits, each active pen receiving circuit is connected to at least one sensor, and includes: an integral delta The analog-to-digital converter converts the vector data signal into a 1-bit bit stream by integral triangular operation; and a first logic gate circuit and a second logic gate circuit, the first logic gate circuit converts the 1-bit bits The stream and the in-phase modulated carrier signal perform logical and quadrature operations to generate demodulated in-phase data. The second logic gate circuit performs logical and quadrature operations on the 1-bit bit stream and the quadrature modulated carrier signal. , and generate the demodulated and transformed quadrature data, so as to obtain the demodulated and transformed vector data.

以上概述與接下來的詳細說明皆為示範性質,是為了進一步說明本發明的申請專利範圍,而有關本發明的其他目的與優點,將在後續的說明與圖式加以闡述。The above overview and the following detailed description are exemplary in nature, and are intended to further illustrate the scope of the present invention, and other objects and advantages of the present invention will be explained in the following descriptions and drawings.

為了使本發明的目的、技術方案及優點更加清楚明白,以下結合附圖及實施例,對本發明進行進一步詳細說明。應當理解,此處所描述的具體實施例僅僅用以解釋本發明的實施方式,並不用於限定本發明。In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the embodiments of the present invention, and are not used to limit the present invention.

圖1所示為依據本發明之使用主動筆的觸控面板系統,其包括有一主動筆10、一觸控面板20、及一接收裝置30,其中,接收裝置30是設置於一積體電路(IC)60中,且積體電路60更具有多數多工器(multiplexer)40及一微控制器(MCU)50。主動筆10具有筆尖(Tip)11及筆環(Ring)13,可發射出向量資料訊號,而觸控面板20具有多數呈矩陣排列的感應器Sx,可感應主動筆10之筆尖11或筆環13所發出之向量資料訊號,接收裝置30具有多數主動筆接收電路31,以接收向量資料訊號來進行處理以獲得向量資料X(t)。1 shows a touch panel system using an active pen according to the present invention, which includes an active pen 10, a touch panel 20, and a receiving device 30, wherein the receiving device 30 is disposed in an integrated circuit ( IC) 60, and the integrated circuit 60 further has a plurality of multiplexers (multiplexers) 40 and a microcontroller (MCU) 50. The active pen 10 has a tip 11 and a ring 13 that can emit vector data signals, and the touch panel 20 has a plurality of sensors Sx arranged in a matrix, which can sense the tip 11 or the ring of the active pen 10 13. The receiving device 30 has a plurality of active pen receiving circuits 31 to receive the vector data signal for processing to obtain the vector data X(t).

圖2顯示前述主動筆10發射向量資料訊號的示意圖,如圖所示,前述主動筆10係例如以載波訊號cos(2πωt)+sin(2πωt)對向量資料X(t)進行調變(modulation),以使向量資料訊號載有向量資料X(t),其中向量資料X(t)包含同相資料Xi(t)及正交資料Xq(t),經調變後的向量資料訊號Xi(t)cos(2πωt)+Xq(t)sin(2πωt)由主動筆10之筆尖11或筆環13發出。FIG. 2 is a schematic diagram of the vector data signal emitted by the active pen 10. As shown in the figure, the active pen 10 modulates the vector data X(t) with the carrier signal cos(2πωt)+sin(2πωt), for example. , so that the vector data signal carries the vector data X(t), wherein the vector data X(t) includes the in-phase data Xi(t) and the quadrature data Xq(t), and the modulated vector data signal Xi(t) cos(2πωt)+Xq(t) sin(2πωt) is emitted by the pen tip 11 or the pen ring 13 of the active pen 10 .

請一併參照圖1及圖2,前述觸控面板20的感應器Sx可感應主動筆10之筆尖11或筆環13所發出之向量資料訊號Xi(t)cos(2πωt)+Xq(t)sin(2πωt),並由接收裝置30的對應主動筆接收電路31所接收,每一感應器Sx可對應一主動筆接收電路31,惟實際上為了減少所需主動筆接收電路31的數量,每一主動筆接收電路31係連接至少一感應器Sx,例如可將N個感應器Sx透過一N對1多工器(multiplexer)40連接至一主動筆接收電路31,其中N為大於1之整數,以使一主動筆接收電路31能夠以多工的方式接收N個感應器Sx 所感應之向量資料訊號Xi(t)cos(2πωt)+Xq(t)sin(2πωt),亦即,藉由多工器40之設置,使得N個感應器Sx對應一主動筆接收電路31,於圖1中顯示N=4,但此僅是舉例,並非用於限制本發明。Please refer to FIG. 1 and FIG. 2 together, the sensor Sx of the touch panel 20 can sense the vector data signal Xi(t)cos(2πωt)+Xq(t) emitted by the pen tip 11 or the pen ring 13 of the active pen 10 sin(2πωt), and received by the corresponding active pen receiving circuit 31 of the receiving device 30, each sensor Sx can correspond to an active pen receiving circuit 31, but in fact, in order to reduce the number of required active pen receiving circuits 31, each sensor Sx An active pen receiving circuit 31 is connected to at least one sensor Sx, for example, N sensors Sx can be connected to an active pen receiving circuit 31 through an N-to-1 multiplexer 40, wherein N is an integer greater than 1 , so that an active pen receiving circuit 31 can receive the vector data signals Xi(t)cos(2πωt)+Xq(t)sin(2πωt) induced by the N sensors Sx in a multiplexed manner, that is, by The multiplexer 40 is set so that the N sensors Sx correspond to an active pen receiving circuit 31 , and N=4 is shown in FIG. 1 , but this is only an example and is not intended to limit the present invention.

圖3為前述主動筆接收電路31的示意圖,如圖所示,每一主動筆接收電路31具有一積分三角類比數位轉換器 (Delta-Sigma ADC) 311、及第一邏輯閘電路312與第二邏輯閘電路313,其中,積分三角類比數位轉換器311用以將接收的向量資料訊號Xi(t)cos(2πωt)+Xq(t)sin(2πωt) 以積分三角運算轉換為1位元的位元流的數位訊號,此1位元的位元流再經由第一邏輯閘電路312與同相調變載波訊號cos(2πωt)進行邏輯及正交運算以達成解調變之效果,而產生解調變後的同相資料Xi(t),且1位元的位元流亦經由第二邏輯閘電路313與正交調變載波訊號sin(2πωt)進行邏輯及正交運算以達成解調變之效果,而產生解調變後的正交資料Xq(t),據此獲得解調變後的向量資料X(t),並傳送至如圖1所示的微控制器 50以進行觸控輸入,經過運算後得到觸控座標。於圖3中顯示第一邏輯閘電路312具有多數個第一等效邏輯及單元321,每一第一等效邏輯及單元321具有一第一輸入端a連接至1位元的位元流、一第二輸入端b連接至同相調變載波訊號cos(2πωt)中的一對應位元、及一輸出端c用以輸出同相資料Xi(t);第二邏輯閘電路313具有多數個第二等效邏輯及單元322,每一第二等效邏輯及單元322具有一第一輸入端a連接至該1位元的位元流、一第二輸入端b連接至正交調變載波訊號sin(2πωt)中的一對應位元、及一輸出端c用以輸出正交資料Xq(t),其中,每一邏輯閘電路312,313所具有的等效邏輯及單元321,322的個數是由同相調變載波訊號cos(2πωt)及正交調變載波訊號sin(2πωt)的精準度所決定,亦即,當同相調變載波訊號cos(2πωt)或正交調變載波訊號sin(2πωt)為具有 M位元的精準度時,每一邏輯閘電路312,313具有M個等效邏輯及單元321,322,據此,M個等效邏輯及單元321,322中的每一等效邏輯及單元321,322的一輸入端a連接積分三角類比數位轉換器 311輸出的1位元的位元流,另一輸入端b則連接同相調變載波訊號cos(2πωt)或正交調變載波訊號sin(2πωt)的M位元中的1位元,而使得一邏輯閘電路312,313的M個等效邏輯及單元321,322的輸出端c得以輸出同相資料Xi(t)或正交資料Xq(t)。FIG. 3 is a schematic diagram of the aforementioned active pen receiving circuit 31 . As shown in the figure, each active pen receiving circuit 31 has a delta-sigma ADC 311 , a first logic gate circuit 312 and a second logic gate circuit 312 . The logic gate circuit 313, wherein the sigma-delta analog-to-digital converter 311 is used to convert the received vector data signal Xi(t)cos(2πωt)+Xq(t)sin(2πωt) into 1-bit bits by sigma-delta operation The digital signal of the bit stream, the 1-bit bit stream is then subjected to logic and quadrature operations with the in-phase modulated carrier signal cos(2πωt) through the first logic gate circuit 312 to achieve the effect of demodulation, and demodulation is generated. The transformed in-phase data Xi(t), and the 1-bit bit stream is also subjected to logic and quadrature operations with the quadrature modulation carrier signal sin(2πωt) through the second logic gate circuit 313 to achieve the effect of demodulation , and the demodulated quadrature data Xq(t) is generated, and the demodulated vector data X(t) is obtained accordingly, and sent to the microcontroller 50 as shown in FIG. 1 for touch input, The touch coordinates are obtained after calculation. 3 shows that the first logic gate circuit 312 has a plurality of first equivalent logic and units 321, each of which has a first input terminal a connected to a 1-bit bit stream, A second input terminal b is connected to a corresponding bit in the in-phase modulated carrier signal cos(2πωt) and an output terminal c for outputting the in-phase data Xi(t); the second logic gate circuit 313 has a plurality of second Equivalent logical sum unit 322, each second equivalent logical sum unit 322 has a first input terminal a connected to the 1-bit bit stream, and a second input terminal b connected to the quadrature modulation carrier signal sin A corresponding bit in (2πωt) and an output terminal c are used to output the quadrature data Xq(t), wherein the equivalent logic of each logic gate circuit 312, 313 and the number of units 321, 322 are adjusted by in-phase modulation It is determined by the accuracy of the variable carrier signal cos(2πωt) and the quadrature modulation carrier signal sin(2πωt), that is, when the in-phase modulation carrier signal cos(2πωt) or the quadrature modulation carrier signal sin(2πωt) has At the M-bit precision, each logic gate circuit 312, 313 has M equivalent logic sum units 321, 322, accordingly, each of the M equivalent logic sum units 321, 322 has an input terminal a of the equivalent logic sum unit 321, 322 The 1-bit bit stream output by the sigma-delta-analog digital converter 311 is connected, and the other input terminal b is connected to the M bits of the in-phase modulation carrier signal cos(2πωt) or the quadrature modulation carrier signal sin(2πωt). 1 bit, so that the output terminals c of the M equivalent logic sum units 321, 322 of a logic gate circuit 312, 313 can output the in-phase data Xi(t) or the quadrature data Xq(t).

圖4為主動筆接收電路的一實施例的電路圖。於此實施例中,前述等效邏輯及單元321,322係由邏輯及閘(AND gate)所實現,如圖所示,第一等效邏輯及單元321或第二等效邏輯及單元321為一邏輯及閘,其中,邏輯及閘具有兩輸入端分別作為第一等效邏輯及單元321或第二等效邏輯及單元322的第一輸入端a及第二輸入端b、及一輸出端作為第一等效邏輯及單元321或第二等效邏輯及單元322的輸出端c。FIG. 4 is a circuit diagram of an embodiment of an active pen receiving circuit. In this embodiment, the aforementioned equivalent logic and units 321 and 322 are implemented by logic AND gates. As shown in the figure, the first equivalent logic and unit 321 or the second equivalent logic and unit 321 is a logic and gate, wherein the logic AND gate has two input terminals as the first input terminal a and the second input terminal b of the first equivalent logic sum unit 321 or the second equivalent logic sum unit 322 respectively, and an output terminal as the first input terminal a and the second input terminal b of the second equivalent logic sum unit 322 An output terminal c of an equivalent logic sum unit 321 or a second equivalent logic sum unit 322 .

圖5為主動筆接收電路的另一實施例的電路圖。於此實施例中,前述等效邏輯及單元321,322係由2至1多工器(multiplexer)所實現,如圖所示,第一等效邏輯及單元321或第二等效邏輯及單元322為一2至1多工器,其中,2至1多工器具有一選擇端作為第一等效邏輯及單元321或第二等效邏輯及單元322的第一輸入端a、兩輸入端分別作為第一等效邏輯及單元321或第二等效邏輯及單元322的第二輸入端b及輸入邏輯0、及一輸出端作為第一等效邏輯及單元321或第二等效邏輯及單元322的輸出端c。FIG. 5 is a circuit diagram of another embodiment of an active pen receiving circuit. In this embodiment, the aforementioned equivalent logic and units 321 and 322 are implemented by a 2-to-1 multiplexer. As shown in the figure, the first equivalent logic and unit 321 or the second equivalent logic and unit 322 are A 2-to-1 multiplexer, wherein the 2-to-1 multiplexer has a selection terminal as the first input terminal a of the first equivalent logic sum unit 321 or the second equivalent logic sum unit 322, and the two input terminals are respectively used as the first input terminal a of the equivalent logic sum unit 321 or the second equivalent logic sum unit 322. The second input terminal b of an equivalent logic sum unit 321 or the second equivalent logic sum unit 322 and the input logic 0, and an output terminal are used as the first equivalent logic sum unit 321 or the second equivalent logic sum unit 322. output c.

圖6為主動筆接收電路的再一實施例的電路圖。於此實施例中,前述等效邏輯及單元321,322係由邏輯或閘(OR gate)及邏輯反閘(NOT gate)所實現,如圖所示,第一等效邏輯及單元321或第二等效邏輯及單元322係由一邏輯或閘及三個邏輯反閘所構成,其中,邏輯或閘具有兩輸入端分別連接一邏輯反閘以作為第一等效邏輯及單元321或第二等效邏輯及單元322的第一輸入端a及第二輸入端b、及一輸出端連接一邏輯反閘以作為第一等效邏輯及單元321或第二等效邏輯及單元322的輸出端c。FIG. 6 is a circuit diagram of still another embodiment of an active pen receiving circuit. In this embodiment, the aforementioned equivalent logic and units 321, 322 are implemented by logical OR gates and logical inversion gates (NOT gate), as shown in the figure, the first equivalent logic and units 321 or the second, etc. The effective logic AND unit 322 is composed of a logical OR gate and three logical inversion gates, wherein the logical OR gate has two input terminals respectively connected to a logic inversion gate as the first equivalent logic sum unit 321 or the second equivalent logic The first input terminal a, the second input terminal b, and an output terminal of the logic sum unit 322 are connected to a logic inversion gate as the output end c of the first equivalent logic sum unit 321 or the second equivalent logic sum unit 322 .

據此,本發明能以簡單的組合邏輯元件來實現邏輯閘電路312,313,達成無需使用複雜的乘法器電路即可進行訊號解調變的功效。此外,除了使用前述邏輯及閘、2至1多工器、邏輯或閘及邏輯反閘之外,前述等效邏輯及單元321,322亦可以其他組合邏輯元件來實現,例如使用一邏輯反及閘(NAND gate)具有一輸出端連接一邏輯反閘、或是使用一邏輯反或閘(NOR gate)具有二輸入端分別連接二邏輯反閘。Accordingly, the present invention can realize the logic gate circuits 312 and 313 with simple combinational logic elements, so as to achieve the effect of signal demodulation without using a complex multiplier circuit. In addition, in addition to using the aforementioned logic AND gates, 2-to-1 multiplexers, logic OR gates, and logic inversion gates, the aforementioned equivalent logic sum units 321 and 322 can also be implemented by other combinational logic elements, such as using a logic inversion and gate ( NAND gate) has an output terminal connected to a logic inversion gate, or a logic inversion NOR gate (NOR gate) with two input terminals connected to the two logic inversion gates respectively.

前述積分三角類比至數位轉換器311為一種超取樣(Oversampling rate)類比至數位轉換器,利用雜訊移頻(Noise Shaping)與超取樣技術來達到足夠的訊號雜訊比(Signal to Noise Ratio,SNR),其二階的輸入(In)/輸出(out)關係可表示為: out(z)=In(z)+Q(z)×(1−Z -1) 2, out(z)=In(z)*SFT+Q(z)*NFT, 其中,z/Z代表z域轉換(z domain transform),STF代表訊號轉變函數(signal transfer function),Q(z) 代表z域量化(z domain quantization)雜訊,NTF代表雜訊轉變函數(noise transfer function),當輸入訊號進入積分三角調變且經過超取樣與雜訊移頻後,不再經由數位濾波降頻(Decimation),直接經由正交調變取得同相資料(Xi_rx)與正交資料(Xq_rx),而雜訊移頻後則被正交調變所濾除,即可達到類比數位轉換器的功能,因此,前述主動筆接收電路31所進行的訊號處理可表示為: ADC IN= Xi×cos(2πωt)+Xq×sin(2πωt), ADC OUT= ADC IN*SFT+Qn*NFT, Xi_rx = Xi+Qn×NFT×cos(2πωt), Xq_rx = Xq+Qn×NFT×sin(2πωt), 其中,ADC IN代表積分三角類比至數位轉換器311的輸入,ADC OUT代表積分三角類比至數位轉換器311的輸出,Xi代表主動筆10所發射的同相(in phase)資料,Xq代表主動筆10所發射的正交(quadrature)資料,cos(2πωt)代表同相調變載波訊號,sin(2πωt) 代表正交調變載波訊號,Xi_rx代表主動筆接收電路31輸出資料(解調後的同相資料),Xq_rx代表主動筆接收電路31輸出資料(解調後正交資料),STF代表訊號轉變函數,Qn代表時域量化(time domain quantization)雜訊,NTF代表雜訊轉變函數。 The aforesaid sigma-delta analog-to-digital converter 311 is an oversampling rate analog-to-digital converter that utilizes noise shaping and oversampling techniques to achieve a sufficient signal-to-noise ratio, SNR), its second-order input (In)/output (out) relationship can be expressed as: out(z)=In(z)+Q(z)×(1−Z -1 ) 2 , out(z)=In (z)*SFT+Q(z)*NFT, where z/Z stands for z domain transform, STF stands for signal transfer function, Q(z) stands for z domain quantization (z domain transform) quantization) noise, NTF stands for noise transfer function (noise transfer function), when the input signal enters the integral triangle modulation and after oversampling and noise frequency shifting, it is no longer through digital filtering and downscaling (Decimation), directly through the positive The in-phase data (Xi_rx) and the quadrature data (Xq_rx) are obtained by intermodulation, and the noise is filtered out by the quadrature modulation after frequency shifting, which can achieve the function of an analog-to-digital converter. Therefore, the above-mentioned active pen receiving circuit The signal processing performed by 31 can be expressed as: ADC IN = Xi×cos(2πωt)+Xq×sin(2πωt), ADC OUT = ADC IN *SFT+Qn*NFT, Xi_rx = Xi+Qn×NFT×cos(2πωt ), Xq_rx = Xq+Qn×NFT×sin(2πωt), where ADC IN represents the input of the sigma-delta analog to digital converter 311 , ADC OUT represents the output of the sigma-delta analog to the digital converter 311 , Xi represents the active pen 10 The transmitted in-phase data, Xq represents the quadrature data transmitted by the active pen 10, cos(2πωt) represents the in-phase modulated carrier signal, sin(2πωt) represents the quadrature modulated carrier signal, and Xi_rx represents the The output data of the active pen receiving circuit 31 (demodulated in-phase data), Xq_rx represents the output data of the active pen receiving circuit 31 (the demodulated quadrature data), STF represents the signal transition function, and Qn represents the time domain quantization (time domain quantization) Noise, NTF stands for Noise Transfer Function.

於前述主動筆接收電路31中,積分三角類比至數位轉換器311的資料率可達10MHz或10MHz以上,因此具有極高的訊號取樣率,可有效提升訊號接收的品質,再者,由於積分三角類比至數位轉換器311輸出的數位訊號為1位元的位元流,因此以邏輯閘電路312,313對1位元的位元流與同相調變載波訊號cos(2πωt)或正交調變載波訊號sin(2πωt)進行邏輯及正交運算即可達成解調變之效果,不但運算簡單且無需使用硬體乘法器,因此可大幅降低硬體成本及節省電路面積,進而有效減少功耗。In the above-mentioned active pen receiving circuit 31, the data rate of the sigma-delta analog to digital converter 311 can reach 10MHz or more, so it has a very high signal sampling rate, which can effectively improve the quality of signal reception. The digital signal output by the analog-to-digital converter 311 is a 1-bit bit stream, so the logic gate circuits 312, 313 are used to modulate the 1-bit bit stream and the in-phase modulation carrier signal cos(2πωt) or the quadrature modulation carrier signal Sin(2πωt) can achieve the effect of demodulation by performing logic and quadrature operations. Not only is the operation simple, but no hardware multiplier is required. Therefore, the hardware cost and circuit area can be greatly reduced, thereby effectively reducing power consumption.

上述實施例僅係為了方便說明而舉例而已,本發明所主張之權利範圍自應以申請專利範圍所述為準,而非僅限於上述實施例。The above-mentioned embodiments are only examples for convenience of description, and the scope of the claims claimed in the present invention should be based on the scope of the patent application, rather than being limited to the above-mentioned embodiments.

10:主動筆 11:筆尖 13:筆環 20:觸控面板 30:接收裝置 31:主動筆接收電路 Sx:感應器 40:多工器 50:微控制器 60:積體電路 311:積分三角類比數位轉換器 312,313:邏輯閘電路 321,322:等效邏輯及單元 a,b:輸入端 c:輸出端10: Active Pen 11: Nib 13: pen ring 20: Touch panel 30: Receiver 31: Active pen receiving circuit Sx: Sensor 40: Multiplexer 50: Microcontroller 60: Integrated Circuits 311: Integral-Delta-Analog-to-Digital Converter 312, 313: Logic Gate Circuits 321, 322: Equivalent Logic and Units a,b: input terminal c: output terminal

圖1顯示依據本發明之使用主動筆的觸控面板系統。 圖2顯示主動筆發射向量資料訊號的示意圖。 圖3為主動筆接收電路的示意圖。 圖4為主動筆接收電路的一實施例的電路圖。 圖5為主動筆接收電路的另一實施例的電路圖。 圖6為主動筆接收電路的再一實施例的電路圖。 FIG. 1 shows a touch panel system using an active pen according to the present invention. FIG. 2 shows a schematic diagram of the active pen emitting vector data signals. FIG. 3 is a schematic diagram of an active pen receiving circuit. FIG. 4 is a circuit diagram of an embodiment of an active pen receiving circuit. FIG. 5 is a circuit diagram of another embodiment of an active pen receiving circuit. FIG. 6 is a circuit diagram of still another embodiment of an active pen receiving circuit.

311:積分三角類比數位轉換器 311: Integral-Delta-Analog-to-Digital Converter

312,313:邏輯閘電路 312, 313: Logic Gate Circuits

321,322:等效邏輯及單元 321, 322: Equivalent Logic and Units

a,b:輸入端 a,b: input terminal

c:輸出端 c: output terminal

Claims (18)

一種主動筆接收電路,接收由一主動筆所發出的向量資料訊號,該向量資料訊號載有向量資料,該向量資料包含同相資料及正交資料,該主動筆接收電路包含: 一積分三角類比數位轉換器,將該向量資料訊號以積分三角運算轉換為1位元的位元流;以及 一第一邏輯閘電路與一第二邏輯閘電路,該第一邏輯閘電路將該1位元的位元流與同相調變載波訊號進行邏輯及正交運算,而產生解調變後的該同相資料,該第二邏輯閘電路將該1位元的位元流與正交調變載波訊號進行邏輯及正交運算,而產生解調變後的該正交資料,據以獲得解調變後的該向量資料。 An active pen receiving circuit receives a vector data signal sent by an active pen, the vector data signal carries vector data, the vector data includes in-phase data and quadrature data, and the active pen receiving circuit includes: a sigma-delta analog-to-digital converter that converts the vector data signal into a 1-bit bit stream using sigma-delta operations; and a first logic gate circuit and a second logic gate circuit, the first logic gate circuit performs logic and quadrature operations on the 1-bit bit stream and the in-phase modulated carrier signal to generate the demodulated In-phase data, the second logic gate circuit performs logic and quadrature operations on the 1-bit bit stream and the quadrature modulation carrier signal to generate the demodulated quadrature data, so as to obtain the demodulation modulation After the vector data. 如請求項1所述之主動筆接收電路,其中,該向量資料訊號為:Xi(t)cos(2πωt)+Xq(t)sin(2πωt),當中,Xi(t)代表同相資料,Xq(t) 代表正交資料,cos(2πωt)代表同相調變載波訊號,sin(2πωt) 代表正交調變載波訊號。The active pen receiving circuit of claim 1, wherein the vector data signal is: Xi(t)cos(2πωt)+Xq(t)sin(2πωt), wherein Xi(t) represents in-phase data, Xq( t) represents the quadrature data, cos(2πωt) represents the in-phase modulated carrier signal, and sin(2πωt) represents the quadrature modulated carrier signal. 如請求項1所述之主動筆接收電路,其中,該積分三角類比至數位轉換器的資料率大於或等於10MHz。The active pen receiving circuit of claim 1, wherein the data rate of the sigma-delta analog-to-digital converter is greater than or equal to 10MHz. 如請求項1所述之主動筆接收電路,其中,該積分三角類比至數位轉換器具有二階的輸入/輸出關係為: out(z)=In(z)+Q(z)×(1−Z -1) 2;及 out(z)=In(z)*SFT+Q(z)*NFT, 其中,z/Z代表z域轉換,STF代表訊號轉變函數,Q(z) 代表z域量化雜訊,NTF代表雜訊轉變函數。 The active pen receiving circuit of claim 1, wherein the sigma-delta analog-to-digital converter has a second-order input/output relationship: out(z)=In(z)+Q(z)×(1−Z -1 ) 2 ; and out(z)=In(z)*SFT+Q(z)*NFT, where z/Z represents z-domain transformation, STF represents signal transition function, and Q(z) represents z-domain quantization noise information, NTF stands for Noise Transfer Function. 如請求項1所述之主動筆接收電路,其中,該第一邏輯閘電路具有多數個第一等效邏輯及單元,每一第一等效邏輯及單元具有一第一輸入端連接至該1位元的位元流、一第二輸入端連接至該同相調變載波訊號中的一對應位元、及一輸出端用以輸出該同相資料;該第二邏輯閘電路具有多數個第二等效邏輯及單元,每一第二等效邏輯及單元具有一第一輸入端連接至該1位元的位元流、一第二輸入端連接至該正交調變載波訊號中的一對應位元、及一輸出端用以輸出該正交資料。The active pen receiving circuit of claim 1, wherein the first logic gate circuit has a plurality of first equivalent logic and units, and each first equivalent logic and unit has a first input terminal connected to the 1 A bit stream of bits, a second input terminal connected to a corresponding bit in the in-phase modulated carrier signal, and an output terminal for outputting the in-phase data; the second logic gate circuit has a plurality of second, etc. Effective logic and unit, each second equivalent logic and unit has a first input connected to the 1-bit bit stream, and a second input connected to a corresponding bit in the quadrature modulated carrier signal element, and an output terminal for outputting the orthogonal data. 如請求項5所述之主動筆接收電路,其中,該第一等效邏輯及單元或第二等效邏輯及單元為一邏輯及閘具有兩輸入端分別作為該第一等效邏輯及單元或第二等效邏輯及單元的第一輸入端及第二輸入端、及一輸出端作為該第一等效邏輯及單元或第二等效邏輯及單元的輸出端。The active pen receiving circuit of claim 5, wherein the first equivalent logic sum unit or the second equivalent logic sum unit is a logic sum gate having two input terminals as the first equivalent logic sum unit or The first input terminal and the second input terminal of the second equivalent logic sum unit, and an output terminal are used as the output end of the first equivalent logic sum unit or the second equivalent logic sum unit. 如請求項5所述之主動筆接收電路,其中,該第一等效邏輯及單元或第二等效邏輯及單元為一2至1多工器,該2至1多工器具有一選擇端作為該第一等效邏輯及單元或第二等效邏輯及單元的第一輸入端、兩輸入端分別作為該第一等效邏輯及單元或第二等效邏輯及單元的第二輸入端及輸入邏輯0、及一輸出端作為該第一等效邏輯及單元或第二等效邏輯及單元的輸出端。The active pen receiving circuit of claim 5, wherein the first equivalent logic sum unit or the second equivalent logic sum unit is a 2-to-1 multiplexer, and the 2-to-1 multiplexer has a selection terminal as a The first input terminal and the two input terminals of the first equivalent logic sum unit or the second equivalent logic sum unit are respectively used as the second input terminal and input of the first equivalent logic sum unit or the second equivalent logic sum unit A logic 0 and an output terminal are used as the output terminal of the first equivalent logic sum unit or the second equivalent logic sum unit. 如請求項5所述之主動筆接收電路,其中,該第一等效邏輯及單元或第二等效邏輯及單元為一邏輯或閘具有兩輸入端分別連接一邏輯反閘以作為該第一等效邏輯及單元或第二等效邏輯及單元的第一輸入端及第二輸入端、及一輸出端連接一邏輯反閘以作為該第一等效邏輯及單元或第二等效邏輯及單元的輸出端。The active pen receiving circuit as claimed in claim 5, wherein the first equivalent logic sum unit or the second equivalent logic sum unit is a logic OR gate with two input ends respectively connected to a logic inversion gate as the first The first input terminal and the second input terminal of the equivalent logic sum unit or the second equivalent logic sum unit, and an output terminal are connected with a logic inversion gate as the first equivalent logic sum unit or the second equivalent logic sum unit output of the unit. 一種觸控面板系統,包括: 一主動筆,發出載有向量資料的向量資料訊號,其中該向量資料包含同相資料及正交資料; 一觸控面板,具有多數感應器,以感應由該主動筆所發出的該向量資料訊號;以及 一接收裝置,具有多數主動筆接收電路,每一主動筆接收電路連接至少一感應器,且包含: 一積分三角類比數位轉換器,將該向量資料訊號以積分三角運算轉換為1位元的位元流;以及 一第一邏輯閘電路與一第二邏輯閘電路,該第一邏輯閘電路將該1位元的位元流與同相調變載波訊號進行邏輯及正交運算,而產生解調變後的該同相資料,該第二邏輯閘電路將該1位元的位元流與正交調變載波訊號進行邏輯及正交運算,而產生解調變後的該正交資料,據以獲得解調變後的該向量資料。 A touch panel system, comprising: an active pen that emits a vector data signal carrying vector data, wherein the vector data includes in-phase data and quadrature data; a touch panel with a plurality of sensors for sensing the vector data signal sent by the active pen; and A receiving device has a plurality of active pen receiving circuits, each active pen receiving circuit is connected to at least one sensor, and includes: a sigma-delta analog-to-digital converter that converts the vector data signal into a 1-bit bit stream using sigma-delta operations; and a first logic gate circuit and a second logic gate circuit, the first logic gate circuit performs logic and quadrature operations on the 1-bit bit stream and the in-phase modulated carrier signal to generate the demodulated In-phase data, the second logic gate circuit performs logic and quadrature operations on the 1-bit bit stream and the quadrature modulation carrier signal to generate the demodulated quadrature data, so as to obtain the demodulation modulation After the vector data. 如請求項9所述之觸控面板系統,其中,該主動筆以載波訊號對向量資料進行調變而產生該向量資料訊號為:Xi(t)cos(2πωt)+Xq(t)sin(2πωt),當中,Xi(t)代表同相資料,Xq(t) 代表正交資料,cos(2πωt) 代表同相調變載波訊號,sin(2πωt)代表正交調變載波訊號。The touch panel system of claim 9, wherein the active pen modulates vector data with a carrier signal to generate the vector data signal: Xi(t)cos(2πωt)+Xq(t)sin(2πωt ), where Xi(t) represents the in-phase data, Xq(t) represents the quadrature data, cos(2πωt) represents the in-phase modulated carrier signal, and sin(2πωt) represents the quadrature modulated carrier signal. 如請求項9所述之觸控面板系統,其中,該觸控面板中的多數感應器中的N個感應器透過一N對1多工器連接至一主動筆接收電路,當中N為大於1之整數。The touch panel system of claim 9, wherein N sensors in the plurality of sensors in the touch panel are connected to an active pen receiving circuit through an N-to-1 multiplexer, wherein N is greater than 1 the integer. 如請求項9所述之觸控面板系統,其中,該向量資料訊號為:Xi(t)cos(2πωt)+Xq(t)sin(2πωt),當中,Xi(t)代表同相資料,Xq(t)代表正交資料,cos(2πωt)代表同相調變載波訊號,sin(2πωt)代表正交調變載波訊號。The touch panel system according to claim 9, wherein the vector data signal is: Xi(t)cos(2πωt)+Xq(t)sin(2πωt), wherein Xi(t) represents in-phase data, Xq( t) represents the quadrature data, cos(2πωt) represents the in-phase modulated carrier signal, and sin(2πωt) represents the quadrature modulated carrier signal. 如請求項9所述之觸控面板系統,其中,該積分三角類比至數位轉換器的資料率大於或等於10MHz。The touch panel system of claim 9, wherein the data rate of the sigma-delta analog-to-digital converter is greater than or equal to 10 MHz. 如請求項9所述之觸控面板系統,其中,該積分三角類比至數位轉換器具有二階的輸入/輸出關係為: out(z)=In(z)+Q(z)×(1−Z -1) 2, out(z)=In(z)*SFT+Q(z)*NFT, 其中,z/Z代表z域轉換,STF代表訊號轉變函數,Q(z) 代表z域量化雜訊,NTF代表雜訊轉變函數。 The touch panel system of claim 9, wherein the sigma-delta analog-to-digital converter has a second-order input/output relationship: out(z)=In(z)+Q(z)×(1−Z -1 ) 2 , out(z)=In(z)*SFT+Q(z)*NFT, where z/Z stands for z-domain transform, STF stands for signal transition function, and Q(z) stands for z-domain quantization noise , NTF stands for Noise Transfer Function. 如請求項9所述之觸控面板系統,其中,該第一邏輯閘電路具有多數個第一等效邏輯及單元,每一第一等效邏輯及單元具有一第一輸入端連接至該1位元的位元流、一第二輸入端連接至該同相調變載波訊號中的一對應位元、及一輸出端用以輸出該同相資料;該第二邏輯閘電路具有多數個第二等效邏輯及單元,每一第二等效邏輯及單元具有一第一輸入端連接至該1位元的位元流、一第二輸入端連接至該正交調變載波訊號中的一對應位元、及一輸出端用以輸出該正交資料。The touch panel system of claim 9, wherein the first logic gate circuit has a plurality of first equivalent logic and units, and each first equivalent logic and unit has a first input terminal connected to the 1 A bit stream of bits, a second input terminal connected to a corresponding bit in the in-phase modulated carrier signal, and an output terminal for outputting the in-phase data; the second logic gate circuit has a plurality of second, etc. Effective logic and unit, each second equivalent logic and unit has a first input connected to the 1-bit bit stream, and a second input connected to a corresponding bit in the quadrature modulated carrier signal element, and an output terminal for outputting the orthogonal data. 如請求項15所述之觸控面板系統,其中,該第一等效邏輯及單元或第二等效邏輯及單元為一邏輯及閘具有兩輸入端分別作為該第一等效邏輯及單元或第二等效邏輯及單元的第一輸入端及第二輸入端、及一輸出端作為該第一等效邏輯及單元或第二等效邏輯及單元的輸出端。The touch panel system of claim 15, wherein the first equivalent logic and unit or the second equivalent logic and unit is a logic and gate having two input terminals as the first equivalent logic and unit or The first input terminal and the second input terminal of the second equivalent logic sum unit, and an output terminal are used as the output end of the first equivalent logic sum unit or the second equivalent logic sum unit. 如請求項15所述之觸控面板系統,其中,該第一等效邏輯及單元或第二等效邏輯及單元為一2至1多工器,該2至1多工器具有一選擇端作為該第一等效邏輯及單元或第二等效邏輯及單元的第一輸入端、兩輸入端分別作為該第一等效邏輯及單元或第二等效邏輯及單元的第二輸入端及輸入邏輯0、及一輸出端作為該第一等效邏輯及單元或第二等效邏輯及單元的輸出端。The touch panel system of claim 15, wherein the first equivalent logic sum unit or the second equivalent logic sum unit is a 2-to-1 multiplexer, and the 2-to-1 multiplexer has a selection terminal as a The first input terminal and the two input terminals of the first equivalent logic sum unit or the second equivalent logic sum unit are respectively used as the second input terminal and input of the first equivalent logic sum unit or the second equivalent logic sum unit A logic 0 and an output terminal are used as the output terminal of the first equivalent logic sum unit or the second equivalent logic sum unit. 如請求項15所述之觸控面板系統,其中,該第一等效邏輯及單元或第二等效邏輯及單元為一邏輯或閘具有兩輸入端分別連接一邏輯反閘以作為該第一等效邏輯及單元或第二等效邏輯及單元的第一輸入端及第二輸入端、及一輸出端連接一邏輯反閘以作為該第一等效邏輯及單元或第二等效邏輯及單元的輸出端。The touch panel system according to claim 15, wherein the first equivalent logic sum unit or the second equivalent logic sum unit is a logic OR gate having two input ends respectively connected to a logic inversion gate as the first The first input terminal and the second input terminal of the equivalent logic sum unit or the second equivalent logic sum unit, and an output terminal are connected with a logic inversion gate as the first equivalent logic sum unit or the second equivalent logic sum unit output of the unit.
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106133664A (en) * 2014-02-04 2016-11-16 触觉实验室股份有限公司 Frequency conversion in touch sensor
TWI728854B (en) * 2020-07-06 2021-05-21 敦泰電子股份有限公司 Driving system and method for touch display panel

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106133664A (en) * 2014-02-04 2016-11-16 触觉实验室股份有限公司 Frequency conversion in touch sensor
TWI728854B (en) * 2020-07-06 2021-05-21 敦泰電子股份有限公司 Driving system and method for touch display panel

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