JP2007158735A - Semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce noise near an input signal frequency and to improve an S/N ratio by the rotation of a unit element using N pointers in a delta sigma A/D converter. <P>SOLUTION: Signals output from a quantizer are converted to the binary number of 3 bits in a DEM 15 provided in an A/D converter, and the pointer to be used and the direction (ascending order/descending order) of the use of the unit element are controlled by a counter 18. The pointer is moved by adding a recorded pointer position and input signals, input x(i) from the quantizer is shifted and output to a D/A converter as y(i) and the unit element is shifted. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a technique for improving an S / N (Signal / Noise) ratio in an A / D converter, and more particularly to noise reduction due to variation in unit elements in a bandpass delta sigma type A / D converter. It relates to effective technology.

  A band-pass delta-sigma A / D (Analog / Digital) converter is widely used for wireless communication that performs demodulation using an intermediate frequency such as a radio receiver or a mobile phone.

  As a method of reducing noise (mismatch noise) caused by variations in unit elements constituting the D / A converter provided in the multi-bit delta sigma A / D converter, the frequency characteristic is included in the transfer characteristic of the noise. A technique for reducing noise in a signal band to be used, mismatch noise shaping, is known.

  In the low-pass type multi-bit delta-sigma A / D converter, the noise in the low frequency band used as a signal can be reduced by making the mismatch noise transfer characteristic a high-pass type.

  As a technique for realizing this, DWA (Data Weighted Averaging) and the like are known (for example, see Non-Patent Document 1).

  On the other hand, the band-pass multi-bit delta sigma A / D converter requires a noise transfer characteristic having a frequency band in which noise is reduced at the input signal frequency fin, that is, a so-called notch.

  In many cases, the bandpass delta sigma A / D converter sets the input signal frequency fin and the sampling frequency fs so that the relationship of fin = fs / 4 is established between the input signal frequency fin and the sampling frequency fs. Set. In this case, a bandpass mismatch matching algorithm is used (for example, refer nonpatent literature 2).

On the other hand, there is a case where the relationship of input signal frequency fin = sampling frequency fs / 4 does not hold due to restrictions depending on the purpose of use. In this case, a secondary DWA or a vector quantizer is used (for example, see Non-Patent Documents 3 to 8).
Ywvs Greerts, et al, 'DESIGN OF MULTI-BIT DELTA- SIGNA A / D CONVERTERS', p74-p97, Kuuwer Academic Publishers T.A. Shui, et al, 'Mismatch Shaping for a Current-Mode Multibit Delta-Sigma DAC', JSSC 1999, Mar. pp331-pp338 R. K. Henderson, et al. 'Dynamic Element Matching with Arbitrary Noise Shaping Function', ISCAS 1996, pp293-pp296 R. Schreier, et. al, 'Noise-shaped multi-bit D / A CONVERTER emitting unit elements,' Electronics Letters, Sept. 1995, Vol. 31, no. 20, pp. 1712-pp. 1713 Tao Shui, R.A. Schreier, F.M. Hudson. 'Mismatch-shaping DAC for Lowpass and Bandpass multi-bit Delta-Sigma Modulators' ISCAS 1998, I-352-355 A. Yasuda, H .; Tanimoto, T .; Iida, 'A Third order Delta-Sigma Modulator using second-order Noise shaping Dynamic Element Matching', JSSC 1998, Dec. pp. 1879-pp. 1886 T.A. Ueno, A .; Yasuda, T .; Yamaji, T .; Itakura, 'A Fourth-order Bandpass Delta-Sigma Modulator using second-order bandpass Noise-shaping DEM'ESCIRC 2001 V. Colonna, et. al, 'A 10.7 MHz Self-Calibrated SC Multibit 2nd-Order Bandpass ΣΔ Modulators' ESCIRC 2002

  However, the present inventors have found that the noise reduction technique using the delta-sigma A / D converter as described above has the following problems.

  When a delta-sigma A / D converter is used for a wireless communication device, the frequency band to be received, the intermediate frequency of the receiver, the sampling frequency of the A / D converter, and the harmonics thereof do not interfere with each other. It is necessary to determine the intermediate frequency and the sampling frequency, and these frequencies cannot be selected freely.

  However, in mismatch noise shaping methods such as DWA and bandpass mismatch shaping, the transfer characteristics of mismatch noise cannot be set freely with respect to the sampling frequency fs, so the input signal frequency is in the vicinity of 0 or from fs / 4. If it is off, mismatch noise cannot be reduced and the S / N ratio is not improved.

  In addition, when giving a notch point to an arbitrary frequency of the transfer characteristic of mismatch noise, the secondary DWA needs to operate logic at a frequency higher than the sample frequency fs, and power consumption increases, resulting in high-speed A / D. Realizing a converter is difficult. Furthermore, the method using the vector quantizer requires a complicated logic circuit and has a drawback that the area and current increase.

  An object of the present invention is to provide a technique capable of reducing noise near the input signal frequency and improving the S / N ratio by rotating unit elements using N pointers in a delta-sigma A / D converter. It is to provide.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  The present invention is a semiconductor integrated circuit device including a bandpass delta-sigma A / D converter that digitally converts a signal other than a quarter of the sampling frequency, and the A / D converter is input to the semiconductor integrated circuit device. A quantizer that converts the received signal into a digital signal and quantizes it, a D / A converter, and a unit element having a manufacturing variation of the D / A converter provided in the D / A converter. And an element matching unit that rotates in rotation, and the element matching unit includes N pointers that store the positions of the unit elements output from the quantizer, shifts unit elements by the pointers, and changes the shift direction. It reverses in ascending order or descending order.

  Moreover, the outline | summary of the other invention of this application is shown briefly.

  In the present invention, the element matching unit is configured so that the sampling frequency fs × k (= 1, 3, 5,... N−1) / (2 × number of pointers N) = input signal frequency fin is satisfied. The unit element of the A converter is rotated.

  In the present invention, the pointer is a register.

  Furthermore, in the present invention, the element matching unit rotates the unit element of the D / A converter using 12 pointers, and gives a notch point of mismatch noise transfer characteristics to 7/24 of the sampling frequency. is there.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  (1) Noise in the A / D converter can be greatly reduced and the S / N ratio can be improved.

  (2) According to the above (1), the performance of the semiconductor integrated circuit device can be improved, and the reception performance can be improved by using the semiconductor integrated circuit device in an electronic system such as a radio receiver.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

  1 is a block diagram of a semiconductor integrated circuit device according to an embodiment of the present invention, FIG. 2 is a block diagram illustrating an example of an A / D converter provided in the semiconductor integrated circuit device of FIG. 1, and FIG. 2 is an explanatory diagram showing the DEM algorithm provided in the A / D converter of FIG. 2, FIG. 4 is a block diagram of the DEM that realizes the rotation algorithm shown in FIG. 3, and FIG. FIG. 6 is an explanatory diagram showing transfer characteristics of mismatch noise, and FIG. 6 is an explanatory diagram of a frequency spectrum showing an example of mismatch noise reduction of the A / D converter of FIG.

  In the present embodiment, the semiconductor integrated circuit device 1 is a microcomputer used for car audio, for example. As shown in FIG. 1, the semiconductor integrated circuit device 1 includes an A / D converter 2, a demodulating DSP (Digital Signal Processor) 3, an A / D converter 4, an audio DSP 5, a D / A converter 6, and a control unit. It is composed of MPU (Multi Processing Unit) 7.

  The A / D converter 2 is composed of a bandpass type delta sigma A / D converter, and converts an input analog signal of the intermediate frequency signal IF into a digital signal. A signal received via the antenna 8 is amplified by an LNA (Low Noise Amp) 9, converted to about 10.7 MHz by a mixer 10 connected to a subsequent stage, and then connected to a PGA ( (Programmable Gain Amplifier) / Analog filter 11 amplifies and filters to an arbitrary output level, and outputs it to A / D converter 2 as intermediate frequency signal IF.

  A demodulating DSP 3 is connected to the output section of the A / D converter 2. The demodulation DSP 3 demodulates the intermediate frequency signal IF and restores it to an audio signal. The A / D conversion unit 4 includes a plurality of A / D converters, and converts, for example, an audio signal output from a CD player or the like into a digital signal.

  The audio DSP 5 is connected to the demodulating DSP 3 and the A / D converter 4. The audio DSP 5 processes an audio signal (for example, equalizer, sound field correction, etc.).

  The D / A converter 6 includes a plurality of D / A converters and is connected to the audio DSP 5. The audio signal processed by the audio DSP 5 is converted into an analog signal. The analog signal converted to the D / A conversion unit 6 is output as an output signal to an amplifier or the like connected to the subsequent stage. The control MPU 7 manages all control in the semiconductor integrated circuit device 1.

  FIG. 2 is a block diagram illustrating a configuration example of the A / D converter 2.

  The A / D converter 2 includes a resonator 12, a quantizer 13, a D / A converter 14, and a DEM (Element Matching Unit) 15. The resonator 12 is used as a band pass filter. The quantizer 13 converts the intermediate frequency signal IF input via the resonator 12 into a digital signal and quantizes it.

  The D / A converter 14 converts the digital signal output from the quantizer 13 into an analog signal. A DEM (Dynamic Element Matching) 15 dynamically rotates unit elements of the D / A converter 14 to be used, and reduces noise (mismatch noise) due to manufacturing variations of the unit elements.

  The DEM 15 is provided between the quantizer 13 and the D / A converter 14, and connection of unit elements between the quantizer 13 and the D / A converter 14 is dynamically switched by the DEM 15. The That is, the combination of unit elements of the D / A converter to be used can be changed for the same quantizer output value.

  Here, the transfer characteristics of mismatch noise have different frequency characteristics depending on the algorithm for rotating the unit elements. If the transfer characteristic of mismatch noise has a notch near the input signal frequency fin, noise is reduced in this frequency band and the S / N ratio is improved.

  FIG. 3 is an explanatory diagram showing an algorithm in the DEM 15. FIG. 3 shows a rotation method of unit elements when the quantizer 13 and the D / A converter 14 are 3 bits (8 unit elements) and N pointers are used as an example.

  First, assume that the quantizer 13 outputs 4 at time T (1). At this time, the D / A converter 14 outputs 4 using e (1), e (2), e (3), and e (4) among the unit element arrays.

  Here, the position 4 of the used unit element is recorded in the pointer p (1). At the next time T (2), the output of the quantizer 14 is 3, using e (1), e (2), e (3), the D / A converter 14 outputs 3, and the pointer Record 3 in p (2).

  This is repeated N times, and pointers p (1)..., P (N) are recorded. When the quantizer output is 3 at time T (N + 1), the D / A converter 14 selects three unit elements in descending order from e (4) recorded in the pointer p (1). That is, 3 is output using e (4), e (3), and e (2), and 2 is recorded in the pointer p (1). This procedure is repeated, and at time T (2N + 1), the D / A converter 14 outputs using unit elements in ascending order from 2 recorded in the pointer p (1).

  Here, for example, when the previously recorded pointer position is 3 and 5 is output in descending order as at time T (N + 2), e (3), e (2), and e (1) are used. Then, returning to e (8) cyclically, data is output with five unit elements e (8) and e (7), and the pointer position is set to e (7).

  Similarly, when e (8) is reached in the ascending order, the unit element is used cyclically returning to e (1). When this is expressed by a mathematical expression, E unit element arrays are represented by e (1), e (2)..., E (k), and the input of the D / A converter 14 at time T (n) is represented by Din (n ), The output of the D / A converter 14 is Dout (n), and the pointer position of the unit element in the D / A converter 14 is P (n).

It becomes.

  Here, e (k + E) = e (k) is defined.

  FIG. 4 is a block diagram illustrating a configuration example of the DEM 15 that implements the rotation algorithm illustrated in FIG. 3.

  As illustrated, the DEM 15 includes a shifter 16, a selector 17, a counter 18, an adder 19, a decoder 20, an encoder 21, and a pointer 22 including pointers p (1) to p (N). The pointers p (1) to p (N) are made up of registers, for example.

  The decoder 20 decodes the signal output from the quantizer 13 into a binary code. The encoder 21 encodes the calculation result of the adder 19 and outputs it to the shifter.

  The signal output from the quantizer 13 is converted into a 3-bit binary number, and the pointer 18 and the direction of use of unit elements (ascending / descending order) are controlled by the counter 18. The pointer is moved by adding the recorded pointer position and the input signal, whereby the input x (i) from the quantizer 13 is shifted to y / (i) as the D / A converter 14. Is output and the unit element is shifted.

  For example, when the number of pointers is N = 12, ascending or descending main path elements are rotated in a cycle of 24 / fs, so the noise transfer characteristics due to mismatch of the D / A converter 14 are shown in FIG. As shown in FIG. 5, the frequency has notches at 1 × fs / 24, 3 × fs / 24, 5 × fs / 24, 7 × fs / 24, 9 × fs / 24, and 11 × fs / 24, respectively. Become.

  In the case of the FM tuner, there is a method in which the signal bandwidth is 0.2 MHz, the intermediate frequency is 10.7 MHz, and the sampling frequency fs is 37.05 MHz. The notch frequency is 37.05 / 24 × 7 = 10.806 MHz, and noise is suppressed in the frequency range of 10.7 ± 0.1 MHz.

  FIG. 6 shows a frequency spectrum at the output of the A / D converter 2 in which the unit elements constituting the D / A converter 14 have manufacturing variations.

  As shown in the figure, it can be seen that noise is suppressed in the vicinity of the input signal frequency fin of 10.7 MHz, and a high S / N ratio is obtained. Thus, by appropriately selecting the number of pointers 22 in the DEM 15, it is possible to create notch points in the transfer characteristics of mismatch noise with a relatively high degree of freedom.

  In this way, by rotating the unit element of the D / A converter 14 using the N pointers 22, fs / (2N) as a mismatch noise transfer function, and a peak or notch at an integer multiple frequency thereof. It is possible to have a frequency characteristic having

  Thereby, according to this Embodiment, the mismatch noise of the A / D converter 2 can be reduced significantly and the S / N ratio can be improved.

  Further, since the circuit scale of the DEM 15 can be reduced, the chip layout area can be reduced and the current consumption of the semiconductor integrated circuit device 1 can be reduced.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, when the intermediate frequency is 10.7 MHz and the sampling frequency fs is 37.05 MHz, the number of pointers N = 5 and the rotation period of the unit element may be 10.

  Therefore, a mismatch noise transfer characteristic notch is formed at 3/10 × fs = 11.0 MHz. In this case, the input frequency band is deviated from 10.7 MHz ± 0.1 MHz, but the mismatch noise is sufficiently suppressed even in this frequency band, and the required S / N ratio is not so high. The number of pointers can be reduced, and the S / N ratio can be improved with a smaller circuit scale.

  The present invention is suitable for a technique for improving the S / N ratio of an A / D converter used in a receiver and realizing low noise.

1 is a block diagram of a semiconductor integrated circuit device according to an embodiment of the present invention. FIG. 2 is a block diagram illustrating an example of an A / D converter provided in the semiconductor integrated circuit device of FIG. 1. It is explanatory drawing which showed the algorithm of DEM provided in the A / D converter of FIG. It is a block diagram of DEM which implement | achieves the rotation algorithm shown in FIG. FIG. 5 is an explanatory diagram showing transfer characteristics of mismatch noise in the DEM of FIG. 4. It is explanatory drawing of the frequency spectrum which shows the example of reduction of the mismatch noise by the A / D converter of FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor integrated circuit device 2 A / D converter 3 Demodulation DSP
4 A / D converter 5 Audio DSP
6 D / A converter 7 MPU for control
8 Antenna 9 LNA
DESCRIPTION OF SYMBOLS 10 Mixer 11 PGA / Analog filter 12 Resonator 13 Quantizer 14 D / A converter 15 DEM (element matching part)
16 Shifter 17 Selector 18 Counter 19 Adder 20 Decoder 21 Encoder 22 Pointer

Claims (4)

A semiconductor integrated circuit device including a bandpass delta sigma type A / D converter that digitally converts a signal other than a quarter of the sampling frequency,
The A / D converter is
A quantizer that converts the input signal into a digital signal and quantizes it;
A D / A converter;
An element matching unit that dynamically rotates unit elements of the D / A converter provided in the D / A converter;
The element matching unit is
N pointers for storing the positions of unit elements output from the quantizer,
A semiconductor integrated circuit device characterized in that a unit element is shifted by the pointer and the shift direction is reversed in ascending order or descending order. The semiconductor integrated circuit device according to claim 1.
The element matching unit is
The unit element of the D / A converter is rotated so that sampling frequency × k (= 1, 3, 5,... N−1) / (2 × number of pointers) = input signal frequency. A semiconductor integrated circuit device. The semiconductor integrated circuit device according to claim 1 or 2,
2. The semiconductor integrated circuit device according to claim 1, wherein the pointer comprises a register. The semiconductor integrated circuit device according to any one of claims 1 to 3,
The element matching unit is
12. A semiconductor integrated circuit device, wherein unit elements of the D / A converter are rotated using twelve pointers, and a notch point of mismatch noise transfer characteristics is provided at 7/24 of a sampling frequency.