TWI770485B - 半導體裝置及其製造方法 - Google Patents
半導體裝置及其製造方法 Download PDFInfo
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- TWI770485B TWI770485B TW109109943A TW109109943A TWI770485B TW I770485 B TWI770485 B TW I770485B TW 109109943 A TW109109943 A TW 109109943A TW 109109943 A TW109109943 A TW 109109943A TW I770485 B TWI770485 B TW I770485B
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/28255—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor belonging to Group IV and not being elemental silicon, e.g. Ge, SiGe, SiGeC
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Abstract
一種半導體裝置製造方法包括提供一通道區,且生長一氧化層於通道區上。 生長氧化層包括:引入提供氧的第一來源氣體;引入提供氫的第二來源氣體,第二來源氣體不同於第一來源氣體;透過將氧與通道區的半導體元素鍵結而形成氧化層;以及透過將氫與通道區的半導體元素鍵結而形成半導體氫化物副產物。可在氧化層上形成閘極介電層及閘極電極。
Description
本發明實施例係關於一種半導體技術,且特別是關於一種半導體裝置及其製造方法。
積體電路(integrated circuit, IC)產業經歷了指數增長。積體電路(IC)材料及設計的技術進步已經產生了幾世代積體電路(IC),其中每一世代都比上一世代具有更小更複雜的電路。在積體電路(IC)發展過程中,通常增加了功能密度(即,每晶片面積的內連接裝置的數量),而幾何尺寸(即,可使用製造製程產生的最小部件(或線))卻減小了。此按比例縮小的製程通常可經由提高生產效率及降低相關成本帶來收益。
上述按比例縮小也增加了積體電路(IC)的加工及製造的複雜性,且對於要實現的這些進展,需要在積體電路(IC)加工和製造中進行相似的發展。舉例來說,隨著鰭式場效電晶體(FinFET)技術朝著更小的特徵部件尺寸發展,不同類型的鰭式場效電晶體(FinFET)採用不同的鰭部材料配置以進一步提高效能。基於所需的裝置效能,可使用不同的材料於鰭式場效電晶體(FinFET)的鰭部內,以提供合適的通道區。當於鰭部的通道區上方形成閘極時,已觀察到可採用形成一界面層於鰭部元件及上方膜層上。提供適合於不同配置的鰭部的界面層帶來了許多挑戰。 特別是,隨著特徵部件尺寸的縮小,製造具有適當厚度的優質膜層的閘極堆疊帶來了許多挑戰。
一種半導體裝置的製造方法包括:提供一基底,具有一通道區;生長一氧化層於通道區上;形成一閘極介電層於氧化層上方;以及形成一閘極電極於閘極介電層上方。生長氧化層包括:引入提供氧的一第一來源氣體;引入提供氫的一第二來源氣體,第二來源氣體不同於第一來源氣體;將氧與通道區的一半導體元素鍵結,以形成氧化層;以及將氫與通道區的半導體元素鍵結,以形成一半導體氫化物副產物。
一種半導體裝置的製造方法包括:提供一基底,具有延伸於基底上方的一第一鰭式部件及一第二鰭式部件,其中第一鰭式部件的組成不同於第二鰭式部件的組成;生長一氧化層於第一鰭式部件及第二鰭式部件上方,其中第一鰭式部件上方的氧化層包括一第一氧化物組成,而第二鰭式部件上方的氧化層包括一第二氧化物組成。生長氧化層包括:以一第一流量將一含氧氣體引入基底;以及以不同於第一流量的一第二流量將一含氫氣體引入基底。
一種半導體裝置包括:一第一鰭式部件結構,自一基底延伸,其中第一鰭式部件結構包括一第一組成,且其中第一鰭式部件結構具有多個圓化角落;一第二鰭式部件結構,自基底延伸,其中第二鰭式部件結構包括不同於第一組成的一第二組成;一第一界面層,直接形成於具有圓化角落的第一鰭式部件結構上,其中第一界面層為由第一組成構成的一氧化物;一第二界面層,直接形成於第二鰭式部件結構上,其中第二界面層為由第二組成構成的一氧化物;以及一閘極介電層,形成於第一界面層及第二界面層上方。
本揭露內容總體上係關於一種裝置(例如,鰭式場效電晶體(FinFET)裝置),且更具體地關於裝置的通道區上方的閘極堆疊的多個膜層(例如,界面層)的製作。
以下的揭露內容提供許多不同的實施例或範例,以實施本發明的不同特徵部件。而以下的揭露內容是敘述各個構件及其排列方式的特定範例,以求簡化本揭露內容。當然,這些僅為範例說明並非用以限定本發明。舉例來說,若是以下的揭露內容敘述了將一第一特徵部件形成於一第二特徵部件之上或上方,即表示其包含了所形成的上述第一特徵部件與上述第二特徵部件是直接接觸的實施例,亦包含了尚可將附加的特徵部件形成於上述第一特徵部件與上述第二特徵部件之間,而使上述第一特徵部件與上述第二特徵部件可能未直接接觸的實施例。
另外,本揭露內容在各個不同範例中會重複標號及/或文字。重複係為了簡化及清晰的目的,且其本身並不代表所討論的各種實施例及/或配置之間的關係。再者,在以下的揭露內容中的一特徵部件位於另一特徵上、連接至及/或耦接至另一特徵部件的製作可包括其中特徵部件以直接接觸形式的實施例,且也可包括其中附加特徵部件夾設於特徵部件之間的實施例,使特徵部件可能未直接接觸。另外,在空間上的相關用語,例如,“下”、“上”、“水平”、“垂直”、“之上”、“上方”、“之下”、“以下”、“向上”、“向下”、“頂部”、“底部”、 ”等及其衍生詞(例如,“水平地”、“向下地”、“向上地”等,在此處係用以容易表達出本說明書中所繪示的圖式中特徵部件與另一特徵部件的關係。這些空間上的相關用語涵蓋包括特徵部件在內的裝置的不同方位。
對於先進的積體電路(IC)技術世代,鰭式場效電晶體(FinFET)(也稱為非平面電晶體)已成為高效能與低漏電應用的流行且具前景的候選者。為了增強通道遷移率,通常使用不同的鰭部材料(特別是不同的通道材料)配置不同類型的鰭式場效電晶體(FinFET)。不同的鰭部材料對後續製程的反應不同,因而在鰭式場效電晶體(FinFET)製造製程中產生了許多挑戰。閘極堆疊形成於這些通道材料上。 閘極堆疊包括多個界面層形成於通道區上,以及形成於界面層之上的閘極介電層和閘極電極。
本揭露內容特別是透過實現用於具有界面層的裝置的方法與結構來解決形成閘極堆疊及界面層的挑戰。在一些實施例中,以下敘述的熱氫化(thermal hydridation)製程用於直接形成界面層於通道區上,從而準備通道區以形成閘極堆疊的多個附加膜層(例如,閘極介電層)。
第1圖係繪示出了根據一些實施例之製造具有界面層的裝置的方法100。方法100可用於製造鰭式場效電晶體(FinFET)裝置或其他類型的場效電晶體(FET)裝置。第2至8圖提供了鰭式場效電晶體(FinFET)裝置的一示例。具體地,第2至8圖係繪示出根據一些實施例之鰭式場效電晶體(FinFET)裝置200在各個製造階段的局部或整體的剖面示意圖,且對應於第1圖的方法示例性步驟。
在所繪示的實施例中,例如在第2圖中,鰭式場效電晶體(FinFET)裝置200包括配置成包括n型裝置(例如,n型鰭式場效電晶體(FinFET))的NMOS區202A及配置成包括p型裝置(例如,p型鰭式場效電晶體(FinFET))的PMOS區202B,使鰭式場效電晶體(FinFET)裝置200包括互補式鰭式場效電晶體(FinFET)。在一些實施方式中,NMOS區202A及PMOS區202B為局部的裝置區,例如核心區(通常稱作邏輯區)、記憶體區(例如,靜態隨機存取記憶體(SRAM)區)、類比區、外圍區(通常稱為I / O區)、虛置區、其他合適區或其組合。裝置區可包括各種被動和主動微電子裝置,例如電阻器、電容器、電感器、二極體、金屬氧化物半導體場效電晶體(metal-oxide semiconductor field effect transistor, MOSFET)、互補金屬氧化物半導體(complementary metal-oxide semiconductor, CMOS)電晶體、雙極結型電晶體(bipolar junction transistor, BJT)、橫向擴散MOS(laterally diffused MOS, LDMOS)電晶體,高壓電晶體、高頻電晶體、其他合適部件或其組合。在一些實施方式中,鰭式場效電晶體(FinFET)裝置200可為積體電路 (IC)晶片的一部分,系統晶片(system on chip, SoC)或其一部分。為了清楚起見,已經簡化相似於本揭露內容其餘圖式的第2至8圖,以更好地理解發明構思。可於鰭式場效電晶體(FinFET)裝置200內加入附加的特徵部件,且於鰭式場效電晶體(FinFET)裝置200的其他實施例中可替換、修改或排除以下所述的某些特徵部件。
方法100開始於區塊步驟102,提供一半導體基底。在一實施例中,半導體基底包括自半導體基底升起的多個鰭部元件。另外,通常要注意的是此處利用鰭式場效電晶體(FinFET)作為示例性半導體裝置。 然而,在其他實施例中,可製造平面裝置,其包括為平面裝置提供本文所述的界面層。舉例來說,生長界面層於平面通道區上。在其他實施例中,可製造出環繞閘極(Gate-All-Around, GAA)裝置,其包括此處所述界面層位於閘極堆疊內的環繞閘極(GAA)多閘極裝置。
請參照第2圖的示例,鰭式場效電晶體(FinFET)裝置200包括一基底(晶圓)204。在所繪示的實施例中,基底204包括矽。替代地或另外地,基底204包括另一種元素半導體(例如,鍺);化合物半導體(例如,碳化矽、磷化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銻化銦);合金半導體(例如,矽鍺(SiGe)、SiPC、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP);或其組合。或者,基底204為絕緣體上覆半導體基底(例如,絕緣體上覆矽(silicon-on-insulator, SOI)基底、絕緣體上覆矽鍺(germanium-on-insulator, SGOI)基底或絕緣體上覆鍺(germanium-on-insulator, GOI)基底。絕緣體上覆半導體基底可透過氧植入隔離(separation by implantation of oxygen, SIMOX)、晶圓接合及/或其他合適方法來製造。在一些實施方式中,基底204包括一或多種III-V族材料,一或多種II-IV族材料或其組合。
如第2圖所示,多個鰭式部件206A及206B自基底204延伸。與在鰭式場效電晶體(FinFET)裝置內一樣,鰭式部件206A及206B包括一凸起部分,凸起部分上將形成一閘極堆疊,而在鰭式部件206A及206B的每一者內形成一通道。基底204及/或以下所述的鰭式部件206可包括根據鰭式場效電晶體(FinFET)裝置200的設計要求配置的各種摻雜區。在一實施例中,基底的PMOS區202B的鰭式部件206B具有與基底的NMOS區202A的鰭式部件206A不同的組成及/或摻雜剖面分佈。在一實施例中,鰭式部件206B為矽鍺。在一實施例中,鰭式部件206A為矽。
在一些實施例中,出於各種考慮,例如用於高遷移率的應變效應或使用高遷移率的半導體材料,鰭式部件206B或其部分中的半導體材料不同於基底204的半導體材料。如以上所述,在一些實施例中,鰭式部件206B包括矽鍺。其他示例包括鍺、矽鍺錫(SiGeSn)、鍺錫(GeSn)或III-V組的化合物半導體材料。在示例性實施例中,來自III-V族的化合物半導體材料包括砷化鎵、磷化砷化鎵、氮化鎵、磷化鎵、砷化銦、砷化銦鎵、氮化銦鎵、磷化銦鎵、氮化銦、磷化銦、砷化鋁、砷化鋁鎵、磷化鋁鎵銦、氮化鋁鎵、磷化鋁鎵、砷化鋁銦、氮化鋁、磷化鋁或其組合。在另外的示例中,鰭式部件206B可包括二或多個半導體材料膜層。需注意的是在一些實施例中,鰭式部件206B包括形成通道區的上部(例如,位於隔離區208上方),通道區可包括例如矽鍺的第一半導體材料,而鰭部的底部(例如在隔離區之內)保留了另一種半導體材料,例如基底的材料(例如,矽)。
在一些實施例中,出於裝置效能的各種考慮,鰭式部件206A中的半導體材料與基底204相同,且可不同於鰭式部件206B中的半導體材料。 在各個示例中,鰭式部件206A包括矽。然而,實施例不限於此,且鰭式部件206A的組成可包括其他組成,包括以上對照鰭式部件206B所述的那些。
如第2圖所示,在鰭式部件206之間形成了隔離特徵部件208。隔離特徵部件208可包括氧化矽、氮化矽、氣隙及/或其他合適的介電材料。隔離特徵部件208可包括具有襯層的多個膜層。在一些實施例中,隔離特徵部件208的多個膜層透過化學氣相沉積(CVD)形成,例如高密度電漿CVD(high density plasma CVD, HDPCVD)、金屬有機CVD(metal organic CVD, MOCVD)、遠程電漿CVD(remote plasma CVD, RPCVD)、PECVD、LPCVD、大氣壓CVD(atmospheric pressure, APCVD)、 次大氣壓氣相沉積(sub-atmospheric vapor deposition, SACVD)、 原子層沉積(ALD)、氧化製程、其他合適方法或其組合。在一些實施例中,隔離特徵部件208稱作淺溝槽隔離(shallow trench isolation, STI)特徵部件。回蝕刻隔離特徵部件208,使得鰭式部件206的通道區延伸於隔離特徵部件208上方。
請再次參照第1圖,方法100延續至區塊步驟104,一或多個虛置閘極結構排置於基底的一或多個通道區(例如,一或多個鰭式部件)上。虛置閘極結構可為定義最終閘極的位置的佔用位置。在將虛置閘極結構設置於通道區上方、定義通道區以及保護通道區的同時,可在基底上進行各種不同製程。請參照第2圖的示例,虛置閘極結構210形成於鰭式部件206A及206B上方。虛置閘極結構210可包括例如虛置氧化層212及虛置電極層214的多個層。虛置氧化層212可包括氧化矽。虛置電極層214可包括多晶矽。然而,虛置閘極結構210也是可能使用其他組成。虛置閘極結構210的材料可實質上相似於基底204的NMOS區202A及PMOS區202B。需要注意的是,裝置200中的虛線係繪示出了可存在附加特徵部件夾設於區PMOS區202B與NMOS區202A之間。鰭式部件206A及206B及虛置閘極結構210的數量僅為示例性的。
可透過毯覆沉積一或多種材料且隨後圖案化這些材料以形成虛置閘極結構210於鰭式部件206A及206B上方。虛置閘極結構210的圖案化包括微影製程及蝕刻。在示例性實施例中微影製程形成圖案化的阻劑層。在一示例中,圖案化的阻劑層的形成包括阻劑層塗覆、軟烘烤、曝光、後曝烤(post-exposure baking, PEB)、顯影及硬烘烤。此後透過蝕刻並使用圖案化的阻劑層作為蝕刻罩幕來圖案化虛置閘極堆疊材料層。蝕刻製程可包括一或多個蝕刻步驟。舉例來說,可應用具有不同蝕刻劑的多道蝕刻步驟來蝕刻對應的閘極堆疊材料層。在其他實施例中,閘極堆疊材料層的圖案化可替代地使用硬式罩幕作為蝕刻罩幕。硬式罩幕可包括氮化矽、氮氧化矽、氧化矽、其他合適材料或其組合。後續可使用適當的製程,例如濕式剝離或電漿灰化,去除圖案化的阻劑層。
在對形成虛置閘極結構210的閘極堆疊進行圖案化之後,可形成間隙壁部件於虛置閘極結構210的側壁上。閘極間隙壁部件可透過任何合適製程形成,並且包括介電材料。可透過沉積介電材料並蝕刻(例如,異向性蝕刻(例如,乾蝕刻))材料以形成間隙壁部件。介電材料可包括矽、氧、碳、氮、其他合適材料或其組合(例如,氧化矽、氮化矽、氧氮化矽或碳化矽)。在一些實施例中,閘極間隙壁部件包括多層結構,例如包括氮化矽的第一介電層及包括氧化矽的第二介電層。在一些實施例中,閘極間隙壁部件包括鄰近於閘極堆疊形成的多於一組的間隙壁部件(例如,密封間隙壁、偏置間隙壁、犧牲間隙壁、虛置間隙壁及/或主間隙壁)。
在形成虛置閘極結構之後,可在形成閘極間隙壁部件之前及/或之後,在鰭部的源極/汲極區中進行佈植、擴散及/或退火製程以形成LDD特徵部件及/或HDD特徵部件(均未繪示)。
請再參照第1圖,方法100延續至區塊步驟106,形成一介電層於基底上,例如內層介電(interlayer dielectric, ILD)層。內層介電(ILD)層形成於虛置閘極結構(包括閘極間隔元件)附近。可在形成具有源極/汲極特徵部件的裝置200之後,沉積內層介電(ILD)層。內層介電(ILD)層包括一或多種介電材料,包括例如氧化矽、氮化矽、氮氧化矽、TEOS形成的氧化物、PSG、BPSG、低k值介電材料、其他合適介電材料或其組合。示例性的低k值介電材料包括FSG、碳摻雜的氧化矽、BlackDiamond®(加州聖克拉拉應用材料)、乾凝膠(Xerogel)、氣凝膠(Aerogel)、氟化非晶碳(amorphous fluorinated carbon)、聚對二甲苯(Parylene)、BCB、SiLK(陶氏化學,米德蘭,密西根州),醯亞胺(polyimide)、其他低k值介電材料或其組合。在一些實施例中,所形成的內層介電(ILD)層具有包括具有多種介電材料的多層結構。在一些實施例中,在形成虛置閘極結構之後,透過沉積製程(例如,CVD、PVD、ALD、FCVD、HDPCVD、MOCVD、RPCVD、PECVD、LPCVD、ALCVD、APCVD、電鍍、其他合適方法或其組合)來形成內層介電(ILD)層。區塊步驟106可更包括形成另外的介電層,其包括例如接觸蝕刻停止層(contact etch stop layer, CESL)。在一實施例中,在內層介電(ILD)層之前,形成接觸蝕刻停止層(CESL)層。在沉積形成內層介電(ILD)層及/或形成其他介電層的材料之後,進行化學機械平坦化(chemical mechanical planarization, CMP)製程及/或其他平坦化製程。平坦化製程去除介電材料,以到達(暴露)虛置閘極的頂部。
然後,方法100延續至區塊步驟108,去除虛置閘極結構或其一部分。可透過施加選擇性蝕刻劑來進行去除,選擇性蝕刻劑在一或多道蝕刻步驟中去除虛置閘極結構的膜層(例如,虛置閘極介電層及虛置閘極電極)。請參照第3圖的示例,已去除虛置閘極結構210而形成溝槽開口302。虛置閘極結構210的去除包括去除(例如,蝕刻)虛置氧化層212及虛置閘極電極214。虛置閘極結構210的去除留下溝槽開口302而露出鰭式部件206A及206B的通道區。在一實施例中,鰭式部件206A及206B的表面露出,其中表面實質上是鰭式部件206A及206B的半導體材料,包括上述材料。
在去除虛置閘極結構之後,方法100延續至區塊步驟110,其中形成一界面層(interface layer, IL)於因去除虛置閘極結構而露出的鰭式部件的區域上。界面層提供一介電層於鰭式部件(例如,通道區)上。
可使用快速熱氫化(rapid thermal hydridation, RTH)製程來形成區塊步驟110所述的界面層,以下將有詳細討論。請參照第4圖的示例,形成一界面層402於鰭式部件206A及206B上方。在一些實施例中,以快速熱氫化(RTH)製程形成界面層402。在一實施例中,快速熱氫化(RTH)製程同時在NMOS區202A的鰭式部件206A及PMOS區202B的鰭式部件206A及206B上方形成界面層(IL)402。儘管可同時形成,但是由於鰭式部件206A及206B的組成不同,所以NMOS區202A中界面層(IL)402的材料不同於PMOS區202B中界面層(IL)402的材料。在一實施例中,PMOS區202B中的界面層(IL)402為SiGeOx
。在一實施例中,NMOS區202A中的界面層(IL)402為SiOx
。相似地,雖然同時形成,但是由於鰭式部件206B的半導體材料的氧化速率與鰭式部件206A的氧化速率不同,所以界面層(IL)402的厚度於PMOS區202B及NMOS區202A並不同。在一實施例中,在PMOS區202B中界面層(IL)402的厚度比在NMOS區202A中厚(例如,矽鍺的氧化速度比矽快)。
如以上所述,在一些實施例中,鰭式部件206B包括半導體組成,其選擇考量在於裝置200的PMOS區202B內待形成裝置的效能。舉例來說,鰭式部件206B的通道區(例如,隔離特徵部件208上方的鰭式部件206B的上部)可為矽鍺。矽鍺通道材料由於其高遷移率而可為PMOS區202B的裝置、PMOS裝置提供優勢。然而,使用這種通道材料也帶來了許多挑戰。舉例來說,在包括鰭式部件的矽鍺上的介電層的化學生長(例如,透過暴露於水蒸氣氣氛而進行的介電層的化學生長),可能導致SiGe通道區的鍺(Ge)相對濃度增加,稱作鍺(Ge)積累狀態(pile-up condition)。鍺(Ge)積累狀態可在通道區的表面處產生過量的鍺。相似的鍺(Ge)積累狀態結果也發生於使用典型乾氧化製程(例如,提供分子氧作為氧氣原料)於SiGe通道區上方進行介電層的化學生長。鍺(Ge)積累會導致遷移率降低,因而降低裝置效能。相似地,這些化學氧化製程可導致通道區表面(例如,矽鍺、矽)粗糙。表面粗糙度也可能引起遷移率降低而降低裝置效能。在一些實施例中,提供了表面粗糙度及/或鍺(Ge)積累的改善,以下參照第8圖進一步詳細討論。 在本揭露內容的討論中,與化學生長氧化物(chemically grown oxide, CIL)(例如,將半導體特徵部件暴露於臭氧(O3)+標準清潔1(Standard Clean 1, SC1)+標準清潔2(Standard Clean 2, SC2)製程順序的濕式清潔製程生長)相比較。標準清潔1(SC1)包括去離子水、氨水及過氧化氫。標準清潔2(SC2)包括去離子水、鹽酸(HCl)及過氧化氫(H2
O2
)。
回到當前所述的方法,方法100於區塊步驟110包括界面層(IL)402的製作。界面層(IL)402使用此處所稱的快速熱氫化(RTH)製程形成。在一些實施例中,經由此處所述的快速熱氫化(RTH)製程形成的界面層(IL)402可用於減少鍺(Ge)積累並改善表面粗糙度。儘管不受任何理論束縛,然而可設想在快速熱氫化(RTH)製程中提供的氫可能有助於-H與Ge鍵結,然後將Ge作為副產物從裝置中去除。因此,減少了鍺在SiGe通道區(例如,鰭式部件)內的積累。因此,相較於鰭式部件206A及206B上化學生長的介電層,使用快速熱氫化(RTH)製程形成界面層(IL)402可使裝置200中的遷移率提高。
在一實施例中,快速熱氫化(RTH)製程包括引入氫(或氫化物,其為氫的陰離子),其將鍵結至鰭式部件206A及206B的可用半導體元素。在一實施例中,鰭式部件206A及206B是矽鍺,快速熱氫化(RTH)製程引入氫與鰭式部件的鍺(Ge)鍵結。在一實施例中,氫與過量的鍺鍵結,因而減輕了鍺(Ge)積累狀態。鍺(Ge)與氫的鍵結形成包括鍺(Ge)和氫(H)的氫化物,例如GeH4
。 然後,氫化鍺作為製程副產品而自反應室中排出。雖然此處討論了鍺及鍺積累的示例,然而用於通道區的其他半導體材料也可提供可用元素與可用氫鍵結,包括但不限於矽、鎵、銦、砷及/或其他合適的元素。
除了引入氫之外,快速熱氫化(RTH)製程也包括引入氧源。氧源用於提供氧以形成具有氧化物成分的界面層(IL)402。舉例來說,在一實施例中,鰭式部件206A及206B是矽鍺,在快速熱氫化(RTH)製程中提供的氧與SiGe鍵結而形成SiGeOx
,其形成界面層(IL)402。另一示例中,鰭式部件206A及206B為矽,在快速熱氫化(RTH)製程中提供的氧與矽(Si)鍵結形成SiO,其形成界面層(IL)402。也可能是不同的其他組成的氧化物,包括以上關於鰭式部件206A及206B所述的那些材料。在一實施例中,PMOS區202B的界面層(IL)402為SiGeOx
,NMOS區202A中的界面層(IL)402為SiOx
。
也可在快速熱氫化(RTH)製程中提供其他組成,例如惰性氣體或載氣,例如氮氣。在另一實施例中,載氣可為氬(Ar)氣。因此,在一實施例中,快速熱氫化(RTH)製程由載氣(N2
)、提供O2
的氧源以及與氧源分開的氫源組成。在另一個實施例中,提供O2
的氧源為唯一的氧源(舉例來說,並無特意提供水蒸氣至腔室)。
在一實施例中,快速熱氫化(RTH)製程透過實現以下示例性製程參數中的一或多個來形成界面層(IL)402。在一實施例中,快速熱氫化(RTH)製程在大約650攝氏溫度至大約850攝氏溫度之間進行。選擇溫度以促進氫及/或氧與鰭式部件206A及206B的材料的反應,同時不損壞鰭式部件206A及206B或周圍的部件。在一實施例中,快速熱氫化(RTH)製程中所提供的腔室的壓力大約5托至大約20托之間。如同溫度範圍一樣,選擇壓力以促進反應,同時降低損壞裝置200的特徵部件。
延續如上所述的快速熱氫化(RTH)製程參數的討論,快速熱氫化(RTH)製程包括提供氫氣、氧氣及載氣(例如,氮氣)。在一實施例中,提供給基底204的氫源(H2
)流量在大約0.8slm至大約4.6slm之間。在一實施例中,提供給基底204的氧源(O2
)流量在大約15sccm至大約150sccm之間。在一實施例中,提供給基底204的載氣(N2
)流量在大約7.2slm至大約10.4slm之間。在一些實施例中,在快速熱氫化(RTH)製程中提供給基底204的氫(例如,H2
)與氧(例如,O2
)之體積比在約5:1至約320:1之間。氧氣、氫氣及/或載氣可同時提供給放置基底204的腔室。在一實施例中,僅供應氧氣至腔室的方式係透過O2
,例如,使用上述流量。在一些實施例中,在快速熱氫化(RTH)製程中,氫(例如,H2
)及氧(例如,O2
)的總和與提供給基底204的載氣(N2
)的體積比在大約13:7至大約16:1之間。
需注意的是氫與氧以不同的流量提供,並且實際上可於進行快速熱氫化(RTH)製程的腔室的不同入口進行提供。換句話說,在一些實施例中,氫源與氧源彼此不同;氫與氧不相互鍵結。
需注意的是必須控制可用於基底204的氫的總量。 大氣中的氫氣過多可能導致與鰭式部件206A及206B發生過度反應,這可能會導致鰭部損壞,例如鰭部塌陷。在一實施例中,氫源可化合物形式提供而非純H2
。這樣做的優點在於能夠在快速熱氫化(RTH)製程中保持高溫,而沒有純H2
可燃性的風險。提供氫的示例性化合物包括HCl。因此,在一實施例中,快速熱氫化(RTH)製程提供了HCl、O2
及N2
。在一實施例中,快速熱氫化(RTH)製程僅由HCl、O2
及N2
氣體組成。
在一實施例中,快速熱氫化(RTH)製程進行大約1至2分鐘。在一實施例中,使用快速熱氫化(RTH)製程的界面層(IL)402的厚度在大約8埃至大約12埃之間。
在形成界面層(例如,使用快速熱氫化(RTH)製程)之後,方法100接著進行區塊步驟112,進行清潔製程。在一實施例中,清潔製程用於調節在區塊步驟110中形成的界面層(IL)的表面,以準備用於後續沉積閘極介電層的表面。在一實施例中,清潔製程透過將-OH官能基團鍵結至表面來調節表面。在一些實施例中,省略了區塊步驟112所進行的清潔步驟。
在一實施例中,清潔製程包括多階段清潔。多階段清潔可包括臭氧+標準清潔1(SC1)+標準清潔2(SC2)。標準清潔1(SC1)包括提供清潔溶液,其包括氨、過氧化氫及去離子水(DI水)。標準清潔液2(SC2)包括提供清潔溶液,其包括鹽酸(HCl)、過氧化氫(H2
O2
)及去離子水(DI水)。臭氧清潔階段包括將去離子水加入臭氧。
請參照第5圖,已經透過清潔製程處理的界面層(IL)402的表面形成界面層(IL)402的表面402’,在一實施例中,表面402’包括露出的-OH官能基團。
接著,方法100進行至區塊步驟114,一閘極介電層形成於區塊步驟110中形成的界面層上。在一實施例中,閘極介電層為高k值介電材料。請參照第6圖,形成一閘極介電層602於界面層(IL)402上。在一實施例中,閘極介電層602直接形成於界面層(IL)402的經處理的表面402’上。
閘極介電層602包括介電材料,例如氧化矽、高k值介電材料、其他合適介電材料或其組合。在所繪示的實施例中,閘極介電層602包括一或多個高k值介電層,例如包括鉿、鋁、鋯、鑭、鉭、鈦、釔、氧、氮,其他合適的組成或其組合。在一些實施方式中,一或多個高k值介電層包括HfO2
、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、ZrO2
、Al2
O3
、HfO2
-Al2
O3
、TiO2
、Ta2
O5
、La2
O3、Y2
O3
、其他合適高k值介電材料或其組合。高k值介電材料通常指具有高介電常數的介電材料,例如介電常數大於氧化矽的介電常數(k≈3.9)。閘極介電層可透過各種製程形成,例如ALD、CVD、PVD及/或其他合適的製程。在NMOS區202A中的閘極介電層602可與在PMOS區202B中的閘極介電層602具有相同的組成或者可不同。閘極介電層602可包括變化介電組成的多個膜層。
裝置200的等效氧化物厚度(equivalent oxide thickness, EOT)可透過閘極介電層602與界面層402的總和來決定。
接著,方法100進行至區塊步驟116,形成閘極電極層於區塊步驟114中的閘極介電層上。在一實施例中,閘極電極直接形成於閘極介電層上。在一實施例中,閘極電極包括提供適當功函數於最終裝置的一導電材料。在一些實施例中,可在閘極電極的功函數層與閘極介電層之間形成附加膜層(例如,蓋層)。
請參照第7圖,閘極電極層704及702分別形成於基底204的NMOS區202A及PMOS區202B內。在一實施例中,閘極電極層702提供p型功函數。在一實施例中,閘極電極層704提供n型功函數。
在一些實施方式中,閘極電極704及702每個都包括多膜層,例如一或多個蓋層、功函數層、膠/阻擋層及/或金屬填充(或塊體)層。蓋層可包括防止或消除閘極介電層602與閘極結構的其他膜層(特別是包括金屬的閘極層)之間的成分發生擴散及/或反應的材料。在一些實施方式中,蓋層包括金屬及氮,例如氮化鈦(TiN)、氮化鉭(TaN)、氮化鎢(W2
N)、氮化矽鈦(TiSiN)、氮化鉭矽(TaSiN)或其組合 。功函數層可包括調整為具有所需的功函數(例如,n型功函數或p型功函數)的導電材料,例如n型功函數材料及/或p型功函數材料。P型功函數材料包括TiN、TaN、Ru、Mo、Al、WN、ZrSi2
、MoSi2
、TaSi2
、NiSi2
、WN、其他p型功函數材料或其組合。N型功函數材料包括Ti、Al、Ag、Mn、Zr、TiAl、TiAlC、TaC、TaCN、TaSiN、TaAl、TaAlC、TiAlN、其他n型功函數材料或其組合。膠/阻擋層可包括促進相鄰膜層(例如,功函數層與金屬填充層)之間的黏著性的一材料,及/或阻止及/或減少閘極層(例如,功函數層與金屬填充層)之間擴散的一材料。舉例來說,膠/阻擋層包括金屬(例如,W、Al、Ta、Ti、Ni、Cu、Co、其他合適金屬或其組合)、金屬氧化物、金屬氮化物(例如,TiN)或其組合。金屬填充層可包括合適導電材料(例如,Al、W及/或Cu)。在一些實施方式中,一硬式罩幕層(例如包括氮化矽或碳化矽)設置於閘極電極702及704的至少一部分上。閘極電極702及704透過各種沉積製程(例如,ALD、CVD、PVD及/或其他合適製程)形成。需注意的是第7圖僅為示例說明,並非意指裝置200須在閘極電極702與704之間包括一界面,然而如上所述,各種不同的特徵部件可位於PMOS區202B與MOS區202A之間。
閘極電極702或704與閘極介電層602及界面層(IL)402一同提供了各自的閘極堆疊706。閘極堆疊706形成了裝置200的閘極結構於鰭式部件206A及206B的通道區上,並控制鰭式部件206A及206B的通道區。
第8圖係繪示出了界面層(IL)402與對應的鰭式部件206B的聚焦圖。第8圖繪示出了鰭式部件206B的角落的圓化(請參見小圖A)。在一實施例中,由於在用以形成界面層(IL)402的快速熱氫化(RTH)製程期間鰭式部件206B的半導體組成回流,因此鰭206B具有如小圖A所示的圓化角落形狀。圓化角落形狀可存在於鰭式部件206A及/或206B。圓化角落形狀可由鰭式部件206B的外表面(其在鰭式部件206B的側壁與鰭式部件206B的上表面之間的交界面處彎曲)所定義。
第8圖也繪示出了在其上形成有界面層(IL)402的鰭式部件206B的表面的相對表面粗糙度,請參見小圖B。在一實施例中,由於界面層(IL)402透過快速熱氫化(RTH)製程形成,因此鰭式部件206B的表面粗糙度降低。在一實施例中,已確定透過化學氧化在其上形成介電層的鰭部的表面粗糙度大約在0.172均方根(Rms)(nm)。透過快速熱氫化(RTH)製程在其上形成界面層(例如,界面層(IL)402)的相似鰭部的表面粗糙度大約在0.164Rms(nm)。在一些實施例中,以Rms測量,表面粗糙度的改善(減小)大約為5%。在一實施例中,可對鰭部(例如,鰭式部件206A及鰭式部件206B)提供表面粗糙度的改善。在一實施例中,上方具有透過快速熱氫化(RTH)製程形成的界面層(IL)402的鰭式部件206A/206B具有一寬度變化(例如,從頂部到底部),上述寬度變化小於上方具有透過化學氧化形成的界面層(IL)402的相似鰭式部件的寬度變化。在另一個實施例中,在其上生長化學氧化物之後,鰭式部件寬度的變動可在大約7.5奈米至大約8.5奈米之間,或者沿著鰭式部件的高度,寬度的變化大約為11-15%。相反,在一實施例中,在透過快速熱氫化(RTH)製程形成氧化物(例如,界面層(IL)402)之後,鰭式部件寬度的變動可在大約8奈米至大約8.5納米之間,或者沿著鰭式部件的高度,寬度的變化大約4%至小於10%。
在一實施例中,快速熱氫化(RTH)製程用於形成界面層402於由矽鍺鰭式部件構成的鰭式部件206B上。快速熱氫化(RTH)製程也會影響提供於界面層(IL)402及鰭式部件206B中的鍺百分比。在一實施例中,已確定後續在其上形成介電層的通道區的鍺百分比為大約為29%至大約35%。在透過化學氧化來生長化學氧化物界面層之後,化學氧化物具有約4%至約6%的鍺濃度。在上方形成有與介電層厚度相似的界面層(例如,透過快速熱氫化(RTH)製程所形成的界面層(IL)402)的相似通道區(如鰭式部件206B所示)的鍺濃度約為25%至28%。因此,在一些實施例中,在形成界面層(IL)之前的鰭式部件的鍺濃度在大約29%至大約35%之間。在透過快速熱氫化(RTH)製程生長界面層(IL)(例如,界面層(IL)402)之後,鍺濃度大約為25%至28%之間。因此,在一些實施例中,鍺濃度可降低10%。在一些實施例中,透過快速熱氫化(RTH)製程形成界面層(IL)402,可將鍺濃度降低約3.5%。以上所述的百分比為原子百分比,且由Si-Si與Si-Ge鍵結總和來計算。在一實施例中,已確定透過SiGe鰭式部件的化學氧化形成的介電層(SiGeOx
)的鍺百分比(GeOx
%)大約為4-6%。相反地,透過快速熱氫化(RTH)製程形成界面層(例如,界面層(IL)402)於SiGe鰭式部件(例如,鰭式部件206B)上,且與介電層的厚度相似時,SiGeOx
具有鍺百分比(GeOx
%)大約為1%至約3%。在一些實施例中,可透過快速熱氫化(RTH)製程於通道區上方形成介電層來將氧化鍺濃度降低大約10%。以上所述的百分比可為特徵部件的原子百分比,且由Si-O與Ge-O鍵結總和的百分比來計算。
請返回參照第1圖及方法100的實施例,在一些實施例中,方法100延續進行裝置(例如,鰭式場效電晶體(FinFET)裝置200)的附加製造步驟。舉例來說,製造可延續至形成多層內連接特徵部件 (包括所述閘極堆疊的接觸連接窗(contact))。
第9圖係繪示出也可使用方法100形成的半導體裝置(鰭式場效電晶體(FinFET)裝置900)。鰭式場效電晶體(FinFET)裝置900可實質上相似於上述參照示例性的第2-8圖所述的鰭式場效電晶體(FinFET)裝置200。在一實施例中,鰭式場效電晶體(FinFET)裝置900係繪示出鰭式場效電晶體(FinFET)裝置200的一部分(例如,單一閘極結構)。
鰭式場效電晶體(FinFET)裝置900包括與閘極結構相鄰的源極/汲極特徵部件902。在一些實施例中,源極/汲極特徵部件902為磊晶特徵部件,形成於鰭式部件206上、上方或內部。在一些實施方式中,在形成虛置閘極(如上文的區塊步驟104中所述)之後,且在替換虛置閘極為金屬閘極(如上文的區塊步驟110至116中所述)之前形成磊晶源極/汲極特徵部件902。舉例來說,在鰭式部件206上磊晶生長半導體材料以形成磊晶源極/汲極特徵部件902。在一些實施方式中,在鰭式部件206上形成磊晶源極/汲極特徵部件902之前凹陷(例如,回蝕製程)鰭式部件206。源極/汲極特徵部件902可透過磊晶製程來形成,包括CVD沉積技術(例如,氣相磊晶(vapor-phase epitaxy, VPE)、超高真空CVD(ultra-high vacuum CVD, UHV-CVD)、LPCVD及/或PECVD)、分子束磊晶,其他合適的SEG製程或其組合。磊晶源極/汲極特徵部件902摻雜有n型摻雜物及/或p型摻雜物。磊晶源極/汲極特徵部件902對應於裝置類型來配置。舉例來說,對於n型裝置與p型裝置,摻雜物類型不同。在一些實施方式中,在沉積磊晶源極/汲極特徵部件902期間,透過於磊晶製程的來源材料內添加雜質,對其進行摻雜。在一些實施方式中,在沉積製程之後,透過離子佈植製程來摻雜磊晶源極/汲極特徵部件902。在一些實施例中,源極/汲極特徵部件902可彼此合併或部分合併。
第2至8圖的鰭式場效電晶體(FinFET)裝置200的剖面示意圖係沿第9圖所示的B-B’軸的剖面示意圖。第10圖係繪示出第9圖所示形成於PMOS區202B的閘極堆疊706沿A-A’軸的剖面示意圖。
以上概略說明了本發明數個實施例的特徵,使所屬技術領域中具有通常知識者對於本揭露的型態可更為容易理解。任何所屬技術領域中具有通常知識者應瞭解到可輕易利用本揭露作為其它製程或結構的變更或設計基礎,以進行相同於此處所述實施例的目的及/或獲得相同的優點。任何所屬技術領域中具有通常知識者也可理解與上述等同的結構並未脫離本揭露之精神和保護範圍內,且可在不脫離本揭露之精神和範圍內,當可作更動、替代與潤飾。
舉例來說,在一些實施例中,此處所述的方法及裝置的實施方式可提高最終裝置的遷移率。可透過於通道區上形成界面層的所使用的製程來減少在通道區處積累的鍺(Ge)及/或提供通道區表面的平滑性而改善遷移率。在一些實施例中,相較於使用化學氧化物界面層製造的裝置,裝置的遷移率可提高約3%至約5%。
根據一實施例,一種半導體裝置的製造方法包括:提供一基底,具有通道區,且生長一氧化層於通道區上。生長氧化層包括多個步驟,例如,引入提供氧的一第一來源氣體及引入提供氫的一第二來源氣體,第二來源氣體不同於第一來源氣體。 生長氧化層包括將氧與通道區的半導體元素鍵結以形成氧化層,以及將氫與通道區的半導體元素鍵結以形成半導體氫化物副產物。然後形成一閘極介電層於氧化層上方。形成一閘極電極於閘極介電層上方。
在另一實施例中,生長氧化層形成矽鍺氧化層。在一實施例中,通道區形成於自基底延伸的鰭式部件上。當半導體元素為鍺時,可透過磊晶生長一矽鍺區於一矽基底上來形成鰭式部件。 在一實施例中,第二來源氣體為HCl。生長氧化層可更包括引入由氮形成的一第三氣體。在一實施例中,氧化層為矽鍺氧化物,且半導體氫化物副產物包括氫及鍺。
根據一實施例,一種半導體裝置的製造方法包括:提供一基底,具有延伸於基底上方的第一鰭式部件及第二鰭式部件。 第一鰭式部件的組成不同於第二鰭式部件的組成。生長一氧化層於第一鰭式部件及第二鰭式部件上方。第一鰭式部件上方的氧化層包括第一氧化物組成,而第二鰭式部件上方的氧化層包括第二氧化物組成。透過以一第一流量將一含氧氣體引入基底,並以不同於第一流量的一第二流量將一含氫氣體引入基底來生長氧化層。
在另一實施例中,第一流量小於第二流量。在一實施例中,同時引入含氧氣體及引入含氫氣體。在一實施例中,第一氧化物組成為氧化矽鍺,而第二氧化物組成為氧化矽。
在一些實施例中,引入含氧氣體包括提供O2
。在另一實施例中,至腔室的氧源由含氧氣體O2
組成。在一實施例中,上述方法包括直接形成一閘極介電層於第一氧化物組成及第二氧化物組成上。
在一實施例中,該方法包括將來自含氧氣體的氧與第一鰭式部件鍵結以形成第一氧化物組成,同時將來自含氫氣體的氫與第一鰭式部件的半導體元素鍵結。進一步的實施例包括在將來自含氫氣體的氫與第一鰭式部件的半導體元素鍵結之後,自一製程腔室去除鍵結的氫與半導體元素。半導體元素為鍺,且自製程腔室內去除氫化鍺。
根據一個實施例,一種半導體裝置包括:一第一鰭式部件結構及一第二鰭式部件結構自一基底延伸。第一鰭式部件結構包括一第一組成,且具有多個圓化角落。第二鰭式部件結構包括不同於第一組成的一第二組成。一第一界面層直接形成於具有圓化角落的第一鰭式部件結構上,而一第二界面層直接形成於第二鰭式部件結構上。第一界面層為由第一組成構成的氧化物,而第二界面層為由第二組成構成的氧化物。一閘極介電層形成於第一界面層及第二界面層上方。圓化角落可由矽鍺構成。
在半導體裝置的另一實施例中,第二鰭式部件結構也包括多個圓化角落。在一實施例中,半導體裝置更包括一第一金屬閘極電極形成於第一鰭式部件結構上方的閘極介電層上以及一第二金屬閘極電極形成於第二鰭式部件結構上方的閘極介電層上。
100:方法
102,104,106,108,110,112,114,116:區塊步驟
200,900:鰭式場效電晶體(FinFET)裝置
202A:NMOS區
202B:PMOS區
204:基底
206,206A,206B:鰭式部件
208:隔離區
210:虛置閘極結構
212:虛置氧化層
214:虛置電極層
302:溝槽開口
402:界面層
402’:表面
602:閘極介電層
702,704:閘極電極層
706:閘極堆疊
902:源極/汲極特徵部件
第1圖係繪示出根據一些實施例之製造半導體裝置的方法流程圖。
第2至8圖係繪示出根據一些實施例之鰭式場效電晶體(FinFET)裝置在各個製造階段的局部或整體的剖面示意圖,且為第1圖的方法示例性步驟。
第9圖係繪示出根據一些實施例之鰭式場效電晶體(FinFET)裝置的局部或整體的立體示意圖。
圖10係繪示出根據一些實施例之鰭式場效電晶體(FinFET)裝置的局部剖面示意圖。
100:方法
102,104,106,108,110,112,114,116:區塊步驟
Claims (15)
- 一種半導體裝置的製造方法,包括:提供一基底,具有一通道區;生長一氧化層於該通道區上,其中生長該氧化層包括:引入提供氧的一第一來源氣體;引入提供氫的一第二來源氣體,該第二來源氣體不同於該第一來源氣體;將該氧與該通道區的一半導體元素鍵結,以形成氧化層;以及將該氫與該通道區的該半導體元素鍵結,以形成一半導體氫化物副產物;形成一閘極介電層於該氧化層上方;以及形成一閘極電極於該閘極介電層上方。
- 如請求項1之半導體裝置的製造方法,其中生長該氧化層形成一矽鍺氧化層。
- 如請求項1或2之半導體裝置的製造方法,其中提供具有該通道區的該基底包括形成該通道區於自該基底延伸的一鰭式部件上,其中透過磊晶生長一矽鍺區於一矽基底上來形成該鰭式部件。
- 如請求項1或2之半導體裝置的製造方法,其中該第二來源氣體為HCl。
- 如請求項1或2之半導體裝置的製造方法,其中生長該氧化層更包括引入由氮形成的一第三氣體。
- 如請求項1或2之半導體裝置的製造方法,其中該氧化層為矽鍺氧化物,且該半導體氫化物副產物包括氫及鍺。
- 一種半導體裝置的製造方法,包括: 提供一基底,具有延伸於該基底上方的一第一鰭式部件及一第二鰭式部件,其中該第一鰭式部件的組成不同於該第二鰭式部件的組成;生長一氧化層於該第一鰭式部件及該第二鰭式部件上方,其中該第一鰭式部件上方的該氧化層包括一第一氧化物組成,而該第二鰭式部件上方的該氧化層包括一第二氧化物組成,生長該氧化層包括:以一第一流量將一含氧氣體引入該基底;以及以不同於該第一流量的一第二流量將一含氫氣體引入該基底。
- 如請求項7之半導體裝置的製造方法,其中該第一流量小於該第二流量。
- 如請求項7或8之半導體裝置的製造方法,其中同時引入該含氧氣體及引入該含氫氣體。
- 如請求項7或8之半導體裝置的製造方法,其中該第一氧化物組成為氧化矽鍺,而該第二氧化物組成為氧化矽。
- 如請求項7或8之半導體裝置的製造方法,其中引入該含氧氣體包括提供O2。
- 如請求項7或8之半導體裝置的製造方法,更包括:將來自該含氧氣體的該氧與該第一鰭式部件鍵結以形成該第一氧化物組成,同時將來自該含氫氣體的該氫與該第一鰭式部件的該半導體元素鍵結;以及在將來自該含氫氣體的該氫與該第一鰭式部件的該半導體元素鍵結之後,自一製程腔室去除鍵結的該氫與該半導體元素。
- 一種半導體裝置,包括: 一第一鰭式部件結構,自一基底延伸,其中該第一鰭式部件結構包括一第一組成,且其中該第一鰭式部件結構具有多個圓化角落,各自形成於該第一鰭式部件結構的一上表面與一側壁的交界處,且該第一鰭式部件結構的該上表面為一實質上平坦的表面;一第二鰭式部件結構,自該基底延伸,其中該第二鰭式部件結構包括不同於第一組成的一第二組成;一第一界面層,直接形成於具有該等圓化角落的該第一鰭式部件結構上,其中該第一界面層為由該第一組成構成的一氧化物;一第二界面層,直接形成於該第二鰭式部件結構上,其中該第二界面層為由該第二組成構成的一氧化物;以及一閘極介電層,形成於該第一界面層及該第二界面層上方。
- 如請求項13之半導體裝置,其中該第二鰭式部件結構包括多個圓化角落,各自形成於該第二鰭式部件結構的一上表面與一側壁的交界處,且該第二鰭式部件結構的該上表面為一實質上平坦的表面。
- 如請求項13之半導體裝置,其中該等圓化角落由矽鍺構成。
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