TWI768714B - Circuit and method for frequency lock error detection and display driving circuit - Google Patents

Abstract

A circuit for frequency lock error detection is disclosed, which includes a comparison unit and a control unit. The comparison unit is configured to compare a common mode signal with a first reference voltage signal and a second reference voltage signal to generate a comparison result, in which the common mode signal corresponds to a different signal pair outputted by a timing controller. The control unit is configured to determine whether to reset a clock and data recovery circuit coupled to the timing controller based on the comparison result.

Description

Frequency lock error detection circuit, frequency lock error detection method and display driving circuit

The present invention relates to frequency lock error detection, and more particularly to a frequency lock error detection circuit with frequency lock error detection function, a frequency lock error detection method and a display driving circuit.

The data driver has a clock and a data recovery circuit, which can perform frequency locking processing on the data signal output by the timing controller, thereby generating a recovery clock signal and a recovery data signal. However, when the system is powered on, the common-mode voltage signal may be disturbed by noise, resulting in an error in subsequent frequency locking, resulting in an incorrect recovery clock signal and recovery data signal, thus causing problems in image display.

The purpose of the present invention is to provide a frequency lock error detection function, which can detect whether the frequency locked by the clock data recovery circuit is wrong when the display device system is turned on, and reset the clock when a frequency lock error is detected. The data recovery circuit avoids the wrong recovery clock signal and recovery data signal caused by the frequency locking error.

One aspect of the present invention is a frequency lock error detection circuit, which includes a comparison unit and a control unit. The comparison unit is used for comparing the common mode voltage signal with the first reference voltage signal and the second reference voltage signal to generate a first comparison result, wherein the common mode voltage signal corresponds to the differential output by the timing controller Signal pair. The control unit is used for determining whether to reset a clock and data recovery circuit coupled to the timing controller according to the first comparison result.

According to one or more embodiments of the present invention, the comparison unit includes a first comparator, a second comparator, and a logic gate. The first input terminal and the second input terminal of the first comparator are respectively used for inputting the first reference voltage signal and the common mode voltage signal. The first input terminal and the second input terminal of the second comparator are respectively used for inputting the common mode voltage signal and the second reference voltage signal. The first input terminal and the second input terminal of the logic gate are respectively coupled to the output terminals of the first comparator and the second comparator, and the output terminal of the logic gate is used for outputting the first comparison result.

According to one or more embodiments of the present invention, the frequency lock error detection circuit further includes a first phase shift circuit coupled to the second input terminal of the first comparator and the first input terminal of the second comparator.

According to one or more embodiments of the present invention, the above-mentioned frequency lock error detection circuit further includes a second phase shift circuit and a third phase shift circuit, which are respectively coupled to the output ends of the first comparator and the second comparator.

According to one or more embodiments of the present invention, the above-mentioned frequency lock error detection circuit further includes a digital comparator, which is used for comparing the recovery data signal generated by the clock data recovery circuit with the comparison data string to generate a second comparison result . The control unit is used for determining whether to reset the clock data recovery circuit according to the first comparison result and the second comparison result.

Another aspect of the present invention is directed to a frequency lock error detection method, which includes: comparing a common-mode voltage signal with a first reference voltage signal and a second reference voltage signal to generate a first comparison result, wherein the common-mode voltage The signal corresponds to the differential signal pair output by the timing controller; and according to the first comparison result, it is determined whether to reset the clock data recovery circuit coupled to the timing controller.

According to one or more embodiments of the present invention, the above-mentioned frequency lock error detection method further comprises: comparing the recovery data signal generated by the clock data recovery circuit with the comparison data string to generate a second comparison result; and according to the first comparison The result and the second comparison result determine whether to reset the clock data recovery circuit.

According to one or more embodiments of the present invention, the above-mentioned differential signal pair is generated according to the clock training data corresponding to the comparison data string.

Another aspect of the present invention is directed to a display driving circuit, which includes a timing controller, a clock data recovery circuit, and a frequency lock error detection circuit. The timing controller is used for generating differential signal pairs. The clock data recovery circuit is coupled to the timing controller and used for generating a recovery data signal and a recovery clock signal according to the differential signal pair. The frequency lock error detection circuit includes a comparison unit and a control unit, wherein the comparison unit is used for comparing the common mode voltage signal of the corresponding differential signal pair with the first reference voltage signal and the second reference voltage signal to generate a first comparison result , and the control unit is used for determining whether to reset the clock data recovery circuit according to the first comparison result.

Embodiments of the present invention are discussed in detail below. It should be appreciated, however, that the embodiments provide many applicable concepts that can be embodied in a wide variety of specific contexts. The discussed and disclosed embodiments are for illustration only, and are not intended to limit the scope of the present invention.

The terms used herein are for the purpose of describing particular embodiments only and are not intended to limit the scope of the claims. Unless otherwise limited, the singular form "a" or "the" may also be used to refer to the plural form.

The following description and claims may use the term "coupled" and its derivatives. In certain embodiments, "coupled" may mean that two or more elements are in direct physical or electrical contact with each other, or are not in direct contact with each other. "Coupled" may also refer to the mutual operation or action of two or more elements.

For simplicity and clarity of illustration, reference numerals and/or letters may be repeated herein among various embodiments, but this does not imply a causal relationship between the various embodiments and/or configurations discussed.

Please refer to FIG. 1 , which is a schematic diagram of a display device 100 according to an embodiment of the present invention. The display device 100 includes a display panel 110 , a data driver 120 , a scan driver 130 and a timing controller 140 . The display panel 110 may be a thin film transistor liquid crystal display panel (TFT-LCD), but is not limited thereto. The display panel 110 includes a plurality of pixel units P, a plurality of data lines D and a plurality of scan lines S. In the display panel 110, all the pixel units P form a matrix of M rows and N columns. Each pixel unit P includes a switching element T, which is driven by a data line D and a scan line S to be turned on in a specific time interval, so that the pixel unit P can display a corresponding gray scale. The data driver 120 is used for generating the data driving signals DS(1)-DS(M), which are respectively used for driving the data lines D, so as to transmit the grayscale data to the pixel units P of each row. The scan driver 130 is used for generating scan driving signals SS( 1 ) to SS(N) to drive each scan line S, so as to control the switching state of the switching element T in the pixel unit P of each column. During a certain time interval, the switching state of the switching element T is turned on, so that the pixel unit P displays the corresponding gray scale. Using the principle of persistence of vision, the human eye can see the complete display screen. The timing controller 140 controls the scan driver 130 to sequentially drive each scan line S of the display panel 110 , and controls the data driver 120 to send corresponding image data to each data of the display panel 110 when each scan line S is driven in sequence line D. In some embodiments, the data driver 120, the scan driver 130 and the timing controller 140 can be integrated into a single display driver circuit and fabricated in a single chip. Further, in some embodiments, the chip integrating the functions of the data driver 120 , the scan driver 130 and the timing controller 140 can also have an in-cell touch sensing structure or a touch panel above it. The display panel 110 provides a touch sensing function.

FIG. 2 is a partial circuit block diagram of a display driving circuit according to an embodiment of the present invention. In FIG. 2 , the clock and data recovery circuit 122 may be a part of the data driver 120 , which is coupled to the timing controller 140 and receives the differential signal pair V _DATA ⁺ output by the timing controller 140 , V _DATA ^- , according to which the reply data signal and the reply clock signal are generated. The frequency lock error detection circuit 200 includes a comparison unit 210 and a control unit 220, wherein the comparison unit 210 is used for comparing the common mode voltage signal corresponding to the differential signal pair V _DATA ⁺ , V _DATA ^- and the reference voltage signal V _REF1 and V _REF2 are compared to generate a comparison result CR1, and the control unit 220 is used for determining whether to reset the clock data recovery circuit 122 according to the comparison result CR1.

FIG. 3 is a flowchart of a frequency lock error detection method 300 according to an embodiment of the present invention. First, step S302 is performed, the system is powered on, the clock data recovery circuit is enabled to perform clock and data recovery, and then step S304 is performed, clock training data is provided, so that the differential signal output by the timing controller 140 is paired with V _DATA ⁺ , V _DATA ^- has a pattern that matches the clock training data. Afterwards, step S306 is performed to determine whether the potential of the common mode voltage signal V _CM is within a predetermined range, that is, within the range of the reference voltage signals V _REF1 and V _REF2 . The potential of the common-mode voltage signal V _CM may be an intermediate value of the potentials of the differential signal pair V _DATA ⁺ , V _DATA ⁻ , that is, V _CM =(V _DATA ⁺ +V _DATA ⁻ )/2. If the potential of the common-mode voltage signal V _CM is within the range of the reference voltage signals V _REF1 and V _REF2 , that is, V _REF2 <V _CM <V _REF1 , then proceed to step S308 to confirm whether the frequency is locked; otherwise, proceed to step S310 , stop the clock and data recovery, and reset the clock data recovery circuit, and then return to step S304.

In step S308, if it is determined that the frequency is locked, then proceed to step S312, complete the clock data recovery, and use the recovered data signal and the recovered clock signal for image display; otherwise, if it is determined that the frequency is not locked, then go back to step S304.

FIG. 4 is a schematic diagram of components of the comparison unit 210 of FIG. 2 . As shown in FIG. 4 , the common mode voltage signal V _CM is obtained by converting the differential signal pair V _DATA ⁺ and V _DATA ^- by the resistors R1 and R2, and the comparators 212A and 212B use the reference voltage signals V _REF1 and V _REF2 to pair the pair, respectively. The common mode voltage signal V _CM is compared, wherein the potential of the reference voltage signal V _REF1 is higher than that of the reference voltage signal V _REF2 . The positive and negative input terminals of the comparator 212A are respectively configured to input the common mode voltage signal V _CM and the reference voltage signal V _REF1 , and the positive and negative input terminals of the comparator 212B are respectively configured to input the reference voltage signal V _REF2 and the common mode voltage signal V _CM . The two input terminals and the output terminal of the logic gate 214 are respectively coupled to the output terminals of the comparators 212A and 212B and output the comparison result CR1 . In other embodiments, the comparators 212A and 212B can be changed to compare the common-mode voltage signal V _CM with the reference voltage signals V _REF1 and V _REF2 , respectively.

The comparison result CR1 output by the logic gate 214 is determined by the signals output by the output terminals of the comparators 212A and 212B. If the potential of the common-mode voltage signal V _CM is higher than the potential of the reference voltage signals V _REF1 and V _REF2 , the comparators 212A and 212B respectively output a low logic potential signal and a high logic potential signal, and the logic gate 214 outputs a comparison result CR1 of The potential is a high logic potential, which means that the potential of the common mode voltage signal V _CM is not within a predetermined range. If the potential of the common-mode voltage signal V _CM is lower than the potential of the reference voltage signal V _REF1 but higher than the potential of the reference voltage signal V _REF2 , the comparators 212A and 212B both output high logic potential signals, and the logic gate 214 outputs the comparison result. The potential of CR1 is a low logic potential, which means that the potential of the common mode voltage signal V _CM is within a predetermined range. If the potential of the common-mode voltage signal V _CM is lower than the potential of the reference voltage signals V _REF1 and V _REF2 , the comparators 212A and 212B respectively output a high logic potential signal and a low logic potential signal, and the logic gate 214 outputs a comparison result CR1 of The potential is a high logic potential, which means that the potential of the common mode voltage signal V _CM is not within a predetermined range. The logic gate 214 may be an exclusive OR gate or a logic unit composed of multiple other types of logic gates. When the comparison result CR1 is at a high logic level, the control signal CTRL output from the control unit 220 is used to stop the clock and data recovery, and reset the clock data recovery circuit 122 .

The negative input terminal of the comparator 212A and the positive input terminal of the comparator 212B may include a phase shift circuit (not shown) for removing the AC component of the common mode voltage signal V _CM . In addition, the output terminals of the comparators 212A and 212B may each include a phase shift circuit (not shown). The phase shift circuit referred to in this article can be an RC filter circuit or other suitable circuits.

FIG. 5 is a partial circuit block diagram of a display driving circuit according to an embodiment of the present invention. In FIG. 5 , the frequency lock error detection circuit 500 includes a comparison unit 510 , a digital comparator 520 and a control unit 530 . The comparison unit 510 is the same as or similar to the comparison unit 210 in the frequency lock error detection circuit 200 , and details are not described here. The digital comparator 520 is used for comparing the reply data signal DATA with the comparison data string COMP to generate a comparison result CR2, wherein the comparison data string COMP corresponds to the clock training data for generating the differential signal pair V _DATA ⁺ , V _DATA ^- . In some embodiments, if the reply data signal DATA conforms to the pattern of the comparison data string COMP, the output comparison result CR2 is a low logic level, and if the reply data signal DATA does not conform to the pattern of the comparison data string COMP, the output comparison result CR2 As a result, CR2 is a high logic level. When at least one of the comparison results CR1 and CR2 is at a high logic level, the control signal CTRL output from the control unit 530 is used to stop the clock and data recovery, and reset the clock data recovery circuit 122 .

FIG. 6 is a flowchart of a frequency lock error detection method 600 according to an embodiment of the present invention. Steps S602 , S604 , S606 , and S610 in the frequency lock error detection method 600 are respectively the same as or similar to steps S302 , S304 , S306 , and S310 in the frequency lock error detection method 300 , and are not repeated here. In step S608, if it is determined that the frequency is locked, the process proceeds to step S612, and the reply data signal is compared with the comparison data string; otherwise, if it is determined that the frequency is not locked, the process returns to step S604.

In step S612, if it is determined that the reply data signal conforms to the type of the comparison data string, then proceed to step S614 to complete the clock data recovery, and use the reply data signal and the reply clock signal for image display; otherwise, if it is determined that the frequency is not locked, Then go to step S610, stop the clock and data recovery, and reset the clock data recovery circuit, and then return to step S604.

FIG. 7A is an example of a comparison data string COMP according to an embodiment of the present invention. As shown in FIG. 7A , in this example, the comparison data string COMP has 9 bits (respectively COMP[1] to COMP[9]), and has the first to ninth types (respectively serial numbers 1 to 9) ), and in either form, the bit values 0 and 1 represent low potential and high potential, respectively. The recovery data signal DATA must conform to one of the first to ninth types, before it is determined that the frequency has been locked correctly, otherwise it is determined that the frequency is locked incorrectly, thereby resetting the clock data recovery circuit. In some embodiments, the reply data signal DATA is continuously compared with the comparison data string COMP in units of 9 bits. If all conform to the same type of the first to ninth types, it is determined that the frequency has been locked correctly; otherwise, it is determined that the frequency is locked incorrectly, thereby resetting the clock data recovery circuit. The above-mentioned judging method is similar to the type of judging whether the reply data signal DATA conforms to 5 consecutive high-level bits and then 4 consecutive low-level bits to cycle in sequence. The number of consecutive comparisons can be adjusted according to circuit design and product specifications.

FIG. 7B is an example of a comparison data string COMP according to an embodiment of the present invention. As shown in FIG. 7B , in this example, the comparison data string COMP also has 9 bits (respectively COMP[1] to COMP[9]), and has the first to ninth types (respectively serial numbers 1 to 9). 9), and in either type, the bit value is 0 and 1 to represent low potential and high potential, respectively, and the bit value X represents high/low potential (ie, no limit to low potential or high potential). The recovery data signal DATA must conform to one of the first to ninth types, before it is determined that the frequency has been locked correctly, otherwise it is determined that the frequency is locked incorrectly, thereby resetting the clock data recovery circuit. In some embodiments, the reply data signal DATA is continuously compared with the comparison data string COMP in units of 9 bits. If all conform to the same type of the 1st to 9th types, it is judged that the frequency has been locked correctly; otherwise, it is judged that the frequency locking is wrong, thereby resetting the clock data recovery circuit. The above judging method is similar to the method of judging whether the reply data signal DATA conforms to 4 consecutive high-level bits, followed by 1-bit, followed by 3 consecutive low-level bits, which are cycled in sequence with 1-bit intervals. Likewise, the number of consecutive comparisons can be adjusted according to circuit design and product specifications.

According to the above embodiments of the present invention, when the display device system is powered on, it is possible to detect whether the frequency locked by the clock data recovery circuit is wrong, and when the frequency locking error is detected, reset the clock data recovery circuit to avoid frequency locking. Errors are caused by the wrong reply clock signal and reply data signal.

Although the present invention has been disclosed above by the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, The protection scope of the present invention shall be determined by the scope of the appended patent application.

100: display device 110: display panel 120: data driver 122: clock data recovery circuit 130: scan driver 140: timing controller 200, 500: frequency lock error detection circuit 210, 510: comparison unit 212A, 212B: comparator 214: logic gate 220, 530: control unit 300, 600: frequency lock error detection method 520: digital comparator COMP: comparison data string CR1, CR2: comparison result CTRL: control signal D: data line DATA: reply data signal DS(1)~DS(M) : Data drive signal LOCK: Recovery clock signal P: Pixel unit R1, R2: Resistor S: Scan line S302, S304, S306, S308, S310, S602, S604, S606, S608, S610, S612, S614: Step SS (1)~SS(N): Scanning drive signal T: Switching element V _CM : Common mode voltage signal V _REF1 , V _REF2 : Reference voltage signal V _DATA ⁺ , V _DATA ^- : differential signal pair

For a more complete understanding of embodiments and their advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, wherein: 1 is a schematic diagram of a display device according to an embodiment of the present invention; [FIG. 2] is a partial circuit block diagram of a display driving circuit according to an embodiment of the present invention; 3 is a flowchart of a frequency lock error detection method according to an embodiment of the present invention; [FIG. 4] is a schematic diagram of the components of the comparison unit of [FIG. 2]; [FIG. 5] is a partial circuit block diagram of a display driving circuit according to an embodiment of the present invention; [FIG. 6] is a flowchart of a frequency lock error detection method according to an embodiment of the present invention; and [FIG. 7A] and [FIG. 7B] are examples of comparison data strings according to the embodiment of the present invention, respectively.

100: Display device

110: Display panel

120:Data Drive

130: Scan Drive

140: Timing Controller

D: data line

DS(1)~DS(M): Data-driven signal

P: pixel unit

S: scan line

SS(1)~SS(N): scan drive signal

T: switching element

Claims (10)

A frequency lock error detection circuit includes: a comparison unit for comparing a common mode voltage signal with a first reference voltage signal and a second reference voltage signal to generate a first comparison result , the common mode voltage signal corresponds to a differential signal pair output by a timing controller; and a control unit for determining whether to reset a clock data recovery (clock data) coupled to the timing controller according to the first comparison result and data recovery) circuit. The frequency lock error detection circuit as claimed in claim 1, wherein the comparison unit comprises: a first comparator, the first input terminal and the second input terminal of which are respectively used for inputting the first reference voltage signal and the common mode voltage signal; a second comparator whose first input terminal and second input terminal are respectively used to input the common mode voltage signal and the second reference voltage signal; and a logic gate whose first input terminal and second input terminal are respectively used The terminals are respectively coupled to the output terminals of the first comparator and the second comparator, and the output terminals are used for outputting the first comparison result. The frequency lock error detection circuit as claimed in claim 2, further comprising: a first phase shift circuit coupled to the second input terminal of the first comparator and the first input terminal of the second comparator. The frequency lock error detection circuit as claimed in claim 1 or 3, further comprising: a second phase shift circuit coupled to the output end of the first comparator; and a third phase shift circuit coupled to the second phase shift circuit Comparator output. The frequency lock error detection circuit as claimed in claim 1, further comprising: a digital comparator for comparing a reply data signal generated by the clock data restoration circuit with a comparison data string to generate a second a comparison result; wherein, the control unit is used for determining whether to reset the clock data recovery circuit according to the first comparison result and the second comparison result. A frequency lock error detection method, comprising: comparing a common mode voltage signal with a first reference voltage signal and a second reference voltage signal to generate a first comparison result, the common mode voltage signal corresponding to a timing control and determining whether to reset a clock data recovery circuit coupled to the timing controller according to the first comparison result. The frequency lock error detection method as claimed in claim 6, further comprising: generating a recovery data signal from the clock data recovery circuit with a comparison The data strings are compared to generate a second comparison result; and according to the first comparison result and the second comparison result, it is determined whether to reset the clock data recovery circuit. The frequency lock error detection method as claimed in claim 7, wherein the differential signal pair is generated according to a clock training data corresponding to the comparison data string. A display driving circuit includes: a timing controller for generating a differential signal pair; a clock data recovery circuit coupled to the timing controller, the clock data recovery circuit for generating a differential signal pair according to the differential signal pair A recovery data signal and a recovery clock signal; and a frequency lock error detection circuit, comprising: a comparison unit for corresponding to a common mode voltage signal of the differential signal pair, a first reference voltage signal and a second The reference voltage signals are compared to generate a first comparison result; and a control unit is used for determining whether to reset the clock data recovery circuit according to the first comparison result. The display driving circuit of claim 9, wherein the frequency lock error detection circuit further comprises: a digital comparator for comparing the reply data signal with a comparison data string to generate a second comparison result; Wherein, the control unit is used for determining whether to reset the clock data recovery circuit according to the first comparison result and the second comparison result.

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