TWI768489B - Structure for hall sensor and method of forming the same - Google Patents

Abstract

Structures for a Hall sensor and methods of forming a structure for a Hall sensor. The structure includes a semiconductor body having a top surface and a sloped sidewall defining a Hall surface that intersects the top surface. The structure further includes a well in the semiconductor body and multiple contacts in the semiconductor body. The well has a section positioned in part beneath the top surface and in part beneath the Hall surface. Each contact is coupled to the section of the well beneath the top surface of the semiconductor body.

Description

Structure of Hall sensor and method of forming the same

The present invention relates to the manufacture of integrated circuits and semiconductor devices, and more particularly, to the structure of a Hall sensor and a method of forming the structure of the Hall sensor.

Hall sensors are a common type of sensing element used in various commercial products such as home appliances, gaming systems, construction equipment, utility meters, and motor vehicles, and are based on sensing magnetic fields. A magnetic field is a vector characterized by a position-dependent field strength and field direction. According to the Lorentz force law, a magnetic field exerts a force on a moving charged particle. Hall sensors rely on creating a voltage difference across an electrical conductor (ie, Hall voltage), which is created by the combination of a current flowing in the conductor and a magnetic field with a field direction perpendicular to the flowing current . Conventional Hall sensors, which are planar devices, have low sensitivity when detecting a magnetic field with a field direction parallel to the surface of the substrate on which the Hall sensor is formed.

There is a need for improved Hall sensor structures and methods of forming Hall sensor structures.

According to an embodiment of the present invention, a structure of a Hall sensor is provided. The structure includes a semiconductor body having a top surface and sloped sidewalls defining a Hall surface that intersects the top surface. The structure further includes a well in the semiconductor body and a plurality of contacts in the semiconductor body. The well has a section partially below the top surface and partially below the Hall surface. Contacts are coupled with the section of the well below the top surface of the semiconductor body.

In another embodiment of the present invention, a method of forming a structure of a Hall sensor is provided. The method includes forming a well in a semiconductor body having a top surface and sloped sidewalls defining a Hall surface intersecting the top surface. The well has a section partially below the top surface and partially below the Hall surface. The method further includes forming a plurality of contacts in the semiconductor body. Contacts are coupled with the section of the well below the top surface of the semiconductor body.

10: Groove

11: Top surface

12: Substrate

13: Section

14: Etch Mask

15: Corner

16: Sidewall

17: Corner

18: Bottom of groove

20: Shallow Trench Isolation Region

22: Well

24: Well

26: Section

28: Section

30: Section

32: Section

34: Section

35: Hall surface

36: Doping region

38: Contact

40: Contact

42: Contact

44: Contact

46: Contact

48: Contact

50: Doping region

60: Corner

62: Corner

64: Semiconductor fins

66: Sidewall

68: Top surface

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate various embodiments of the invention and, together with the general description of the invention given above and the detailed description of these embodiments given below, serve to explain the advantages of the invention. these examples. In the drawings, the same reference numerals designate similar features in the different views.

1 shows a top view of the structure of a Hall sensor in an initial manufacturing stage of a process method according to an embodiment of the present invention.

FIG. 2 shows a cross-sectional view taken generally along line 2-2 in FIG. 1 .

FIG. 3 shows the structure of the Hall sensor at a manufacturing stage subsequent to that of FIG. 1 top view.

FIG. 4 shows a cross-sectional view taken generally along line 4-4 in FIG. 3 .

FIG. 5 shows a top view of the structure of the Hall sensor at a manufacturing stage subsequent to that of FIG. 3 .

FIG. 6 shows a cross-sectional view taken generally along line 6-6 in FIG. 5. FIG.

7 shows a top view of the structure of a Hall sensor according to an alternative embodiment of the present invention.

Referring to FIGS. 1 and 2 and according to an embodiment of the present invention, the grooves 10 are formed in the substrate 12 in the form of cavities or grooves. Substrate 12 may be a bulk wafer composed of a single crystal semiconductor material (eg, single crystal silicon), and in one embodiment, substrate 12 may have lightly doped p-type conductivity. In one embodiment, the grooves 10 may be formed by lithography and etching processes. To this end, an etch mask 14 is formed over the top surface of the substrate 12 . The etch mask 14 may be a hard mask that is patterned by lithography and etching processes to define openings with a given area at predetermined locations of the recesses 10 . The recesses 10 are etched in the substrate 12 using one or more etch processes in the presence of the etch mask 14 . The portion of the substrate 12 not covered by the etching mask 14 is removed by the etching process.

The grooves 10 in the substrate 12 may have cross-sectional profiles created by selective etchants. In one embodiment, groove 10 may have a V-shaped cross-sectional profile. For example, the etchant may be a wet chemical etchant such as a solution comprising tetramethylammonium hydroxide (TMAH), a solution comprising potassium hydroxide (KOH), or a solution comprising ethylenediamine and catechol (EDP). solution. The etchant can exhibit selectivity with respect to the crystallographic orientation of the semiconductor material of the substrate 12, and different etchings occur along different crystallographic orientations rate. The difference in etch rate produces the shape of the groove 10 . For example, if the substrate 12 includes [100] oriented silicon, the (100) planes are etched at a significantly higher rate than the (111) planes, resulting in a self-limiting etch process that forms the recesses 10, wherein vertical etching The rate is significantly greater than the lateral etch rate.

The cross-sectional profile of the substrate 12 surrounding the recess 10 includes sidewalls 16 extending from the top surface 11 of the substrate 12 to the surface of the substrate at the bottom 18 of the recess. Sidewall 16 defines an angled or inclined surface relative to a plane containing top surface 11 of substrate 12 . In one embodiment in which the substrate 12 includes [100] oriented silicon with a diamond lattice, the sidewalls 16 may be inclined at an angle of inclination of about 35 degrees relative to the plane including the top surface 11 , as opposed to an angle of inclination relative to the [100] surface normal. [111] The angle of the normal to the plane is consistent. The side walls 16 extend from the top surface 11 of the base plate 12 to a given depth into the base plate 12 and intersect the groove bottoms 18 disposed laterally between the opposing side walls 16 .

The surface of substrate 12 exposed to groove bottom 18 may be contained in a plane parallel to the plane containing top surface 11 of substrate 12 . Each side wall 16 intersects the surface at the bottom 18 of the groove at a corner 17 extending along the lower edge of the side wall 16 . Corners 17 are provided along opposite sides of a groove bottom 18 which extends laterally from one corner 17 to the opposite corner 17 . Each side wall 16 also intersects the top surface 11 of the substrate 12 at a corner 15 extending along the upper edge of the side wall 16 . The surface of substrate 12 at groove bottom 18 may be rectangular around the perimeter defined by corners 17 , and the top surface 11 of substrate 12 around the entrance to groove 10 may likewise have a rectangular shape around the perimeter defined by corner 15 .

Please refer to FIGS. 3 and 4 , wherein the same reference numerals denote similar features in FIGS. 1 and 2 , and in the next manufacturing stage, the etch mask 14 is removed and a shallow groove 10 is formed around the groove 10 . trench isolation region 20 . Shallow trench isolation regions 20 may include a dielectric material, such as silicon dioxide, deposited by chemical vapor deposition in trenches etched in substrate 12 by a masked etch process, polished, and deglazed. The shallow trench isolation regions 20 are slightly larger in size (eg, in length and width) than the grooves 10 such that the corners 15 are surrounded by the shallow trench isolation regions 20 . Due to this dimensional difference, portions 13 of substrate 12 are provided in stripes on top surface 11 between corners 15 and shallow trench isolation regions 20 . The top surface 11 of the portion 13 of the substrate 12 may be flat and planar.

Wells 22 , 24 of opposite polarity conductivity types are formed in the substrate 12 below the surface of the sidewall 16 and in the portion 13 of the substrate 12 below the top surface 11 . Well 22 may be formed by introducing a dopant of one conductivity type, eg, by ion implantation in the portion of substrate 12 below each sidewall 16 of recess 10 and in portion 13 of substrate 12 surrounding recess 10 . The wells 24 may be formed by introducing dopants of opposite conductivity types, eg, by ion implantation in the portion of the substrate 12 below each sidewall 16 and in the portion 13 of the substrate 12 surrounding the recess 10 . Corresponding patterned implant masks may be used to define selected locations of the wells 22, 24 and stripped after each well 22, 24 is formed. In one embodiment, well 22 may be formed before well 24 is formed.

In one embodiment, the semiconductor material of well 22 may include an n-type dopant (eg, phosphorous or arsenic) effective to impart n-type conductivity, and the semiconductor material of well 24 may include p-type effective to impart p-type conductivity dopant (eg, boron). Implantation conditions (eg, kinetic energy and dose) are selected to form each well 22, 24 with the desired doping profile and concentration. In one embodiment, the wells 22, 24 may be composed of a moderately doped semiconductor material formed by selecting implant conditions. The wells 22 , 24 located below the top surface 11 respectively extend a given depth into the substrate 12 relative to the top surface 11 . In one embodiment, the wells 22, 24 may extend the same depth relative to the top surface 11 to in the substrate 12 .

The well 22 includes sections 26 , 28 extending in strips down the sidewall 16 of the groove 10 in the base plate 12 and also in the portion 13 of the base plate 12 . The well 22 further includes a section 30 extending in the substrate 12 down the sidewall 16 of the groove 10 in the form of a strip, and also in the portion 13 of the substrate 12 at the top surface 11 . Section 30 may be of larger size than either section 26, 28. The well 24 further includes sections 32 , 34 extending in strips down the sidewall 16 of the groove 10 and also in the portion 13 of the substrate 12 at the top surface 11 . Section 32 of well 24 is laterally located between sections 26 and 30 of well 22 , and section 34 of well 24 is laterally located between sections 28 and 30 of well 22 .

The surface of the substrate 12 located at the groove bottom 18 is masked during the implantation to form the wells 22, 24, so that the portion of the substrate 12 located below the groove bottom 18 retains its original conductivity (eg, lightly doped p-type conductivity sex). The wells 22 , 24 terminate at the corners 17 because the surface of the substrate 12 at the bottom 18 of the grooves is masked during the implantation in which the wells 22 , 24 are formed. Portions of the sidewall 16 around the sections 26 , 28 are also masked during implants to form wells 22 and during implants to form wells 24 . Thus, the substrate 12 below these portions of the sidewalls 16 also maintains the original conductivity of the substrate 12 . The wells 22, 24 may comprise moderately doped semiconductor material.

Please refer to FIGS. 5 and 6 , wherein the same reference numerals denote similar features in FIGS. 3 and 4 , and in the next manufacturing stage, the process is continued in parallel to form corresponding Hall sensors on each side wall 16 . Subsequent discussion will relate to forming a Hall sensor on one of the side walls 16, it being understood that another Hall sensor is being formed on the other side wall 16. FIG.

A doped region 36 is formed in the portion of the section 30 of the well 22, and contacts 38, 40 are formed in the doped region 36 in the form of discrete doped regions. Contacts 38 , 40 have a phase with doped region 36 Reverse polarity conductivity type. Doped regions 36 and contacts 38 , 40 are located in portion 13 of substrate 12 . The doped regions 36 extend to a shallower depth into the substrate 12 than the wells 22 to retain portions of the wells 22 below the doped regions 36 . The contacts 38 , 40 are coupled to the portion of the well 22 below the doped region 36 , which in turn couple the contacts 38 , 40 to the section 30 of the well 22 below the sidewall 16 . Portions of doped region 36 are located between contacts 38 and 40 to provide electrical isolation. The doped region 36 has the same conductivity type but a higher dopant concentration than the sections 32 , 34 .

In the portions of the sections 26, 28 of the well 22 located in the portion 13 of the substrate 12 of the top surface 11, contacts 42, 44 are formed, respectively, in the form of doped regions. Contacts 42 , 44 are of the same conductivity type as sections 26 , 28 but higher dopant concentrations, and are coupled to sections 26 , 28 of well 22 , respectively. Contacts 46, 48 are respectively formed in the form of doped regions in the portion of the substrate 12 located at the bottom 18 of the recess. Contact 46 couples section 26 of well 22 with section 30 of well 22 . Contact 48 couples section 28 of well 22 with section 30 of well 22 . Contacts 46, 48 have the same conductivity type as segments 26, 28 but higher dopant concentrations. A doped region 50 is also formed in the portion of the substrate 12 exposed by the groove bottom 18 . The doped region 50 has the opposite conductivity type as the contacts 46 , 48 .

The doped regions 36 , 50 may be formed by introducing dopants, eg, by ion implantation at selected locations in the substrate 12 . A patterned implant mask can be used to define the selected locations of the doped regions 36, 50 and stripped after implantation. In one embodiment where well 22 is an n-type semiconductor material and well 24 is a p-type semiconductor material, the semiconductor material comprising doped regions 36, 50 may include p-type dopants effective to impart p-type conductivity, and may be heavy doping. Implantation conditions are selected to form doped regions 36, 50 with desired doping profiles and concentrations.

Doping is introduced by, for example, ion implantation at selected locations in the substrate 12 objects, contacts 38, 40, 42, 44, 46, 48 may be formed. A patterned implant mask can be used to define this selected location of the contacts 38, 40, 42, 44, 46, 48 and stripped after implantation. In one embodiment where well 22 is an n-type semiconductor material and well 24 is a p-type semiconductor material, the semiconductor material making up contacts 38, 40, 42, 44, 46, 48 may comprise n-type dopant effective to impart n-type conductivity impurities, and can be heavily doped. Implantation conditions are selected to form doped regions 36, 50 with desired doping profiles and concentrations.

The portion of section 30 of well 22 below sidewall 16 is bounded by doped region 36 , doped region 50 , section 32 of well 24 , and section 34 of well 24 . These boundaries define a Hall surface 35 having a given area (eg, length and width) at the surface of sidewall 16 . Hall surface 35 may extend the entire height of sidewall 16 from corner 15 to corner 17, and Hall surface 35 has a width w extending from one of the sections 32 of the well 24 to the opposite one of the sections 34 of the well 24 . The Hall surface 35 is contained in a plane inclined at an inclination relative to the top surface 11 of the substrate 12 and having a vertical component relative to the plane containing the top surface 11 of the substrate 12 .

In the representative embodiment, the grooves 10 are etched in the substrate 12 before the wells 22 , 24 of opposite conductivity types are formed in the substrate 12 . In an alternative embodiment, after wells 22 , 24 of opposite conductivity types are formed in substrate 12 , recess 10 may be etched in substrate 12 , followed by doped regions 36 , 50 and contacts 38 , 40 , 42 , 44 , 46, 48.

In use, a bias potential may be applied between the terminals provided by contacts 38 and 44 to establish current flow in well 22 . A magnetic field with a field direction that intersects the Hall surface 35 located on the sidewall 16 will generate a Hall voltage. Hall surface 35 defines the sensing surface of the Hall sensor. The interaction between the current and the magnetic field generates a potential difference that is sensed between the terminals provided by contact 42 and contact 40 at the Hall voltage. Due to the provision of non-planar geometry The inclination of the side walls 16 allows the Hall sensor to sense magnetic fields characterized by a field direction parallel or nearly parallel to the top surface 11 of the substrate 12 with greater sensitivity than conventional Hall sensors.

Please refer to FIG. 7 , wherein like reference numerals refer to similar features in FIG. 5 , and according to an alternative embodiment, instead of recesses 10 in the form of cavities recessed with respect to the top surface 11 of the substrate 12 , the substrate 12 may be The semiconductor fins 64 protruding from the top surface 11 of the semiconductor fins 64 form Hall sensors. Sidewalls 66 of semiconductor fin 64 and top surface 68 of semiconductor fin 64 may be used to form wells 22, 24, doped regions 36, 50, and contacts 38, 40, 42, 44, 46, 48. Similar to the sidewalls 16 of the recess 10 , the sidewalls 66 of the semiconductor fins 64 are inclined or angled with respect to the plane containing the top surface 11 of the substrate 12 . Portions of the top surface 11 of the substrate 12 surround the bases of the semiconductor fins 64 . The top surface 68 of the semiconductor fin 64 may be contained in a plane parallel to the plane of the top surface 11 of the substrate 12 . Each side wall 66 intersects a top surface 68 at a corner 62 that extends along the upper edge of the side wall 66 . Each side wall 66 also intersects the top surface 11 of the substrate 12 at a corner 60 extending along the lower edge of the side wall 66 . The top surfaces 68 of the semiconductor fins 64 may be rectangular at the corners 62 , and the semiconductor fins 64 may have a similarly rectangular shape at the corners 62 .

Hall surface 35 may extend the entire height of each sidewall 66 from corner 15 to corner 17, and Hall surface 35 has a width extending from one of the sections 32 of the well 24 to an opposite one of the sections 34 of the well 24 . Hall surface 35 is contained in a plane inclined at an inclination relative to top surface 68 of semiconductor fin 64 and having a vertical component relative to the plane containing top surface 68 of semiconductor fin 64 .

The above method is used for the manufacture of integrated circuit chips. Manufacturers can use raw wafer form (eg, as a single wafer with multiple unpackaged dies), as a bare die, or in packaged Form distribution of the resulting integrated circuit die. The wafer may be integrated with other wafers, discrete circuit elements and/or other signal processing devices as part of an intermediate or final product. The final product can be any product that includes an integrated circuit chip, such as a computer product with a central processing unit or a smartphone.

References herein to terms modified by approximate language such as "about," "approximately," and "substantially" are not limited to the precise value specified. The approximation language may correspond to the precision of the instrument used to measure the value, and unless otherwise relied on the precision of the instrument, may represent +/- 10% of the stated value.

Terms such as "vertical", "horizontal", etc. are cited herein as examples to establish a frame of reference, not limitation. The term "horizontal" as used herein is defined as a plane parallel to the conventional plane of the semiconductor substrate, regardless of its actual three-dimensional spatial orientation. The terms "vertical" and "orthogonal" refer to directions perpendicular to the horizontal plane as just defined. The term "lateral" refers to the direction within the horizontal plane.

A feature that is "connected" or "coupled" to another feature may be directly connected or coupled to the other feature, or one or more intervening features may be present. A feature may be "directly connected" or "directly coupled" to another feature if there are no intervening features. A feature may be "indirectly connected" or "indirectly coupled" to another feature if at least one intervening feature is present. A feature that is "on" or "in contact with" another feature may be directly on or in direct contact with the other feature, or one or more intervening features may be present. A feature may be directly "on" or "directly in contact with" another feature if there are no intervening features. A feature may be "not directly on" or "not in direct contact with" another feature if at least one intervening feature is present.

Various embodiments of the present invention have been described for purposes of illustration, and are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over techniques known in the marketplace, or to enable one of ordinary skill in the art to understand the embodiments disclosed herein.

11: Top surface

12: Substrate

22: Well

24: Well

26: Section

28: Section

30: Section

32: Section

34: Section

36: Doping region

38: Contact

40: Contact

42: Contact

44: Contact

Claims (20)

A structure for a Hall sensor, the structure comprising: a semiconductor body including a first surface and sloped sidewalls defining a Hall surface intersecting the first surface; a first well in the semiconductor body, the first well a well having a first section partially under the first surface and partially under the Hall surface; and a plurality of contacts in the semiconductor body, each of the plurality of contacts with the first surface of the semiconductor body The first section of the first well below is coupled. The structure of claim 1, wherein the semiconductor body is a semiconductor substrate, and the sloped sidewalls extend from the first surface of the semiconductor substrate into the semiconductor substrate to define portions of the recess. The structure of claim 2, wherein the semiconductor substrate includes a second surface exposed at the bottom of the groove, and the Hall surface on the inclined sidewall intersects the second surface of the semiconductor substrate at a corner . The structure of claim 2, wherein the Hall surface on the inclined sidewall intersects the first surface of the semiconductor substrate at a corner. The structure of claim 1, further comprising: a semiconductor substrate having a top surface, wherein the semiconductor body is a semiconductor fin protruding from the top surface of the semiconductor substrate, the first surface being the top of the semiconductor fin surface, and the Hall surface on the inclined sidewall is inclined at an angle relative to the top surface of the semiconductor fin. The structure of claim 5, wherein the horn on the inclined side wall The Er surface intersects the top surface of the semiconductor substrate at a corner. The structure of claim 5, wherein the Hall surface on the sloped sidewall intersects the top surface of the semiconductor fin at a corner. The structure of claim 1, wherein the first well is of a first conductivity type, and further comprising: a second well in the semiconductor body, the second wells having first regions each extending along the sloped sidewalls segment and a second section, and the second well has a second conductivity type of opposite polarity to the first conductivity type, wherein the Hall surface on the sloping sidewall is located laterally to the first conductivity type of the second well between the section and the second section of the second well. The structure of claim 1, wherein the first well includes a second section located below the first surface of the semiconductor body and extending along the sloped sidewall, and further comprising: a second well located in the semiconductor body , the second well has a first section partially laterally disposed between the second section of the first well and the Hall surface, wherein the first well has a first conductivity type, and the second The well has a second conductivity type of opposite polarity to the first conductivity type. The structure of claim 9, wherein the first well includes a third section extending in the semiconductor body below the first surface of the semiconductor body and below the sloped sidewall, and the second well includes A portion of the second section laterally located between the third section of the first well and the Hall surface. The structure of claim 10, wherein the plurality of contacts includes a first contact and a second contact located in the semiconductor body, the plurality of contacts having the first conductivity type type having a higher dopant concentration than the first well, the first contact is coupled to the second section of the first well located on the first surface of the semiconductor body, and the second A contact is coupled with the third section of the first well located on the first surface of the semiconductor body. The structure of claim 11, further comprising: a doped region in the semiconductor body at the first surface, the doped region having the second conductivity type, and the doped region comprising the doped region positioned to The first contact is isolated from the portion of the second contact. The structure of claim 12, wherein the semiconductor body is a semiconductor substrate, and the Hall surface on the sloped sidewall extends from the first surface of the semiconductor substrate into the semiconductor substrate to define a portion of the groove , the semiconductor substrate includes a second surface exposed at the bottom of the groove, and the doped region is located in the semiconductor substrate below the second surface. The structure of claim 12, further comprising: a semiconductor substrate having a top surface, wherein the semiconductor body is a semiconductor fin protruding from the top surface of the semiconductor substrate, the first surface being a top of the semiconductor fin surface, the Hall surface on the inclined sidewall is inclined at an angle relative to the top surface of the semiconductor fin, and the doped region is located in the semiconductor substrate below the top surface. A method of forming a structure of a Hall sensor, the method comprising forming a first well in a semiconductor body including a first surface and sloping sidewalls defining a Hall surface intersecting the first surface, wherein the first surface a well having a first section partially under the first surface and partially under the hall surface; and forming a plurality of contacts in the semiconductor body, wherein each of the plurality of contacts is associated with The first section of the first well below the first surface of the semiconductor body is coupled. The method of claim 15, wherein the semiconductor body is a semiconductor substrate, and further comprising: etching a groove in the semiconductor substrate, wherein the sloped sidewall extends from the first surface of the semiconductor substrate to the semiconductor substrate , to define the portion of the groove. The method of claim 16, wherein the semiconductor substrate includes a second surface exposed at the bottom of the groove, and the Hall surface on the sloped sidewall intersects the second surface of the semiconductor substrate at the first corner, and the Hall surface on the inclined sidewall intersects the second surface of the semiconductor substrate at the second corner. The method of claim 15, further comprising: patterning a semiconductor fin protruding from a top surface of a semiconductor substrate, wherein the first surface is the top surface of the semiconductor fin and the horn on the sloped sidewall The fin surface is inclined at an angle relative to the top surface of the semiconductor fin. The method of claim 15, wherein the first well is of a first conductivity type, and further comprising: forming a second well in the semiconductor body, wherein the second well has a first well each extending along the sloped sidewall A section and a second section, the second well has a second conductivity type of opposite polarity to the first conductivity type, and the Hall surface on the sloping sidewall is located laterally to the first conductivity type of the second well between the section and the second section of the second well. The method of claim 15, wherein the first well comprises a a second section of the conductor body extending below the first surface and along the sloping sidewall, and further comprising: forming a second well in the semiconductor body, wherein the second well has a portion laterally disposed from the first well The first section between the second section and the Hall surface, the first well has a first conductivity type, and the second well has a second conductivity type of opposite polarity to the first conductivity type.

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