TW202125804A - Hall sensors with a three-dimensional structure - Google Patents

Abstract

Structures for a Hall sensor and methods of forming a structure for a Hall sensor. The structure includes a semiconductor body having a top surface and a sloped sidewall defining a Hall surface that intersects the top surface. The structure further includes a well in the semiconductor body and multiple contacts in the semiconductor body. The well has a section positioned in part beneath the top surface and in part beneath the Hall surface. Each contact is coupled to the section of the well beneath the top surface of the semiconductor body.

Description

Hall sensor with three-dimensional structure

The present invention relates to the manufacture of integrated circuits and semiconductor devices, in particular to the structure of the Hall sensor and the method of forming the structure of the Hall sensor.

Hall sensors are a common type of sensing element used in various commercial products such as household appliances, gaming systems, construction equipment, utility meters, and motor vehicles, and are based on sensing magnetic fields. The magnetic field is a vector characterized by position-dependent field strength and field direction. According to Lorentz's force law, a magnetic field can exert a force on moving charged particles. The Hall sensor relies on generating a voltage difference (ie, Hall voltage) across an electrical conductor, which is generated by a combination of a current flowing in the conductor and a magnetic field whose field direction is perpendicular to the flowing current . The conventional Hall sensor (which is a planar device) has low sensitivity when the detection field direction is parallel to the magnetic field on the surface of the substrate forming the Hall sensor.

There is a need for an improved structure of the Hall sensor and a method of forming the structure of the Hall sensor.

According to an embodiment of the present invention, a structure of a Hall sensor is provided. The structure includes a semiconductor body having a top surface and inclined sidewalls defining a Hall surface intersecting the top surface. The structure further includes a well in the semiconductor body and a plurality of contacts in the semiconductor body. The well has a section partly below the top surface and partly below the Hall surface. Each contact is coupled with the section of the well located below the top surface of the semiconductor body.

In another embodiment of the present invention, a method of forming the structure of a Hall sensor is provided. The method includes forming a well in a semiconductor body having a top surface and inclined sidewalls defining a Hall surface intersecting the top surface. The well has a section partly below the top surface and partly below the Hall surface. The method further includes forming a plurality of contacts in the semiconductor body. Each contact is coupled with the section of the well located below the top surface of the semiconductor body.

10: Groove

11: top surface

12: substrate

13: part

14: Etching mask

15: corner

16: sidewall

17: corner

18: The bottom of the groove

20: Shallow trench isolation area

22: trap

24: trap

26: section

28: section

30: section

32: section

34: section

35: Hall surface

36: doped area

38: contact

40: contact

42: contact

44: contact

46: contact

48: contact

50: doped area

60: corner

62: corner

64: semiconductor fins

66: side wall

68: top surface

The drawings included in and constituting a part of this specification illustrate various embodiments of the present invention, and together with the above general description of the present invention and the following detailed description of these embodiments are used to explain the present invention. These examples. In the drawings, the same reference symbols indicate similar features in different views.

FIG. 1 shows a top view of the structure of the Hall sensor in the initial manufacturing stage of the manufacturing method according to an embodiment of the present invention.

Fig. 2 shows a cross-sectional view taken generally along the line 2-2 in Fig. 1.

Figure 3 shows the structure of the Hall sensor in the manufacturing stage after Figure 1 Top view.

Fig. 4 shows a cross-sectional view taken generally along the line 4-4 in Fig. 3.

FIG. 5 shows a top view of the structure of the Hall sensor in a manufacturing stage after FIG. 3.

Fig. 6 shows a cross-sectional view taken generally along line 6-6 in Fig. 5.

FIG. 7 shows a top view of the structure of the Hall sensor according to an alternative embodiment of the present invention.

Please refer to FIGS. 1 and 2 and according to an embodiment of the present invention, a groove 10 is formed in the substrate 12 in the form of a cavity or a groove. The substrate 12 may be a bulk wafer composed of a single crystal semiconductor material (for example, single crystal silicon), and in one embodiment, the substrate 12 may have lightly doped p-type conductivity. In one embodiment, the groove 10 may be formed by a lithography and etching process. To this end, an etching mask 14 is formed over the top surface of the substrate 12. The etching mask 14 may be a hard mask, which is patterned by a lithography and etching process to define an opening with a given area at a predetermined position of the groove 10. In the presence of the etching mask 14, one or more etching processes are used to etch the groove 10 in the substrate 12. The portion of the substrate 12 that is not covered by the etching mask 14 is removed by the etching process.

The groove 10 in the substrate 12 may have a cross-sectional profile produced by selecting an etchant. In one embodiment, the groove 10 may have a V-shaped cross-sectional profile. For example, the etchant may be a wet chemical etchant, such as a solution containing tetramethylammonium hydroxide (TMAH), a solution containing potassium hydroxide (KOH), or a solution containing ethylenediamine and catechol (EDP) Solution. The etchant can exhibit selectivity with respect to the crystal orientation of the semiconductor material of the substrate 12, and different etching occurs along different crystal directions. rate. The difference in the etching rate produces the shape of the groove 10. For example, if the substrate 12 contains [100]-oriented silicon, the (100) plane is etched at a significantly higher rate than the (111) plane, resulting in a self-limiting etching process for forming the groove 10, where the vertical etching The rate is significantly greater than the lateral etch rate.

The cross-sectional profile of the substrate 12 surrounding the groove 10 includes a side wall 16 extending from the top surface 11 of the substrate 12 to the surface of the substrate at the bottom 18 of the groove. The side wall 16 defines a surface that is angled or inclined with respect to the plane containing the top surface 11 of the substrate 12. In an embodiment where the substrate 12 includes [100] oriented silicon with a diamond lattice, the sidewalls 16 may be inclined at an inclination angle of about 35 degrees with respect to the plane containing the top surface 11, as opposed to the [100] surface normal [111] The angles of the normals of the plane are the same. The side wall 16 penetrates a given depth from the top surface 11 of the substrate 12 into the substrate 12 and intersects the bottom 18 of the groove, which is laterally arranged between the opposite side walls 16.

The surface of the substrate 12 exposed to the bottom 18 of the groove may be contained in a plane parallel to the plane containing the top surface 11 of the substrate 12. Each side wall 16 intersects the surface at the bottom 18 of the groove at a corner 17 extending along the lower edge of the side wall 16. The corners 17 are arranged along opposite sides of the groove bottom 18, and the groove bottom extends laterally from one corner 17 to the opposite corner 17. Each side wall 16 also intersects the top surface 11 of the substrate 12 at a corner 15 extending along the upper edge of the side wall 16. The surface of the substrate 12 located at the bottom 18 of the groove may be rectangular around the periphery defined by the corner 17, and the top surface 11 of the substrate 12 surrounding the entrance of the groove 10 may also have a rectangular shape around the periphery defined by the corner 15.

Please refer to FIGS. 3 and 4, where the same component symbols represent similar features in FIGS. Trench isolation region 20. The shallow trench isolation region 20 may include a dielectric material, such as silicon dioxide, which is deposited by chemical vapor deposition in the trench etched in the substrate 12 by a masked etching process, polished, and deglazed. The shallow trench isolation region 20 is slightly larger in size (for example, in length and width) than the groove 10 so that the corner 15 is surrounded by the shallow trench isolation region 20. Due to this size difference, the portion 13 of the substrate 12 is provided in a strip form on the top surface 11 between the corner 15 and the shallow trench isolation region 20. The top surface 11 of the portion 13 of the substrate 12 may be flat and planar.

In the substrate 12 below the surface of the side wall 16 and in the portion 13 of the substrate 12 below the top surface 11, wells 22, 24 of conductivity type having opposite polarities are formed. The well 22 can be formed by introducing dopants of one conductivity type, for example, by ion implantation in the portion of the substrate 12 under the side walls 16 of the groove 10 and in the portion 13 of the substrate 12 surrounding the groove 10. The well 24 may be formed by, for example, ion implantation in the portion of the substrate 12 under each side wall 16 and in the portion 13 of the substrate 12 surrounding the recess 10 to introduce dopants having opposite conductivity types. Corresponding patterned implant masks can be used to define selected locations of the wells 22, 24, and peel off after the wells 22, 24 are formed. In one embodiment, the well 22 may be formed before the well 24 is formed.

In one embodiment, the semiconductor material of the well 22 may include an n-type dopant (for example, phosphorus or arsenic) that is effective to impart n-type conductivity, and the semiconductor material of the well 24 may include a p-type that effectively imparts p-type conductivity. Dopants (for example, boron). The implantation conditions (e.g., kinetic energy and dose) are selected to form each well 22, 24 with the desired doping profile and concentration. In one embodiment, the wells 22, 24 may be composed of a moderately doped semiconductor material formed by selective implantation conditions. The wells 22 and 24 located below the top surface 11 respectively extend into the substrate 12 by a given depth relative to the top surface 11. In one embodiment, the wells 22, 24 may extend to the same depth relative to the top surface 11 to In the substrate 12.

The well 22 includes sections 26, 28, which extend in the form of a strip in the substrate 12 along the side wall 16 of the groove 10 and are also located in the portion 13 of the substrate 12. The well 22 further includes a section 30 which extends in the form of a strip in the substrate 12 along the side wall 16 of the groove 10 and is also located in the portion 13 of the substrate 12 at the top surface 11. Compared to any of the sections 26, 28, the section 30 may have a larger size. The well 24 further includes sections 32, 34 that extend down the sidewall 16 of the groove 10 in the form of a strip and are also located in the portion 13 of the substrate 12 at the top surface 11. The section 32 of the well 24 is laterally located between the section 26 and the section 30 of the well 22, and the section 34 of the well 24 is laterally located between the section 28 and the section 30 of the well 22.

During the implantation of the wells 22 and 24, the surface of the substrate 12 located at the bottom 18 of the groove is masked. Therefore, the portion of the substrate 12 located below the bottom 18 of the groove maintains its initial conductivity (for example, lightly doped p-type conductive sex). The wells 22, 24 terminate at the corner 17, because the surface of the substrate 12 at the bottom 18 of the groove is masked during the implantation to form the wells 22, 24. The portions of the sidewall 16 around the sections 26, 28 are also masked during the implantation to form the well 22 and during the implantation to form the well 24. Therefore, the substrate 12 below these portions of the sidewall 16 also maintains the initial conductivity of the substrate 12. The wells 22, 24 may include moderately doped semiconductor materials.

Please refer to FIGS. 5 and 6, where the same component symbols represent similar features in FIGS. 3 and 4, and in the next manufacturing stage, the manufacturing process is continued in parallel to form a corresponding Hall sensor on each side wall 16. Subsequent discussion will involve forming a Hall sensor on one of the side walls 16. It should be understood that another Hall sensor is being formed on the other side wall 16.

A doped region 36 is formed in the portion of the section 30 of the well 22, and contacts 38, 40 are formed in the doped region 36 in the form of discrete doped regions. The contacts 38, 40 have phases with the doped region 36 Reverse polarity conductivity type. The doped region 36 and the contacts 38 and 40 are located in the portion 13 of the substrate 12. Compared with the well 22, the doped region 36 extends to a shallower depth into the substrate 12 to retain a portion of the well 22 under the doped region 36. The contacts 38, 40 are coupled to the portion of the well 22 located below the doped region 36, thereby coupling the contacts 38, 40 to the section 30 of the well 22 located below the sidewall 16 respectively. A portion of the doped region 36 is located between the contact 38 and the contact 40 to provide electrical isolation. Compared with the sections 32 and 34, the doped region 36 has the same conductivity type but a higher dopant concentration.

In the portions of the sections 26, 28 of the well 22 in the portion 13 of the substrate 12 of the top surface 11, contacts 42, 44 are formed in the form of doped regions, respectively. The contacts 42, 44 have the same conductivity type as the sections 26, 28 but a higher dopant concentration, and are coupled to the sections 26, 28 of the well 22, respectively. In the part of the substrate 12 located at the bottom 18 of the groove, contacts 46 and 48 are formed in the form of doped regions, respectively. Contact 46 couples section 26 of well 22 with section 30 of well 22. Contact 48 couples section 28 of well 22 with section 30 of well 22. The contacts 46, 48 have the same conductivity type as the sections 26, 28 but a higher dopant concentration. A doped region 50 is also formed in the portion of the substrate 12 exposed at the bottom 18 of the groove. The doped region 50 has a conductivity type opposite to that of the contacts 46,48.

The dopant regions 36 and 50 can be formed by, for example, ion implantation at selected locations in the substrate 12 to introduce dopants. The patterned implant mask can be used to define the selected location of the doped regions 36, 50 and peel off after implantation. In an embodiment where the well 22 is an n-type semiconductor material and the well 24 is a p-type semiconductor material, the semiconductor material constituting the doped regions 36 and 50 may include p-type dopants that effectively impart p-type conductivity, and may be heavy Doped. The implantation conditions are selected to form doped regions 36, 50 with the desired doping profile and concentration.

Doping is introduced by, for example, ion implantation at selected locations in the substrate 12 Objects can form contacts 38, 40, 42, 44, 46, 48. A patterned implant mask can be used to define this selected location of contacts 38, 40, 42, 44, 46, 48, and peel off after implantation. In an embodiment in which the well 22 is an n-type semiconductor material and the well 24 is a p-type semiconductor material, the semiconductor material constituting the contacts 38, 40, 42, 44, 46, 48 may include an n-type dopant that effectively imparts n-type conductivity. Impurities, and can be heavily doped. The implantation conditions are selected to form doped regions 36, 50 with the desired doping profile and concentration.

The portion of the region 30 of the well 22 located below the sidewall 16 is limited by the doped region 36, the doped region 50, the region 32 of the well 24, and the region 34 of the well 24. These boundaries define a Hall surface 35 with a given area (for example, length and width) at the surface of the side wall 16. The Hall surface 35 can extend from the corner 15 to the corner 17 over the entire height of the side wall 16, and the Hall surface 35 has a width extending from one of the sections 32 of the well 24 to the opposite one of the sections 34 of the well 24 w. The Hall surface 35 is included in a plane that is inclined at an inclination with respect to the top surface 11 of the substrate 12 and has a vertical component with respect to a plane including the top surface 11 of the substrate 12.

In this representative embodiment, the groove 10 is etched in the substrate 12 before the wells 22, 24 of opposite conductivity types are formed in the substrate 12. In an alternative embodiment, after forming wells 22, 24 with opposite conductivity types in the substrate 12, the groove 10 is etched in the substrate 12, and then the doped regions 36, 50 and the contacts 38, 40, 42, 44 are formed. , 46, 48.

In use, a bias potential can be applied between the terminals provided by contact 38 and contact 44 to establish the current flowing in well 22. A magnetic field with a field direction that intersects the Hall surface 35 located on the side wall 16 will generate a Hall voltage. The Hall surface 35 defines the sensing surface of the Hall sensor. The interaction between the current and the magnetic field generates a potential difference, which is sensed between the terminals provided by contact 42 and contact 40 under Hall voltage. Due to the provision of non-planar geometry With the inclination of the side wall 16, the Hall sensor can sense a magnetic field characterized by a field direction parallel or almost parallel to the top surface 11 of the substrate 12 with greater sensitivity than the conventional Hall sensor.

Please refer to FIG. 7, where the same component symbols represent similar features in FIG. The semiconductor fins 64 protruding from the top surface 11 form a Hall sensor. The sidewall 66 of the semiconductor fin 64 and the top surface 68 of the semiconductor fin 64 can be used to form wells 22, 24, doped regions 36, 50, and contacts 38, 40, 42, 44, 46, of the Hall sensor. 48. Similar to the sidewall 16 of the groove 10, the sidewall 66 of the semiconductor fin 64 is inclined or angled with respect to the plane containing the top surface 11 of the substrate 12. A portion of the top surface 11 of the substrate 12 surrounds the base of the semiconductor fin 64. The top surface 68 of the semiconductor fin 64 may be contained in a plane parallel to the plane of the top surface 11 of the substrate 12. Each side wall 66 intersects the top surface 68 at a corner 62 extending along the upper edge of the side wall 66. Each side wall 66 also intersects the top surface 11 of the substrate 12 at a corner 60 extending along the lower edge of the side wall 66. The top surface 68 of the semiconductor fin 64 may be rectangular at the corner 62, and the semiconductor fin 64 may have a similar rectangular shape at the corner 62.

The Hall surface 35 can extend from the corner 15 to the corner 17 over the entire height of each side wall 66, and the Hall surface 35 has an area extending from one of the sections 32 of the well 24 to the opposite one of the sections 34 of the well 24. width. The Hall surface 35 is included in a plane that is inclined at an inclination with respect to the top surface 68 of the semiconductor fin 64 and has a vertical component with respect to the plane containing the top surface 68 of the semiconductor fin 64.

The above method is used for the manufacture of integrated circuit wafers. The manufacturer can be in raw wafer form (for example, as a single wafer with multiple unpackaged wafers), as a bare die, or as a package The integrated circuit chip obtained by form distribution. The chip can be integrated with other chips, discrete circuit components and/or other signal processing devices as part of an intermediate product or final product. The final product can be any product that includes an integrated circuit chip, such as a computer product or a smart phone with a central processing unit.

The terms modified by approximate language such as "about", "approximately" and "substantially" cited herein are not limited to the precise values specified. The approximate language may correspond to the accuracy of the instrument used to measure the value, and unless otherwise dependent on the accuracy of the instrument, may represent +/- 10% of the value.

Terms such as "vertical", "horizontal", etc. are cited as examples in this document to establish a frame of reference, and are not limiting. The term "horizontal" as used herein is defined as a plane parallel to the conventional plane of the semiconductor substrate, regardless of its actual three-dimensional spatial orientation. The terms "perpendicular" and "orthogonal" refer to directions perpendicular to the horizontal plane as just defined. The term "lateral" refers to the direction in the horizontal plane.

A feature “connected” or “coupled” to another feature may be directly connected or coupled to the other feature, or one or more intervening features may be present. If there is no intermediate feature, the feature can be "directly connected" or "directly coupled" with another feature. If there is at least one intermediate feature, the feature can be "indirectly connected" or "indirectly coupled" with another feature. A feature that is "on" or "in contact with" another feature may be directly on or in direct contact with the other feature, or one or more intervening features may be present. If there is no intermediate feature, the feature can be directly "on" or "directly in contact" with another feature. If there is at least one intermediate feature, the feature can be "not directly" on or "not in direct contact" with another feature.

The description of the various embodiments of the present invention is for illustrative purposes, and is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and changes will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the embodiments. The terms used herein are selected to best explain the principles of the embodiments, practical applications, or technical improvements in the known technologies in the market, or to enable those of ordinary skill in the art to understand the embodiments disclosed herein.

11: top surface

12: substrate

22: trap

24: trap

26: section

28: section

30: section

32: section

34: section

36: doped area

38: contact

40: contact

42: contact

44: contact

Claims (20)

A structure for a Hall sensor, the structure includes: The semiconductor body includes a first surface and an inclined side wall defining a Hall surface intersecting the first surface; A first well located in the semiconductor body, the first well having a first section partly under the first surface and partly under the Hall surface; and A plurality of contacts are located in the semiconductor body, and each of the plurality of contacts is coupled to the first section of the first well located under the first surface of the semiconductor body. The structure according to claim 1, wherein the semiconductor body is a semiconductor substrate, and the inclined sidewall extends from the first surface of the semiconductor substrate into the semiconductor substrate to define a portion of the groove. The structure of claim 2, wherein the semiconductor substrate includes a second surface exposed at the bottom of the groove, and the Hall surface on the inclined sidewall and the second surface of the semiconductor substrate intersect at a corner . The structure according to claim 2, wherein the Hall surface on the inclined sidewall and the first surface of the semiconductor substrate intersect at a corner. The structure described in claim 1, further including: A semiconductor substrate with a top surface, Wherein, the semiconductor body is a semiconductor fin protruding from the top surface of the semiconductor substrate, the first surface is the top surface of the semiconductor fin, and the Hall surface on the inclined sidewall is opposite to the semiconductor fin The top surface is inclined at an angle. The structure according to claim 5, wherein the Huo located on the inclined side wall The Er surface and the top surface of the semiconductor substrate intersect at a corner. The structure according to claim 5, wherein the Hall surface on the inclined sidewall and the top surface of the semiconductor fin intersect at a corner. The structure according to claim 1, wherein the first well has the first conductivity type, and further includes: A second well is located in the semiconductor body, the second well has a first section and a second section each extending along the inclined sidewall, and the second well has a second polarity opposite to the first conductivity type Conductivity type, Wherein, the Hall surface on the inclined sidewall is laterally located between the first section of the second well and the second section of the second well. The structure according to claim 1, wherein the first well includes a second section located below the first surface of the semiconductor body and extending along the inclined sidewall, and further includes: A second well located in the semiconductor body, the second well has a first section partially disposed laterally between the second section of the first well and the Hall surface, Wherein, the first well has a first conductivity type, and the second well has a second conductivity type with a polarity opposite to the first conductivity type. The structure according to claim 9, wherein the first well includes a third section located below the first surface of the semiconductor body and extending in the semiconductor body below the inclined sidewall, and the second well includes Part laterally located in the second section between the third of the first well and the Hall surface. The structure according to claim 10, wherein the plurality of contacts includes a first contact and a second contact located in the semiconductor body, and the plurality of contacts has the first conductive type Type, having a higher dopant concentration than the first well, the first contact is coupled to the second section of the first well located on the first surface of the semiconductor body, and the second The contact is coupled to the third section of the first well located on the first surface of the semiconductor body. The structure described in claim 11 further includes: A doped region is located in the semiconductor body at the first surface, the doped region has the second conductivity type, and the doped region includes a portion positioned to isolate the first contact from the second contact. The structure of claim 12, wherein the semiconductor body is a semiconductor substrate, and the Hall surface on the inclined sidewall extends from the first surface of the semiconductor substrate into the semiconductor substrate to define a portion of the groove The semiconductor substrate includes a second surface exposed at the bottom of the groove, and the doped region is located in the semiconductor substrate below the second surface. The structure described in claim 12 further includes: A semiconductor substrate with a top surface, Wherein, the semiconductor body is a semiconductor fin protruding from the top surface of the semiconductor substrate, the first surface is the top surface of the semiconductor fin, and the Hall surface on the inclined sidewall is opposite to the semiconductor fin The top surface is inclined at an angle, and the doped region is located in the semiconductor substrate below the top surface. A method of forming a structure of a Hall sensor, the method comprising: A first well is formed in the semiconductor body including a first surface and an inclined sidewall defining a Hall surface intersecting the first surface, wherein the first well has a portion located below the first surface and partially located on the Hall surface The first section below; and A plurality of contacts are formed in the semiconductor body, wherein each of the plurality of contacts is located in the The first section of the first well under the first surface of the semiconductor body is coupled. The method according to claim 15, wherein the semiconductor body is a semiconductor substrate, and further includes: Etching grooves in the semiconductor substrate, Wherein, the inclined sidewall extends from the first surface of the semiconductor substrate into the semiconductor substrate to define a portion of the groove. The method according to claim 16, wherein the semiconductor substrate includes a second surface exposed at the bottom of the groove, and the Hall surface on the inclined sidewall and the second surface of the semiconductor substrate intersect at the first surface. Corners, and the Hall surface on the inclined sidewall and the second surface of the semiconductor substrate intersect at a second corner. The method according to claim 15, further comprising: Patterning the semiconductor fins protruding from the top surface of the semiconductor substrate, Wherein, the first surface is the top surface of the semiconductor fin, and the Hall surface on the inclined sidewall is inclined at an angle with respect to the top surface of the semiconductor fin. The method according to claim 15, wherein the first well has the first conductivity type, and further comprises: Forming a second well in the semiconductor body, Wherein, the second well has a first section and a second section each extending along the inclined sidewall, and the second well has a second conductivity type with a polarity opposite to the first conductivity type, and is located on the inclined sidewall The Hall surface of is laterally located between the first section of the second well and the second section of the second well. The method according to claim 15, wherein the first well includes A second section below the first surface of the conductor body and extending along the inclined sidewall, and further includes: Forming a second well in the semiconductor body, Wherein, the second well has a first section partially disposed laterally between the second section of the first well and the Hall surface, the first well has the first conductivity type, and the second well has A second conductivity type with a polarity opposite to the first conductivity type.

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