TWI766616B - Seniconductor structure and method of manufacturing the same - Google Patents

Abstract

A semiconductor structure and its manufacturing method are provided. The semiconductor structure includes a substrate and a buried gate structure. The buried gate structure includes a gate dielectric layer formed on the sidewall and the bottom surface of a trench in the substrate, a barrier layer formed in the trench and on the sidewall and the bottom surface of the gate dielectric layer, a first work function layer formed in the trench and including a main portion and a protruding portion, a second work function layer formed at opposite sides of the protruding portion, and an insulating layer formed in the trench, wherein the insulating layer is formed on the protruding portion of the first work function layer and the second work function layer. Also, the barrier layer surrounds the sidewall and the bottom surface of the main portion of the first work function layer, and the area of the top surface of the protruding portion is less than the area of the bottom surface of the protruding portion.

Description

Semiconductor structure and method of making the same

The present invention relates to a semiconductor structure and a manufacturing method thereof, and in particular, to a semiconductor structure of a dynamic random access memory and a manufacturing method thereof.

Dynamic random access memory (Dynamic Random Access Memory, DRAM) devices are widely used in consumer electronic products. With the improvement of semiconductor technology, in order to meet consumer demand for miniaturized electronic devices, the size of memory cells in dynamic random access memory is reduced, and the integration degree of memory cells is also increased. The development of the embedded word line DRAM is to meet the requirement of increasing the integration of the DRAM, so as to speed up the operation speed of the device. However, as the size of memory devices continues to shrink, many challenges arise. For example, gate induced drain leakage (GIDL) needs to be reduced. Therefore, the industry still needs to improve the manufacturing method of the DRAM device to overcome the problems caused by the shrinking device size.

The invention discloses a semiconductor structure, comprising a substrate and a buried gate structure disposed in the substrate, wherein the buried gate structure comprises: a gate dielectric layer on the sidewall and bottom surface of a trench in the substrate, the The trench is extended downward from the top surface of the substrate; the barrier layer is located in the trench and is located on the sidewall and the bottom surface of the gate dielectric layer; the first work function layer is located in the trench, and the first work function layer includes a main body part located on the lower part of the groove and a protrusion part located above the main body part and connected to the main body part, wherein the barrier layer surrounds the side wall and the bottom surface of the main body part, and the top surface area of the protruding part is smaller than the bottom surface area of the protruding part; Two work function layers are located on both sides of the protruding part of the first work function layer; and an insulating layer is located in the trench and on the protruding part of the first work function layer and the second work function layer.

The invention discloses a method for manufacturing a semiconductor structure, comprising: providing a substrate, and forming a downwardly extending trench in the substrate; forming a gate dielectric layer on the side and bottom surfaces of the trench; and forming a gate dielectric layer under the gate dielectric layer A barrier layer is formed on the sidewalls and the bottom surface, and a first work function layer is formed in the lower portion of the trench. The first work function layer includes a main body portion located at a lower portion of the trench, and a protruding portion located above the main body portion and connecting the main body portion, wherein the barrier layer surrounds the side surface and the bottom surface of the main body portion, and the top surface area of the protruding portion is less than The area of the bottom surface of the protrusion. The manufacturing method further includes forming a second work function layer on both sides of the protruding portion of the first work function layer, and forming an insulating layer over the protruding portion of the first work function layer and the second work function layer.

100: base

103: Groove

112: gate dielectric layer

100a, 112a, 1150a, 115a, 1170a, 118a, 116P-a, 121a, 122a, 124a: Top surface

103s, 117s, 118s, 1150s, 119-s1, 119-s2: Sidewalls

103b, 116M-b, 116P-b, 121b, 122b: Bottom

1150: Barrier Material Layer

115: Barrier layer

1160, 1160R: the first work function material layer

116: The first work function layer

116M: main body

116P: Protrusions

116M-s, 116P-s1, 116P-s2: Side

117: first dielectric layer

1170: First Dielectric Material Layer

118: Second Dielectric Layer

1180: Second Dielectric Material Layer

1171: Opening

119-1, 119-2: Holes

1200: the second work function material layer

120: Second work function layer

121: Part One

122: Part II

124: Insulation layer

t1: thickness

W _H ,W _t ,W _P : width

E1, E2: Electric field

e ^- : electronic

FIGS. 1A-1M are schematic cross-sectional views corresponding to different intermediate stages of fabricating a semiconductor structure according to an embodiment of the present disclosure.

FIGS. 1A-1M are schematic cross-sectional views corresponding to different intermediate stages of fabricating a semiconductor structure according to an embodiment of the present disclosure. Referring to FIG. 1A, a substrate 100 is provided, and the substrate 100 includes a plurality of trenches 103 extending downward. The material of the substrate 100 may contain, for example, a semiconductor material. In one embodiment, the substrate 100 includes silicon, gallium arsenide, gallium nitride, germanium silicide, or a combination thereof. In other embodiments, the substrate 100 is a silicon-on-insulator substrate.

Next, a gate dielectric layer 112 and a barrier material layer 1150 are sequentially formed conformably on the surface of the substrate 100 . As shown in FIG. 1A , the gate dielectric layer 112 covers the sidewalls 103 s and the bottom surface 103 b of the trench 103 and extends to the top surface 100 a of the substrate 100 , and the barrier material layer 1150 is formed on the gate dielectric layer 112 .

In one embodiment, the gate dielectric layer 112 can be a single-layer structure or a multi-layer structure, and its material can include silicon oxide, silicon nitride, silicon dioxide, or a combination thereof. For example, the gate dielectric layer 112 may be a silicon oxide/silicon nitride/silicon oxide structure (ONO structure), or a NONON structure. Furthermore, the gate dielectric layer 112 can be formed by a thermal oxidation process, a deposition process, or a combination thereof.

In one embodiment, the barrier material layer 1150 includes a conductive metal, such as a metal, metal alloy, metal nitride, or metal silicide. In one embodiment, the barrier material layer 1150 includes titanium nitride (TiN), titanium silicon nitride (TiSiN), tantalum nitride (TaN), Tungsten nitride (WN), tantalum (Ta), titanium (Ti), tungsten (W), ruthenium (Ru), aluminum (Al), or a combination of the foregoing. Furthermore, the barrier material layer 1150 may be formed on the gate dielectric layer 112 by using a deposition process, such as a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process.

Referring to FIG. 1B , next, a first work function material layer 1160 is formed on the barrier material layer 1150 and the trench 103 is filled. In one embodiment, the first work function material layer 1160 may include copper, tungsten, or other suitable conductive materials. Furthermore, the first work function material layer 1160 may be composed of a single-layer or multi-layer conductive metal structure. In this example, the first work function material layer 1160 includes tungsten.

Referring to FIG. 1C , next, the first work function material layer 1160 is recessed. In one embodiment, the first work function material layer 1160 located outside the trenches 103 can be removed by a chemical mechanical polishing process, an etch-back process or other suitable processes. Afterwards, a selective etching process may be used, for example, to dent the first work function material layer 1160 in the trench 103 and leave a portion of the first work function material layer 1160R at the lower portion of the trench 103 . After the first work function material layer 1160 is recessed, the upper portion of the sidewall 1150s of the barrier material layer 1150 is exposed.

Afterwards, according to an embodiment of the present disclosure, a mask can be formed on the first work function material layer 1160R left after the recess, and etching is performed according to the mask to remove the first part of the part not covered by the mask. The work function material layer 1160R and corresponding holes are formed. Then, a second work function material is filled in the aforementioned holes. Below, FIGS. 1D to 1G illustrate the process of forming a mask on the concave first work function material layer 1160R. a method of making. However, it should be understood by those skilled in the art that the details of the steps described below are for illustration only, and are not intended to limit the process of the present disclosure.

Referring to FIG. 1D , next, a first dielectric material layer 1170 is compliantly deposited on the barrier material layer 1150 . As shown in the figure, the first dielectric material layer 1170 covers the top surface 1150a of the barrier material layer 1150 and the upper portion of the sidewalls 1150s of the barrier material layer 1150 , and an opening 1171 is formed in the trench 103 . Furthermore, the first dielectric material layer 1170 may include silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric materials, and may be formed by chemical vapor deposition or other suitable methods.

The thickness t1 of the first dielectric material layer 1170 can be determined according to the size of the gap between the barrier material layers 1150 in the trench 103, and can be used to control the first part 121 and the second part 121 of the second work function layer 120 formed subsequently. The width of the second portion 122 (FIG. 1M). Specifically, the width of the opening 1171 can be controlled by adjusting the thickness t1 of the first dielectric material layer 1170 , so as to control the width of the mask HM formed subsequently, thereby controlling the first portion 121 and the second work function layer 120 formed subsequently. The width of the second portion 122 .

As shown in FIG. 1D , in one embodiment, the width W _H of the opening 1171 is in the range of about 1/6 to about 1/2 of the width W _t of the trench 103 . For example, in one example, the width W _H of the opening 1171 is about 1/4 of the width W _t of the trench 103 . However, the present invention is not limited thereto, and the width W _H of the opening 1171 can be adjusted according to design requirements.

Referring to FIG. 1E , next, a second dielectric material layer 1180 is formed over the first dielectric material layer 1170 and fills the opening 1171 . In one embodiment, the second dielectric material layer 1180 may include silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric materials, and may be formed by chemical vapor deposition or other suitable methods.

In one embodiment, the material of the first dielectric material layer 1170 is different from that of the second dielectric material layer 1180 . For example, in one example, the first dielectric material layer 1170 is silicon oxide, and the second dielectric material layer 1180 is silicon nitride. In another example, the first dielectric material layer 1170 is silicon nitride, and the second dielectric material layer 1180 is silicon oxide. However, the present disclosure is not limited to the aforementioned materials.

Referring to FIG. 1F , after that, part of the second dielectric material layer 1180 is removed to expose the top surface 1170 a of the first dielectric material layer 1170 . In one embodiment, the second dielectric material layer 1180 located outside the opening 1171 may be removed by a chemical mechanical polishing process or an etch-back process. The remaining portion of the second dielectric material layer 1180 forms the second dielectric layer 118 in the opening 1171 . At this time, the top surface 1170a of the first dielectric material layer 1170 is coplanar with the top surface 118a of the second dielectric layer 118 .

Referring to FIG. 1G, next, the part of the first dielectric material layer 1170 not covered by the second dielectric layer 118 is removed. In one embodiment, part of the first dielectric material layer 1170 not covered by the second dielectric layer 118 may be removed by an etch back process. The remaining portion of the first dielectric material layer 1170 forms the first dielectric layer 117 . At this time, the sidewalls 117s of the first dielectric layer 117 and the sidewalls 118s of the second dielectric layer 118 are coplanar. In this embodiment, the first dielectric layer 117 and the second dielectric layer 118 are jointly used as the mask HM used in the subsequent process.

Referring to FIG. 1H, then, an etching step is performed to remove part of the first work function material layer 1160R not covered by the mask HM to form the first work function layer 116 . In one embodiment, a portion of the first work function material layer 1160R not covered by the mask HM may be removed by, for example, reactive ion etching (RIE) or other suitable dry etching methods. In this example, after the etch step is performed, the first work function layer 116 is Holes 119-1 and 119-2 are formed on both sides of the . It is worth mentioning that the first work function material layer 1160R can be etched here because only the mask HM is needed and no additional photomask is required, so this etching step is also called a self-aligned etching process.

Please refer to FIG. 1H again, after the etching step, the size of the formed holes 119-1 and 119-2 is from the top surface of the first work function material layer 1160R toward the direction entering the first work function material layer 1160R gradually reduced. As shown in the figure, the sidewall 119-s1 of the hole 119-1 and the sidewall 119-s2 of the hole 119-2 are inclined to the sidewall 1150s of the barrier material layer 1150, respectively. In one embodiment, the sidewall 119-s1 of the hole 119-1 and the sidewall 119-s2 of the hole 119-2 are curved sidewalls.

Referring to FIG. 1I , next, the mask HM is removed, including removing the first dielectric layer 117 and the second dielectric layer 118 , so as to expose the first work function layer 116 in the trench 103 . As shown in FIG. 1I, the first work function layer 116 includes a main portion 116M and a protruding portion 116P, wherein the main portion 116M is located, for example, at the lower portion of the trench 103, and the protruding portion 116P is located between the main portion 116M. superior.

Referring to FIG. 1J , next, part of the barrier material layer 1150 is removed, and the remaining barrier material layer 1150 forms the barrier layer 115 . In one embodiment, the upper portion of the barrier material layer 1150 may be removed, for example, as shown in FIG. 1J, where a portion of the barrier material layer above the bottom surface of the hole 119-1 and the hole 119-2 is removed, for example 1150, while the remaining barrier layer 115 surrounds the side surfaces 116M-s and the bottom surface 116M-b of the body portion 116M. In addition, the top surface 115a of the barrier layer 115 may be substantially coplanar with the bottom surface 116P-b of the protrusion 116P. In one embodiment, the method of removing part of the barrier material layer 1150 may be, for example, a dry etching process or a wet etching process.

1J again, the width of the protruding portion 116P of the first work function layer 116 gradually increases from the top surface 116P-a of the protruding portion 116P toward the bottom surface 116P-b of the protruding portion 116P. In one embodiment, the width W _P of the top surface 116P-a of the protruding portion 116P of the first work function layer 116 is in the range of about 1/6 to about 1/2 of the width W _t of the trench 103 , for example 1 /3 to about 1/2 range. In one example, the width W _P of the top surface 116P-a of the protrusion 116P is, for example, about 1/2 of the width W _t of the trench 103 .

Referring to FIG. 1K , next, a second work function material layer 1200 is formed over the barrier layer 115 and the first work function layer 116 . The second work function material layer 1200 covers the barrier layer 115 and fills the trenches 103 , and further fills the holes 119 - 1 and 119 - 2 on both sides of the protrusion 116P of the first work function layer 116 . In one embodiment, the second work function material layer 1200 may include doped or undoped polysilicon, or include metals, metal alloys, metal nitrides, metal silicides, and the like. In one embodiment, the material of the second work function material layer 1200 includes polysilicon, titanium nitride, titanium silicon nitride, tantalum nitride, tungsten nitride, tantalum, titanium, tungsten, ruthenium, aluminum, or other suitable conductive materials. Material. In one embodiment, the second work function material layer 1200 may be formed by using a deposition process, such as a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process.

In one embodiment, the second work function material layer 1200 is different from the material of the barrier layer 115 and also different from the material of the first work function layer 116 . Furthermore, in one embodiment, the work function of the second work function material layer 1200 is smaller than that of the barrier layer 115 , and the work function of the barrier layer 115 is smaller than that of the first work function layer 116 .

Referring to FIG. 1L, then, a part of the second work function material layer 1200 is removed until the first work function layer 116 is exposed, and the second work function layer 120 is formed. In one embodiment, a part of the second work function material layer 1200 may be removed by, for example, an etch back process. As shown in FIG. 1L, the second work function layer 120 includes a first portion 121 and a second portion 122 located on opposite sides of the protruding portion 116P of the first work function layer 116, respectively, and the top surface 116P-a of the protruding portion 116P is Coplanar with the top surfaces 121 a and 122 a of the second work function layer 120 . In addition, in one embodiment, the second work function layer 120 covers the top surface 115 a of the barrier layer 115 , for example, the bottom surface 121 b of the first portion 121 and the bottom surface 122 b of the second portion 122 are in contact with and cover the barrier layer 115 .

As shown in FIG. 1L, according to an embodiment, two opposite sides of the second work function layer 120, namely the first side 116P-s1 and the second side 116P-s2 of the protruding portion 116 in the figure, are inclined to the first side 116P-s1 and the second side 116P-s2 respectively. The top surfaces of the two work function layers 120, namely the top surfaces 121a and 122a. In one example, two opposite sides of the second work function layer 120 have arcuate sides.

Referring to FIG. 1M, next, an insulating layer 124 is formed in the trench 103, and the insulating layer 124 covers the top surface 116P-a of the protrusion 116P and the top surfaces 121a and 122a of the second work function layer 120. In one embodiment, for example, an insulating material can be blanket formed on the substrate 100 first, and the insulating material covers the top surface of the gate dielectric layer 112 and fills the trenches 103 , and then removes the insulating material outside the trenches 103 . Part of the insulating material is removed, and part of the gate dielectric layer 112 is removed until the top surface 100 a of the substrate 100 is exposed, and an insulating layer 124 is formed in the trench 103 . In one embodiment, the material of the insulating layer 124 is, for example, silicon nitride or other suitable insulating materials, and can be formed by chemical vapor deposition or other suitable processes. In one embodiment, the top surface 124 a of the insulating layer 124 is substantially coplanar with the top surface 112 a of the gate dielectric layer 112 and the top surface 100 a of the substrate 100 .

As shown in FIG. 1M , the insulating layer 124 is located above the protrusions 116P of the first work function layer 116 and above the second work function layer 120 . The insulating layer 124 covers and contacts the top surface 121 a of the first part 121 of the second work function layer 120 , the top surface 122 a of the second part 122 and the top surface 116P-a of the protrusion 116P of the first work function layer 116 .

In view of the above, according to the semiconductor structure and the manufacturing method thereof proposed in one embodiment of the present disclosure, the second work function layer 120 is disposed on both sides of the protruding portion 116P of the first work function layer 116, so that the adjacent doped regions are formed with the second work function layer 120 . The intensity of the electric field (eg, electric field E2 ) generated by the second work function layer 120 when the channel is turned on decreases. Please refer to FIG. 1M again, that is, when the channel of the memory device is turned on, an electric field is generated on the side of the main body portion 116M of the first work function layer 116 (which is adjacent to the doped region of the substrate 100 serving as the drain region) E1, while an electric field E2 is generated on the protruding portion 116P side of the first work function layer 116 (which is adjacent to the doped region of the substrate 100 serving as the drain region), and the intensity of the electric field E2 is smaller than that of the generated electric field E1, thereby improving the The conventional gate-induced drain leakage (GIDL) problem is easily generated.

Furthermore, according to an embodiment of the present disclosure, the top surface area of the protruding portion 116P of the first work function layer 116 is smaller than the bottom surface area of the protruding portion 116P. For example, the width of the protruding portion 116P is from the top surface of the protruding portion 116P to the protruding portion. The bottom surface of the portion 116P gradually increases. When the channel of the memory device is turned on, the intensity of the electric field E2 shown in FIG. 1M can be made smaller than that of the electric field E1, and the electric field E2 can also be gradually increased from top to bottom to reduce the electric field. The difference in electric field strength at the junction of E2 and electric field E1 can effectively improve the gate-induced drain leakage current (GIDL). If the strength difference between the electric field E2 and the electric field E1 is too large, the electron e ^- may have a tunneling effect, and the electron e ^- originally staying in the electric field E2 will be pulled into the electric field E1 by the sudden increase of the electric field E1, and will still be A huge leakage current is generated, so the problem of gate-induced drain leakage current (GIDL) cannot be effectively improved.

Furthermore, when the memory device is operated, if the strength difference between the electric field E2 and the electric field E1 is too large, not only will the stability of the operation performance of each word line be affected, but also the overall electrical performance of the memory device. For example, a general memory device includes 600-900 (or even more) word lines. When each word line is in an on state, if there is a rapidly changing electric field between the electric field E2 and the electric field E1 The leakage current caused by the intensity of the leakage current will not be able to stably control the leakage current of each word line to be consistent in size. In addition to affecting the consistency of the electrical performance of each word line, it will also affect the overall operation speed of the device (such as operating The slowest word line, whose response time determines the overall response time of the device). Therefore, according to the semiconductor structure and the manufacturing method thereof proposed in an embodiment of the present disclosure, in addition to effectively reducing the gate-induced drain leakage current, the electrical uniformity of each word line can be obtained, and further Improve the electronic characteristics of the application device, so that the operation performance is more stable.

In addition, according to the manufacturing method proposed in an embodiment of the present disclosure, the thickness of the first dielectric material layer can be adjusted according to the requirements of actual application conditions, so as to determine the width of the mask formed subsequently, and the mask can be used to affect the first function below. The functional material layer is etched, thereby controlling the position and size of the holes required for the subsequent formation of another work function material (eg, polysilicon), without setting an additional mask for etching (ie, a self-aligned process). Therefore, according to the manufacturing method proposed by the embodiments of the present disclosure, the manufacturing steps can be simplified, and the mask size can be reduced. The quantity used, thereby reducing the process cost. Furthermore, the manufacturing method proposed in the embodiment of the present disclosure is compatible with the current existing manufacturing process, and is also highly economical in application.

Although the present invention has been disclosed above with several preferred embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make any changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the appended patent application.

100: base

112: gate dielectric layer

100a, 112a, 115a, 116P-a, 121a, 122a, 124a: top surface

121b, 122b: Bottom

115: Barrier layer

116: The first work function layer

116M: main body

116P: Protrusions

116P-s1, 116P-s2: Side

120: Second work function layer

121: Part One

122: Part II

124: Insulation layer

W _t , W _P : width

E1, E2: Electric field

e ^- : electronic

Claims (14)

A semiconductor structure, comprising: a substrate; a buried gate structure disposed in the substrate, the buried gate structure comprising: a gate dielectric layer, a sidewall of a trench in the substrate and On the bottom surface, the trench extends downward from the top surface of the substrate; a barrier layer is located in the trench and is located on the sidewall and bottom surface of the gate dielectric layer; a first work function layer is located in the trench In the groove, the first work function layer includes: a main body part located at the lower part of the groove, and the barrier layer surrounds the sidewall and bottom surface of the main body part; and a protruding part located on the main body part and connecting the main body part, wherein the area of the top surface of the protruding part is smaller than the area of the bottom surface of the protruding part; a second work function layer located on both sides of the protruding part of the first work function layer and the second work function layer Two opposite sides of the layer have arcuate sides; and an insulating layer located in the trench and above the protrusion of the first work function layer and the second work function layer. The semiconductor structure of claim 1, wherein the width of the protruding portion of the first work function layer gradually increases from the top surface of the protruding portion toward the bottom surface of the protruding portion. The semiconductor structure of claim 1, wherein the top surface of the protruding portion of the first work function layer is coplanar with the top surface of the second work function layer. The semiconductor structure of claim 1, wherein the second work function layer covers a top surface of the barrier layer. The semiconductor structure of claim 1, wherein the area of the top surface of the second work function layer is greater than the area of the bottom surface of the second work function layer. A method of manufacturing a semiconductor structure, comprising: providing a substrate, and forming a downwardly extending trench in the substrate; forming a gate dielectric layer on the side and bottom surfaces of the trench; and forming a gate dielectric layer on the gate dielectric A barrier layer is formed on the lower sidewall and bottom surface of the layer, and a first work function layer is formed in the lower portion of the trench, wherein the first work function layer includes: a main body portion located in the lower portion of the trench, and the barrier layer surrounds the side and bottom surfaces of the main body part; and a protruding part located on the main body part and connecting the main body part, wherein the area of the top surface of the protruding part is smaller than the area of the bottom surface of the protruding part; in A second work function layer is formed on both sides of the protruding portion of the first work function layer; and an insulating layer is formed over the protruding portion of the first work function layer and the second work function layer, wherein the The barrier layer and forming the first work function layer include: forming a barrier material layer on the gate dielectric layer; forming a first work function material layer on the barrier material layer; concave the first a work function material layer; a mask is formed on the concave first work function material layer, and the mask exposes the top surface of the concave part of the first work function material layer; Etching is performed according to the mask to remove part of the concave first work function material layer not covered by the mask to form the first work function layer; and the mask is removed. The method for manufacturing a semiconductor structure as claimed in claim 6, wherein after the first work function material layer is recessed, the upper portion of the sidewall of the barrier material layer is exposed in the trench, wherein forming the mask comprises: compliance depositing a first dielectric material layer on the top surface of the barrier material layer and the upper portion of the sidewall, and the first dielectric material layer forms an opening in the trench; filling the opening filling a second dielectric material layer; and removing a portion of the first dielectric material layer not covered by the bottom surface of the second dielectric material layer to form the mask, wherein the mask comprises filling the The portion of the second dielectric material layer formed by the opening and the remaining portion of the first dielectric material layer. The method for manufacturing a semiconductor structure as claimed in claim 7, wherein the mask comprises: a first dielectric layer located above the recessed first work function material layer; and a second dielectric layer, Located above the first dielectric layer, wherein the sidewalls of the first dielectric layer are coplanar with the sidewalls of the second dielectric layer. The method for manufacturing a semiconductor structure as claimed in claim 7, wherein one of the first dielectric material layer and the second dielectric material layer is an oxide material layer, and the other is a nitride material layer . The method for manufacturing a semiconductor structure as claimed in claim 6, wherein after forming the first work function layer, part of the barrier material layer is removed, and the remaining The barrier material layer forms the barrier layer, wherein the top surface of the barrier layer is coplanar with the bottom surface of the protrusion. The method for manufacturing a semiconductor structure as claimed in claim 6, wherein the width of the protruding portion of the first work function layer gradually increases from the top surface of the protruding portion to the bottom surface of the protruding portion. The method for manufacturing a semiconductor structure as claimed in claim 6, wherein the top surface of the protruding portion of the first work function layer is coplanar with the top surface of the second work function layer. The method for manufacturing a semiconductor structure as claimed in claim 6, wherein the second work function layer covers the top surface of the barrier layer. The method for manufacturing a semiconductor structure as claimed in claim 6, wherein two opposite side surfaces of the second work function layer are respectively inclined to the top surface of the second work function layer.

Images