TWI808383B - Seniconductor structure and method of manufacturing the same - Google Patents

Abstract

A semiconductor structure includes a substrate and a buried gate structure in the substrate. The buried gate structure includes a gate dielectric layer, a first work function layer, a barrier layer and a second work function layer. The gate dielectric layer is formed on the sidewalls and the bottom surface of a trench. The work function layer is formed in the trench and contacts the sidewalls and the bottom surface of the gate dielectric layer. The barrier layer is formed on the top surface of the first work function layer. The second work function layer is formed on the barrier layer, and the sidewall of the second work function layer is separated from the gate dielectric layer by a distance. The semiconductor structure further includes an insulating layer in the trench and on the second work function layer.

Description

Semiconductor structure and manufacturing method thereof

The present invention relates to a semiconductor structure and its manufacturing method, and in particular to a dynamic random access memory semiconductor structure and its manufacturing method.

Dynamic Random Access Memory (DRAM) devices are widely used in consumer electronic products. In order to increase the density of components in the DRAM device and improve its overall performance, the current manufacturing technology of the DRAM device continues to strive towards the miniaturization of the device size. However, as component dimensions continue to shrink, many challenges arise. For example, improving gate induced drain leakage (GIDL). Therefore, the industry still needs to improve the manufacturing method of the DRAM device to overcome the problems caused by the shrinking device size.

The invention discloses a semiconductor structure, including: a substrate and a buried gate structure disposed in the substrate. The buried gate structure includes a gate dielectric layer, a first work function layer, a barrier layer and a second work function layer. The gate dielectric layer is located on the sidewall and the bottom surface of one of the trenches in the aforementioned substrate. The first work function layer is located in the trench and contacts the sidewall and the bottom surface of the aforementioned gate dielectric layer. The barrier layer is on top of the first work function layer. The second work function layer is located above the barrier layer, and there is a distance between the sidewall of the second work function layer and the gate dielectric layer. The semiconductor structure further includes an insulating layer located in the trench and on the aforementioned second work function layer.

The present invention discloses a method for manufacturing a semiconductor structure, comprising providing a substrate and forming a trench extending downward in the substrate; forming a gate dielectric layer on the sidewall and bottom of the trench; forming a first work function layer on the lower sidewall and bottom of the gate dielectric layer and in the lower portion of the trench; forming a barrier material layer on the upper sidewall of the gate dielectric layer and the top surface of the first work function layer; forming a second work function material layer on the barrier material layer; The functional material layer is used to form a second work function layer on the barrier material layer and expose a portion of the barrier material layer on the upper sidewall of the gate dielectric layer; remove part of the barrier material layer to form a barrier layer between the second work function layer and the first work function layer, and form a gap between the sidewall of the second work function layer and the gate dielectric layer; and form an insulating layer in the trench and on the second work function layer.

100: base

102:Shallow trench isolation structure

103: Groove

A _A : active area

BL: bit line

104: character line group

104A, 104B: Embedded word lines

106: The bottom surface of the doped region

107: Capacitor contact

109: bit line contact

111: mask layer

100a, 102a, 111a, 115a, 117a, 123a: top surface

103s, 112s, 117s, 120s, 123s: side wall

103b, 112b, 117b: bottom surface

112: gate dielectric layer

112s-2: The lower sidewall of the gate dielectric layer

112s-1: Upper sidewall of the gate dielectric layer

115: The first barrier layer

WF-1: The first work function layer

117: conductive layer

119: barrier material layer

120: Second barrier layer

122: Second work function material layer

123: Second work function layer

125,125': gap

125G: air gap

126,127: insulation part

128: insulation layer

605: insulation cover

607: spacer

610: interlayer insulating layer

t1, t2: thickness

D1, D2, D3: direction

1A-1F are schematic cross-sectional views corresponding to different intermediate stages of fabricating a semiconductor structure according to an embodiment of the present invention.

FIG. 2 is a schematic cross-sectional view of an intermediate stage of fabricating a semiconductor structure according to another embodiment of the present invention.

FIG. 3 is a schematic cross-sectional view of an intermediate stage of fabricating a semiconductor structure according to another embodiment of the present invention.

FIG. 4 is a schematic cross-sectional view of an intermediate stage of fabricating a semiconductor structure according to another embodiment of the present invention.

FIG. 5 is a schematic cross-sectional view of an intermediate stage of fabricating a semiconductor structure according to an embodiment of the present invention.

FIG. 6 is a schematic top view of a memory device according to an embodiment of the present invention, and FIG. 7 is a schematic cross-sectional view drawn according to section line 7-7 in FIG. 6 .

The present invention will be described more fully with reference to the drawings of the embodiments of the present invention. However, the present invention can also be embodied in various forms and should not be limited to the embodiments described herein. The thicknesses of layers and regions in the drawings may be exaggerated for clarity. same or similar The reference numerals of the components indicate the same or similar components, and the following paragraphs will not repeat them one by one.

1A-1F are schematic cross-sectional views corresponding to different intermediate stages of fabricating a semiconductor structure according to an embodiment of the present invention. FIG. 6 is a schematic top view of a memory device according to an embodiment of the present invention. Figures 1A-1F are drawn corresponding to section line 7-7 in Figure 6.

Referring to FIG. 1A , a substrate 100 is provided, the substrate 100 includes a trench 103 extending downward, and a gate dielectric layer 112 is formed on the sidewall 103s and the bottom surface 103b of the trench 103 . The material of the substrate 100 may include semiconductor material, for example. In one embodiment, the substrate 100 includes silicon, gallium arsenide, gallium nitride, germanium silicide, other suitable materials, or a combination thereof. In other embodiments, the substrate 100 is a silicon-on-insulator substrate.

In one embodiment, a mask material layer may be formed on the substrate 100 , and the mask material layer is patterned to form the mask layer 111 . The mask layer 111 may include silicon oxide or other suitable materials, for example. The mask layer 111 includes, for example, tetraethoxysilane (TEOS). Next, using the mask layer 111 as an etching mask, the mask layer 111 and the underlying substrate 100 can be etched and filled with isolation materials to form shallow trench isolation structures 102 surrounding a plurality of active regions _AA (as shown in FIG. 6 outside the active region _AA ). Afterwards, at the positions corresponding to subsequent word lines, the mask layer 111 and the underlying substrate 100 are etched to form trenches 103, wherein adjacent trenches 103 are separated from each other in the direction D1 (FIG. 6), and each trench 103 extends horizontally in the substrate 100 along the direction D3 and extends downward along the direction D2.

Returning to FIG. 1A , next, a gate dielectric layer 112 is formed on the sidewall 103 s and the bottom surface 103 b of the trench 103 . The gate dielectric layer 112 can be formed by a thermal oxidation process, a deposition process, any suitable process, or a combination thereof. In one embodiment, for example, a thermal oxidation process is performed on the silicon-containing substrate 100 to form a silicon oxide layer on the sidewall 103 s and the bottom surface 103 b of the trench 103 as the gate dielectric layer 112 . In other embodiments, for example, a polysilicon liner (including the sidewalls covering the mask layer 111 ) may be formed in the trench 103 of the substrate 100 first, and then a thermal oxidation process is performed to oxidize the polysilicon liner to form the gate dielectric layer 112 .

In one embodiment, the gate dielectric layer 112 can be a single-layer structure or a multi-layer structure, and its material can include silicon oxide, silicon nitride, other suitable materials, or a combination thereof. For example, the gate dielectric layer 112 can be a silicon oxide/silicon nitride/silicon oxide structure (ONO structure), or a NONON structure. To simplify the drawing, a single gate dielectric layer 112 is shown for illustration. In one example, the gate dielectric layer 112 is a silicon oxide layer.

Afterwards, a first work function layer WF- 1 is formed on the lower portion of the trench 103 . The first work function layer WF-1 may include a single layer or multiple layers of material, such as a single metal layer, or a combination of a metal nitride layer and a metal layer. In this embodiment, the first work function layer WF- 1 includes, for example but not limited to, a first barrier layer 115 and a conductive layer 117 . Continue to refer to Figure 1A. A first barrier material layer (not shown) can be conformably deposited on the substrate 100 and the gate dielectric layer 112 of the trench 103 , and then a conductive material layer (not shown) is formed on the substrate 100 and the first barrier material layer to fill the trench 103 . After that, using such as chemical mechanical polishing (CMP) process, etch back (etching back) process or other suitable processes to remove the first barrier material layer and the conductive material layer outside the trench 103 . Afterwards, for example, by using a selective etching process, the first barrier material layer and the conductive material layer in the trench 103 are recessed, and the parts of the first barrier material layer and the conductive material layer remaining in the lower part of the trench 103 form the first barrier layer 115 and the conductive layer 117 respectively, and the top surface 115a of the first barrier layer 115 and the top surface 117a of the conductive layer 117 are substantially coplanar.

As shown in FIG. 1A , the first barrier layer 115 and the conductive layer 117 are formed at the lower portion of the trench 103 and constitute the first work function layer WF-1. Wherein, the first barrier layer 115 contacts the gate dielectric layer 112 and is formed between the gate dielectric layer 112 and the conductive layer 117 . Specifically, the first barrier layer 115 is located between the lower sidewall 112s - 2 and the bottom surface 112b of the gate dielectric layer 112 and the sidewall 117s and the bottom surface 117b of the conductive layer 117 .

In one embodiment, the material of the first barrier layer 115 includes conductive metal, such as metal, metal alloy, metal nitride or metal silicide. In one embodiment, the material of the first barrier layer 115 includes titanium nitride (TiN), titanium silicon nitride (TiSiN), tantalum nitride (TaN), tungsten nitride (WN), tantalum (Ta), titanium (Ti), tungsten (W), ruthenium (Ru), aluminum (Al), or other suitable conductive materials. In one embodiment, the first barrier layer 115 can be formed by using a deposition process, such as a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, or an atomic layer deposition (ALD) process.

In one embodiment, the material of the conductive layer 117 includes conductive metal, such as metal, metal alloy, metal nitride or metal silicide. In one embodiment, conductive The material of layer 117 includes tungsten, tantalum, titanium, ruthenium, aluminum, tungsten nitride, titanium nitride, titanium silicon nitride, tantalum nitride, or other suitable conductive materials. In one embodiment, the conductive layer 117 can be formed by using a deposition process such as PVD, CVD, or ALD.

Next, as shown in FIG. 1B , a barrier material layer 119 is conformally formed above the substrate 100 and above the trench 103 . In one embodiment, the barrier material layer 119 is formed on the upper sidewall 112 s - 1 of the gate dielectric layer 112 , on the top surface 115 a of the first barrier layer 115 , and on the top surface 117 a of the conductive layer 117 . As shown in FIG. 1B , the barrier material layer 119 extends above the substrate 100 , for example, extends onto the top surface 111 a of the mask layer 111 .

In one embodiment, the first barrier layer 115 has a substantially uniform thickness, such as a thickness t1 ; the barrier material layer 119 has a substantially uniform thickness, such as a thickness t2 . According to the manufacturing method proposed in the embodiment, the thickness t2 of the barrier material layer 119 defines the width in the direction D1 of the gaps formed in the subsequent manufacturing process (such as the gaps 125 and 125' shown in subsequent FIG. 1E and FIG. 2 ), thereby affecting the distance between the subsequently fabricated gate structure and the gate dielectric layer 112 on the sidewall of the trench 103. The thicker the barrier material layer 119 is, the longer the distance between the subsequently formed second work function layer (such as the second work function layer 123 shown in FIG. 1E and FIG. 2 ) and the gate dielectric layer 112 is, the smaller the electric field induced by the second work function layer 123 in the substrate can narrow the width of the channel formed in the substrate, thereby suppressing the drain leakage current caused by the gate.

In one embodiment, the thickness t2 of the barrier material layer 119 is substantially equal to the first The thickness t1 of the barrier layer 115 is shown in FIG. 1B. In other embodiments, the thickness t2 is greater than the thickness t1. In an example, the thickness t1 is in the range of 3.5 nm to 5.5 nm, such as 4 nm to 5 nm; the thickness t2 is in the range of 4.5 nm to 7.5 nm, such as 5 nm to 7 nm.

In one embodiment, the material of the barrier material layer 119 includes conductive metal, such as metal, metal alloy, metal nitride or metal silicide. In one embodiment, the material of the barrier material layer 119 includes titanium nitride, titanium silicon nitride, tantalum nitride, tungsten nitride, tantalum, titanium, tungsten, ruthenium, aluminum, or other suitable conductive materials. In one embodiment, the barrier material layer 119 may be formed by a deposition process, such as PVD, CVD, or ALD.

In one embodiment, the barrier material layer 119 and the first barrier layer 115 include the same conductive material. In other embodiments, the barrier material layer 119 and the first barrier layer 115 contain different conductive materials. Moreover, in one embodiment, the barrier material layer 119 is a material different from the conductive layer 117 , and the work function of the barrier material layer 119 is smaller than the work function of the conductive layer 117 . In one embodiment, the first barrier layer 115 and the barrier material layer 119 include titanium nitride, and the conductive layer 117 includes tungsten.

Next, as shown in FIG. 1C , a second work function material layer 122 is formed on the barrier material layer 119 , which includes, for example, a conductor material. The second work function material layer 122 , for example, fills the remaining space of the trench 103 and is in direct contact with the barrier material layer 119 . In one embodiment, the conductive layer 117 and the second work function material layer 122 pass through the barrier material layer 119 and isolated; that is, the second work function material layer 122 is not in contact with the conductive layer 117 .

In one embodiment, the second work function material layer 122 includes, for example, doped or undoped polysilicon, or metal, metal alloy, metal nitride, metal silicide, and the like. In one embodiment, the material of the second work function material layer 122 includes polysilicon, titanium nitride, titanium silicon nitride, tantalum nitride, tungsten nitride, tantalum, titanium, tungsten, ruthenium, aluminum, or other suitable conductive materials. In one embodiment, the second work function material layer 122 can be formed by using a deposition process, such as PVD, CVD, ALD and other processes.

In one embodiment, the second work function material layer 122 is different from the material of the first barrier layer 115 , the material of the conductive layer 117 and the material of the barrier material layer 119 . Furthermore, in one embodiment, the work function of the second work function material layer 122 is smaller than the work function of the conductive layer 117 .

Next, as shown in FIG. 1D , the second work function material layer 122 on the substrate 100 is removed, and the second work function material layer 122 in the trench 103 is recessed to form a second work function layer 123 . In one embodiment, the second work function layer 123 is formed corresponding to the top surface 117 a of the conductive layer 117 , and the second work function layer 123 and the conductive layer 117 are separated from each other by a part of the barrier material layer 119 . In one embodiment, a portion of the second work function material layer 122 located outside the trench 103 may be removed by CMP, an etch back process, a selective etching process, other suitable processes, or a combination thereof, and then a portion of the second work function material layer 122 located in the trench 103 may be recessed to form the second work function layer 123. In one embodiment, the top surface 123a of the second work function layer 123 is The level of the bottom surface of the doped region (not shown) in the active region (eg, as the source/drain region) is not higher than that to increase the distance between the bottom of the doped region and the buried gate structure, thereby helping to reduce the leakage current situation.

Next, as shown in FIG. 1E , in one embodiment, part of the barrier material layer 119 is removed, and the remaining part of the barrier material layer 119 forms a second barrier layer 120 . The formed second barrier layer 120 is, for example, located between the second work function layer 123 and the conductive layer 117 . Furthermore, after removing part of the barrier material layer 119 , a spacing 125 is formed between the sidewall 123 s of the second work function layer 123 and the gate dielectric layer 112 .

In one embodiment, the exposed portion of the barrier material layer 119 and at least a portion of the barrier material layer 119 between the sidewall 123 s of the second work function layer 123 and the gate dielectric layer 112 may be removed to form the gap 125 . In one embodiment, the barrier material layer 119 is removed using a selective etching process. For example, an etchant or an etching gas that is selective to the material of the second work function layer 123 can be selected to perform wet etching or dry etching on the barrier material layer 119 .

It is worth mentioning that the width of the gap 125 in the direction D1 is determined according to the thickness t2 of the barrier material layer 119. Therefore, the distance between the second work function layer 123 and the substrate 100 in the direction D1 can be controlled by controlling the thickness t2, thereby controlling the electric field formed by the second work function layer 123 to suppress the path of the GIDL.

In addition, the depth of the formed gap 125 can be properly controlled and adjusted according to actual application conditions. For example, in this embodiment, void 125 may be fully exposed The sidewall 123s of the second work function layer 123 (as shown in FIG. 1E ). Specifically, the portion of the barrier material layer 119 not covered by the second work function layer 123 is completely removed, so the formed gap 125 exposes a portion of the gate dielectric layer 112, all sidewalls 123s of the second work function layer 123, and the top surface 115a of the first barrier layer 115. In another embodiment, the gap 125 may only expose a portion of the sidewall 123s of the second work function layer 123 (as shown in FIG. 2 ). In other embodiments, the gap 125 may also extend down to the sidewall 117s exposing a portion of the conductive layer 117 .

Referring to FIG. 1E , after the aforementioned step of removing part of the barrier material layer 119 , the sidewall 123s of the second work function layer 123 is substantially coplanar with the formed sidewall 120s of the second barrier layer 120 . In addition, in one embodiment, after the aforementioned step of removing part of the barrier material layer 119 , the conductive layer 117 is surrounded by the first barrier layer 115 and the second barrier layer 120 .

FIG. 2 is a schematic cross-sectional view of an intermediate stage in the fabrication of a semiconductor structure according to another embodiment of the present invention, which is an alternative embodiment of the steps of FIG. 1E. With respect to FIG. 1E , only a part of the barrier material layer 119 beside the sidewall 123 s of the second work function layer 123 can be removed here. Therefore, the gap 125' only exposes a portion of the sidewall 123s of the second work function layer 123. Referring to FIG.

Next, referring to FIG. 1F, after forming the void 125 (FIG. 1E), an insulating layer 128 is formed in the trench 103 and above the second work function layer 123 to cover the second work function layer 123, the second barrier layer 120, and the first barrier layer 115. This implementation In one example, the insulating layer 128 further fills the gap 125 between the sidewall 123 s of the second work function layer 123 and the gate dielectric layer 112 . In other embodiments, the insulating layer 128 may also partially fill the gap 125 or keep the gap 125 intact (as shown in FIG. 3 ). In addition, in other embodiments, multiple layers of insulating material may also be filled in the trench 103 . That is, the insulating layer 128 includes multiple layers of insulating material (as shown in FIG. 4 ).

The material of the insulating layer 128 includes, for example, nitride, oxide, other suitable dielectric materials, or a combination thereof. In one embodiment, the material of the insulating layer 128 includes silicon nitride, silicon oxide, other suitable materials, or a combination thereof. The insulating layer 128 may be a single layer or multiple layers of insulating material. In one embodiment, the insulating layer 128 comprises a different insulating material than the gate dielectric layer 112 . Furthermore, the insulating layer 128 can be formed by PVD, CVD, ALD, spin-coating process, other suitable processes, or a combination of the foregoing.

FIG. 3 is a schematic cross-sectional view of an intermediate stage of fabricating a semiconductor structure according to another embodiment of the present invention. FIG. 4 is a schematic cross-sectional view of an intermediate stage of fabricating a semiconductor structure according to another embodiment of the present invention. Figures 3 and 4 are alternative embodiments of the steps of Figure 1F.

3, the insulating layer 128 formed here only partially fills or does not fill the gap 125, so there is an air gap (air gap) 125G between the sidewall 123s of the second work function layer 123 and the gate dielectric layer 112, and the insulating layer 128 is located above the top surface 123a of the second work function layer 123 and the air gap 125G. In this embodiment, since the dielectric constant of air is higher than that of the insulating layer 128, compared to the embodiment of Fig. 1F, the air gap 125G can further reduce the situation of leakage current.

Please refer to FIG. 4 , the insulating layer 128 formed here includes two insulating portions 126 and 127 . Specifically, after the step in FIG. 1E , the insulating portion 126 may be conformally formed first on the substrate 100 and in the trench 103 , and then the insulating portion 127 may be blanket formed on the substrate 100 and in the trench 103 . As shown, the insulating portion 126 is located in the trench 103 and on the second work function layer 123 , and the insulating portion 126 fills the gap 125 between the sidewall 123 s of the second work function layer 123 and the gate dielectric layer 112 . The insulating portion 126 further covers the top surface 123 a and the sidewall 123 s of the second work function layer 123 . In one embodiment, the insulating part 126 and the insulating part 127 may comprise different materials. For example, the insulating portion 126 is an oxide layer, and the insulating portion 127 is a nitride layer. In another embodiment, the insulating portion 126 may include the same insulating material as the gate dielectric layer 112 , such as silicon oxide. In this embodiment, by forming the insulating layer 128 with a multi-layer structure, insulating materials with different dielectric constants can be further selected to increase the overall dielectric constant of the insulating layer 128. Therefore, compared with the embodiment of FIG. 1F, the situation of leakage current can be further reduced.

FIG. 5 is a schematic cross-sectional view of an intermediate stage of fabricating a semiconductor structure according to an embodiment of the present invention. Following FIG. 1F , after the insulating layer 128 is formed, a planarization process may be performed to remove part of the insulating layer 128 until the top surface 111 a of the mask layer 111 is exposed. As shown in FIG. 5, after planarization, the first work function layer WF-1, the second work function layer 123, and the second barrier layer 120 located under the remaining insulating layer 128 in the trench 103 constitute the buried gate structure of the present invention. In this embodiment, the first work function layer WF- 1 includes a first barrier layer 115 and a conductive layer 117 . In other embodiments Among them, the first work function layer WF-1 may also only include the conductive layer 117 .

The buried gate structure of the embodiment of the present invention can be applied to a dynamic random access memory (DRAM) device as a buried word line. The following is an example to illustrate the subsequent process of manufacturing a DRAM device after forming the buried gate structure according to the embodiment. Please refer to Figures 6 and 7. FIG. 6 is a schematic top view of a memory device according to an embodiment of the present invention, and FIG. 7 is a schematic cross-sectional view drawn according to section line 7-7 in FIG. 6 . The same or similar elements in Figures 6 and 7 as those in Figures 1A-1F and 2-5 continue to use the same or similar symbols for clarity. Furthermore, the buried gate structure shown in FIG. 7 is described in continuation of the buried gate structure shown in FIG. 5 , but the present invention is not limited thereto.

As shown in FIG. 6, the memory device includes a substrate 100, a plurality of shallow trench isolation structures 102, a plurality of active regions _AA , a plurality of bit lines BL, a plurality of word line groups 104, a plurality of capacitor contacts 107 and a plurality of bit line contacts 109. A plurality of doped regions are formed in the substrate 100 as active regions A _A , and each active region A _A is roughly arranged along a direction D1 (eg, X direction) and forms an included angle with the direction D1 . A shallow trench isolation structure 102 (not shown) surrounding the active region _AA is also formed in the substrate 100 . In this embodiment, the active areas A _A are alternately formed in the direction D1 in the form of waves, but the invention is not limited thereto.

A plurality of bit lines BL are formed above the substrate 100 , each bit line BL extends along the direction D1 , and adjacent bit lines BL are arranged at a distance from each other along the direction D3 . A plurality of word line groups 104 are formed in the substrate 100 and respectively extend along the direction D3. In one embodiment, each wordline group 104 has two buried wordlines 104A, 104B, And the adjacent buried word lines 104A, 104B are arranged with a distance in the direction D1. The cross-sectional structure of each buried word line 104A/ 104B is the same as the buried gate structure shown in FIG. 5 , and will not be repeated here.

As shown in FIG. 6, each active area _AA crosses a set of corresponding word line groups 104 (for example, including buried word lines 104A, 104B), and each active area _AA and the corresponding bit line BL have an overlapping area (for example, a middle section of the active area _AA ) and non-overlapping areas on both sides. There is a capacitor contact 107 in the two non-overlapping regions of each active area _AA and the bit line BL, which is electrically connected to the upper capacitor (not shown). Each capacitor contact 107 is located between two adjacent bit lines BL. In one embodiment, the capacitor contact 107 is located on the substrate 100 and contacts a portion of the upper surface of the doped region of the substrate 100 . For example, as shown in FIGS. 6 and 7, two capacitor contacts 107 corresponding to an active area A _A are respectively disposed on both sides of the word line group 104 in the active area A _A to electrically connect the doped regions (active area A _A ) adjacent to both sides of the word line group 104. Thus, the doped regions where the capacitor contacts 107 contact the substrate 100 serve as source/drain regions of the memory device.

As shown in FIGS. 6 and 7, each active area _AA has a bit line contact 109 at the overlapping area with the bit line BL. In one embodiment, the bitline contact 109 is buried between the insulating layer 128 of two adjacent buried wordlines 104A and 104B, wherein the bottom surface of the bitline contact 109 is in contact with the doped region of the substrate 100 . The manufacturing method of the bit line contact 109 is, for example, forming an opening between the insulating layer 128 of two adjacent buried word lines 104A and 104B, and the aforementioned opening exposes a part of the doped region of the substrate 100, and then depositing polysilicon on the substrate and in the aforementioned opening, and then depositing one or more conductive materials such as titanium, tungsten, tantalum, titanium nitride, tantalum nitride, tungsten nitride, etc. A photolithographic etching process is performed to form a stack structure including the bit line contact 109 , the bit line BL and the insulating capping layer 605 . It is worth mentioning that the polysilicon located in the aforementioned opening serves as the bit line contact 109, and the bit line BL located on the bit line contact 109 may include one or more conductive materials such as titanium, tungsten, tantalum, titanium nitride, tantalum nitride, and tungsten nitride, and the bit line BL extends along the direction D1.

As shown in FIGS. 6 and 7, when each bit line BL crosses the corresponding word line group 104, it can use the bit line contact 109 to electrically connect the corresponding two embedded word lines 104A, 104B. For example, the bottom of the bit line contact 109 is in contact with the upper surface of the doped region of the substrate 100 between the two word lines.

Furthermore, as shown in FIG. 7 , spacers 607 (materials thereof include one or more materials such as silicon oxide, silicon nitride, and air gaps) can be formed on the insulating cap layer 605 and the sidewalls of the bit lines BL. For example, after the aforementioned lithographic etching process, a liner (such as silicon nitride) can be conformally deposited on the substrate and dry-etched to form spacers 607 on the insulating cap layer 605 and the sidewalls of the bit lines BL. Next, after the insulating material is completely formed on the substrate, a planarization process is performed with the insulating cap layer 605 as a stop layer to form an interlayer insulating layer 610 on both sides of the bit line BL. Afterwards, a contact hole (not shown) is formed through the interlayer insulating layer 610 and the mask layer 111 by using a process such as lithographic etching to expose a part of the doped region of the substrate 100 . Next, one or more conductive materials including polysilicon, titanium nitride, or tungsten are deposited in the contact holes, and redundant conductive materials above the interlayer insulating layer 610 are removed by CMP, to form capacitor contacts 107 . In an embodiment Among them, the capacitor contact 107, the bit line contact 109, the bit line BL, and the insulating cover layer 605 are formed in the interlayer insulating layer 610, and the top surface of the capacitor contact 107 and the top surface of the insulating cover layer 605 can be substantially coplanar with the top surface of the interlayer insulating layer 610, for example.

To sum up the above, the semiconductor structure and its manufacturing method proposed by the present invention have the second work function layer 123 having a different work function from the first work function layer 117, wherein the work function of the second work function layer 123 is smaller than the work function of the first work function layer 117, so the electric field induced by the second work function layer 123 in the substrate can be reduced, and the width of the gate channel can be adjusted to suppress the drain leakage current caused by the gate.

In addition, the present invention can control the distance from the second work function layer 123 to the substrate 100 by controlling the width of the gap 125/125' (i.e., the thickness t2 of the barrier material layer), so as to adjust the electric field induced by the second work function layer 123 in the substrate to suppress the gate-induced drain leakage current. In addition, the present invention can also form dielectrics with different structures above the second work function layer 123 and between the second work function layer 123 and the substrate 100 to suppress gate-induced drain leakage current. For example, a single-layer structure (such as the insulating layer 128 in FIG. 1E ) or a multi-layer structure (such as the air gap 125G and the insulating layer 128 in FIG. 3 , or the insulating portion 128 including the insulating portions 126 and 127 in FIG. 4 ) can be formed to suppress gate-induced drain leakage current.

Although the present invention has been disclosed as above with several preferred embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make any changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the scope of the appended patent application.

100: base

102:Shallow trench isolation structure

111: mask layer

100a, 111a, 123a: top surface

103s, 112s, 117s, 120s, 123s: side wall

103b, 117b: bottom surface

112: gate dielectric layer

112s-2: The lower sidewall of the gate dielectric layer

112s-1: Upper sidewall of the gate dielectric layer

WF-1: The first work function layer

115: The first barrier layer

117: conductive layer

120: Second barrier layer

123: Second work function layer

125: Gap

128: insulation layer

Claims (15)

A semiconductor structure comprising: a substrate; a buried gate structure disposed in the substrate, the buried gate structure comprising: a gate dielectric layer located on the sidewall and bottom of a trench in the substrate; a first work function layer located in the trench and in contact with the sidewall and bottom of the gate dielectric layer; a barrier layer located on the top surface of the first work function layer; There is a distance between the gate dielectric layers, wherein the thickness of the barrier layer defines the width of the distance, and the width of the distance is equal to the thickness of the barrier layer, wherein the sidewall of the barrier layer is coplanar with the sidewall of the second work function layer, and all parts of the side wall of the second work function layer and the gate dielectric layer and between all parts of the side wall of the barrier layer and the gate dielectric layer are completely filled with air or completely filled with a dielectric material layer that does not contain metal; and an insulating layer located in the trench and on the second work function layer. The semiconductor structure as claimed in claim 1, wherein an extension portion of the insulating layer is the aforementioned dielectric material layer filling gaps between the sidewall of the second work function layer and the gate dielectric layer and between the sidewall of the barrier layer and the gate dielectric layer. The semiconductor structure as claimed in claim 1, wherein the insulating layer comprises: A first insulating part is located in the trench, and the first insulating part is the aforementioned dielectric material layer filling the space between the sidewall of the second work function layer and the gate dielectric layer and the gap between the sidewall of the barrier layer and the gate dielectric layer; and a second insulating part is located in the trench and on the first insulating part. The semiconductor structure according to claim 3, wherein the first insulating portion further covers the top surface and the sidewall of the second work function layer, and the second insulating portion and the second work function layer are separated from each other by the first insulating portion. The semiconductor structure of claim 3, wherein the first insulating portion comprises the same material as the gate dielectric layer, and the first insulating portion and the second insulating portion comprise different materials. The semiconductor structure as claimed in claim 1, wherein there is an air gap between the sidewall of the second work function layer and the gate dielectric layer and between the side wall of the barrier layer and the gate dielectric layer, and the insulating layer is located on the top surface of the second work function layer and above the air gap. The semiconductor structure as claimed in claim 1, wherein the first work function layer comprises: a first barrier layer located in the trench and on the sidewall and the bottom surface of the gate dielectric layer; and a conductive layer located in the trench, and the first barrier layer surrounds the sidewall and bottom surface of the conductive layer, wherein the barrier layer located on the top surface of the first work function layer is a second barrier layer barrier layer. The semiconductor structure as claimed in claim 7, wherein the work function of the second barrier layer is smaller than the work function of the conductive layer and greater than the work function of the second work function layer. A method for manufacturing a semiconductor structure, comprising: providing a substrate, and forming a trench extending downward in the substrate; forming a gate dielectric layer on the sidewall and bottom of the trench; forming a first work function layer on the lower sidewall and bottom of the gate dielectric layer and in the lower part of the trench; forming a barrier material layer on the upper sidewall of the gate dielectric layer and the top surface of the first work function layer; forming a second work function material layer on the barrier material layer; a material layer to form a second work function layer on the barrier material layer, and expose a portion of the barrier material layer located on the upper sidewall of the gate dielectric layer; remove a portion of the barrier material layer to form a barrier layer between the second work function layer and the first work function layer, and form a space between the sidewall of the second work function layer and the gate dielectric layer, wherein the width of the space is equal to the thickness of the barrier layer, and the side wall of the barrier layer and the The sidewalls of the second work function layer are coplanar, and between all parts of the side walls of the second work function layer and the gate dielectric layer and between all parts of the side walls of the barrier layer and the gate dielectric layer are completely filled with air or completely filled with a dielectric material layer not containing metal; and forming an insulating layer in the trench and on the second work function layer. The method for manufacturing a semiconductor structure as claimed in item 9, wherein in the When the second work function material layer is formed on the barrier material layer, the second work function material layer directly contacts the aforementioned portion of the barrier material layer on the upper sidewall of the gate dielectric layer. The method for manufacturing a semiconductor structure as claimed in item 9, wherein an extension of the insulating layer is the aforementioned dielectric material layer filling the gap between the sidewall of the second work function layer and the gate dielectric layer and the gap between the sidewall of the barrier layer and the gate dielectric layer. The method for manufacturing a semiconductor structure as claimed in claim 9, wherein the insulating layer comprises: a first insulating portion located in the trench and on the second work function material layer, and the first insulating portion is the aforementioned dielectric material layer, filling the space between the side wall of the second work function layer and the gate dielectric layer and the gap between the side wall of the barrier layer and the gate dielectric layer, the first insulating portion further covers the top surface and the side wall of the second work function layer; and a second insulating portion is located in the trench and Located on the first insulating portion, wherein the second insulating portion and the second work function layer are separated from each other by the first insulating portion. The method for manufacturing a semiconductor structure as claimed in item 9, wherein there is an air gap between the sidewall of the second work function layer and the gate dielectric layer and between the side wall of the barrier layer and the gate dielectric layer, and the insulating layer is located on the top surface of the second work function layer and above the air gap. The method for manufacturing a semiconductor structure as claimed in claim 9, wherein forming the first work function layer comprises: A first barrier layer is formed on the lower sidewall and the bottom surface of the gate dielectric layer, and a conductive layer is formed in the lower portion of the trench, and the first barrier layer surrounds the sidewall and the bottom surface of the conductive layer, wherein the first barrier layer and the conductive layer form the first work function layer, wherein the barrier material layer is formed on the upper sidewall of the gate dielectric layer, the top surface of the first barrier layer, and the top surface of the conductive layer, wherein part of the barrier material layer is removed. The barrier layer is a second barrier layer. The method of manufacturing a semiconductor structure as claimed in claim 14, wherein the work function of the barrier material layer is smaller than the work function of the conductive layer and greater than the work function of the second work function material layer.

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