TWI750858B - Semiconductor structure and method for forming the same - Google Patents

Abstract

A semiconductor structure includes a semiconductor substrate and a gate structure embedded in the semiconductor substrate. The gate structure includes a gate electrode layer, a barrier layer disposed over the gate electrode layer, and a semiconductor layer disposed over the barrier layer. The semiconductor structure also includes an air gap in the semiconductor substrate and exposing the barrier layer and the semiconductor layer.

Description

Semiconductor structure and method of forming the same

The present disclosure relates to a semiconductor structure, and more particularly, to dynamic random access memory.

Dynamic Random Access Memory (DRAM) devices are widely used in consumer electronic products. In order to increase the device density within a DRAM device and improve its overall performance, current DRAM device fabrication techniques continue to strive towards the miniaturization of device size. However, as component sizes continue to shrink, many challenges arise. For example, gate induced drain leakage (GIDL) is improved. Therefore, the industry still needs to improve the manufacturing method of the DRAM device to overcome the problems caused by the shrinking device size.

Embodiments of the present invention provide semiconductor structures. The semiconductor structure includes a semiconductor substrate and a gate structure embedded in the semiconductor substrate. The gate structure includes a gate electrode layer, a barrier layer arranged on the gate electrode layer, and a semiconductor layer arranged on the barrier layer. The semiconductor structure also includes a barrier layer in the semiconductor substrate and exposing the gate structure and an air gap of the semiconductor layer.

Embodiments of the present invention provide a method of forming a semiconductor structure, the method comprising forming a trench in a semiconductor substrate, forming a gate liner along a lower portion of the trench, and filling a gate electrode layer in the lower portion of the trench and on the gate above the lining. The method also includes forming a first sacrificial layer along the sidewalls of the upper portion of the trench, and forming a barrier layer along the sidewalls of the first sacrificial layer and a top surface of the gate electrode layer. The method also includes removing a first portion of the barrier layer along the sidewalls of the first sacrificial layer, thereby leaving a second portion of the barrier layer along the top surface of the gate electrode layer. The method also includes forming a semiconductor layer over the second portion of the gate electrode layer, removing the first sacrificial layer, and forming a capping layer over the semiconductor layer.

The present disclosure is more fully described below with reference to the drawings of embodiments of the present invention. However, the present disclosure can also be practiced in various different embodiments and should not be limited to the embodiments described herein. The thicknesses of layers and regions in the figures may be exaggerated for clarity, and the same or similar reference numbers indicate the same or similar elements throughout the various figures.

FIGS. 1A to 1O are schematic cross-sectional views illustrating different stages of forming a semiconductor structure according to some embodiments of the present invention. FIG. 3 is a schematic plan view showing a semiconductor structure according to some embodiments of the present invention, wherein FIGS. 1A to 10 are taken along the section A-A in FIG. 3 .

FIG. 3 shows the semiconductor structure 100 . The semiconductor structure 100 includes a semiconductor substrate 102 . The semiconductor substrate 102 includes an active region 103 , an isolation region 101 , and a chop region 105 . The active regions 103 are semiconductor blocks extending along the first direction D1 , and each active region 103 is defined by two isolation regions 101 and two blocking regions 105 . Isolation structures (not shown) are formed in the isolation regions 101 and the blocking regions 105 of the semiconductor substrate 102 so as to surround and electrically isolate these active regions 103 .

The isolation regions 101 extend along the first direction D1 and are spaced in the second direction D2, thereby dividing the semiconductor substrate 102 into a plurality of semiconductor strips (not shown). The first direction D1 is the channel extending direction, and the second direction D2 is the gate extending direction. An acute angle is formed between the first direction D1 and the second direction D2, the range of which is, for example, about 10 degrees to about 80 degrees. The cut-off regions 105 (represented by dotted lines) are disposed corresponding to the semiconductor strips, and cut the semiconductor strips into a plurality of active regions 103 . In the second direction D2, the adjacent cut-off regions 105 may be misaligned or non-overlapping. For example, in the second direction D2, the cut-off regions 105 may be periodically arranged (eg, overlapped) every several semiconductor strips (eg, 2 to 5).

The semiconductor structure 100 also includes a gate structure 124 . The gate structure 124 is embedded in the semiconductor substrate 102 and extends along the second direction D2. Each gate structure 124 extends alternately through the active region 103 and the isolation structure. The two gate structures 124 extend through the single active region 103 , and the two gate structures 124 extend through the cut-off regions 105 on both sides of the active region 103 . For clarity of the drawings, FIG. 3 only shows the above-mentioned components, and the remaining components of the semiconductor structure 100 can be seen in the schematic cross-sectional views of FIGS. 1A to 10 , which are taken along the A-A section of FIG.

A method of forming the semiconductor structure will be described below. Referring to FIG. 1A , a semiconductor substrate 102 is provided, and an isolation structure 104 is formed in the semiconductor substrate 102 . In some embodiments, the semiconductor substrate 102 is an elemental semiconductor substrate, such as a silicon substrate, or a germanium substrate; or a compound semiconductor substrate, such as a silicon carbide substrate, or a gallium arsenide substrate. In some embodiments, the semiconductor substrate 102 may be a semiconductor-on-insulator (SOI) substrate.

The isolation structure 104 extends downward from the upper surface of the semiconductor substrate 102 . The isolation structure 104 is configured to define the active region 103 of the semiconductor substrate 102 . In some embodiments, the isolation structure 104 is formed of a dielectric material, eg, silicon nitride (SiN), silicon oxide (SiO), silicon oxynitride (SiON), and/or combinations thereof.

The formation of the isolation structure 104 may include using one or more etching processes to form trenches corresponding to the isolation region 101 and the blocking region 105 of FIG. 3, followed by chemical vapor deposition (CVD) and/or atomic layer deposition Atomic layer deposition (ALD) deposits a dielectric material for the isolation structure 104 . Afterwards, a planarization process, such as an etch-back process and/or chemical mechanical polishing, is performed on the semiconductor structure 100 .

A patterning process is performed on the semiconductor structure 100 to form trenches 106 in the semiconductor substrate 102, as shown in FIG. 1B. The trenches 106 extend through the isolation structures 104 and the active region of the semiconductor substrate 102 . FIG. 1B only shows the part of the trench 106 in the isolation structure 104 , and the trench 106 also includes other parts in the active region 103 of the semiconductor substrate 102 .

The patterning process may include one or more deposition processes, one or more etching processes, and one or more lithography processes. For example, a hard mask layer can be formed on the semiconductor substrate 102 through a deposition process. A patterned photoresist layer can be formed on the hard mask layer through a lithography process. The trenches 106 may be formed by transferring the opening pattern of the patterned photoresist layer to the hard mask layer and then to the semiconductor substrate 102 through an etching process.

A gate dielectric layer 108 , a gate liner layer 110 , and a gate electrode layer 112 are sequentially formed in the trench 106 , as shown in FIG. 1C . The gate liner 110 is lined between the gate dielectric layer 108 and the gate electrode layer 112 .

A gate dielectric layer 108 is formed along sidewalls and bottom surfaces of the trenches 106 to partially fill the trenches 106 . FIG. 1C only shows the portion of the gate dielectric layer 108 lining the isolation structure 104 , and the gate dielectric layer 108 also includes other portions lining the active region 103 of the semiconductor substrate 102 . In some embodiments, the gate dielectric layer 108 is formed of silicon oxide, silicon nitride, silicon oxynitride, and/or high-k dielectric materials. In some embodiments, the gate dielectric layer 108 is formed using in-situ steam generation (ISSG), chemical vapor deposition (CVD), and/or atomic layer deposition (ALD).

A gate liner 110 is formed over the gate dielectric layer 108 at the lower portion of the trench 106 to partially fill the trench 106 . In some embodiments, the gate liner 110 is formed of titanium nitride (TiN), tungsten nitride (WN), and/or tantalum nitride (TaN). The gate liner layer 110 may be deposited using chemical vapor deposition (CVD), physical vapor deposition (PVD), and/or atomic layer deposition (ALD).

A gate electrode layer 112 is formed on the gate liner 110 to fill the lower portion of the trench 106 . The gate electrode layer 112 is nested within the gate liner layer 110 . In some embodiments, the gate electrode layer 112 is formed of a metallic material, eg, tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), ruthenium (Ru), and/or other metallic materials. The gate electrode layer 112 may be deposited using physical vapor deposition (PVD), chemical vapor deposition (CVD), and/or atomic layer deposition (ALD).

The gate liner layer 110 and the gate electrode layer 112 may be etched back after depositing the materials for the gate dielectric layer 108 , the gate liner layer 110 and the gate electrode layer 112 .

A first sacrificial layer 114 is formed on the semiconductor substrate 102 to partially fill the trench 106, as shown in FIG. 1D. The first sacrificial layer 114 covers and follows the sidewalls of the gate dielectric layer 108 , the top surface of the gate liner layer 110 , and the top surface of the gate electrode layer 112 . According to some embodiments, the thickness of the first sacrificial layer 114 along the gate dielectric layer 108 is equal to or greater than the thickness of the gate liner layer 110 . In some embodiments, the first sacrificial layer 114 is formed of a dielectric material, eg, silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), and/or combinations thereof. An etching selectivity ratio exists between the first sacrificial layer 114 and the isolation structure 104 . For example, when the isolation structure 104 is formed of silicon nitride, the first sacrificial layer 114 is formed of silicon oxide. When the isolation structure 104 is formed of silicon oxide, the first sacrificial layer 114 is formed of silicon nitride. The first sacrificial layer 114 may be deposited using chemical vapor deposition (CVD) and/or atomic layer deposition (ALD).

An etching process is performed on the first sacrificial layer 114 to remove horizontal portions of the first sacrificial layer 114 along the upper surface of the semiconductor 102 and along the top surface of the gate electrode layer 112, as shown in FIG. 1E. After the etching process, the top surface of the gate electrode layer 112 is exposed, and the vertical portion of the first sacrificial layer 114 along the gate dielectric layer 108 is left. The vertical portion of the first sacrificial layer 114 completely covers the top surface of the gate liner 110 . The vertical portion of the first sacrificial layer 114 may also partially cover the gate electrode layer 112 . In some embodiments, the etching process may include an overetch step to slightly etch back the gate electrode layer 112 such that the gate electrode layer 112 has a top surface 112A that is lower than the top surface of the gate liner layer 110 .

A barrier layer 116 is formed over the semiconductor substrate 102 to partially fill the trench 106, as shown in FIG. 1F. The barrier layer 116 covers and extends along the sidewalls of the first sacrificial layer 114 and the top surface of the gate electrode layer 112 . The barrier layer 116 is not in contact with the gate liner 110 .

There is an etch selectivity ratio between the barrier layer 116 and the gate electrode layer 112 . In some embodiments, the barrier layer 116 is formed of titanium nitride (TiN), tungsten nitride (WN), and/or tantalum nitride (TaN). The barrier layer 116 may be deposited using physical vapor deposition (PVD), chemical vapor deposition (CVD), and/or atomic layer deposition (ALD). In some embodiments, barrier layer 116 and gate liner 110 are formed of the same material.

A fill layer 118 is formed over the barrier layer 116 to overfill the upper portion of the trench 106, as shown in FIG. 1G. In some embodiments, the fill layer 116 is formed of a carbon-rich material, eg, spin-on coating (SOC). The fill layer 118 may be formed using a spin coating process.

The filling layer 118 is etched back to remove the portion of the filling layer 118 formed on the upper surface of the semiconductor substrate 102, and the portion of the filling layer 118 formed in the trench 106 is etched back, as shown in FIG. 1H. After the etch-back process, the upper portion of trench 106 is again formed and designated as trench 106'. After the etch-back process, the barrier layer 116 is exposed from the trench 106' along the upper portion of the vertical portion of the first sacrificial layer 114.

According to some embodiments, one or more etching processes are performed on the barrier layer 116 to remove portions of the barrier layer 116 above the upper surface of the semiconductor substrate 102 and vertical portions along the first sacrificial layer 114 until exposed The gate electrode layer 112 is shown in FIG. 1I. The fill layer 118 protects the horizontal portion of the barrier layer 116 along the top surface of the gate electrode layer 112 from being removed during the etching process.

Since there is an etching selectivity ratio between the barrier layer 116 and the gate electrode layer 112, the etching process can be better controlled by detecting the etching stop point. In addition, during the etching process, the first sacrificial layer 114 covers and protects the gate liner 110 such that the gate liner 110 is substantially unetched.

In some embodiments, the etching process may include an over-etch step to slightly etch back the gate electrode layer 112 such that the gate electrode layer 112 has a top surface 112B that is lower than the level of the top surface of the gate liner 110 and the gate The level of the top surface 112A of the electrode layer.

The fill layer 118 is etched away to expose the barrier layer 116, as shown in FIG. 1J.

A second sacrificial layer 120 is formed over the semiconductor substrate 102 to partially fill the trench 106', as shown in FIG. 1K. The second sacrificial layer 120 covers and follows the sidewalls of the first sacrificial layer 114 and the top surface of the barrier layer 116 . In some embodiments, the second sacrificial layer 120 is formed of a dielectric material, eg, silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), and/or combinations thereof. There is an etching selectivity ratio between the second sacrificial layer 120 and the isolation structure 104 . For example, when the isolation structure 104 is formed of silicon nitride, the second sacrificial layer 120 is formed of silicon oxide. When the isolation structure 104 is formed of silicon oxide, the second sacrificial layer 120 is formed of silicon nitride. The second sacrificial layer 120 may be formed of the same material as the first sacrificial layer 114 . For clarity, FIG. 1K shows the interface between the first sacrificial layer 114 and the second sacrificial layer 120 , however, there may be no physical interface between the first sacrificial layer 114 and the second sacrificial layer 120 . The second sacrificial layer 120 may be deposited using chemical vapor deposition (CVD) and/or atomic layer deposition (ALD).

An etching process is performed on the second sacrificial layer 120 to remove horizontal portions of the second sacrificial layer 120 along the upper surface of the semiconductor 102 and along the top surface of the barrier layer 116, as shown in FIG. 1L. After the etching process, the top surface of the barrier layer 116 is exposed, and the vertical portion of the second sacrificial layer 120 along the first sacrificial layer 114 is left. The top surfaces 112A and 112B of the gate electrode layer 112 are covered by the barrier layer 116 and the second sacrificial layer 120, respectively.

A semiconductor layer 122 is formed in the trench 106' to fill the lower portion of the trench 106', as shown in FIG. 1M. The gate dielectric layer 108 , the gate liner layer 110 , the gate electrode layer 112 , the barrier layer 116 , and the semiconductor layer 122 combine to form the gate structure 124 . The gate structure 124 may be configured as a word line of the resulting semiconductor memory device, such as a buried word line (BWL). In some embodiments, the barrier layer 116 and the semiconductor layer 122 may serve as work function adjustment layers of the gate structure 124 . In some embodiments, the semiconductor layer 122 is formed of polysilicon. The formation of semiconductor layer 122 may include depositing semiconductor layer 122 using a chemical vapor deposition (CVD) process to overfill trench 106', and then etching semiconductor layer 122 back.

In some embodiments, the sidewalls of the semiconductor layer 122 are substantially aligned with the sidewalls of the barrier layer 116 . The widths of the semiconductor layer 122 and the barrier layer 116 are smaller than the maximum width of the gate electrode layer 112 . For example, the ratio of the width of the semiconductor layer 122 and the barrier layer 116 to the maximum width of the gate electrode layer 112 ranges from about 0.5 to about 0.9. Since the top surface of the gate electrode layer 112 is covered by the second sacrificial layer 120 and the barrier layer 116 , the semiconductor layer 122 may be formed not to be in contact with the top surface of the gate electrode layer 112 . When the semiconductor layer is in contact with the gate electrode layer, the silicon from the semiconductor layer and the metal of the gate electrode layer may form metal silicide, thereby increasing the overall resistance value of the gate structure.

The first sacrificial layer 114 and the second sacrificial layer 120 are removed by etching until the gate electrode layer 112 and the gate liner layer 110 are exposed, as shown in FIG. 1N . After the etching process, a gap 107 is formed between the semiconductor layer 122 (and the barrier layer 116 ) and the gate dielectric layer 108 .

A capping layer 126 is formed in the trench 106' as shown in FIG. 10 . Cap layer 126 seals gap 107 to form air gap 128 between semiconductor layer 122 (and barrier layer 116 ) and gate dielectric layer 108 .

Additional components, such as source/drain regions in the semiconductor substrate 102, contact plugs connected to the source/drain regions, bit lines, capacitors, and/or other components, may be formed within the semiconductor structure 100 , to produce a semiconductor memory device. In some embodiments, the semiconductor memory device is a dynamic random access memory (DRAM).

According to the embodiment of the present invention, the gate structure 124 includes a dual work function adjustment layer (ie, the barrier layer 116 and the semiconductor layer 122 ), which can reduce the electric field intensity generated by the gate electrode layer 112 of the gate structure 124 , thereby reducing the gate gate induced drain leakage (GIDL). In addition, the semiconductor structure 100 includes air gaps 128 on both sides of the semiconductor layer 122 (and the barrier layer 116 ), which can further reduce the gate-induced drain leakage current, which improves the reliability and manufacturing yield of the semiconductor memory device. Furthermore, according to the embodiment of the present invention, the dual work function adjustment layer of the gate structure 124 does not need to be formed through an additional mask. In this way, the overlay window limitation of the lithography process is avoided. Furthermore, according to the embodiment of the present invention, by forming the first sacrificial layer 114 to protect the gate liner 110, during the etching process of the barrier layer 116, the loss of the gate liner 110 can be greatly reduced and the etching can be better controlled The end point of the process. Furthermore, the second sacrificial layer 120 is formed to cover the top surface 112B of the gate electrode layer 112 to prevent the semiconductor layer 122 from contacting the gate electrode layer 112 to form metal silicide. In this way, the resistance value of the gate structure 124 is prevented from increasing due to the formation of metal silicide.

FIG. 2 is a diagram showing a modification of the semiconductor structure of FIG. 10 in accordance with some embodiments of the present invention. The semiconductor structure 200 shown in FIG. 2 is similar to the semiconductor structure 100 of FIG. 10 , except that the barrier layer 116 surrounds the lower portion of the semiconductor layer 122 .

In the step depicted in FIG. 1I, a partial etch removes the vertical portion of the barrier layer 116 along the first sacrificial layer 114 . After the etching process, the remaining barrier layer 116 has a U-shaped profile. The gate electrode layer 112 is covered by the remaining barrier layer 116 without being exposed. Next, the steps described in FIG. 1J are performed to remove the filling layer 118 to expose the barrier layer 116 .

The steps described in Figures 1K and 1L are omitted, and the steps described in Figures 1M to 10 are performed. A semiconductor layer 122 is formed in the trench 106'. The semiconductor layer 122 includes a lower portion surrounded by the barrier layer 116 and an upper portion formed over the top surface of the barrier layer 116, as shown in FIG. 2 . Cap layer 126 is formed in trench 106' to form air gap 128 between semiconductor layer 122 (and barrier layer 116) and gate dielectric layer 108 to produce semiconductor structure 200.

Based on the above, embodiments of the present invention provide a semiconductor structure including a buried gate structure and a method for forming the same. The buried gate structure includes a dual work function adjustment layer and air gaps on both sides of the dual work function adjustment layer. Therefore, the gate induced drain leakage current is reduced, which improves the reliability and manufacturing yield of the semiconductor memory device.

Although the present invention is disclosed in the foregoing embodiments, it is not intended to limit the present invention. Those with ordinary knowledge in the technical field to which the present invention pertains may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be determined by the scope of the appended patent application.

100: Semiconductor Structure 101: Quarantine 102: Semiconductor substrate 103: Active Zone 104: Isolation Structure 105: Truncation area 106: Groove 106’: Groove 107: Gap 108: gate dielectric layer 110: Gate liner 112: gate electrode layer 112A: Top surface 112B: Top surface 114: The first sacrificial layer 116: Barrier layer 118: Fill Layer 120: Second sacrificial layer 122: Semiconductor layer 124: Gate structure 126: Cover Layer 128: Air gap 200: Semiconductor Structure

To make the features and advantages of the present invention more obvious and easy to understand, different embodiments are exemplified below, and are described in detail in conjunction with the accompanying drawings as follows: FIGS. 1A to 10 are schematic cross-sectional views showing various stages of forming a semiconductor structure according to some embodiments of the present invention. FIG. 2 is a diagram showing a modification of the semiconductor structure of FIG. 10 in accordance with some embodiments of the present invention. FIG. 3 is a schematic plan view showing a semiconductor structure according to some embodiments of the present invention.

100: Semiconductor Structure

102: Semiconductor substrate

103: Active Zone

104: Isolation Structure

105: Truncation area

108: gate dielectric layer

110: Gate liner

112: gate electrode layer

112A: Top surface

112B: Top surface

116: Barrier layer

122: Semiconductor layer

124: Gate structure

126: Cover Layer

128: Air gap

Claims (13)

A semiconductor structure, comprising: a semiconductor substrate; and a gate structure embedded in the semiconductor substrate and comprising: a gate electrode layer; a barrier layer disposed on the gate electrode layer; and a semiconductor layer disposed on the barrier layer; an isolation structure disposed in the semiconductor substrate, wherein the gate structure is at least partially embedded in the isolation structure; and an air gap located in the semiconductor substrate and exposing the The barrier layer and the semiconductor layer of the gate structure. The semiconductor structure of claim 1, further comprising: a cap layer disposed on the gate structure and sealing the air gap. The semiconductor structure of claim 1, wherein the sidewall of the semiconductor layer is aligned with the sidewall of the barrier layer, and the width of the barrier layer is smaller than the width of the gate electrode layer. The semiconductor structure of claim 1, wherein the gate structure further comprises: a gate liner, wherein the gate electrode layer is nested in the gate liner, and the top surface of the gate liner is higher than the the top surface of the gate electrode layer. The semiconductor structure of claim 1, wherein the gate structure further comprises: a gate dielectric layer lining the isolation structure, wherein the air gap exposes a portion of the gate dielectric layer. The semiconductor structure of claim 1, wherein the semiconductor layer is formed of polysilicon, and the barrier layer is formed of titanium nitride. The semiconductor structure of claim 1, wherein the barrier layer has a U-shaped profile. A method for forming a semiconductor structure, comprising: forming a trench in a semiconductor substrate; forming a gate lining layer along a lower portion of the trench; filling a gate electrode layer in the lower portion of the trench and On the gate liner; forming a first sacrificial layer along the sidewall of an upper part of the trench; forming a barrier layer along the sidewall of the first sacrificial layer and the top surface of the gate electrode layer; moving removing a first portion of the barrier layer along the sidewall of the first sacrificial layer, thereby leaving a second portion of the barrier layer along the top surface of the gate electrode layer; forming a semiconductor layer on the barrier over the second portion of the layer; removing the first sacrificial layer; and forming a capping layer over the semiconductor layer. The method for forming a semiconductor structure of claim 8, further comprising: before removing the first portion of the barrier layer, forming a filling layer on the barrier layer to fill the upper portion of the trench; etching the a filling layer to at least partially expose the first portion of the barrier layer; and After removing the first portion of the barrier layer, the fill layer is removed to expose the second portion of the barrier layer. The method for forming a semiconductor structure of claim 8, further comprising: before forming the semiconductor layer, forming a second sacrificial layer along the sidewall of the first sacrificial layer and the top surface of the barrier layer; and removing the first sacrificial layer Two sacrificial layers are along a first portion of the top surface of the barrier layer, wherein after removing the first portion of the second sacrificial layer, the second sacrificial layer is along a second portion of the sidewalls of the first sacrificial layer A portion of the gate electrode layer is partially covered. The method for forming a semiconductor structure of claim 10, further comprising: removing the second portion of the second sacrificial layer while removing the first sacrificial layer, wherein removing the first sacrificial layer and the second sacrificial layer The sacrificial layer forms a gap between the semiconductor layer and the semiconductor substrate, and forms the cap layer to seal the gap. The method for forming a semiconductor structure of claim 8, wherein the first sacrificial layer has a first thickness along the upper portion of the trench, and the gate liner has a first thickness along the lower portion of the trench two thicknesses, and the first thickness is greater than the second thickness. A semiconductor structure, comprising: a semiconductor substrate; a gate structure embedded in the semiconductor substrate and comprising: a gate electrode layer; a barrier layer disposed on the gate electrode layer; a gate dielectric layer disposed at least between the gate electrode layer and the semiconductor substrate; a semiconductor layer disposed on the barrier layer; and an air gap in the semiconductor substrate, wherein the air gap is exposed A portion of the top surface of the gate electrode layer exits, wherein the air gap is located between the gate dielectric layer and the semiconductor layer, and between the gate dielectric layer and the barrier layer.

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