TWI766595B - Method for bonding two semiconductor structures - Google Patents

Abstract

The invention provides a method for bonding two semiconductor structures, the method includes the following steps: providing a substrate, an element pattern is formed on the substrate and a peripheral area is defined on the substrate, inclining the substrate at an angle, carrying out an oblique angle deposition step, forming a bonding layer on the substrate and the element pattern, and carrying out a planarization step to remove part of the bonding layer.

Description

Method for bonding two semiconductor structures

The present invention relates to a semiconductor manufacturing process, and more particularly, to a method for improving the bonding quality of semiconductor wafers by means of bevel deposition.

In the field of semiconductor manufacturing, different wafers or different dies may contain different circuit elements. In order to save product space, different wafers or different bare die are often bonded to each other to achieve a three-dimensional stack structure, and to reduce the area of the product and increase the component density of the product.

When different wafers or dies are bonded to each other, problems can often occur at the borders. For example, when two dies are bonded to each other, the boundary region between the two dies may not be completely covered by the material layer (such as a silicon oxide layer) used for bonding. A void is generated, so that in the subsequent manufacturing process, the structure at the void is relatively fragile, which is likely to cause damage to the finished product.

In order to avoid the above problems, the present invention provides a method for bonding two semiconductor structures, including providing a substrate, a pattern is formed on the substrate, and a peripheral area is defined on the substrate, the substrate is inclined at an angle, and a bevel angle is performed depositing step, forming a bonding layer on the substrate and the pattern, performing a planarizing step, removing part of the bonding layer, and after the planarizing step, further comprising: The substrate is bonded with a second substrate.

In some embodiments, if the pattern (eg, device pattern) on the wafer or die cannot cover the entire wafer or die, after the bonding layer (eg, silicon oxide) is deposited on the pattern, it will The circle or die leaves a portion of the area where the bonding layer is not deposited, which can create voids and affect the performance of the device after the two wafers or dies are bonded to each other. One of the features of the present invention is that, in other improved embodiments, an oblique deposition method is used, so that the unfilled peripheral area can be fully filled with the bonding layer, so that the two wafers are bonded to each other when the two wafers are bonded to each other. After bonding, it is not easy to generate voids in the peripheral area, which improves the quality of the device.

10: Base

12: Component area

14: Surrounding area

16: Component pattern

18:Unfilled area

20: Bonding layer

30: Base

40: Protruding side walls

FIG. 1 to FIG. 3 are schematic diagrams illustrating a cross-sectional structure flow of bonding two wafers according to an embodiment of the present invention.

FIG. 4 to FIG. 6 are schematic diagrams illustrating a cross-sectional structure flow of bonding two wafers according to another embodiment of the present invention.

In order to enable those of ordinary skill in the technical field to which the present invention pertains to further understand the present invention, preferred embodiments of the present invention are specifically listed below, and in conjunction with the accompanying drawings, the composition of the present invention and the desired effect will be described in detail. .

For the convenience of description, the drawings of the present invention are only schematic diagrams to facilitate the understanding of the present invention, and the detailed proportions thereof can be adjusted according to design requirements. As for the upper and lower relationship of the relative elements in the drawings described in the text, those skilled in the art should understand that it refers to the relative positions of the objects, so they can be Turning over to present the same components should all fall within the scope disclosed in this specification, and will be described here first.

Please refer to FIGS. 1 to 3. FIGS. 1 to 3 are schematic diagrams illustrating a cross-sectional structure flow of bonding two wafers according to an embodiment of the present invention. As shown in FIG. 1, first, a substrate 10 is provided, the substrate 10 includes an element area 12 and a peripheral area 14, wherein the element area 12 includes at least one element pattern 16, and the element pattern 16 is, for example, various electronic element patterns, Such as conductive lines, transistors, switches, capacitors, resistors, etc. The device pattern 16 is formed in the device region 12 on the substrate 10 but not formed in the peripheral region 14 .

The substrate 10 described here is, for example, a common semiconductor substrate, such as a silicon substrate, a silicon germanium substrate, a silicon carbide substrate, a silicon-on-insulator (SOI) substrate, or a substrate made of other semiconductor materials. In practice, the substrate 10 described herein may be a whole wafer or a diced die, which are all within the scope of the present invention.

It is also worth noting that, in some embodiments, a cross-sectional structure similar to an oblique angle may be generated where the element pattern 16 is close to the peripheral area 14 , and the reason for this may include that the part of the element pattern close to the peripheral area has elements Fewer or looser arrangements result in slightly lower stress support in this area than in other areas. However, the present invention does not limit that the element pattern 16 must include an oblique angle, and whether or not the cross-section of the element pattern 16 includes an oblique angle falls within the scope of the present invention.

As shown in FIG. 2, in order to bond the substrate 10 with another substrate (not shown), a bonding layer 20 is deposited on the substrate 10, wherein physical vapor deposition (PVD), chemical vapor deposition can be used. The bonding layer 20 is formed by means of (CVD) or atomic layer deposition (ALD), and the material of the bonding layer 20 is silicon oxide, for example, but not limited thereto. The bonding layer 20 covers the device pattern 16 of the device region 12 and part of the peripheral region 14 . Next, there may be a planarization step, such as chemical mechanical polishing (CMP), to remove excess bonds Layer 20. It should be noted that, in some cases, the bonding layer 20 may not be deposited in sufficient thickness in the peripheral region 14 during the deposition process, or because the bonding layer 20 may be in the peripheral region 14 during the planarization step. The inner bonding layer 20 is removed at a faster rate (because the stress close to the boundary may be greater) and other reasons, resulting in that after the planarization step, the bonding layer 20 does not completely cover the peripheral area 14, resulting in the peripheral area 14 A portion of the substrate 10 is exposed, where an underfilled area 18 may be defined (as shown in FIG. 2). Or in some embodiments, although the bonding layer 20 completely covers the peripheral region 14 without the substrate 10 being exposed, the top surface of the bonding layer 20 on the peripheral region 14 is lower (than the bonding layer 20 on the element pattern 16) The top surface of the lamination layer 20 is lower), an underfilled area 18 may also be created. If there are any underfilled areas above, it may affect the subsequent bonding steps.

As shown in FIG. 3 , when the substrate 10 and the other substrate 30 are bonded to each other through the contact bonding layer 20 , due to the existence of the unfilled area 18 left above, there is no gap between the substrate 10 and the substrate 30 . A gap will be left between (ie, the area 18 is not filled). In the subsequent steps, the gap will become a weak point in the structure, which will cause the component to easily break or separate from here. If it undergoes some soaking processes, the solvent may also penetrate into the gap between the two substrates, which is not conducive to the product quality. quality.

In order to avoid the above situation, the present invention proposes another improved method for bonding two wafers. Please refer to FIGS. 4 to 6 . FIGS. 4 to 6 are schematic diagrams illustrating a cross-sectional structure flow of bonding two wafers according to another embodiment of the present invention. First, FIG. 4 continues the structure of FIG. 1, that is to say, the same as the above-mentioned embodiment, a substrate 10 is provided, the substrate 10 includes an element area 12 and a peripheral area 14, wherein the element area 12 includes at least one element pattern. 16. The element pattern 16 is, for example, various electronic element patterns, such as conductive lines, transistors, switches, capacitors, resistors, and the like. The device pattern 16 is formed in the device region 12 on the substrate 10 but not formed in the peripheral region 14 .

Next, as shown in FIG. 4, a bonding layer 20 is deposited. The difference between this embodiment and the above-mentioned embodiment is that when the deposition step is performed to form the bonding layer 20 in this embodiment, the substrate 10 is first inclined at an angle. The horizontal position of the peripheral area 14 may be higher than that of the element patterns 16 in the element area 12 . Next, the bonding layer 20 is formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD). Since the deposition step starts from a higher horizontal position first, after the substrate 10 is tilted, the bonding layer 20 is more likely to fill the peripheral region 14 , and thus less likely to generate an unfilled region than the above-described embodiment.

In some embodiments of the present invention, the deposition method after tilting the substrate angle can also be performed in conjunction with processes such as rotating the substrate, so as to improve the uniformity of the deposited material layer. For example, a constant-speed rotating substrate can be used with an oblique deposition process, so that a layer of material of uniform thickness can be deposited on each of the different boundaries of the substrate. The above-described embodiments also fall within the scope of the present invention.

Next, as shown in FIG. 5, after returning the substrate 10 to the original horizontal plane (the horizontal direction before tilting), a planarization step is performed to remove the excess bonding layer 20, and then as shown in FIG. 6 , the other substrate 30 is brought into contact with the bonding layer 20 on the substrate 10 to bond the substrate 10 and the substrate 30 .

It is worth noting that in this embodiment, since the substrate 10 is inclined at an angle (as shown in FIG. 4 ) before the bonding layer 20 is deposited, it is easier to preferentially fill the peripheral region 14 on the substrate 10 during the deposition process. If it is full, a portion of the peripheral area 14 may protrude. Therefore, after the subsequent planarization step is completed (FIG. 5), the bonding layer 20 in the peripheral area 14 may include a protruding sidewall 40. The protruding sidewalls 40 can effectively protect the bonding structure between the substrate 10 and the substrate 30 , and are not prone to structural weak points similar to those shown in the first embodiment ( FIG. 3 ). Therefore, it also contributes to the improvement of the quality of the semiconductor element.

To sum up, in some embodiments, such as the embodiments shown in FIG. 1 to FIG. 3 , if the pattern (eg device pattern) on the wafer or die cannot cover the entire wafer or die , After the bonding layer (such as silicon oxide) is deposited on the pattern, there will be a part of the wafer or bare die where the bonding layer is not deposited. This area is after the two wafers or bare die are bonded to each other. , will create voids and affect the performance of the device. One of the features of the present invention is that in other improved embodiments (such as the embodiments shown in FIGS. 4 to 6 ), the method of bevel deposition is used, so that the above-mentioned unfilled peripheral area can be fully Therefore, after the two wafers are bonded to each other, it is not easy to generate voids in the peripheral area, which improves the quality of the device.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.

10: Base

12: Component area

14: Surrounding area

16: Component pattern

20: Bonding layer

Claims (6)

A method for bonding two semiconductor structures, comprising: providing a substrate on which an element pattern is formed, and defining a peripheral region on the substrate; inclining the substrate at an angle, and performing an oblique angle deposition step, on the substrate A bonding layer is formed on the element pattern; after the oblique deposition step is completed, the substrate is first restored to an original horizontal direction, and then a planarization step is performed to remove part of the bonding layer. The method of claim 1, wherein the bonding layer is included in the peripheral region on the substrate after the bevel deposition step. The method of claim 1, wherein the pattern on the substrate also has a bevel, and the bevel is close to the peripheral area. The method of claim 1, wherein after the planarizing step, further comprising bonding the substrate with a second substrate. The method of claim 4, wherein after the substrate and the second substrate are bonded, the bonding layer is located in the peripheral region between the substrate and the second substrate. The method of claim 1, wherein the bonding layer comprises silicon oxide.

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