TWI766416B - Single-layer polysilicon nonvolatile memory cell and memory including the same - Google Patents

Abstract

The present invention relates to a single-layer polysilicon non-volatile memory cell and its group structure and memory. The storage unit includes a selection transistor and a storage transistor, the selection transistor and the storage transistor are connected in series, and the two are arranged on the substrate in a mutually perpendicular manner. The memory cell group includes 4 memory cells, which are arranged in a center-symmetrical array of 2 rows×2 columns. The memory includes at least one group of storage cells. The storage unit and its memory are used as a one-time programming storage unit and memory, and have the advantages of small area, high programming efficiency and capability, and strong data retention capability.

Description

Single-layer polysilicon non-volatile memory cell and its structure and memory

The present invention relates to a single-layer polysilicon non-volatile memory unit and its memory, in particular to a one-time programmable non-volatile memory unit and its memory.

Non-volatile memory has the advantages that it will not disappear even if the power is turned off after data is stored, and the data can be retained for a long time. Therefore, it is widely used in electronic equipment at present. Among them, the development of single-layer polysilicon non-volatile memory is very rapid. It is simple in structure and stable in performance, and is widely used in various integrated circuits.

Single-layer polysilicon non-volatile memory is divided into multiple erasable programmable memory and one-time programmable memory. The area of the storage unit of the multiple erasable and programmable memory is generally large, which cannot meet the requirements of a large storage area, and the cost is high. One-time programmable memory has relatively weak programming ability and low data retention ability.

In addition, the design of non-volatile memory is constantly developing in the direction of saving space, and is committed to reducing the size and improving the integration level.

As a result, the industry continues to demand programmable memory that is smaller in size, has strong programming capabilities, and has high data retention capabilities.

The present invention relates to a single-layer polysilicon non-volatile memory cell, an array thereof and a memory structure, especially a one-time programmable memory cell and its memory.

A first aspect of the present invention relates to a single-layer polysilicon non-volatile memory cell structure, comprising: a select transistor and a storage transistor, both located in a substrate, the select transistor including a select gate, under the select gate gate oxide, source and drain; the storage transistor includes a floating gate, a gate oxide under the floating gate, a source and a drain; the selection transistor is connected in series with the storage transistor, and the two are perpendicular to each other arranged on the substrate.

In a preferred embodiment, the storage unit structure further includes a capacitor, and the capacitor and the selection transistor are located on two sides of the storage transistor, respectively. The capacitor is formed such that the end of the storage transistor floating gate and its gate oxide remote from the selection transistor extends in a direction perpendicular to and away from the selection transistor, covering a portion of the substrate surface to form a capacitor.

In another preferred embodiment, the selection transistor and the storage transistor in the storage unit are of the same type, and both are PMOS transistors, or both are NMOS transistors. In the case where both transistors are PMOS transistors, the substrate is an N-well with a P-substrate below the N-well.

The second aspect of the present invention relates to a single-layer polysilicon nonvolatile memory cell group structure, which includes 4 of the above-mentioned memory cells of the present invention, arranged in a center-symmetrical array of 2 rows×2 columns, and all memory cells are lined with The bottom is merged into one; the two memory cells in each row are mirror-symmetrical, two select transistors are arranged on both sides of the group, the two storage transistors are adjacent to each other in the middle, and there is one in the center of each row. source region, located in the substrate between two storage transistors; two storage transistors in each column The storage unit is mirror-symmetrical up and down, wherein the floating gates of the upper and lower selection transistors are connected up and down to form a whole, and the upper and lower storage transistors share a source electrode and are sandwiched between the upper and lower storage transistors; The doping type is the same as that of the common source region, and the active regions at the center of the upper and lower rows are connected together up and down, and between the upper and lower rows, and the shared source between the upper and lower storage transistors on the left and right sides extremely connected.

In a preferred embodiment, the four memory cells in the memory cell group are completely identical, including the composition, composition, and structure of each part, and all aspects are the same.

In another preferred embodiment, each memory cell in the memory cell group further includes a capacitor, and the capacitor and the selection transistor are located on two sides of the storage transistor, respectively, and are formed in such a way that the floating gate of the storage transistor is formed. and the end of its gate oxide away from the selection transistor, extending in a direction perpendicular to and away from the selection transistor, covering a part of the surface of the substrate to form a capacitor; the active area at the center of each row is located at the left and right two between the two capacitors of the memory cell.

In another preferred embodiment, all select transistors and storage transistors in the memory cell group are of the same type. In the case where the transistor is a PMOS transistor, the substrate is an N well, and there is a P substrate under the N well, and the active region is a P-doped region.

In yet another preferred embodiment, the memory cell group structure further comprises: one bit line in each row, connected to the drains of the select transistors of each memory cell in the row; one word line in each column, connected to the gates of the select transistors of the memory cells in the column; there is a common line in the middle of the two columns, connected to the active area between the two memory transistors in the two columns, and through the active area Connect to the sources of the storage transistors of all memory cells in the group.

In a more preferred embodiment, in the memory cell group structure, in the active region located at the center of the group between the four center-symmetrically arranged memory transistors, there is a contact hole , the common line connects the contact hole, and thus through the active region, to the sources of all storage transistors in the group.

A third aspect of the present invention relates to a single-layer polysilicon non-volatile memory structure, which includes: at least one of the above-mentioned non-volatile memory cell groups of the present invention, forming an array, and each group is arranged in the array in the same manner are the same, and the substrates of the memory cells of each group are merged into one body to form the substrate of the array; wherein the floating gates of the selection transistors at the upper and lower corresponding positions of different groups in each column are connected up and down to form a whole; different in each column The active regions in the row center at the upper and lower corresponding positions of the group are connected up and down to form a whole; there is a bit line in each row, which is connected to the drains of the selection transistors of all memory cells in each group in the row; There is a word line in a column, which is connected to the gates of the select transistors of all memory cells of each group in the column; there is a common line in the middle of two adjacent columns, which is connected to the two memory cells of each group in the column. Active regions between transistors, and connected to the sources of all storage transistors in each group through the active regions.

In a preferred embodiment, each group in the memory array is the same, including composition, structure, arrangement and other aspects.

In another preferred embodiment, in the memory array, in the active area of each group located at the center of the group between the four center-symmetrically arranged storage transistors, there is a contact hole, so The common line connects the contact hole and thus through the active region to the sources of all the storage transistors in each group.

A fourth aspect of the present invention relates to the use of the above-mentioned storage unit and its memory of the present invention, which are used as a one-time programmable storage unit and a one-time programmable memory, respectively.

The storage unit and its memory of the present invention can reduce the area and cost by optimizing the structure and the arrangement of components, and at the same time improve the programming efficiency, ability and data retention ability, and do not need to adjust the wafer process to meet the memory requirements. Data retention capability.

The single-layer polysilicon memory cell and its memory of the present invention can be manufactured by using a 130nm or 180nm logic process.

101, 101', 201, 201': select transistors

102, 102', 202, 202': storage transistors

203, 203': Capacitor

104, 204: Active area

105, 205: Contact hole

106, 106', 206, 206': source

400, 401, 402: storage unit

SG: Selection gate

WL: word line

BL: bit line

STI: Shallow Trench Region

FG: floating gate

COM:Common line

FIG. 1a shows a top view of a group array including upper and lower groups of memory cells without capacitors according to an embodiment of the present invention.

Figure 1b shows a cross-sectional view taken along section line A-A in Figure 1a.

Figure 2a shows a top view of a memory cell array in the same embodiment as shown in Figure 1a.

Figure 2b shows a cross-sectional view of the structure of the upper bank of memory cells taken along section line B-B in Figure 2a.

FIG. 3 a shows a top view of a group array including upper and lower groups of memory cells with capacitors according to an embodiment of the present invention.

Figure 3b shows a cross-sectional view taken along section line A-A in Figure 3a.

Figure 4a shows a top view of a memory cell array in the same embodiment as shown in Figure 3a.

Figure 4b shows a cross-sectional view of the upper memory cell group structure taken along section line B-B in Figure 4a.

Figure 5 illustrates a bank array comprising 6 banks (2x3) of capacitorless memory cells in one embodiment of the present invention.

FIG. 6 shows the bias signals connected to the array of memory cell groups shown in FIG. 5 during different operations.

Figure 7 illustrates a bank array comprising 6 banks (2 x 3) of memory cells with capacitors in one embodiment of the present invention.

FIG. 8 shows the bias signals connected to the array of memory cell groups shown in FIG. 7 during various operations.

Like numbers in the figures indicate similar elements.

Embodiments of the present invention are described by way of example and are not limited to the examples shown in the figures of the accompanying drawings. It should be understood that the accompanying drawings only illustrate certain embodiments of the present invention, and therefore should not be regarded as limiting the scope. For those skilled in the art, without creative efforts, they can also These figures obtain other related figures.

In the single-layer polysilicon nonvolatile memory cell of the present invention, the selection transistor and the storage transistor are connected in series, and the two are arranged on the substrate in a mutually perpendicular manner. This can increase the distance between the active regions of the two transistors without increasing the area of the memory cell, that is, increase the shallow trench isolation region between the two, effectively separating the two transistors active area. This is especially beneficial for transistor memories, which are shrinking in size. During its preparation and processing, when the source and drain of the active region are formed by ion implantation, the increased spacing between the active regions can ensure that the source and drain of the active regions of the two transistors are fully formed, thereby reducing the cost of the two transistors. The impedance between them improves the programming efficiency during operation and also improves the read current after programming.

In the memory cell structure of the present invention, a capacitor may not be included, or a capacitor may be included. Preferably, a capacitor is included that is formed such that the end of the storage transistor floating gate remote from the select transistor extends in a direction perpendicular to and away from the select transistor, covering a small portion of the substrate surface to form a small capacitor. The floating gate is the upper plate of the capacitor, the substrate is the lower plate of the capacitor, and the gate oxide under the floating gate is the medium between the two plates.

During the programming operation, the capacitor can couple the potential of the substrate to the floating gate of the storage transistor, which is conducive to the faster injection of more hot electrons into the floating gate, improves the programming efficiency, and also improves the programming capability and data retention capability of the memory cell. .

Preferably, the selection transistor and the storage transistor in the memory cell of the present invention are of the same type, and both are PMOS transistors, or both are NMOS transistors.

In the case where the two transistors are of the PMOS type, the substrate is an N-well with a P-substrate below the N-well.

In the case where the two transistors are of the NMOS type, the substrate is a P-well, preferably with a deep N-well below the P-well, on the P-substrate.

The single-layer polysilicon non-volatile memory cell group structure of the present invention includes four of the above-mentioned memory cells of the present invention, which are arranged in a center-symmetric array of 2 rows and 2 columns. The substrates of all memory cells are merged into one; the two memory cells in each row are mirror-symmetrical, two select transistors are arranged on both sides of the group, and the two storage transistors are adjacent to each other in the middle. There is an active region in the center, which is located in the substrate between the two storage transistors; the two storage cells in each column are mirror-symmetrical up and down, and the floating gates of the upper and lower selection transistors are connected up and down to form a whole. The two storage transistors share a source electrode and are sandwiched between the upper and lower storage transistors; the doping type of the active region is the same as that of the common source region, and the active region at the center of the upper and lower rows The upper and lower lines are connected into one, and between the upper and lower rows, it is connected with the common source between the upper and lower storage transistors on the left and right sides.

The four memory cells in the above-mentioned memory cell group may be the same or different. It is preferably identical, including the composition, composition, structure, etc. of each part thereof, and is identical in all aspects.

In the case where the memory cells in the memory cell group contain capacitors, the active region at the center of each row in the group is located between the two capacitors of the left and right memory cells.

All selection transistors and storage transistors in the memory cell group are preferably of the same type. In the case of a PMOS type transistor, the substrate is an N-well, under which there is also a P-substrate, and the active region is a P-doped region. In the case of NMOS-type transistors, the substrate is a P-well, preferably with a deep N-well below the P-well, on the P-substrate.

The memory cell group also includes: a bit line in each row, connected to the drains of the selection transistors of the memory cells in the row; a word line in each column, connected to the selection transistors of the memory cells in the column. The gate of the crystal; there is a common line in the middle of the two columns, connected to the active area between the two storage transistors in the two columns, and connected through the active area to the storage transistors of all memory cells in the group source of the crystal. Active region at the center of the group between the 4 center-symmetrically arranged storage transistors Inside, there is a contact hole to which the common line connects, and thus through the active area, to the sources of all storage transistors in the group.

In the group structure, two columns share one common line, and four storage transistors in the group share one contact hole to communicate with the common line, which helps to reduce the area of the memory cell group, simplifies the processing steps in the preparation process, and reduces the cost .

The single-layer polysilicon non-volatile memory structure of the present invention includes: at least one of the above-mentioned non-volatile memory cell groups of the present invention, forming an array, each group is arranged in the same manner in the array, and the The substrates of the memory cells are merged into one body to form the substrate of the array; wherein the floating gates of the selection transistors at the upper and lower corresponding positions of different groups in each column are connected up and down to form a whole; the upper and lower corresponding positions of different groups in each column are connected up and down. The active regions in the center of the row are connected up and down to form a whole; there is a bit line in each row, which is connected to the drains of the selection transistors of all memory cells in each group in the row; there is a word line in each column , connected to the gates of the selection transistors of all memory cells in each group in the column; there is a common line between the two adjacent columns, which is connected to the gate between the two memory transistors in each group in the column source regions, and are connected to the sources of all storage transistors in each group through the active regions.

Each group in the memory array may be the same or different, and preferably, each group is completely identical, including composition, structure and other aspects.

In the memory array of the present invention, two adjacent columns in each group share one common line, and four storage transistors in each group share one contact hole to communicate with the common line, which helps reduce the area of the array and simplifies the manufacturing process processing steps, reducing costs.

Each non-volatile memory cell in the memory cell group of the present invention and its array can be programmed independently.

The memory cell and its group structure and array structure of the present invention will be described below with reference to the accompanying drawings. Obviously, the specific implementations described in the accompanying drawings are only a part of implementations of the present invention, but not all implementations. Elements of the embodiments of the invention generally described and illustrated in the drawings herein Pieces can be arranged and designed in a variety of different configurations. Accordingly, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the invention as claimed, but is merely representative of selected embodiments of the invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work fall within the protection scope of the present invention.

FIG. 1a shows an array of groups comprising upper and lower two groups of non-capacitance memory cells according to an embodiment of the present invention, and the array of groups in FIG. 2a is the same as that of FIG. 1a. Figure 1b is a cross-sectional view taken along section line A-A in Figure 1a, Figure 2b is a cross-sectional view of the upper group taken along section line B-B in Figure 2a, and the cross-sectional view of the lower group is the same as that of the upper group.

A memory cell in FIG. 1a includes a select transistor 101 and storage transistor 102, both of which are PMOS transistors, located in an N-well substrate. The N-well substrate is on the P-substrate. The select transistor has a floating gate, also called the select gate (SG), which connects to the word line (WL), and the drain of the select transistor connects to the bit line (BL). The selection transistor 101 and the storage transistor 102 are connected in series, and the two are arranged in the N-well in a mutually perpendicular arrangement and spaced apart from each other, and the active regions of the two are separated by a shallow trench region (STI). . The storage transistor 102 has a floating gate (FG).

The group structure of each group of memory cells without capacitors shown in FIG. 1a includes 4 memory cells, which are located in the same N well. The 4 memory cells are arranged in a center-symmetrical array of 2 rows by 2 columns. The four storage units in the group are the same, including the same composition, composition, and structure, but with different arrangement positions and orientations.

Take the above group as an example, the two memory cells in each row are mirror-symmetrical, for example, the two selection transistors 101 and 101' in the first row are arranged on both sides of the upper group, and the two storage transistors 102 and 102' Left and right adjacent to the middle, there is a P-type active region 104 at the center of the first row, located in the N-well substrate between the two storage transistors 102 and 102'.

In this group, the two memory cells in each column are mirror-symmetrical up and down, wherein the floating gates of the upper and lower selection transistors are connected up and down to form a whole, and the upper and lower storage transistors share a source electrode, which is sandwiched between between the upper and lower storage transistors. For example, the upper and lower storage transistors in the first column share one source electrode 106 .

In this group, the P active regions 104 at the center of the upper and lower rows are connected up and down as a whole, and between the upper and lower rows, are connected to the common sources 106 and 106' between the upper and lower storage transistors on the left and right sides.

In this group, there is a contact hole 105 in the active region 104 at the center position of the group between the four center-symmetrically arranged storage transistors, and the common line COM connects the contact hole and passes through the Active region 104 is connected to sources 106 and 106' of all storage transistors in the group.

In each group, there is a bit line (BL) in each row, connected to the drains of the select transistors of the memory cells in the row, and a word line (WL) in each column, connected to the memory cells in the column. The gate of the cell's select transistor.

There is a common line (COM) between two adjacent columns in each group, connected to the active area between the two storage transistors in the group, and connected to the storage of all memory cells in the group through the active area source of the transistor.

The array of memory cell groups shown in FIG. 1a includes: upper and lower two memory cell groups of the present invention, each group in the array is arranged in the same manner, and the substrates of the memory cells in each group are combined into one body, An N-well substrate forming an array; wherein the floating gates of the selection transistors at the upper and lower corresponding positions of the upper and lower groups in each column are connected up and down to form an integral body; the row centers at the upper and lower corresponding positions of the upper and lower groups in each column have The source region is connected up and down to form a whole. There is a bit line (BL) in each row, connected to the drains of the select transistors of all memory cells of each group in the row; and a word line (WL) in each column, connected to all The gate of the select transistor of the memory cell; there is a common line (COM) in the middle of two adjacent columns, connected to the active area between the two memory transistors in the column, and connected to each group through the active area source of all storage transistors in .

In this array, each group is identical, including composition, composition, structure, arrangement, and the like.

Fig. 3a shows an array of groups including upper and lower groups of memory cells with capacitors according to an embodiment of the present invention. The array of groups in Fig. 4a is the same as that of Fig. 3a. Figure 3b is a cross-sectional view taken along section line A-A in Figure 3a, Figure 4b is a cross-sectional view of the upper group taken along section line B-B in Figure 4a, and the cross-sectional view of the lower group is the same as that of the upper group.

A memory cell in FIG. 3a includes a select transistor 201, a storage transistor 202, and a capacitor 203, both of which are PMOS transistors, located in an N-well substrate. The N-well substrate is on the P-substrate. The select transistor has a floating gate, also called the select gate (SG), which connects to the word line (WL), and the drain of the select transistor connects to the bit line (BL). The selection transistor 201 and the storage transistor 202 are connected in series, and the two are arranged in the N-well in a mutually perpendicular arrangement and spaced apart from each other, and the active regions of the two are separated by a shallow trench region (STI). . The storage transistor 202 has a floating gate (FG).

The capacitor 203 and the selection transistor 201 are located on both sides of the storage transistor 202, respectively, and the capacitor is formed such that the floating gate of the storage transistor 202 and its gate oxide end away from the selection transistor 201, along the vertical direction and away from the selection transistor 201. The direction of the transistor extends, covering a portion of the substrate surface, forming a capacitor.

The group structure of each group of memory cells with capacitance shown in FIG. 3a includes 4 memory cells, which are located in the same N well. The 4 memory cells are arranged in a center-symmetrical array of 2 rows by 2 columns. The four storage units in the group are the same, including the same composition, composition, and structure, but with different arrangement positions and orientations.

Take the above group as an example, the two memory cells in each row are mirror-symmetrical on the left and right, for example, the two selection transistors 201 and 201' in the first row are arranged on both sides of the upper group, and the two storage transistors 202 and 202' The left and right neighbors are in the middle, and there is a P-type active region 204 at the center of the first row, which is located in the N-well substrate between the two capacitors 203 and 203'.

In this group, the two memory cells in each column are mirror-symmetrical up and down, wherein the floating gates of the upper and lower selection transistors are connected up and down to form a whole, and the upper and lower storage transistors share a source electrode, which is sandwiched between between the upper and lower storage transistors. For example, the upper and lower storage transistors in the first column share one source electrode 206 .

In this group, the P active regions 204 at the center of the upper and lower rows are connected up and down as a whole, and between the upper and lower rows, are connected to the common sources 206 and 206' between the upper and lower storage transistors on the left and right sides.

In the group, there is a contact hole 205 in the active region 204 located at the center of the group between the four center-symmetrically arranged storage transistors, and the common line COM connects the contact hole and passes through the Active region 204 is connected to sources 206 and 206' of all storage transistors in the group.

In each group, there is a bit line (BL) in each row, connected to the drains of the select transistors of the memory cells in the row, and a word line (WL) in each column, connected to the memory cells in the column. The gate of the cell's select transistor.

There is a common line (COM) between two adjacent columns in each group, connected to the active area between the two storage transistors in the group, and connected to the storage of all memory cells in the group through the active area source of the transistor.

The array of memory cell groups shown in FIG. 3a includes: upper and lower two memory cell groups of the present invention, each group in the array is arranged in the same manner, and the substrates of the memory cells in each group are integrated into one body, An N-well substrate forming an array; wherein the floating gates of the selection transistors at the upper and lower corresponding positions of the upper and lower groups in each column are connected up and down to form an integral body; the row centers at the upper and lower corresponding positions of the upper and lower groups in each column have The source region is connected up and down to form a whole. There is a bit line (BL) in each row, connected to the drains of the select transistors of all memory cells of each group in the row; and a word line (WL) in each column, connected to all The gate of the select transistor of the memory cell; there is a common line (COM) in the middle of two adjacent columns, connected to the active area between the two memory transistors in the column, and connected to each group through the active area source of all storage transistors in .

In this array, each group is identical, including composition, composition, structure, arrangement, etc.

Figure 5 shows an array of the present invention comprising groups of 6 (2x3) capacitorless memory cells. Taking the first group in the array as an example, its operating voltage and its working process are described.

FIG. 6 shows the bias signals connected to the array for the first group of memory cells in the array shown in FIG. 5 during different operations. In Figure 6, Vpp is a positive high voltage, and for a 5v process, Vpp is, for example, 7-8v. Vrd is the operating voltage (positive voltage) at the time of reading, for example, about 2v. Vdd is the supply voltage, eg 5v or 3.3v.

Each memory cell in the group can be programmed independently. During programming, electrons are injected into the floating gate of the selected cell, causing the threshold voltage of the sense transistor to decrease, making it easier to turn on, causing the sense current to increase during the sense operation. During programming, the BL and N wells are driven to high voltage Vpp (eg, 7-8v). The P base is grounded.

In work operation, one memory cell in the bank can be designated for programming.

As shown in FIG. 6, in the working operation, it is assumed that the memory cells 400 in the first group are designated as programming cells and read cells. Memory cell 400 can be programmed to drive WL to 0v, BL to Vpp, COM to 0v, and N-well to Vpp. Since the gate potential WL of the selection transistor in the memory cell 400 is 0, which is lower than the BL potential, the selection transistor is turned on, and the BL is connected to the drain of the storage transistor, resulting in a gap between the source and drain of the storage transistor. A high voltage difference of Vpp is applied, resulting in a high lateral electric field across the channel. This results in the generation of high-energy hot electrons at the drain depletion region. At the same time, the floating gate is coupled to a positive potential by the programming high voltage, and the hot electrons generated by the impact ionization are attracted by the floating gate and injected into the floating gate. Therefore, the number of electrons in the floating gate increases during programming.

The gate WL potential of the selection transistor of the storage unit 401 is the same as the BL potential, both of which are Vpp. The selection transistor cannot be turned on, so a lateral electric field cannot be formed between the source and drain of the storage transistor, and no hot electrons are generated. programming.

The gate WL potential of the selection transistor of the memory cell 402 is 0, which is the same as the BL potential, and the selection transistor is not conducting. And there is no potential difference between the drain and the source of the storage transistor, and a lateral electric field cannot be formed, so it cannot be programmed.

The gate WL potential of the selection transistor of the memory cell 403 is higher than the BL potential, and the selection transistor cannot be turned on. Therefore, a lateral electric field cannot be formed between the source and drain of the storage transistor, and programming cannot be performed.

As shown in FIG. 6 , when the memory cell 400 is designated as a read cell, the gate WL potential of its selection transistor is 0, which is lower than the BL potential Vrd, and the selection transistor is turned on, so that BL is connected to the drain of the storage transistor , there is a potential difference between the source and drain of the storage transistor, forming an electric field. Since the storage transistor in the programmed 400 cells stores a large amount of electrons after programming, the storage transistor is turned on, and a readout current is generated under the action of the channel transverse electric field of the storage transistor.

In the memory cell 401, the gate WL potential of its selection transistor is Vdd, which is higher than the BL potential, and the selection transistor is turned off. Therefore, no BL current is generated in the memory cell 401 .

In the memory cell 402, the gate WL potential of the selection transistor is 0, which is the same as the BL potential, the selection transistor is not turned on, and the storage transistor does not have a lateral electric field at the source and drain terminals.

In the memory cell 403, the gate WL potential of its selection transistor is Vdd, which is higher than the BL potential, and the selection transistor is turned off.

Figure 7 shows an array of the present invention comprising 6 groups (2 x 3) groups of memory cells with capacitors. Figure 8 shows the bias signals connected to the array during different operations for the first group of memory cells in the array shown in Figure 7 . Its programming and reading operations are the same as the above-described group array of capacitorless memory cells. The difference is that when there is a capacitor in the memory cell, in the programming operation, since the N-well substrate is at a high potential, the capacitor is beneficial to couple the floating gate of the storage transistor in the memory cell to the high potential, so that the floating gate can be more efficient during programming. Capture more hot electrons faster, improve programming efficiency, and improve data retention.

101, 101': select transistor

102, 102': storage transistor

104: Active area

COM:Common line

Claims (15)

A single-layer polysilicon non-volatile memory cell structure comprises: a selection transistor and a storage transistor, both of which are located in a substrate, the selection transistor comprising a selection gate, a gate oxide under the selection gate, a source and a drain; the storage transistor includes a floating gate, a gate oxide under the floating gate, a source, and a drain; the select transistor is connected in series with the storage transistor, and the two are connected to each other. arranged on the substrate in a vertical manner. The single-layer polysilicon non-volatile memory cell structure according to claim 1, further comprising a capacitor, which is located on both sides of the storage transistor and the selection transistor, and the capacitor is formed such that all The floating gate of the storage transistor and the end of the gate oxide away from the selection transistor extend in a direction perpendicular to and away from the selection transistor, covering a part of the surface of the substrate to form the capacitor. The single-layer polysilicon nonvolatile memory cell structure according to claim 1 or 2, wherein the selection transistor and the storage transistor are of the same type, and both are PMOS transistors, or both are NMOS transistors . A single-layer polysilicon non-volatile memory cell group structure, which includes 4 memory cells as described in claim 1, arranged in a center-symmetric array of 2 rows×2 columns, and the substrates of all memory cells are combined into one ; The two described storage cells in each row are mirror-symmetrical on the left and right, wherein the two described selection transistors are arranged on both sides of the group, the two described storage transistors are adjacent to each other on the left and right in the middle, and there is one at the center of each row. The active area is located in the substrate between the two storage transistors; the two storage cells in each column are mirror-symmetrical up and down, and the floating gates of the upper and lower selection transistors are connected up and down to form a whole , the upper and lower storage transistors share a source electrode and are sandwiched between the upper and lower storage transistors; The doping type of the active region is the same as the doping type of the common source region sharing one source, and the active regions at the center of the upper and lower rows are connected together up and down, and the upper and lower rows are connected together. is connected to the common source between the upper and lower storage transistors on the left and right sides. According to the single-layer polysilicon nonvolatile memory cell group structure according to claim 4, the composition, composition and structure of the four memory cells in the group are all the same. The single-layer polysilicon non-volatile memory cell group structure according to claim 4 or 5, wherein each of the memory cells further includes a capacitor, and in each of the memory cells, the capacitor is connected to all the memory cells. The selection transistors are respectively located on both sides of the storage transistor, and the capacitor is formed such that the floating gate of the storage transistor and the end of its gate oxide far away from the selection transistor, along the vertical direction and away from the storage transistor The direction of the selection transistor extends to cover a part of the surface of the substrate to form the capacitor; the active area at the center of each row is located between the capacitors of the left and right memory cells. The single-layer polysilicon nonvolatile memory cell group structure as claimed in claim 4 or 5, further comprising: one bit line in each row, connected to the select transistors of each of the memory cells in the row drains; a word line in each column, connected to the gates of the select transistors of each of the memory cells in the column; a common line in the middle of the two columns, connected to the two of the two columns the active region between the storage transistors, and connected to the sources of the storage transistors of all the memory cells in the group through the active region. The single-layer polysilicon nonvolatile memory cell group structure as claimed in claim 6, further comprising: one bit line in each row, connected to the drain of the select transistor of each of the memory cells in the row ; There is a word line in each column, connected to the gates of the select transistors of each of the memory cells in the column; a common line in the middle of the two columns, connected to the two memory transistors in the two columns The active regions are between, and are connected to the sources of the storage transistors of all the memory cells in the group through the active regions. The single-layer polysilicon nonvolatile memory cell group structure according to claim 7, wherein, in the active area at the center of the group between the four center-symmetrically arranged memory transistors, there is a A contact hole to which the common line is connected and thereby connected through the active region to the sources of all the storage transistors in the group. The single-layer polysilicon non-volatile memory cell group structure according to claim 8, wherein, in the active region at the center of the group between the four center-symmetrically arranged memory transistors, there is a A contact hole to which the common line is connected and thereby connected through the active region to the sources of all the storage transistors in the group. A single-layer polysilicon non-volatile memory structure, comprising: at least one single-layer polysilicon non-volatile memory cell group structure as described in any one of claims 4 to 10, forming an array in which the array is The arrangement of each group is the same, and the substrates of the memory cells of the respective groups are combined into one body to form the substrate of the array; wherein the selection transistors at the upper and lower corresponding positions of different groups in each column are The floating gates are connected up and down to form a whole; the active regions in the row centers at the upper and lower corresponding positions of different groups in each column are connected up and down to form a whole; there is a bit line in each row, which is connected to each group in the row the drains of the select transistors of all the memory cells; There is a word line in each column, which is connected to the gates of the select transistors of all the memory cells of each group in the column; there is a common line in the middle of two adjacent columns, which is connected to the gates of the select transistors of each group in the column. The active region between the two storage transistors is connected to the sources of all the storage transistors in each group through the source region. The single-layer polysilicon non-volatile memory structure of claim 11, wherein each of the arrays is identical. The single-layer polysilicon non-volatile memory structure according to claim 11 or 12, wherein, in the array, the center of each group is located between the four center-symmetrically arranged storage transistors In the active region at the location, there is a contact hole to which the common line is connected and thus connected through the active region to the sources of all the storage transistors in each group. A use of a single-layer polysilicon non-volatile memory cell structure as claimed in any one of claims 1 or 2 as a one-time programmable memory cell. A use of a single-layer polysilicon non-volatile memory structure as claimed in any one of claims 11 to 13 as a one-time programmable memory.

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