TWI839849B - Low power multi-time programmable non-volatile memory unit and memory thereof - Google Patents

Abstract

The present invention relates to a multi-time programmable non-volatile memory cell and a memory cell group and a memory. The memory cell comprises: a deep N-well; a first P-well, a second P-well, and an N-well, which are arranged in parallel in the deep N-well, and the two P-wells are separated by the N-well; an NMOS floating gate transistor is arranged in the first P-well, and the floating gate transistor comprises a polysilicon floating gate and a gate oxide thereunder; a capacitor is arranged in the second P-well, and the capacitor comprises one or two N-type coupling regions in the second P-well; the floating gate and the gate oxide of the floating gate transistor in the first P-well are perpendicular to the parallel direction of the P-well and the N-well, and extend across the N-well until covering the capacitor in the second P-well, respectively forming an upper plate and a gate oxide of the capacitor. The programming and erasing operations of the memory unit are both performed through Fuller-Nordheim tunneling, which can significantly reduce power consumption and has high erasing efficiency.

Description

Low power multi-time programmable non-volatile memory unit and memory thereof

The present invention generally relates to electrically erasable and programmable non-volatile memory, and more specifically, to a low-power electrically erasable and programmable non-volatile memory unit.

The data stored in non-volatile memory will not disappear after power failure, and the data can be retained for a long time. Based on this advantage, this type of memory is widely used in electronic devices. In particular, non-volatile memory that is electrically erasable and programmable multiple times can write and erase data multiple times, and is widely used. This type of non-volatile memory is mostly a single-layer polysilicon floating gate type, and programming and erasing are mainly achieved through channel hot electron injection. During programming, channel hot electrons jump to the floating gate, and the current in the channel is large, resulting in high power consumption.

Currently, the industry is in great demand for low-power memory. Therefore, it is necessary to optimize this type of memory to achieve low power consumption.

The present invention provides a low-power, multi-time electrically erasable and programmable non-volatile memory unit and its memory.

The memory cell and memory of the present invention perform programming and erasing operations by Fuller-Nordheim (F-N) tunneling at the gate oxide layer of the tunnel capacitor. Compared with the existing memory cell that is programmed by channel hot electron injection into the floating gate, the generated current is very small (nA level), thereby achieving low power consumption.

The first aspect of the present invention relates to a low-power, multi-time electrically erasable and programmable non-volatile memory cell. It comprises: a deep N-well; a first P-well, a second P-well, and an N-well, which are located in parallel in the deep N-well, and the two P-wells are separated by the N-well; an NMOS floating gate transistor is located in the first P-well, and the floating gate transistor includes a polysilicon floating gate and a gate oxide thereunder; a capacitor is located in the second P-well, and the capacitor includes one or two N-type coupling regions located in the second P-well; the floating gate and the gate oxide of the floating gate transistor in the first P-well extend across the N-well perpendicular to the parallel direction of the P-well and the N-well until covering the capacitor in the second P-well, forming the upper plate and gate oxide of the capacitor respectively.

In a preferred embodiment, the programming and erasing operations of the memory cell are both performed through Fuller-Nordheim tunneling. The programming and erasing operations are performed at the same location, which is a gate oxide layer in a floating gate transistor or a gate oxide layer in a capacitor. Preferably, the operations are performed at a gate oxide layer in a capacitor. In this case, preferably, the area of the top plate in the capacitor is smaller than the area of the floating gate in the floating gate transistor, and the ratio of the area of the floating gate in the floating gate transistor to the area of the top plate in the capacitor is 1.1:1.0 to 50:1.0. More preferably, the thickness of the gate oxide layer in the capacitor is smaller than the thickness of the gate oxide layer in the floating gate transistor, and the ratio of the thickness of the gate oxide layer in the floating gate transistor to the thickness of the gate oxide layer in the capacitor is: 1.1:1.0~5.0:1.0.

In another preferred embodiment, the capacitor in the memory cell is a transistor, comprising two N-type coupling regions located in the second P-well, arranged on both sides of the upper plate.

In another preferred embodiment, the memory cell further includes an NMOS selection transistor located in the first P well and connected in series with the floating gate transistor, wherein the selection transistor includes a selection gate and a gate oxide thereunder. The selection transistor and the floating gate transistor each include a source and a drain. Preferably, the source of the selection transistor and the drain of the floating gate transistor are a common electrode.

The second aspect of the present invention relates to a multi-time programmable non-volatile memory device, constructed on a P-type substrate, the memory device comprising: at least one of the above-mentioned non-volatile memory cells; wherein the deep N-wells of all memory cells are merged into one, located in the P-type substrate; all memory cells are arranged into multiple rows and columns in the same orientation and arrangement, the direction of the column is consistent with the parallel direction of the P-well and the N-well in the memory cell, and the first P-well, the second P-well, and the N-well of the memory cell in each column are merged into one along the direction of the column.

In a preferred embodiment, the non-volatile memory device further comprises: a bit line, a common line, and a control line; wherein the common line is connected to the source of each floating gate transistor in a row of memory cells; the control line is connected to one or two N-type coupling regions of each capacitor in a row of memory cells; when there is no selection transistor in the device, the bit line is connected to the drain of each floating gate transistor in a row of memory cells; when there is a selection transistor in the device, the bit line is connected to the drain of each selection transistor in a row of memory cells, and in this case there is also a word line connected to the gate of each selection transistor in a row of memory cells. More preferably, the control line is connected to two N-type coupling regions of each capacitor in a row of memory cells and the second P well where it is located.

The third aspect of the present invention relates to a multi-time programmable non-volatile memory cell group, which comprises: two of the above-mentioned memory cells, namely: a first memory cell and a second memory cell, wherein the source of the floating gate transistor in the first memory cell and an N-type coupling region of the capacitor are respectively shared with an N-type coupling region of the capacitor and the source of the floating gate transistor in the second memory cell; wherein the deep N-wells of the two cells are merged into one, and the first P-well and the second P-well of the first cell are respectively merged into one with the second P-well and the first P-well of the second cell.

In a preferred embodiment, the first and second memory cells are programmed and erased by Fuller-Nordheim tunneling. Programming and erasing in each cell are performed at one location, and the location of the two cells is the same. Preferably, both are performed at the gate oxide layer in the capacitor.

In another preferred embodiment, in each memory cell, the area of the upper plate in the capacitor is smaller than the area of the floating gate in the floating gate transistor, and the ratio of the area of the floating gate in the floating gate transistor to the area of the upper plate in the capacitor is 1.1:1.0~50:1.0. More preferably, the thickness of the gate oxide layer in the capacitor is also smaller than the thickness of the gate oxide layer in the floating gate transistor, and the ratio of the thickness of the gate oxide layer in the floating gate transistor to the thickness of the gate oxide layer in the capacitor is: 1.1:1.0~5.0:1.0.

In another preferred embodiment, the structure and composition of the first memory unit and the second memory unit are exactly the same.

The fourth aspect of the present invention relates to a multi-time programmable non-volatile memory device, constructed on a P-type substrate, the memory device comprising: at least one of the above-mentioned memory cell groups; wherein the deep N-wells of all memory cell groups are merged into one, located in the P-type substrate; all memory cell groups are arranged into multiple rows and columns in the same orientation and arrangement, the direction of the column is consistent with the parallel direction of the P-well and the N-well in the memory cell, and the two P-wells and the N-well of the memory cell group in each column are merged into one along the direction of the column.

In a preferred embodiment, the nonvolatile memory device further comprises: a bit line, a common line, and a control line; wherein: the common line is connected to the source of the floating gate transistor of the first memory cell in each memory cell group in a column, and one or two N-type coupling regions of the capacitor of the second memory cell; the control line is connected to one or two N-type coupling regions of the capacitor of the first memory cell in each memory cell group in a row, and The source of the floating gate transistor of the second memory cell; when there is no selection transistor in the device, the bit line is connected to the drain of the two floating gate transistors in each memory cell group in a column; when there is a selection transistor in the device, the bit line is connected to the drain of the two selection transistors in each memory cell group in a column, and there is also a word line in this case, connected to the gate of the two selection transistors in each memory cell group in a row. More preferably, the common line is connected to the two N-type coupling regions of the capacitor of the second memory cell in each memory cell group in a column and the P-well in which it is located; the control line is connected to the two N-type coupling regions of the capacitor of the first memory cell in each memory cell group in a row and the P-well in which it is located.

The programming and erasing operations of the memory cell of the present invention are performed through the Fuller-Nordheim (F-N) tunneling in the gate oxide layer in the floating gate transistor or the gate oxide layer in the capacitor. Compared with the multi-programmable memory cell in the prior art that is programmed by injecting channel hot electrons into the floating gate, the present invention is programmed through the Fuller-Nordheim tunneling, and the current generated is very small (nA level), which can greatly reduce power consumption. At the same time, the erasing of the present invention is also performed through the Fuller-Nordheim tunneling, and the erasing efficiency is high.

In addition, the memory cell group of the present invention, which includes two memory cells, can realize that under the same operating conditions, one memory cell is programmed and the other memory cell is erased at the same time. In this way, in the read operation, one memory cell in the group can be read out as a reference cell of the other cell for comparison, which greatly improves the reliability of the read. This is because when a memory cell is read out, it needs to be compared with a reference memory cell, and the current value of the reference memory cell is generally 50% of the programming current value of the memory cell; while in the memory cell group of the present invention, the current value of the memory cell used as a reference cell is its own value. When a memory unit in the group is in a programming state, another memory unit as a reference unit is in an erased state; when the memory unit is in an erased state, another memory unit as a reference unit is in a programming state.

The memory unit group of the present invention contains two memory units and stores 1 bit of data. Compared with a single memory unit storing 1 bit of data, although it is slightly larger in area, it is easy to operate, and the efficiency and read reliability are greatly improved.

100~103: memory unit

200~203: Memory unit group

AA: Active area

PW:P well

NW: N well

DNW: Deep N Well

BL, BL0, BL1, BL2, BL3: bit lines

CL, CL0, CL1: control lines

WL, WL0, WL1: word line

COM,COM0,COM1: public lines

CG: Go up to the pole board

FG: Floating Gate

SG: Select Gate

FOX: Thick Field Oxide

The implementation of the embodiment is illustrated by way of example, but is not limited to the examples shown in the accompanying drawings.

The same reference numerals in the accompanying drawings indicate the same or similar components.

FIG1 shows a top view of a non-volatile memory cell in one embodiment of the present invention.

Figures 2 to 4 respectively show cross-sectional views of the memory unit in the embodiment shown in Figure 1 along section lines a-a, b-b, and c-c.

Figure 5 shows an array of 2 rows × 2 columns composed of the memory cells shown in Figure 1.

Figure 6 shows the bias signals connected to the array shown in Figure 5 during different operations.

FIG7 shows a top view of a memory cell group in one embodiment of the present invention.

FIG8 shows the storage array of the memory cell group shown in FIG7.

Other features of the embodiments of the present invention can be clearly seen from the accompanying drawings and the following detailed description.

In the multi-programmable non-volatile memory cell described in the present invention, there is a conventional active area (AA) in the upper part of the first and second P wells, and the floating gate transistor and the capacitor are respectively located on the active area in each P well. The memory cell and its memory of the present invention are located on a P-type substrate.

The floating gate transistor includes a floating gate, a gate oxide layer under the floating gate, and a source and a drain located in the active area. The gate oxide layer is located above the trench between the source and the drain. The floating gate and the gate oxide layer below it extend from the first P well to the capacitor in the second P well, forming the upper plate of the capacitor and the gate oxide layer below it.

The multi-programmable non-volatile memory cell described in the present invention performs programming and erasing operations through Fuller-Nordheim (F-N) tunneling. Compared with the existing memory cell that is programmed through channel hot electron injection into the floating gate, the generated current is very small (nA level), thereby achieving low power consumption.

In the programming operation, a sufficient voltage difference is applied on both sides of the gate oxide layer at the tunneling site to cause F-N tunneling, and the electrons jump into the floating gate. In the erase operation, a reverse voltage difference is applied on both sides of the gate oxide layer at the tunneling site to cause F-N tunneling in the opposite direction, and the electrons are extracted from the floating gate.

The tunneling of the programming and erasing operations is performed in the same location, which can be the gate oxide layer in the floating gate transistor or the gate oxide layer in the capacitor. They can also be called the tunneling gate oxide layer of the transistor and the tunneling gate oxide layer of the capacitor, respectively.

In order to facilitate the occurrence of F-N tunneling, the gate oxide layer at the tunneling site preferably has a smaller area and/or a thinner thickness.

The area of the gate oxide layer in the floating gate transistor is equal to the area of the floating gate in the floating gate transistor, that is, the product of the length and width of the floating gate in the transistor; the floating gate length is the size of the floating gate in the transistor between the source and drain along the first direction, and the first direction is the direction from the source to the drain of the floating gate transistor; the floating gate width is the size of the floating gate in the normal direction along the first direction on the active area where it is located. The first direction is also the parallel arrangement direction of the P well and the N well.

The area of the gate oxide layer in the capacitor is equal to the area of the upper plate in the capacitor, that is, the product of the dimension of the floating gate extending from the first P-well to the second P-well in the normal direction along the first direction on the active area where the capacitor is located and the dimension along the first direction.

In the case where both the programming and erasing tunneling are performed in the gate oxide layer in the capacitor, preferably, the area of the upper plate in the capacitor is smaller than the area of the floating gate in the floating gate transistor, and the ratio of the area of the floating gate in the floating gate transistor to the area of the upper plate in the capacitor is 1.1:1.0~50:1.0. More preferably, at the same time, the thickness of the gate oxide layer in the capacitor is smaller than the thickness of the gate oxide layer in the floating gate transistor, and the ratio of the thickness of the gate oxide layer in the floating gate transistor to the thickness of the gate oxide layer in the capacitor is 1.1:1.0~5.0:1.0. The ratio of the area of the floating gate in the floating gate transistor to the area of the upper plate in the capacitor is more preferably 3.0:1.0~40:1.0, more preferably 5.0:1.0~30:1.0, and more preferably 7.0:1.0~20:1.0. The ratio of the thickness of the gate oxide layer in the floating gate transistor to the thickness of the gate oxide layer in the capacitor is more preferably 1.5:1.0~4.5:1.0, more preferably 2.0:1.0~4.0:1.0, and more preferably 2.5:1.0~3.5:1.0.

When programming and erasing occur in the gate oxide layer in the floating gate transistor, it is preferred that the area of the top plate in the capacitor is larger than the area of the floating gate in the floating gate transistor. In this case, the ratio of the two areas is preferably 1.1:1.0~50:1.0, more preferably 3.0:1.0~40:1.0, more preferably 5.0:1.0~30:1.0, and more preferably 7.0:1.0~30:1.0. More preferably, at the same time, the thickness of the gate oxide layer in the capacitor is also greater than the thickness of the gate oxide layer in the floating gate transistor. In this case, the thickness ratio of the two is preferably 1.1:1.0~5.0:1.0, more preferably 1.5:1.0~4.5:1.0, more preferably 2.0:1.0~4.0:1.0, and even more preferably 2.5:1.0~3.5:1.0.

The preferred tunneling site for programming and erasing is the gate oxide layer in the capacitor. Because the NMOS floating gate transistor needs to perform a read operation, when tunneling occurs in the gate oxide layer in the NMOS floating gate transistor, the residual electrons trapped in the floating gate oxide layer will affect the read characteristics of its channel. In addition, during the preparation process, it is easier to adjust the area and thickness of the gate oxide layer in the control capacitor than the gate oxide layer in the floating gate transistor.

The capacitor in the memory cell of the present invention preferably includes two N-type coupling regions located in the second P-well, arranged on both sides of the upper plate. In this case, the capacitor is also a transistor.

The memory cell of the present invention also preferably includes an NMOS selection transistor, which is located in the first P well and is connected in series with the floating gate transistor. The selection transistor includes a selection gate and a gate oxide thereunder, and a source and a drain located in the active region, wherein the source and the drain of the floating gate transistor are a common electrode. The presence of the selection transistor can reduce the operational interference of the floating gate transistor, such as read interference.

In the present invention, programming and erasing occur at one location. A voltage difference sufficient to induce F-N tunneling is applied on both sides of the gate oxide layer at the location to achieve tunneling. The voltage difference in the programming operation is equal to or close to that in the erasing operation, but in the opposite direction.

Specifically, for example, in a programming operation, the same potential is applied to the source, drain, and/or the P-well of the floating gate transistor. At the same time, the same potential is also applied to the N-type coupling region of the capacitor and/or the P-well. The potentials applied to the two components (floating gate transistor and capacitor) are opposite to each other. The capacitance of the component (floating gate transistor or capacitor) in which tunneling does not occur in the gate oxide layer is larger than the capacitance of the component in which tunneling occurs, so that the floating gate is coupled to the potential of the same direction from the terminal of the non-tunneling component and/or its P-well. The potential coupled to the floating gate and the potential of the terminal/N-type coupling region of the tunneling element, and/or its P-well, are opposite to each other, and a voltage difference sufficient to induce F-N tunneling is formed on both sides of the gate oxide layer of the tunneling element, inducing tunneling, allowing electrons to jump into the floating gate for programming. The gate oxide area of the non-tunneling element is preferably larger than the gate oxide area of the tunneling element, so that its capacitance is greater than that of the tunneling element.

In the erase operation, the potential applied to the source, drain, and/or the P-well of the floating gate transistor is opposite to that in programming; the potential applied to the N-type coupling region of the capacitor and/or the P-well is also opposite to that in programming. As a result, a reverse voltage difference is formed on both sides of the gate oxide layer of the tunneling element to induce F-N tunneling, and tunneling occurs. This voltage difference is opposite to the voltage difference in programming, thereby extracting electrons from the floating gate for erasure.

At least one of the above-mentioned memory cells of the present invention can be arranged in multiple rows and columns in the same orientation and arrangement, and constructed on a P-type substrate to form a multi-time programmable non-volatile memory device. The direction of the column is consistent with the parallel direction of the P well and the N well in the memory cell, and the row and column are perpendicular to each other.

In the memory device, the deep N-wells of all memory cells are merged into one and located in the P-type substrate. The first P-well, the second P-well, and the N-well of the memory cells in each column are merged into one along the column direction. Each N-well is connected to the deep N-well. The storage array is constructed in the P-type substrate, and the substrate is grounded or 0V.

The non-volatile memory device preferably further comprises: a bit line, a common line, and a control line; wherein the common line is connected to the source of each floating gate transistor in a column of memory cells; the control line is connected to one or two N-type coupling regions of each capacitor in a row of memory cells; when there is no select transistor in the device, the bit line is connected to the drain of each floating gate transistor in a column of memory cells; when there is a select transistor in the device, the bit line is connected to the drain of each select transistor in a column of memory cells, and in this case there is also a word line connected to the gate of each select transistor in a row of memory cells.

To facilitate the occurrence of tunneling, it is more preferred that the control line is connected to the two N-type coupling regions of each capacitor in a row of memory cells and the second P-well in which it is located.

Each memory cell in the array can be erased or programmed independently. Therefore, the storage array can be used to form a large electrically programmable and erasable memory (EEPROM). Alternatively, the storage array can also form a FLASH memory by erasing or programming the cells in the array together.

The present invention also relates to a multi-time programmable non-volatile memory cell group, which comprises: two memory cells of the present invention, namely: a first memory cell and a second memory cell, wherein the source of the floating gate transistor in the first memory cell and an N-type coupling region of the capacitor are respectively shared with an N-type coupling region of the capacitor and the source of the floating gate transistor in the second memory cell; wherein the deep N-wells of the two cells are merged into one, and the first P-well and the second P-well of the first cell are respectively merged into one with the second P-well and the first P-well of the second cell.

Any memory unit in a group can be called the first memory unit. When one memory unit is called the first memory unit, the other memory unit is called the second memory unit.

The first and second memory cells in the group are both programmed and erased via Fuller-Nordheim tunneling. The programming and erasing tunneling in each cell is performed at the same location. The tunneling location can be a gate oxide layer in a floating gate transistor or a gate oxide layer in a capacitor. As described above.

The tunneling sites of the two cells are preferably the same. In this way, since the source of the floating gate transistor in the first cell and an N-type coupling region of the capacitor are shared with an N-type coupling region of the capacitor and the source of the floating gate transistor in the second cell, respectively, it is possible to realize that under the same operating condition, the first memory cell is programmed and the second memory cell is erased at the same time; or under one operating condition, the first memory cell is erased and the second memory cell is programmed at the same time. In this way, in the read operation, a memory cell in the group can be used as a reference cell of another cell for comparative reading, which greatly improves the reliability of the read.

More preferably, the tunneling sites of both memory cells in the group are gate oxide layers within the capacitor.

In this case, in each memory cell in the preferred group, the area of the upper plate in the capacitor is smaller than the area of the floating gate in the floating gate transistor. More preferably, the thickness of the gate oxide layer in the capacitor is also smaller than the thickness of the gate oxide layer in the floating gate transistor.

The range of the ratio of the area of the floating gate in the floating gate transistor to the area of the top plate in the capacitor, and the range of the ratio of the thickness of the gate oxide layer in the floating gate transistor to the thickness of the gate oxide layer in the capacitor, are applicable to the range described above for a single memory cell.

Most preferably, the first memory unit in the group is identical in structure and composition to the second memory unit.

The present invention also relates to a multi-time programmable non-volatile memory device, constructed on a P-type substrate, the memory device comprising: at least one of the above-mentioned memory cell groups; wherein the deep N-wells of all memory cell groups are merged into one, located in the P-type substrate; all memory cell groups are arranged into multiple rows and columns in the same orientation and arrangement, the direction of the column is consistent with the parallel direction of the P-well and the N-well in the memory cell, and the two P-wells and the N-well of the memory cell group in each column are respectively merged into one along the direction of the column.

The nonvolatile memory device preferably further comprises: a bit line, a common line, and a control line; wherein: the common line is connected to the source of the floating gate transistor of the first memory cell in each memory cell group in a column, and one or two N-type coupling regions of the capacitor of the second memory cell; the control line is connected to one or two N-type coupling regions of the capacitor of the first memory cell in each memory cell group in a row, and one or two N-type coupling regions of the capacitor of the second memory cell. The source of the floating gate transistor; when there is no selection transistor in the device, the bit line is connected to the drain of the two floating gate transistors in each memory cell group in a column; when there is a selection transistor in the device, the bit line is connected to the drain of the two selection transistors in each memory cell group in a column, and there is also a word line in this case, connected to the gate of the two selection transistors in each memory cell group in a row. More preferably, the common line is connected to the two N-type coupling regions of the capacitor of the second memory cell in each memory cell group in a column and the P-well in which it is located; the control line is connected to the two N-type coupling regions of the capacitor of the first memory cell in each memory cell group in a row and the P-well in which it is located. This facilitates more effective induction of tunneling.

The memory unit group of the present invention contains two memory units and stores 1 bit of data. Compared with a single memory unit storing 1 bit of data, although it is slightly larger in area, it is easy to operate, and the efficiency and read reliability are greatly improved.

The array of memory cell groups, each of which can be erased or programmed independently. Therefore, the storage array can be used to form a large electrically programmable and erasable memory (EEPROM). Alternatively, the storage array can also form a FLASH memory by erasing or programming the cell groups in the array together.

The memory cell and memory of the present invention can be prepared using conventional mature standard logic processes, such as 180nm, 130nm, or 110nm standard logic processes.

The floating gate area in the floating gate transistor and the upper plate area in the capacitor may be different. The floating gate area in the transistor or the upper plate area in the capacitor depends on the pattern size of the floating gate on the active area where they are located. They can be formed by conventional methods commonly used in the industry. For example, the pattern size of the floating gate on the active area where the transistor or capacitor is located is generated by the corresponding photomask through photolithography and dry etching, and its shape and size are designed and defined in the layout.

The thickness of the floating gate oxide layer in the transistor and the gate oxide layer in the capacitor can also be different, and they are also formed by the common growth method in the industry. For example, in the case where the thickness of the gate oxide layer in the transistor is greater than the thickness of the gate oxide layer in the capacitor, a layer of gate oxide is first grown to a thickness of 1 in the area where the floating gate oxide layer in the transistor and the gate oxide layer in the capacitor are to be generated by thermal oxidation. The thickness 1 is the difference between the thickness of the floating gate oxide layer in the transistor and the gate oxide layer in the capacitor. Then, in the area where the gate oxide layer in the capacitor is to be generated, the generated gate oxide layer is completely removed by wet method; then, a new gate oxide layer is formed in both gate oxide areas by thermal oxidation again to achieve the required thickness of the gate oxide in the capacitor. Similarly, when the thickness of the gate oxide layer in the capacitor is greater than the thickness of the gate oxide layer in the transistor, a gate oxide layer is first formed, the thickness of which is the difference between the thicknesses of the two gate oxide layers, and then the formed gate oxide layer on the area where the gate oxide layer in the transistor is to be formed is removed, and then a gate oxide layer is formed again to achieve the required thickness of the gate oxide layer in the transistor.

The present invention is described in detail below in conjunction with the specific embodiments in the attached figures. The specific examples in the attached figures are only used to illustrate and help understand the technical solution of the present invention, and do not constitute a limitation on the scope of protection of the present invention. Without departing from the purpose and scope of the present invention, ordinary technical personnel can make structural, logical and electrical modifications to the following specific embodiments and apply them to other embodiments. These are all within the scope of protection of the present invention.

In addition, although the embodiments in the accompanying figures provide specific voltage values, it should be understood that these values are not necessarily precise values, but are used to express the general concept of the biasing scheme.

According to a preferred embodiment of the present invention, a non-volatile memory cell is provided, which can perform programming tunneling and erasing tunneling in the gate oxide layer in the capacitor. The floating gate area in the floating gate transistor is larger than the area of the upper plate in the capacitor, and the area ratio of the two is 8:1~10:1. The thickness of the gate oxide layer in the transistor is the same as the thickness of the gate oxide layer in the capacitor, which is the conventional thickness of the gate oxide layer in the transistor. The cell is manufactured using a 130nm logic process.

Figure 1 shows a top view of the non-volatile memory unit. Figures 2 to 4 are cross-sectional views along section lines a-a, b-b, and c-c, respectively.

As can be seen from Figures 1 to 4, the non-volatile memory cell is built on a P-type silicon substrate. A deep N-well (DNW) is set in the P substrate to electrically isolate the memory cell from the substrate. Two P-wells (PW) are separated by an N-well (NW), and three wells are set in parallel in the deep N-well.

There is an active area (AA) on the top of each P-well. An NMOS floating gate transistor is connected in series with an NMOS select transistor and is set on the active area (AA) of one P-well. An NMOS capacitor transistor is set on the active area (AA) of another P-well. The transistor is surrounded by a shallow trench filled with a thick field oxide (FOX). As shown in Figure 4.

FIG2 shows a cross-sectional view of a floating gate transistor and a select transistor along the section line a-a, where the floating gate transistor is connected in series with the select transistor.

As shown in Figures 1 and 2, the floating gate transistor includes a floating gate (FG) and a gate oxide layer below it, located on the active area (AA); it also includes an N-type drain and source, located in the active area (AA). The drain and source each include a lightly doped N region and a heavily doped N+ contact region. The floating gate (FG) is a conductively doped polysilicon gate, placed on top of the gate oxide layer.

The selection transistor includes a selection gate (SG) and a gate oxide layer thereunder, located on the active area (AA); and an N-type drain and source, located in the active area (AA). The drain and source each include a lightly doped N region and a heavily doped N+ contact region, respectively. The source N+ contact region of the selection transistor is shared with the drain N+ contact region of the floating gate transistor. The selection gate is also a polysilicon gate.

As shown in Figures 2 to 4, the floating gate and the select gate are surrounded by a sidewall isolation layer, which is generally formed by silicon nitride or silicon oxide. When forming the N+ or P+ region, the sidewall isolation layer prevents the N+ or P+ implant from entering the lightly doped N region or P region.

Figure 3 shows a cross-sectional view of the capacitor along the section line b-b.

As shown in Figures 1 and 3, the capacitor includes a top plate (CG) and a gate oxide layer underneath it, located on the active area (AA). They are formed by the floating gate of the floating gate transistor and the gate oxide layer underneath it, extending perpendicularly to the P-well and N-well, across the N-well, and extending until it completely covers the active area in the P-well where the capacitor is located.

The length of the capacitor top plate (CG) along the first direction is smaller than the length of the floating gate in the floating gate transistor; and the area where the active area in the P well where the capacitor is located intersects with the capacitor top plate has a size in the normal direction along the first direction that is smaller than the size of other areas of the active area. This makes the top plate area in the capacitor smaller than the floating gate area in the floating gate transistor, which is conducive to tunneling at the gate oxide layer of the capacitor. As shown in Figure 1.

The capacitor also includes two N-type coupling regions located in the active region of the P-well. Each N-type coupling region preferably includes a lightly doped N region and a heavily doped N+ contact region. As shown in FIG3, next to a heavily doped N+ contact region of the capacitor, there is also a P-type P+ contact region, which is connected to the second P-well and is used to control the potential of the second P-well.

As shown in Figures 1 to 3, the drain of the selection transistor is connected to the bit line (BL), and the selection gate (SG) is connected to the word line (WL). The source of the floating gate transistor is connected to the common line (COM). By controlling the selection gate voltage through the word line (WL), the selection transistor can be turned on or off, thereby connecting or separating the floating gate transistor from the bit line (BL). The two N coupling regions (preferably the N+ contact region) of the capacitor are connected to the control line (CL). The P+ contact region next to an N+ contact region of the capacitor is also connected to the control line (CL), which facilitates the application of a potential to the second P well where the capacitor is located. The first P well where the floating gate transistor is located also has a contact region (not shown in the figure), which is connected to the first P well, so as to facilitate the application of a potential to the first P well.

In most applications, multiple non-volatile cells are put together to form a storage array.

For the purpose of illustration, Figures 5 to 6 describe and illustrate a 2×2 storage array composed of the memory cells shown in Figures 1 to 4 and its operation.

The array contains 4 memory cells arranged in 2 rows and 2 columns. The storage array includes memory cells 100, 101, 102, and 103. Arrays of different sizes can be formed by increasing and/or decreasing the number of rows and/or columns.

In one embodiment, the WL and CL of memory cells 100 and 101 are connected to WL0 and CL0, respectively, to form a storage row, and the WL and CL of memory cells 102 and 103 are connected to WL1 and CL1, respectively, to form another storage row. The bit lines (BL) and common lines (COM) of memory cells 100 and 102 are connected to BL0 and COM0, respectively, to form a storage column. Similarly, the bit lines (BL) and common lines (COM) of memory cells 101 and 103 are connected to BL1 and COM1, respectively, to form another storage column.

The first P-well, the second P-well, and the N-well of the memory cells in a storage column are merged into one along the column direction. Thus, each storage column contains two P-wells and one N-well. Each N-well is connected to a deep N-well, and the deep N-wells of all memory cells in the array are merged to form a single deep N-well. The storage array is constructed in a P-type substrate, which is grounded or 0V.

Figure 6 shows the bias voltage of the storage array shown in Figure 5 in different operation modes.

Among them, Vpp is a positive high voltage, and Vnn is a negative high voltage. For I/O memory devices made with 5V process, Vpp is 7 to 8V, Vnn is -7V to -8V, VDD is 5V, and Vrd is 2.5 to 3.3V; for I/O memory devices made with 3.3V process, Vpp is 5 to 6V, Vnn is -5V to -6V, VDD is 3.3V, and Vrd is 1.5 to 2.5V.

Specified memory cells can be programmed or erased individually.

For example, memory cell 100 can be programmed and erased individually. The "programming cell 100" in FIG. 6 is used to indicate that the memory cell 100 can be programmed individually, while other memory cells 101 to 103 cannot be programmed. The memory cell 100 is programmed by driving the COM0 potential to Vpp and the CL0 potential to Vnn. BL0 and WL0 are in a suspended state (the symbol "\" indicates a suspended state).

When the potential of COM0 connected to the source of the driving floating gate transistor is a positive high voltage Vpp, the potential of the first P-well where the floating gate transistor is located is also driven to Vpp through the contact area of the first P-well (not shown in the figure). Since the floating gate area in the floating gate transistor is larger than the upper plate area in the capacitor, the floating gate is coupled to the positive high voltage from the source under the floating gate transistor and the first P-well, and applied to the upper plate of the capacitor in the second P-well. At the same time, when the potential of CL0 connected to the two N+ contact areas of the driving capacitor is a negative high voltage Vnn, the potential of the second P-well is also driven to Vnn through the P+ contact area of the second P-well. As a result, above the gate oxide layer of the capacitor, the upper plate is at a positive high voltage; while below the gate oxide layer, the N+ contact area and the second P well are at a negative high voltage potential Vnn. A strong voltage difference is formed on both sides of the gate oxide layer of the capacitor, causing tunneling, and electrons tunnel to the upper plate of the capacitor for programming.

The source of the floating gate transistor of the memory cell 101 is connected to COM1, whose potential is 0, and the potential of the first P-well where the floating gate transistor is driven is also 0. Although the potential of CL0 connected to the N+ contact area of the capacitor is a negative high voltage Vnn, and the potential of the second P-well where the capacitor is driven is a negative high voltage Vnn, a strong voltage difference that causes tunneling cannot be formed on both sides of the gate oxide layer of the capacitor. Therefore, programming is not possible.

The source of the floating gate transistor of the memory cell 102 is connected to COM0, and the potential is a positive high voltage Vpp. At the same time, the potential of the first P-well where the floating gate transistor is driven is Vpp. However, the potential of CL1 connected to the N+ contact area of the capacitor is 0, and the potential of the second P-well where the capacitor is located is also 0. Therefore, a strong voltage difference that causes tunneling cannot be formed on both sides of the gate oxide layer of the capacitor, and programming cannot be performed.

The source of the floating gate transistor of the memory cell 103 is connected to COM1, whose potential is 0V, and the potential of the first P-well is also 0V. The potential of CL1 connected to the N+ contact area of the capacitor is 0, and the potential of the second P-well is also 0V. A strong voltage difference that causes tunneling cannot be formed on both sides of the gate oxide layer of the capacitor, and programming cannot be performed.

When erasing memory cells 100, 101, 102, and 103, the operating potential values applied are respectively opposite to those during programming.

For example, the potential of COM0 connected to the source of the floating gate transistor of the memory cell 100 is a negative high voltage Vnn, and the potential of CL0 connected to the N+ contact area of the capacitor is a positive high voltage Vpp. The potential of the first P well is the same as the source of the floating gate transistor, and the potential of the second P well is the same as the N+ contact area of the capacitor. As a result, a strong voltage difference in the opposite direction of programming is formed on both sides of the gate oxide layer of the capacitor, resulting in tunneling, and electrons are extracted from the upper plate of the capacitor and tunnel to the second P well.

Memory cells 101, 102, and 103 cannot form a strong voltage difference on both sides of the gate oxide layer of the capacitor that can induce tunneling, and cannot be erased.

In the read operation, for the memory cell 100, its word line WL is driven to VDD, the bit line BL is driven to Vrd, and the selection transistor is turned on. When the memory cell 100 is programmed, there are electrons in the floating gate, which is negative, and the NMOS floating gate transistor cannot be turned on. Therefore, the potential of the bit line BL remains unchanged, and no current is generated between the drain of the selection transistor (connected to BL) and the source of the floating gate transistor (connected to COM). The sensitive amplifier receives 0 current and compares it with the current value of the reference memory cell. After amplification, it outputs a data signal of state "1".

When the memory cell 100 is erased, the electrons in the floating gate are extracted, the floating gate is positive, and the NMOS floating gate transistor is turned on. The selection transistor is also turned on, and a current is generated between the drain of the selection transistor (connected to BL) and the source of the floating gate transistor (connected to COM). The sensitive amplifier receives the current and compares it with the current value of the reference memory cell. After comparison and amplification, it outputs a data signal of state "0".

The bit lines BL and common lines COM of memory cells 101 and 103 are both suspended, and no signal is read. The selection transistor of memory cell 102 is not turned on, and no signal is read.

FIG7 shows a memory cell group, which includes two memory cells shown in FIG1. The source of the floating gate transistor and an N-type coupling region of the capacitor of one of the cells are shared with an N-type coupling region of the capacitor and the source of the floating gate transistor in the other cell respectively; and the deep N-wells of the two cells are merged into one, the first P-well and the second P-well of one cell are merged into one with the second P-well and the first P-well of the other cell respectively, and the N-wells in the two cells are also merged into one.

In the memory unit group shown in Figure 7, the upper memory unit can be called the first memory unit, and the other (lower) memory unit is called the second memory unit.

The structure and composition of the two memory cells in the memory cell group are exactly the same. Including the floating gate area and gate oxide layer thickness in the floating gate transistor, the upper plate area and gate oxide layer thickness in the capacitor, the two cells are the same. Both memory cells are programmed and erased through tunneling at the gate oxide layer in the capacitor.

When one memory cell in a memory cell group is being programmed, another memory cell can be erased at the same time. Therefore, during the read operation, one memory cell in the memory cell group can be used as a reference cell for another memory cell for comparison and reading, thereby improving the reliability of the read operation.

The connection method of the bit line BL, word line WL, common line COM, and control line CL of each memory cell in the memory cell group is the same as that of the single memory cell mentioned above in this article.

FIG8 shows four memory cell groups shown in FIG7, arranged in two rows and two columns. In each memory cell group in FIG8, the left half of the circuit diagram is for the first memory cell, and the right half of the circuit diagram is for the second memory cell.

As can be seen from Figure 8, the source of the floating gate transistor of the first memory cell in each memory cell group, the two N-type coupling regions of the capacitor of the second memory cell and the P+ contact region of the second P well, are all connected to a common line COM; and the two N-type coupling regions of the capacitor of the first memory cell and the P+ contact region of the second P well, and the source of the floating gate transistor of the second memory cell are all connected to a control line CL. The drains of the two selection transistors in each memory cell group are respectively connected to two bit lines BL; the gates of the two selection transistors are connected to a word line WL.

The differential end sensitive amplifier is connected to the two bit lines of each memory cell group. The differential circuit in the amplifier can set the operation of one memory cell (for example, the first memory cell) in each memory cell group as the operation of the corresponding type of the memory cell group, and the operation of the other memory cell as the operation of the reference memory cell. During the programming, erasing, and reading operations, the amplifier receives signals from the two memory cells, compares and amplifies them, and then outputs a signal reflecting the operation of the group.

When the first memory cell in a memory cell group is programmed, electrons jump into the floating gate through tunneling, the NMOS floating gate transistor cannot be turned on, and no current is generated between the drain of the selection transistor (connected to BL) and the source of the floating gate transistor (connected to COM). At the same time, the second memory cell, which serves as the reference memory cell, is erased, the electrons in the floating gate are extracted, the NMOS floating gate transistor is turned on, the selection transistor is also turned on, and a current is generated between the drain of the selection transistor (connected to BL) and the source of the floating gate transistor (connected to COM). The current of the reference memory cell is input into the differential sense amplifier. The amplifier receives and compares the 0 current of the first memory unit and the current value of the second memory unit, and after comparison and amplification, outputs a data signal of state "1".

When the first memory cell in a memory cell group is erased, the electrons in the floating gate are extracted through tunneling, the NMOS floating gate transistor is turned on, the select transistor is also turned on, and a current is generated between the drain of the select transistor (connected to BL) and the source of the floating gate transistor (connected to COM). At the same time, the second memory cell, which serves as the reference memory cell, is programmed, the floating gate transistor is not turned on, and no current is generated between the drain of the select transistor (connected to BL) and the source of the floating gate transistor (connected to COM), and the current value of the reference memory cell is 0. The differential amplifier receives and compares the two currents, and after comparison and amplification, outputs a data signal of state "0".

Taking the 2×2 array shown in FIG8 as an example, the operation process of the array is described. The storage array includes memory cell groups 200, 201, 202, and 203. Arrays of different sizes can be formed by increasing and/or decreasing the number of rows and/or columns.

In one embodiment, the CL and WL of the memory cell groups 200 and 201 are connected to CL0 and WL0, respectively, to form a storage row, and the CL and WL of the memory cell groups 202 and 203 are connected to CL1 and WL1, respectively, to form another storage row. The two bit lines BL and the common line COM of the cell groups 200 and 202 are connected to BL0, BL1, and COM0, respectively, to form a storage column. Similarly, the two bit lines BL and the common line COM of the cell groups 201 and 203 are connected to BL2, BL3, and COM1, respectively, to form another storage column. The differential sense amplifier connects the two bit lines of each memory cell group.

The left half of each memory cell group is the first memory cell, and the right half is the second memory cell. The differential amplifier sets the programming and erasing of the first memory cell in each memory cell group as the programming and erasing operation of the memory cell group, and the operation of the second memory cell is used as the operation of the reference memory cell.

Specified groups of memory cells can be programmed or erased individually.

For example, the memory cell group 200 can be programmed, erased, and read, that is, the first memory cell in the memory cell group 200 can be programmed, erased, and read.

In these operations, the bias voltage settings of the first memory cells in the four memory cell groups 200, 201, 202, and 203 are respectively the same as those of the memory cells 100, 101, 102, and 103 shown in FIG6. The programming, erasing, and reading operations of the first memory cells in these memory cell groups 200, 201, 202, and 203 are also respectively the same as those of the memory cells 100, 101, 102, and 103, as described above. That is, only the first memory cell in the memory cell group 200 can be programmed and erased. The first memory cells in the other memory cell groups 201, 202, and 203 cannot be programmed and erased.

The second memory cell in the memory cell group 200 performs the opposite operation to the first memory cell. That is, when the first memory cell is programmed, the second memory cell is erased; when the first memory cell is erased, the second memory cell is programmed.

In the read operation, the current comparator connects the two bit lines of the two memory cells in the memory cell group 200, receives and compares the current values input from the two memory cells, and outputs the data signal through the sense amplifier.

When the first memory cell of the memory cell group 200 is programmed, electrons jump into the floating gate, the NMOS floating gate transistor cannot be turned on, and no current is generated between the drain of the selection transistor (connected to BL) and the source of the floating gate transistor (connected to COM). At the same time, the second memory cell is erased, the electrons in the floating gate are drawn out, the NMOS floating gate transistor and the selection transistor are turned on, and a current is generated between the drain of the selection transistor (connected to BL) and the source of the floating gate transistor (connected to COM), which is used as the current of the reference memory cell and input into the differential amplifier. The amplifier receives and compares the 0 current of the first memory unit and the current value of the second memory unit, and after comparison and amplification, outputs a data signal of state "1".

When the first memory cell of the memory cell group 200 is erased, the electrons in the floating gate are extracted through tunneling, the NMOS floating gate transistor and the selection transistor are both turned on, and a current is generated between the drain of the selection transistor (connected to BL) and the source of the floating gate transistor (connected to COM). At the same time, the second memory cell, which serves as a reference memory cell, is programmed, the floating gate transistor is not turned on, and no current is generated between the drain of the selection transistor (connected to BL) and the source of the floating gate transistor (connected to COM), and the current value of the reference memory cell is 0. The differential amplifier receives and compares the two currents, and after comparison and amplification, outputs a data signal of state "0".

The other memory unit groups 201, 202, and 203 did not read the signal.

In the read operation, the current value of the reference memory cell of a single memory cell and its array can generally only reach 50% of the programmed current value of the memory cell. In the memory cell group and its array, the second memory cell is used as a reference memory cell, and its output current value is 100% of the programmed current value of the memory cell. Therefore, the read reliability of the memory cell group and its array is greatly improved.

AA: Active area

PW:P well

NW: N well

DNW: Deep N Well

BL: bit line

CL: Control line

WL: Word Line

COM: Public line

CG: Go up to the pole board

FG: Floating Gate

SG: Select Gate

Claims (29)

A multi-time programmable non-volatile memory cell comprises: a deep N-well; a first P-well, a second P-well and an N-well, the three being located in parallel in the deep N-well, and the two P-wells being separated by the N-well; an NMOS-type floating gate transistor located in the first P-well, the floating gate transistor comprising a polysilicon floating gate and a gate oxide layer thereunder; a capacitor located in the second P-well, the capacitor comprising one or two N-type coupling regions located in the second P-well; the floating gate and the gate oxide layer of the floating gate transistor in the first P-well extend across the N-well perpendicular to the parallel direction of the P-well and the N-well until covering the capacitor in the second P-well, forming the upper plate and the gate oxide layer of the capacitor respectively. A multi-time programmable non-volatile memory cell as described in claim 1, wherein the programming and erasing operations of the multi-time programmable non-volatile memory cell are performed through Fuller-Nordheim tunneling. A multi-time programmable non-volatile memory cell as described in claim 2, wherein the programming and erasing operations of the multi-time programmable non-volatile memory cell are performed at one location, which is a gate oxide layer in a floating gate transistor or a gate oxide layer in a capacitor. A multi-programmable non-volatile memory cell as described in claim 3, wherein the programming and erasing operations are performed at the gate oxide layer in the capacitor. A multi-programmable non-volatile memory cell as described in claim 4, wherein the area of the upper plate in the capacitor is smaller than the area of the floating gate in the floating gate transistor, and the ratio of the area of the floating gate in the floating gate transistor to the area of the upper plate in the capacitor is 1.1:1.0~50:1.0. A multi-programmable non-volatile memory cell as described in claim 5, wherein the thickness of the gate oxide layer in the capacitor is less than the thickness of the gate oxide layer in the floating gate transistor; the ratio of the thickness of the gate oxide layer in the floating gate transistor to the thickness of the gate oxide layer in the capacitor is: 1.1:1.0~5.0:1.0. A multi-programmable non-volatile memory cell as described in any one of claims 1 to 6, wherein the capacitor is a transistor comprising two N-type coupling regions located in the second P-well and arranged on both sides of the upper plate. The multi-programmable non-volatile memory cell as described in any one of claims 1 to 6 further includes an NMOS type selection transistor located in the first P well, the selection transistor is connected in series with the floating gate transistor, and the selection transistor includes a selection gate and a gate oxide layer thereunder. A multi-time programmable non-volatile memory device is constructed on a P-type substrate, and the multi-time programmable non-volatile memory device comprises: at least one multi-time programmable non-volatile memory unit as described in any one of claims 1 to 7; wherein the deep N-wells of all multi-time programmable non-volatile memory units are merged into one body and located in the P-type substrate; all multi-time programmable non-volatile memory units are arranged into multiple rows and multiple columns in the same orientation and arrangement, and the direction of the column is consistent with the parallel direction of the P-well and the N-well in the multi-time programmable non-volatile memory unit, and the first P-well, the second P-well, and the N-well of the multi-time programmable non-volatile memory unit in each column are merged into one body along the direction of the column. The multi-time programmable non-volatile memory device as described in claim 9 further comprises: a bit line, a common line, and a control line; wherein: the common line is connected to the source of each floating gate transistor in a multi-time programmable non-volatile memory cell in a column; the control line is connected to one or two N-type coupling regions of each capacitor in a multi-time programmable non-volatile memory cell in a row; wherein, the bit line is connected to the drain of each floating gate transistor in a multi-time programmable non-volatile memory cell in a column. A multi-time programmable non-volatile memory device as described in claim 10, wherein the control line is connected to two N-type coupling regions of each capacitor in a multi-time programmable non-volatile memory unit in a row and the second P-well in which it is located. A multi-time programmable non-volatile memory device is constructed on a P-type substrate, and the multi-time programmable non-volatile memory device comprises: at least one multi-time programmable non-volatile memory unit as described in claim 8; wherein the deep N-wells of all multi-time programmable non-volatile memory units are merged into one body and located in the P-type substrate; all multi-time programmable non-volatile memory units are arranged into multiple rows and multiple columns in the same orientation and arrangement, and the direction of the column is consistent with the parallel direction of the P-well and the N-well in the multi-time programmable non-volatile memory unit, and the first P-well, the second P-well, and the N-well of the multi-time programmable non-volatile memory unit in each column are merged into one body along the direction of the column. The multi-time programmable non-volatile memory device as described in claim 12 further comprises: a bit line, a common line, a word line, and a control line; wherein: the common line is connected to the source of each floating gate transistor in a multi-time programmable non-volatile memory cell in a column; the control line is connected to one or two N-type coupling regions of each capacitor in a row of multi-time programmable non-volatile memory cells; wherein the bit line is connected to the drain of each select transistor in a column of multi-time programmable non-volatile memory cells, and the word line is connected to the gate of each select transistor in a row of multi-time programmable non-volatile memory cells. A multi-time programmable non-volatile memory device as described in claim 13, wherein the control line is connected to two N-type coupling regions of each capacitor in a multi-time programmable non-volatile memory unit in a row and the second P-well in which it is located. A multi-time programmable non-volatile memory cell group, comprising: two multi-time programmable non-volatile memory cells as described in any one of claim items 1 to 7, namely, a first memory cell and a second memory cell; wherein the source of the floating gate transistor in the first memory cell and an N-type coupling region of the capacitor are respectively shared with an N-type coupling region of the capacitor and the source of the floating gate transistor in the second memory cell; wherein the deep N-wells of the first memory cell and the second memory cell are merged into one, and the first P-well and the second P-well of the first memory cell are respectively merged into one with the second P-well and the first P-well of the second memory cell. As described in claim 15, the programming and erasing operations in the first memory cell and the second memory cell are performed at one location, and the location in the first memory cell and the second memory cell is the same, which is the gate oxide layer in the floating gate transistor or the gate oxide layer in the capacitor. A multi-programmable non-volatile memory cell group as described in claim 16, wherein the programming and erasing locations in the first memory cell and the second memory cell are both gate oxide layers in the capacitor. A multi-programmable non-volatile memory cell group as described in claim 17, wherein in each of the first memory cell and the second memory cell, the area of the upper plate in the capacitor is smaller than the area of the floating gate in the floating gate transistor, and the ratio of the area of the floating gate in the floating gate transistor to the area of the upper plate in the capacitor is 1.1:1.0~50:1.0. A multi-programmable non-volatile memory cell set as described in claim 18, wherein in each of the first memory cell and the second memory cell, the thickness of the gate oxide layer in the capacitor is less than the thickness of the gate oxide layer in the floating gate transistor, and the ratio of the thickness of the gate oxide layer in the floating gate transistor to the thickness of the gate oxide layer in the capacitor is: 1.1:1.0~5.0:1.0. A multi-programmable non-volatile memory cell group as described in any one of claims 15 to 19, wherein the structure and composition of the first memory cell and the second memory cell are exactly the same. A multi-time programmable non-volatile memory cell group, comprising: two multi-time programmable non-volatile memory cells as described in claim 8, namely, a first memory cell and a second memory cell; wherein the source of the floating gate transistor in the first memory cell and an N-type coupling region of the capacitor are respectively shared with an N-type coupling region of the capacitor and the source of the floating gate transistor in the second memory cell; wherein the deep N-wells of the first memory cell and the second memory cell are merged into one, and the first P-well and the second P-well of the first memory cell are respectively merged into one with the second P-well and the first P-well of the second memory cell. A multi-programmable non-volatile memory cell group as described in claim 21, wherein the programming and erasing operations in the first memory cell and the second memory cell are performed at one location, and the location in the first memory cell and the second memory cell is the same, which is the gate oxide layer in the floating gate transistor or the gate oxide layer in the capacitor. A multi-programmable non-volatile memory cell group as described in claim 21, wherein the programming and erasing locations in the first memory cell and the second memory cell are both gate oxide layers in the capacitor. A multi-time programmable non-volatile memory device is constructed on a P-type substrate, and the multi-time programmable non-volatile memory device comprises: at least one multi-time programmable non-volatile memory cell group as described in claim 15; wherein: the deep N-wells of all multi-time programmable non-volatile memory cell groups are merged into one body and located in the P-type substrate; All multi-time programmable non-volatile memory cell groups are arranged into multiple rows and multiple columns in the same orientation and arrangement, and the direction of the column is consistent with the parallel direction of the P-well and the N-well in the multi-time programmable non-volatile memory cell, and the two P-wells and the N-wells of the multi-time programmable non-volatile memory cell group in each column are respectively merged into one body along the direction of the column. The multi-time programmable non-volatile memory device as described in claim 24 further comprises: a bit line, a common line, and a control line; wherein: the common line is connected to the source of the floating gate transistor of the first memory cell in each multi-time programmable non-volatile memory cell group in a column, and one or two N-type coupling regions of the capacitor of the second memory cell; the control line is connected to one or two N-type coupling regions of the capacitor of the first memory cell in each multi-time programmable non-volatile memory cell group in a row, and the source of the floating gate transistor of the second memory cell; wherein the bit line is connected to the drain of two floating gate transistors in each multi-time programmable non-volatile memory cell group in a column. A multi-time programmable non-volatile memory device as described in claim 25, wherein: the common line is connected to two N-type coupling regions of the capacitor of the second memory cell in each multi-time programmable non-volatile memory cell group in a column and the P-well in which it is located, and the control line is connected to two N-type coupling regions of the capacitor of the first memory cell in each multi-time programmable non-volatile memory cell group in a row and the P-well in which it is located. A multi-time programmable non-volatile memory device is constructed on a P-type substrate, and the multi-time programmable non-volatile memory device comprises: at least one multi-time programmable non-volatile memory cell group as described in claim 21; wherein: the deep N-wells of all multi-time programmable non-volatile memory cell groups are merged into one body and located in the P-type substrate; all multi-time programmable non-volatile memory cell groups are arranged into multiple rows and multiple columns in the same orientation and arrangement, and the direction of the column is consistent with the parallel direction of the P-well and the N-well in the multi-time programmable non-volatile memory cell. The two P-wells and the N-wells of the multi-time programmable non-volatile memory cell group in each column are merged into one body respectively along the direction of the column. The multi-time programmable non-volatile memory device as described in claim 27 further comprises: a bit line, a common line, a word line, and a control line; wherein: the common line is connected to the source of the floating gate transistor of the first memory cell in each multi-time programmable non-volatile memory cell group in a column, and one or two N-type coupling regions of the capacitor of the second memory cell; the control line is connected to each multi-time programmable non-volatile memory cell group in a row; One or two N-type coupling regions of the capacitor of the first memory cell in the volatile memory cell group, and the source of the floating gate transistor of the second memory cell; wherein the bit line is connected to the drain of the two selection transistors in each multi-time programmable non-volatile memory cell group in a column, and the word line is connected to the gate of the two selection transistors in each multi-time programmable non-volatile memory cell group in a row. A multi-time programmable non-volatile memory device as described in claim 28, wherein: the common line is connected to two N-type coupling regions of the capacitor of the second memory cell in each multi-time programmable non-volatile memory cell group in a column and the P-well in which it is located, and the control line is connected to two N-type coupling regions of the capacitor of the first memory cell in each multi-time programmable non-volatile memory cell group in a row and the P-well in which it is located.