KR102533714B1 - Single-layer polysilicon nonvolatile memory cell and memory including the same - Google Patents

Abstract

The present invention relates to a single-layer polysilicon non-volatile memory cell and its group structure and memory. The memory cell includes a selection transistor and a memory transistor, the selection transistor is connected in series with the memory transistor, and the two are arranged on a substrate perpendicular to each other. The memory cell group includes four memory cells, and is arranged in a centrosymmetric array of 2 rows x 2 columns. The memory includes at least one group of memory cells. The memory cell and its memory are used as a one-time programming memory cell and memory, and have advantages such as a small area, high programming efficiency and high performance, and excellent data holding capacity.

Description

Single-layer polysilicon non-volatile memory cell and its memory

The present invention relates to a single-layer polysilicon non-volatile memory cell and memory therefor, and more particularly to a one-time programmable non-volatile memory cell and memory therefor.

Non-volatile memory has the advantage of not being lost even if power is turned off after storing data, and has the advantage of being able to store data for a long time, and is currently widely used in electronic devices. Among them, the development of single-layer polysilicon non-volatile memory is progressing very rapidly. It has a simple structure, stable performance, and is widely used in various integrated circuits.

Single-layer polysilicon non-volatile memory is divided into programmable memory that can be erased many times and programmable one-time. The memory cell area of the multi-erasable programmable memory is generally large, which cannot meet the large-capacity storage demand and the cost is high. One-time programmable memory has relatively weak programming ability and low data retention ability.

In addition, the design of non-volatile memory continues to evolve in the direction of saving space, and the focus is on reducing size and improving integration.

As a result, the industry continues to demand programmable memories with smaller size, powerful programmability and high data retention capacity.

The present invention relates to a single-layer polysilicon non-volatile memory cell and its memory and memory structure, and more particularly to a one-time programmable memory cell and its memory.

A first aspect of the present invention relates to a single layer polysilicon non-volatile memory cell structure comprising a select transistor and a memory transistor, both located in a substrate. The select transistor includes a select gate, a gate oxide under the select gate, a source, and a drain, and the memory transistor includes a floating gate, a gate oxide under the floating gate, a source, and a drain. The select transistor is connected in series with a memory transistor, and the two are arranged on the substrate in a mutually perpendicular manner.

In a preferred embodiment, the memory cell structure further includes a capacitor, and the capacitor and select transistor are located on opposite sides of the memory transistor, respectively. The capacitor is formed as follows. That is, one end of the memory transistor floating gate and its gate oxide extending away from the selection transistor extends in a direction perpendicular to and away from the selection transistor, covers a part of the substrate surface, and forms a capacitor.

In another preferred embodiment, the select transistors and memory transistors in the memory cell are of the same type, both PMOS transistors or both NMOS transistors. When both transistors are PMOS transistors, the substrate is an N-well and there is further a P substrate below the N-well.

A second aspect of the present invention relates to a single-layer polysilicon non-volatile memory cell group structure comprising four memory cells according to the present invention, arranged in a centrally symmetrical array of two rows by two columns, all memory cells The substrate of is integrally merged. Here, the two memory cells in each row are symmetrical in left and right mirror images, where two select transistors are respectively arranged on both sides of the group, the two memory transistors are adjacent to the middle on the left and right, and the active area is located at the center of each row. is located on the substrate between the two memory transistors, and the two memory cells in each column are symmetrical in a top and bottom mirror image, where the floating gates of the top and bottom two selection transistors are in communication with each other and form an integral body, and the top and bottom two memory transistors form a source shared, sandwiched between the upper and lower two memory transistors, the doping type of the active region is the same as that of the common source region, and the active region at the central point of the upper and lower two rows communicates with the upper and lower sides and is integral, and between the upper and lower two rows It is connected to the common source between the upper and lower memory transistors on both the left and right sides.

In one preferred embodiment, four memory cells in a group of memory cells are completely identical, including the composition, composition and structure of each part, and are identical in each aspect.

In another preferred embodiment, each memory cell in the group of memory cells further includes a capacitor, and the capacitor and the select transistor are located on both sides of the memory transistor, respectively, and in this way is formed as follows. That is, one end of the memory transistor floating gate and its gate oxide extending away from the selection transistor extends in a direction perpendicular to and away from the selection transistor, covers a part of the substrate surface, and forms a capacitor. At the central point of each row, there is an active region located between two capacitors of two left and right memory cells.

In another preferred embodiment, all select transistors and memory transistors in a group of memory cells are of the same type. When the transistor is a PMOS transistor, the substrate is an N-well, there is further a P substrate under the N-well, and the active region is a P-doped region.

In another preferred embodiment, the memory cell group structure includes: a bit line in each row connected to a drain of a select transistor of each memory cell in the row; a word line in each column and connected to a gate of a select transistor of each memory cell among the columns; and a common line connected to an active region between the two memory transistors of the two columns, connected to sources of memory transistors of all memory cells of the group through the active region, and intermediate the two columns.

In a more preferred embodiment, in the memory cell group structure, there is a contact hole in an active region located at a group center point between the four centrally symmetrical memory transistors, and the common line connects the contact hole; Here, it is connected to the sources of all memory transistors of the group through active regions.

A third aspect of the invention relates to a single-layer polysilicon non-volatile memory structure, including the following. That is, at least one nonvolatile memory cell group according to the present invention constitutes one array, each group has the same arrangement method in the array, and the substrates of the memory cells of each group are integrally combined with the substrates of the array. form Here, the upper and lower parts of the floating gates of the selection transistors of the upper and lower corresponding positions of the different groups in each column are connected to each other to form an integral body. The top and bottom of the active region in the center of the row of the top and bottom corresponding position points of different groups in each column are communicated to form an integral body. A bit line in each row is connected to drains of select transistors of all memory cells in each group of rows. A word line in each column is coupled to the gates of select transistors of all memory cells in each group of columns. In the middle of two adjacent columns is a common line, connected to an active region between the two memory transistors of each group of columns, and through the active region to the sources of all memory transistors of each group.

In one preferred embodiment, each group in the memory array is all identical in terms of configuration, structure, arrangement, and the like.

In another preferred embodiment, in the memory array, there is a contact hole in an active region located at a group center point between the four centrally symmetric array memory transistors of each group, and the common line connects the contact hole; Here it is connected to the source of all memory transistors in the group through the active region.

A fourth aspect of the present invention relates to the use of the memory cell and memory thereof according to the present invention, which is used in a one-time programmable memory cell and a one-time programmable memory, respectively.

The memory cell and its memory of the present invention can reduce area and cost through an optimized structure and arrangement of each component, and at the same time improve programming efficiency, capacity, and data holding capacity, and retain data in the memory. There is no need to adjust the chip process to meet capability requirements.

The single-layer polysilicon memory cell and memory thereof of the present invention can be manufactured by employing a 130 nm or 180 nm logic process.

1A is a plan view of a group array including upper and lower groups of memory cells without capacitors according to an embodiment of the present invention.
Fig. 1B is a cross-sectional view taken along the line AA of Fig. 1A.
FIG. 2A is a plan view of a memory cell array in the same embodiment as shown in FIG. 1A.
FIG. 2B is a cross-sectional view of the upper group memory cell group structure taken along the line BB in FIG. 2A.
3A is a plan view of a group array including memory cells having two upper and lower groups of capacitors according to an embodiment of the present invention.
FIG. 3B is a cross-sectional view taken along the line AA of FIG. 3A.
FIG. 4A is a plan view of a memory cell array in the same embodiment as shown in FIG. 3A.
FIG. 4B is a cross-sectional view of the structure of an upper group memory cell group taken along cut line BB in FIG. 4A.
5 illustrates a group array including 6 groups (2x3) of non-capacitor memory cells according to one embodiment of the present invention.
FIG. 6 shows the bias signals coupled to the array in the memory cell group array shown in FIG. 5 for different operating periods.
7 illustrates a group array including memory cells with 6 groups (2x3) of capacitors according to an embodiment of the present invention.
FIG. 8 shows the bias signals coupled to the array in the memory cell group array shown in FIG. 7 for different operating periods.
In the accompanying drawings, like reference numerals denote like elements.
Embodiments of the present invention are described through examples, but are not limited to the examples shown in the accompanying drawings. Since the accompanying drawings show only specific embodiments of the present invention, they should not be regarded as limiting the scope, and those skilled in the art to which the present invention belongs can obtain other related accompanying drawings based on these accompanying drawings without creative efforts. should understand

In the single-layer polysilicon non-volatile memory cell of the present invention, a select transistor and a memory transistor are connected in series, and the two are arranged perpendicular to each other on the substrate. This can widen the gap between the active regions of the two transistors without increasing the area of the memory cell. That is, active regions of the two transistors may be effectively isolated by increasing shallow trench isolation (STI) between the two transistors. This is particularly useful for transistor memories, which are shrinking in size. In the process of manufacturing and processing, when ions are implanted into the source and drain of the active region, the distance between the active regions increases so that both the source and drain of the active regions of the two transistors are sufficiently formed, thereby lowering the impedance between the two transistors and It can improve the programming efficiency, and also improve the read current after programming.

The memory cell structure of the present invention may not include a capacitor or may include a capacitor. Preferably a capacitor is included, which is formed as follows. That is, an end far from the selection transistor of the memory transistor floating gate extends along a direction perpendicular to and far from the selection transistor, covers a part of the surface of the substrate, and forms a small capacitor. The floating gate is the top plate of the capacitor, the substrate is the bottom plate of the capacitor, and the gate oxide under the floating gate is the medium between the two plates.

When programming works, the capacitor couples the potential of the substrate to the floating gate of the memory transistor, allowing more hot electrons to be injected into the floating gate faster, improving programming efficiency and improving the programmability and data retention of the memory cell. do.

The select transistor and the memory transistor of the memory cell of the present invention are preferably of the same type and are either PMOS transistors or NMOS transistors.

If both transistors are of the PMOS type, the substrate is an N-well and there is further a P substrate below the N-well.

If both transistors are of the NMOS type, the substrate is a P-well, below the P-well is a preferably deep N-well, located on the P substrate.

The monolayer polysilicon non-volatile memory cell group structure of the present invention includes four memory cells of the present invention, which are arranged in a centrosymmetric array of 2 rows by 2 columns. Here, the substrates of all memory cells are integrally integrated. The two memory cells in each row are symmetrical in left and right mirror images, where two select transistors are arranged on both sides of the group, the two memory transistors are adjacent in the middle on the left and right, and there is an active area at the center point of each row; It is located on the substrate between two memory transistors. The two memory cells in each column are symmetrical in their upper and lower mirror images, wherein the floating gates of the upper and lower select transistors communicate with each other and form an integral body, the upper and lower two memory transistors share a source, and are sandwiched between the upper and lower two memory transistors. The doping type of the active region is the same as that of the common source region, and the active region at the central point of the upper and lower rows communicates vertically and forms an integral body, and is connected to a common source between upper and lower memory transistors on both left and right sides between the upper and lower rows. do.

Four memory cells of the memory cell group may be the same or different. They are preferably exactly the same, and are completely the same in each aspect, including the composition, components, structure, etc. of each part.

When a memory cell of a memory cell group includes a capacitor, an active region at a center point of each row of the group is located between two capacitors of two left and right memory cells.

All select transistors and memory transistors of a group of memory cells are preferably of the same type. In the case of a PMOS type transistor, the substrate is an N-well, there is further a P substrate under the N-well, and the active region is a P-doped region. In the case of a transistor of the NMOS type, the substrate is a P-well, below the P-well is a preferably deep N-well, located on the P substrate.

The memory cell group structure includes a bit line in each row and connected to a drain of a select transistor of each memory cell in the row; a word line in each column and connected to a gate of a select transistor of each memory cell among the columns; and a common line connected to an active region between the two memory transistors of the two columns, connected to sources of memory transistors of all memory cells of the group through the active region, and intermediate the two columns. There is a contact hole in an active region located at a group center point between the four centrally symmetric arrayed memory transistors, and the common line connects the contact hole, where the source of all memory transistors of the group is through the active region. connected to

Two columns of the group structure share a common line, and four memory transistors of the group share a contact hole communication common line, thereby reducing the area of the memory cell group, simplifying the processing steps in the manufacturing process, and reducing cost. Helpful.

The present invention relates to a single-layer polysilicon non-volatile memory structure, including the following. That is, at least one nonvolatile memory cell group according to the present invention constitutes one array, each group has the same arrangement method in the array, and the substrates of the memory cells of each group are integrally combined with the substrates of the array. form Here, the upper and lower parts of the floating gates of the selection transistors of the upper and lower corresponding positions of the different groups in each column are connected to each other to form an integral body. The top and bottom of the active region in the center of the row of the top and bottom corresponding position points of different groups in each column are communicated to form an integral body. A bit line in each row is connected to drains of select transistors of all memory cells in each group of rows. A word line in each column is connected to the gates of select transistors of all memory cells in each group of columns. In the middle of two adjacent columns is a common line, connected to the active area between the two memory transistors of each group of columns, and through the active area to the sources of all memory transistors in each group.

Each group in the memory array may be the same or different, preferably completely identical, including each aspect of configuration, structure and the like.

In the memory array of the present invention, two adjacent columns in each group share a common line, and four memory transistors in each group share a common contact hole communicating line, thereby reducing the area of the array and simplifying the processing steps in the manufacturing process. and help cut costs.

Each non-volatile memory cell of the memory cell group and array of the present invention is independently programmable.

Hereinafter, a memory cell and its group structure and array structure of the present invention will be described with reference to the accompanying drawings. Specific implementation methods described in the accompanying drawings are only a part, not all implementation methods of the present invention. In general, the components according to the embodiments of the present invention described and shown in the accompanying drawings may be arranged and designed in various configurations. Therefore, the following describes in detail the embodiments of the present invention provided in the accompanying drawings, which do not limit the scope of the present invention for which protection is claimed, but only indicate selective embodiments of the present invention. All other embodiments obtained by a person skilled in the art based on the embodiments of the present application without creative work fall within the protection scope of the present application.

FIG. 1A shows an array of groups including upper and lower groups of memory cells without capacitors according to an embodiment of the present invention, and the group array of FIG. 2A is the same as that of FIG. 1A. Fig. 1B is a cross-sectional view taken along the cut line A-A in Fig. 1A, Fig. 2B is a cross-sectional view of the upper group taken along the cut line B-B in Fig. 2A, and the cross-sectional view of the lower group is the same as that of the upper group.

The memory cell of Figure 1A includes a select transistor 101 and a memory transistor 102, both PMOS transistors and located in an N-well substrate. An N-well substrate is placed on the P substrate. The select transistor has a floating gate, also called a select gate (SG), connects the word line (WL), and connects the drain of the select transistor to the bit line (BL). The selection transistor 101 and the memory transistor 102 are connected in series, and the two are arranged in an N-well in a mutually perpendicular arrangement at intervals, and the active regions of the two are spaced apart by shallow trench isolation (STI). The memory transistor 102 has a floating gate (FG).

The group structure of memory cells without a capacitor in each group shown in FIG. 1A includes four memory cells located in the same N-well. The four memory cells are arranged in a centrosymmetric array of 2 rows by 2 columns. The four memory cells in the group are identical, including composition, components, structures, etc. are completely identical, but the arrangement position and direction are different.

Taking the group as an example, two memory cells in each row are symmetrical in left and right mirror images. For example, the two selection transistors 101 and 101' in the first row are located on both sides of the upper group, the left and right sides of the two memory transistors 102 and 102' are adjacently located in the middle, and the P-type is located at the center of the first row. There is an active region 104 and is located on the N-well substrate between the two memory transistors 102 and 102'.

In each group, the two memory cells in each column are symmetrical in their upper and lower mirror images, where the floating gates of the upper and lower two selection transistors are connected vertically to form an integral body, and the upper and lower two memory transistors share a source and are sandwiched between the upper and lower two memory transistors. . For example, the top and bottom two memory transistors in the first column share one source 106 .

In the above group, the P active region 104 at the central point of the upper and lower rows is integrally connected to the upper and lower rows, and is connected to the common sources 106 and 106' between the upper and lower memory transistors on the left and right sides between the upper and lower rows.

There is a contact hole 105 in the active region 104 located at the center point of the group between the four centrally symmetrical array memory transistors in the group, and a common line (COM) connects the contact hole, where the active Through region 104 it is connected to the sources 106, 106' of all memory transistors of the group.

Each row in each group has a bit line (BL), which is connected to the drain of the select transistor of each memory cell in each row. Each column has a word line (WL), which is connected to the gate of the select transistor of each memory cell in each column.

Between two adjacent columns of each group is a common line (COM), which connects to the active area between the two memory transistors of the group and through the active area to the source of the memory transistor of every memory cell in the group.

The array of memory cell groups shown in FIG. 1A includes upper and lower two memory cell groups according to the present invention, each group of the array has the same arrangement method, and the substrates of the memory cells of each group are integrated into the array. to form an N-well substrate. Here, the floating gates of the selection transistors of the upper and lower corresponding positions of the upper and lower groups of each column are communicated vertically to form an integral body. The active regions of the row zoom cores of the upper and lower corresponding positions of the upper and lower groups of each column are communicated vertically to form an integral body. Each row has a bit line (BL), which is connected to the drains of select transistors of all memory cells in each group of each row. Each column has a word line (WL), which is connected to the gates of select transistors of all memory cells in each group of each column. In the middle of two adjacent columns is a common line (COM), which is connected to the active area between two memory transistors of the columns and through the active area to the sources of all memory transistors in each group.

Each group in the array is identical and is completely identical including composition, composition, structure, arrangement, and the like.

FIG. 3A shows a group array including memory cells having two upper and lower groups of capacitors according to an embodiment of the present invention, and the group array of FIG. 4A is the same as that of FIG. 3A. Fig. 3b is a cross-sectional view taken along the cut line A-A in Fig. 3a, and Fig. 4b is a cross-sectional view of the upper group taken along the cut line B-B in Fig. 4a, and the cross-sectional view of the lower group is the same as that of the upper group.

The memory cell of FIG. 3A includes a select transistor 201 and a memory transistor 202 and a capacitor 203, both of which are PMOS transistors and are located in an N-well substrate. An N-well substrate is placed on the P substrate. The select transistor has a floating gate, also called a select gate (SG), connects the word line (WL), and connects the drain of the select transistor to the bit line (BL). The selection transistor 201 and the memory transistor 202 are connected in series, and the two are arranged in an N-well in a mutually perpendicular arrangement at intervals, and the active regions of the two are spaced apart by shallow trench isolation (STI). The memory transistor 202 has a floating gate (FG).

A capacitor 203 and a selection transistor 201 are located on both sides of the memory transistor 202, respectively, and the capacitor is formed as follows. That is, the ends far from the selection transistor 201 of the floating gate and gate oxide of the memory transistor 202 extend along a direction perpendicular to and far from the selection transistor, and cover a portion of the substrate surface to form a capacitor.

The group structure of memory cells with each group of capacitors shown in FIG. 3A includes four memory cells located in the same N-well. The four memory cells are arranged in a centrosymmetric array of 2 rows by 2 columns. The four memory cells in the group are identical, including composition, components, structures, etc. are completely identical, but the arrangement position and direction are different.

Taking the group as an example, two memory cells in each row are symmetrical in left and right mirror images. For example, the two selection transistors 201 and 201' in the first row are located on both sides of the upper group, the left and right sides of the two memory transistors 202 and 202' are adjacently located in the middle, and the P-type is located at the center of the first row. There is an active region 204 and is located on the N-well substrate between the two capacitors 203 and 203'.

In each group, the two memory cells in each column are symmetrical in their upper and lower mirror images, where the floating gates of the upper and lower two selection transistors are connected vertically to form an integral body, and the upper and lower two memory transistors share a source and are sandwiched between the upper and lower two memory transistors. . For example, the top and bottom two memory transistors in the first column share one source 206 .

In the above group, the P active region 204 at the central point of the upper and lower rows is integrally connected to the upper and lower rows, and is connected to the common source 206, 206' between the upper and lower memory transistors on the left and right sides between the upper and lower rows.

There is a contact hole 205 in the active region 204 located at the center point of the group between the four centrally symmetrical array memory transistors in the group, and a common line (COM) connects the contact hole, where the active Connected through region 204 to the sources 206, 206' of all memory transistors of the group.

Each row in each group has a bit line (BL), which is connected to the drain of the select transistor of each memory cell in each row. Each column has a word line (WL), which is connected to the gate of the select transistor of each memory cell in each column.

Between two adjacent columns of each group is a common line (COM), which connects to the active area between the two memory transistors of the group and through the active area to the source of the memory transistor of every memory cell in the group.

The array of memory cell groups shown in FIG. 3A includes upper and lower two memory cell groups according to the present invention, each group of the array is arranged in the same way, and the substrates of the memory cells of each group are integrated into the array. to form an N-well substrate. Here, the floating gates of the selection transistors of the upper and lower corresponding positions of the upper and lower groups of each column are communicated vertically to form an integral body. The active regions at the center of the row of the upper and lower corresponding positions of the upper and lower groups of each column are communicated vertically to form an integral body. Each row has a bit line (BL), which is connected to the drains of select transistors of all memory cells in each group of each row. Each column has a word line (WL), which is connected to the gates of select transistors of all memory cells in each group of each column. In the middle of two adjacent columns is a common line (COM), which is connected to the active area between two memory transistors of the columns and through the active area to the sources of all memory transistors in each group.

Each group in the array is completely identical, including composition, composition, structure, arrangement, and the like.

Figure 5 shows a group array comprising six groups (2x3) of capacitorless memory cells according to the present invention. The first group of the array will be described as an example of an operating voltage and its operation process.

FIG. 6 shows the bias signals coupled to the array in a first memory cell group array of the array shown in FIG. 5 for different operating periods. In FIG. 6, Vpp is a positive high voltage, and in the case of a 5v process, Vpp is, for example, 7-8v. Vrd is the operating voltage (constant voltage) at the time of reading, for example about 2v. Vdd is the supply voltage, for example 5v or 3.3v.

Each memory cell in the group is independently programmable. During programming, electrons are injected into the floating gate of the selected cell, reducing the threshold voltage of the read transistor to facilitate turn-on, thereby increasing the read current during operation. During programming, the BL and N-well are driven with high voltage Vpp (eg 7-8v). The P board is grounded.

In a working operation, memory cells in a group can be designated to be used for programming.

As shown in FIG. 6 , it is assumed that the first group of memory cells 400 are designated as programming cells and read cells in the work operation. The memory cell 400 can be programmed such as driving WL to 0v, BL to Vpp, COM to 0v, and N-well to Vpp. Since the gate potential (WL) of the selection transistor of the memory cell 400 is 0 lower than the BL potential, the selection transistor is turned on, and the BL is connected to the drain of the memory transistor, so that Vpp is applied between the source and drain of the memory transistor, and a high voltage The difference is generated, resulting in a high transverse electric field penetrating the channel. Therefore, high-energy hot electrons are generated in the drain depletion region. At the same time, the floating gate is programmed and connected to a positive potential, and hot electrons generated by collisional ionization are attracted to the floating gate and injected into the floating gate. Therefore, the number of electrons in the floating gate increases during programming.

Since the gate WL potentials of the select transistors of the memory cell 401 are all Vpp, the same as the BL potentials, and the select transistors cannot be turned on, a horizontal electric field cannot be formed between the source and drain of the memory transistors, so hot electrons are not generated. and programming cannot be performed.

The gate WL potential of the select transistor of the memory cell 402 is 0 equal to the BL potential, and the select transistor is not turned on. Programming cannot be performed because there is no potential difference between the drain and source of the memory transistor and no transversal electric field can be formed.

Since the gate WL potential of the selection transistor of the memory cell 403 is higher than the BL potential and the selection transistor cannot be turned on, a horizontal electric field cannot be formed between the source and drain of the memory transistor either, so that programming cannot be performed.

As shown in Fig. 6, when the memory cell 400 is designated as a read cell, the gate WL potential of the select transistor is 0 lower than the BL potential Vrd, the select transistor is turned on, the BL is connected to the drain of the memory transistor, and the memory There is a potential difference between the source and drain of the transistor and an electric field is formed. Since the memory transistors among the programmed 400 cells store a large amount of electrons after programming, the memory transistors are turned on and a read current is generated due to the cross-electrical field action of the memory transistors.

In the memory cell 401, the gate WL potential of the select transistor is Vdd higher than the BL potential, and the select transistor is turned off. Therefore, no BL current is generated in the memory cell 401 .

In the memory cell 402, the gate WL potential of the selection transistor is 0, which is the same as the BL potential, the selection transistor is not turned on, and no transverse electric field exists between the source and drain terminals of the memory transistor.

In the memory cell 403, the gate WL potential of the select transistor is Vdd higher than the BL potential, and the select transistor is turned off.

7 shows a group array including memory cells with 6 groups (2x3) of capacitors according to an example of the present invention. FIG. 8 shows bias signals coupled to the array in a first memory cell group array of the arrays shown in FIG. 7 for different operating periods. The programming operation and read operation are identical to the group array of memory cells without the capacitor. The difference is that in the programming operation, when there is a capacitor in the memory cell, because the N-well substrate is high potential, it is advantageous for the capacitor to connect the floating gate of the memory transistor in the memory cell to a high potential, so during programming, the floating gate is faster and more hot electrons. , which increases programming efficiency and improves data retention.

Claims (13)

In a single-layer polysilicon non-volatile memory cell structure,
a select transistor and a memory transistor are included, both located on a substrate, the select transistor comprising a select gate, a gate oxide under the select gate, a source and a drain; The memory transistor includes a floating gate, a gate oxide under the floating gate, a source and a drain; The single-layer polysilicon non-volatile memory cell structure of claim 1 , wherein the select transistor is connected in series with a memory transistor, and the two are arranged on the substrate in a mutually perpendicular manner. According to claim 1,
Further comprising a capacitor, wherein the capacitor and the select transistor are located on both sides of the memory transistor, respectively, and the capacitor is formed as follows, wherein the memory transistor floating gate and one end far from the select transistor of the gate oxide are perpendicular to the select transistor A memory cell structure extending along a distal direction, covering a portion of a substrate surface and forming a capacitor. According to claim 1 or 2,
The memory cell structure of claim 1 , wherein the select transistor and the memory transistor are of the same type, both PMOS transistors and NMOS transistors. In the single-layer polysilicon non-volatile memory cell group structure,
Four memory cells of claim 1 are included, arranged in a centrosymmetric array of 2 rows by 2 columns, and the substrates of all the memory cells are integrally integrated;
The two memory cells in each row are symmetrical in left and right mirror images, where two select transistors are respectively arranged on both sides of the group, the two memory transistors are adjacent to the middle on the left and right, and the active area is at the center of each row. , located on the substrate between the two memory transistors;
The two memory cells in each column are symmetrical in their upper and lower mirror images, wherein the floating gates of the upper and lower two selection transistors are integrally communicated with each other, and the upper and lower two memory transistors share a source and are sandwiched between the upper and lower two memory transistors;
The doping type of the active region is the same as that of the common source region, and the active region at the central point of the upper and lower rows communicates vertically and forms an integral body, and is connected to a common source between upper and lower memory transistors on both left and right sides between the upper and lower rows. memory cell group structure. According to claim 4,
A memory cell group structure in which all four memory cells in the group have the same composition, composition, and structure. According to claim 4 or 5,
Each of the memory cells further includes a capacitor, and in each memory cell, the capacitor and the select transistor are located on both sides of the memory transistor, and the capacitor has a memory transistor floating gate and one end far from the select transistor of the gate oxide, extending along a direction perpendicular to and distal to the selection transistor and covering a portion of the surface of the substrate to form a capacitor; The memory cell group structure of claim 1, wherein the active region of each row center point is located between two capacitors of two left and right memory cells. According to claim 4,
a bit line in each row and connected to a drain of a select transistor of each memory cell among the rows;
a word line in each column and connected to a gate of a select transistor of each memory cell among the columns; and
and a common line connected to an active region between the two memory transistors of the two columns, connected to sources of memory transistors of all memory cells of the group through the active region, and a common line intermediate the two columns. According to claim 7,
There is a contact hole in an active region located at a group center point between the four centrally symmetric array memory transistors, and the common line connects the contact hole, where it is connected to the sources of all memory transistors in the group through the active region. memory cell group structure. In a single-layer polysilicon non-volatile memory structure,
the group of non-volatile memory cells of claim 4 constituting at least one array is included, each group of the array is arranged in the same way, and the substrates of the memory cells of each group are integrally combined to form a substrate of the array;
Here, the floating gates of the selection transistors of the upper and lower corresponding position points of different groups in each column are connected vertically to form an integral body; the active regions at the center of the row of the upper and lower corresponding position points of different groups in each column communicate with each other to form an integral body;
a bit line in each row and connected to drains of select transistors of all memory cells in each group of the rows;
word lines in each column and connected to gates of select transistors of all memory cells in each group of the columns;
a single-layer polysilicon non-volatile memory comprising a common line coupled to an active region between the two memory transistors of each group of the columns and coupled to sources of all memory transistors of each group through the active region and intermediate to two adjacent columns; structure. According to claim 9,
Each group in the array has the same memory structure. The method of claim 9 or 10,
In the array, there is a contact hole in an active region located at a group center point between the four centrally symmetrical array memory transistors of each group, and the common line connects the contact hole, wherein the common line connects the contact hole in each group through the active region. A memory structure connected to all memory transistor sources. Use of the single-layer polysilicon non-volatile memory cell of claim 1 or 2 used in a one-time programmable memory cell. Use of the single-layer polysilicon non-volatile memory of claim 9 or 10 in a one-time programmable memory.

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