TWI759022B - Semiconductor devices and methods for forming the same - Google Patents

Abstract

The present disclosure relates to a semiconductor device including first and second terminals formed on a fin region and a seal layer formed between the first and second terminals. The seal layer includes a silicon carbide material doped with oxygen. The semiconductor device also includes an air gap surrounded by the seal layer, the fin region, and the first and second terminals.

Description

Semiconductor device and method of forming the same

Embodiments of the invention relate to semiconductor technology, and more particularly, to semiconductor devices and methods of forming the same.

The integrated circuit (IC) industry has experienced rapid growth. Technological advances in integrated circuit materials and design have produced generations of integrated circuits, each generation having smaller and more complex circuits than the previous generation. In the history of integrated circuits, functional density (ie, the number of devices interconnected per wafer area) has increased while geometry size (ie, the smallest component or line produced during fabrication) has shrunk. This process of device size miniaturization provides the benefits of increased production efficiency and reduced associated costs.

In some embodiments, a semiconductor device is provided, the semiconductor device includes a first terminal and a second terminal formed on the fin region; a sealing layer formed between the first terminal and the second terminal; and a spacer between the first terminal and the second terminal on the fin region; a contact etch stop layer on the second terminal; and an air gap surrounded by the sealing layer, the spacers, and the contact etch stop layer.

In some other embodiments, a semiconductor device is provided, the semiconductor device includes a gate structure on the fin region, the gate structure includes a gate electrode; and a self-aligned contact formed on the gate electrode; source/drain contact; contact etch stop layer, contacting source/drain contacts; sealing layer, comprising a first portion, located between the gate structure and the source/drain contact; and a second portion, located at the self-aligned contact and the top surfaces of the source/drain contacts; spacers, on the fin regions; and air gaps, surrounded by a sealing layer, spacers, and contact etch stop layers.

In other embodiments, a method of forming a semiconductor device is provided, the method comprising forming an opening over a top surface of a substrate and between a first terminal and a second terminal of the semiconductor device; and forming an opening in the opening and the first terminal and the second terminal depositing silicon carbide material between the terminals, wherein an air gap is enclosed by an opening surrounded by the silicon carbide material, the first and second terminals, and the substrate; performing an oxygen annealing process on the silicon carbide material; and A dielectric layer is deposited on the top surface of the second terminal.

It is to be understood that the following disclosure provides many different embodiments or examples for implementing different components of the provided subject matter. Specific examples of various components and their arrangements are described below in order to simplify the description of the disclosure. Of course, these are only examples and are not intended to limit the present invention. For example, the following disclosure describes that a first part is formed on or over a second part, which means that it includes embodiments in which the formed first part and the second part are in direct contact, and also includes For example, an additional component may be formed between the first component and the second component, and the first component and the second component may not be in direct contact with each other. In addition, different examples in the disclosure may use repeated reference symbols and/or words. These repeated symbols or words are used for the purpose of simplicity and clarity, and are not used to limit the relationship between the various embodiments and/or the appearance structures.

Furthermore, for convenience in describing the relationship of one element or component to another (plural) element or (plural) component in the drawings, spatially relative terms such as "under", "under", "under" may be used. ”, “above”, “upper” and similar terms. In addition to the orientation depicted in the drawings, spatially relative terms also encompass different orientations of the device in use or operation. The device may also be otherwise oriented (eg, rotated 90 degrees or at other orientations) and the description of the spatially relative terms used interpreted accordingly.

As used herein, the term "nominal" refers to expected or target values for characteristics or parameters of component or process operation set during the design phase of a product or process, as well as ranges of values above and/or below expected values. Values generally range for slight variations due to manufacturing processes or tolerances.

As used herein, the terms "about" and "approximately" refer to a numerical value by a given amount that may vary depending on the particular technology node associated with the host semiconductor device. In some embodiments, the terms "about", "approximately" may refer to, for example, within 5% of the target value (eg, ±1%, ±2%, ±3%, ±4%, ±4%, ±5%) variation of the given value.

Fins can be patterned by any suitable method. For example, fins can be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. In general, double-patterning or multi-patterning processes combine photolithography and self-alignment processes to create patterns with smaller pitches that, for example, have a Patterns with smaller spacing. For example, in one embodiment, a sacrificial layer is formed over the substrate and patterned by using a photolithography process. Spacers are formed beside the patterned sacrificial layer by using a self-aligned process. Next, the sacrificial layer is removed, and the fins can then be patterned using the remaining spacers.

As planar semiconductor devices, such as metal-oxide-semiconductor field effect transistors (MOSFETs), scale through various technology nodes, other approaches to increasing device density and speed have been proposed. One approach is the fin field effect transistor (finFET) of a three-dimensional field effect transistor that includes the formation of fin channels extending from a substrate. FinFETs are compatible with conventional complementary metal-oxide-semiconductor (CMOS) processes, and the three-dimensional structure of FinFETs enables them to be aggressively scaled while maintaining gate control and Alleviate the short channel effect. Gate stacks are used in planar and three-dimensional field effect transistors to control the conductivity of semiconductor devices. A gate stack including a gate dielectric layer and a gate electrode in a finFET can be formed by a replacement gate process, in which a polysilicon sacrificial gate structure is replaced with a metal gate structure. A gate dielectric layer (eg, a dielectric layer having a dielectric constant greater than about 3.9) is formed between the channel and the gate electrode. Spacers may be disposed on the sidewalls of the gate stack to protect the gate structures during fabrication processes such as ion implantation, gate replacement processes, epitaxial source/drain structure formation, and other suitable processes. Air gaps can be used to replace spacers to lower the effective dielectric constant, which in turn can reduce parasitic capacitance and improve device performance. Air gaps may enclose air between the terminals by depositing a sealing material over the openings between the terminals of the semiconductor device. The sealing material or the sealing layer can serve as the structure of the cover layer to close the opening. Since the dielectric constant of air is generally lower than that of dielectric materials, the effective dielectric constant can be lowered. However, low compliance and low corrosion resistance in encapsulation materials can lead to defects in semiconductor devices. For example, fabrication processes for forming interconnect structures, such as vias for metal source/drain and gate terminals of finFET devices, may involve multiple etching and cleaning processes for the terminals , these etching and cleaning processes can etch through a portion of the encapsulant through the crevice and cause damage to the air gap. Examples of damage may include collapse of the sealing material or trapping chemical solutions in air gaps. Additionally, gaps in the sealing material can also lead to physical failures and electrical shorts. Damaged air gaps can lead to defects in semiconductor devices and lead to low device yields and even device failures.

To address the above disadvantages, the present disclosure provides a semiconductor device and a method of fabricating the same to provide a simple and cost-effective structure and process for producing a high rigidity sealing layer in a semiconductor device. The sealing layer can be used to seal openings and form air gaps between terminals of the semiconductor device, and can be used as a contact etch stop layer (CESL) for subsequent formation of structures such as interconnect structures. In particular, a high-rigidity sealing layer can be used as the sealing material. For example, highly rigid silicon carbide doped with oxygen (HRSCO) can be used as the sealing material. High rigidity silicon carbide doped with oxygen can also be formed as an etch stop layer. In addition, oxygen-doped high-rigidity silicon carbide layers can also be formed between terminals of semiconductor devices and used as self-aligned contacts (SACs). For example, high rigidity sealing layers may also be formed on terminals of semiconductor devices. The terminals may include source terminals, drain terminals, gate terminals, and/or other suitable structures.

In some embodiments, the high rigidity sealing layer may be formed through a deposition process followed by a processing process. For example, a silicon carbide layer can be deposited, followed by an oxygen annealing process to increase the oxygen content in the deposited layer. Various deposition parameters can be varied to tune the film density, with greater densities providing greater stiffness. A high rigidity sealing layer may be deposited in the openings between the sidewalls of the semiconductor device terminals. The high-rigidity sealing layer may be deposited on the sidewalls of the opening toward the top of the opening, and the deposition process may continue until the high-rigidity sealing materials on the two sidewalls merge to physically contact and form a closed space between the two sidewalls.

In some embodiments, increasing the density of the high rigidity sealing layer may provide greater etch resistance. In some embodiments, reducing the deposition rate of the high rigidity sealing layer can improve the uniformity (eg, uniform thickness) of the film. In some embodiments, the high rigidity sealing layer can be deposited by using a suitable deposition process using suitable precursors such as tetramethyldisiloxane (TSMDSO), hydrogen, oxygen and any other suitable precursor.

In some embodiments, the high-rigidity sealing layer is a double-layered sealing material, and the double-layered sealing material can be formed by depositing a first sealing material, depositing a second sealing material, and performing at least one processing process on the deposited first and second sealing materials to form. The processing sequence is performed after the deposition of the first encapsulation material, after the deposition of the second encapsulation material, or after the deposition of both. The first and second sealing materials may be dielectric materials. A first sealing material is deposited on a portion of both sidewalls of the opening toward the top of the opening, and a second sealing material is deposited on the first sealing material and on exposed surfaces in the opening. The second sealing material is deposited on the first sealing material on both sidewalls. The deposition process of the second sealing material continues until the second sealing materials on the two sidewalls are combined to form a closed space between the two sidewalls. The deposited first and second encapsulant materials may be processed to remove gaps at least through expansion of the second encapsulant material. In some embodiments, the treatment process may be an annealing process performed in an oxygen environment. In some embodiments, the deposition rate of the first sealing material is greater than the deposition rate of the second sealing material. In some embodiments, the first and second encapsulation materials may be formed by using precursors such as tetramethyldisiloxane (TSMDSO), hydrogen, oxygen, and any other suitable precursors.

FIG. 1 is an isometric view of an exemplary fin field effect transistors (finFETs) structure. Figures 2-7 provide various exemplary semiconductor structures and fabrication processes showing the formation of multi-spacer structures with air gaps and high rigidity encapsulation materials in accordance with some embodiments. 8-16 provide various structures and fabrication processes for forming air gaps, encapsulation materials, contact etch stop layers, and other structures of semiconductor devices. The encapsulant and contact etch stop layer can be formed by using a high rigidity encapsulant that provides greater etch resistance, improved uniformity, and less leakage current. In some embodiments, the high stiffness material may be an oxygen doped high stiffness silicon carbide material. The fabrication processes provided herein are exemplary, and alternative processes may be performed in accordance with the present disclosure (although these processes are not shown in the drawings).

FIG. 1 is an isometric view of a semiconductor structure in accordance with some embodiments. FinFET 100 may be included in a microprocessor, memory cell, or other integrated circuit. The finFET 100 shown in FIG. 1 is for display purposes and may not be drawn to scale. FinFET 100 may include other suitable structures, such as additional spacers, liner layers, contact structures, and FIG. 1 does not show any other suitable structures for clarity.

The fin field effect transistor 100 may be formed on the substrate 102 , and the fin field effect transistor 100 may include a fin structure 104 having a fin region 121 and a source/drain region 106 , and a gate structure 108 disposed on the fin structure 104 and spacers 110 and shallow trench isolation (STI) regions 112 disposed on both sides of each gate structure 108 . FIG. 1 shows five gate structures 108 . However, based on the disclosure herein, the finFET 100 may have more or less gate structures. In addition, the finFET 100 can be incorporated into an integrated circuit by using other structural components such as source/drain contact structures, gate contact structures, vias, wires, dielectric layers, and protective layers, in order to These structural components are omitted for clarity.

The substrate 102 may be a semiconductor material, such as silicon. In some embodiments, the substrate 102 comprises a crystalline silicon substrate (eg, a wafer). In some embodiments, the substrate 102 includes elemental semiconductors (eg, germanium), compound semiconductors (including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide), alloy semiconductors (including Silicon germanium carbide, silicon germanium, gallium arsenide phosphide, gallium indium phosphide, gallium indium arsenide, gallium indium arsenide, aluminum indium arsenide and/or aluminum gallium arsenide or a combination of the foregoing. Again, depending on design The substrate 102 may be doped (eg, a p-type substrate or an n-type substrate) as desired. In some embodiments, the substrate 102 may be doped with a p-type dopant (eg, boron, indium, aluminum, or gallium) or an n-type dopant. substances (such as phosphorus or arsenic).

Fin structure 104 represents the current carrying structure of FinFET 100 and may extend along the Y axis and through gate structure 108 . Fin structures 104 may include portions of fin regions 121 below gate structures 108 and source/drain regions 106 disposed on portions of fin regions 121 formed on each gate structure 108 on both sides. The portion of the fin region 121 of the fin structure 104 (not shown in FIG. 1 ) below the gate structure 108 may extend over the shallow trench isolation region 112 and may be surrounded by the corresponding gate structure 108 . The fin regions 121 on both sides of the gate structure 108 can be etched back so that the source/drain regions 106 can be epitaxially grown on the portions of the fin regions 121 that are etched back.

Fin region 121 of fin structure 104 may comprise a material similar to substrate 102, and source/drain regions 106 may comprise epitaxially grown semiconductor material. In some embodiments, the epitaxially grown semiconductor material is the same material as the substrate 102 . In some embodiments, the epitaxially grown semiconductor material comprises a different material than the substrate 102 . Epitaxially grown semiconductor materials may include semiconductor materials (eg, germanium and silicon), compound semiconductor materials (eg, gallium arsenide and aluminum gallium arsenide), or semiconductor alloys (eg, silicon germanium and gallium arsenide phosphide). Other materials for the fin structure 104 are also within the scope of embodiments of the present invention.

In some embodiments, the source/drain regions 106 can be deposited by chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), ultrahigh vacuum chemical vapor deposition (ultrahigh vacuum) CVD, UHVCVD), reduced pressure chemical vapor deposition (reduced pressure CVD, RPCVD), suitable chemical vapor deposition process, molecular beam epitaxy (molecular beam epitaxy, MBE) process, suitable epitaxial process or a combination of the above growth . In some embodiments, the source/drain regions 106 may be grown through an epitaxial deposition/partial etch process, and the epitaxial deposition/partial etch process may be repeated at least once. This repetitive deposition/partial etch process is also referred to as a "cyclic deposition-etch (CDE) process." In some embodiments, the source/drain regions 106 may be grown by selective epitaxial growth (SEG), in which an etchant gas is added to promote the selective growth of semiconductor material on the exposed surfaces of the fin structures. Not grown on insulating material (eg, the dielectric material of shallow trench isolation regions 112). Other methods for epitaxially growing the source/drain regions 106 are also within the scope of embodiments of the present invention.

The source/drain regions 106 may be p-type or n-type regions. In some embodiments, p-type source/drain regions 106 may comprise SiGe, and may be doped in-situ with p-type dopants (eg, boron, indium, and gallium) during epitaxial growth. For p-type in situ doping, p _- type doping precursors such as diborane ( _B2H6 ), boron trifluoride ( _BF3 ) and other p-type doping precursors can be used. In some embodiments, the n-type source/drain regions 106 may comprise Si, and may be doped in-situ with n-type dopants such as phosphorous and arsenic during epitaxial growth. For n-type in situ doping, n-type doping precursors such as phosphine (PH3 ₎ , arsine (AsH3) and other n _- type doping precursors can be used. In some embodiments, the source/drain regions 106 are not doped in-situ, and an ion implantation process is performed to doped the source/drain regions 106 .

The spacers 110 may include spacer portions 110 a formed on the sidewalls of the gate structures 108 and contacting the dielectric layer 118 , spacer portions 110 b formed on the sidewalls of the fin structures 104 , and formed as shallow trench isolation regions 112 . The spacer portion 110c of the protective layer. Each spacer portion may also be a multiple spacer structure comprising more than one spacer structure. For example, the spacer portion 110a may include more than one spacer and an air gap formed between the gate structure 108 and the fin structure 104 . A sealing material may be formed over the air gap to close and protect the air gap from subsequent manufacturing processes. For brevity, the air gap and sealing material are not shown in Figure 1. The spacers 110 may include insulating materials such as silicon oxide, silicon nitride, low-k materials, and combinations thereof. Spacer 110 may comprise a low dielectric constant material having a dielectric constant less than 3.9 (eg, less than 3.5, 3, and 2.8). Since the air gap may have a dielectric constant of about 1, the effective dielectric constant of the spacer 110 may be further reduced compared to spacers formed using a low dielectric constant material. The low-k material of the spacer 110 can be formed by a suitable deposition process, such as atomic layer deposition (ALD). In some embodiments, the spacer 110 may be formed by using chemical vapor deposition, low pressure chemical vapor deposition, ultra-high vacuum chemical vapor deposition, reduced pressure chemical vapor deposition, physical vapor deposition (PVD), Any other suitable deposition process or combination of the foregoing. In some embodiments, the sealing material may be a high rigidity material, such as oxygen doped high rigidity silicon carbide. In some embodiments, the sealing material may be a multi-layer sealing material by depositing a first sealing material on top of the opening formed between the gate structure 108 and the source/drain regions 106 , followed by the first sealing material A second sealing material is deposited on the sealing material to form a sealing body having air in the opening. Other materials and thicknesses for spacers 110 are also within the scope of embodiments of the present invention.

Each gate structure 108 may include a gate electrode 116 , a dielectric layer 118 adjacent to and contacting the gate electrode 116 , and a gate capping layer 120 . The gate structure 108 may be formed through a gate replacement process.

In some embodiments, the dielectric layer 118 may be formed by using a high-k dielectric material (eg, a dielectric material having a dielectric constant greater than about 3.9). The dielectric layer 118 may be formed by chemical vapor deposition, atomic layer deposition, physical vapor deposition, electron beam evaporation, or other suitable processes. In some embodiments, the dielectric layer 118 may include a silicon oxide layer, a silicon nitride layer and/or a silicon oxynitride layer, a high-k dielectric material (eg, HfO ₂ , TiO ₂ , HfZrO, Ta ₂ O ₃ , HfSiO ₄ , ZrO ₂ and ZrSiO ₂ ), with lithium (Li), beryllium (Be), magnesium (Mg), calcium (Ca), strontium (Sr), scandium (Sc), yttrium (Y), zirconium (Zr) , aluminum (Al), lanthanum (La), cerium (Ce), strontium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), abium (Tb), dysprosium (Dy) , — (Ho), erbium (Er), tantalum (Tm), ytterbium (Yb) or tungsten (Lu) oxides \ high dielectric constant dielectric materials or a combination of the foregoing. The high-k dielectric layer can be formed by atomic layer deposition and/or other suitable methods. In some embodiments, the dielectric layer 118 may comprise a single layer or a stack of layers of insulating material. Other materials and formation methods for dielectric layer 118 are also within the scope of embodiments of the present invention. For example, a portion of the dielectric layer 118 is formed on a horizontal surface, such as the top surface of the shallow trench isolation region 112 . Although not shown in FIG. 1 , the dielectric layer 118 may also be formed on the top and sidewalls of the fin region 121 below the gate electrode 116 . In some embodiments, the dielectric layer 118 may also be formed between the sidewall of the gate electrode 116 and the spacer portion 110a, as shown in FIG. 1 . In some embodiments, the dielectric layer 118 has a thickness 118t in the range of about 1 nm to about 5 nm.

The gate electrode 116 may include a gate work function metal layer 122 and a gate metal fill layer 124 . In some embodiments, the gate work function metal layer 122 is disposed on the dielectric layer 118 . The gate work function metal layer 122 may comprise a single metal layer or a stack of metal layers. The stack of metal layers may include metal layers having work functions that are similar to each other or different from each other. In some embodiments, the gate work function metal layer 122 may include, for example, aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), titanium nitride (TiN), nitride Tantalum (TaN), Nickel Silicon (NiSi), Cobalt Silicon (CoSi), Silver (Ag), Tantalum Carbide (TaC), Tantalum Silicon Nitride (TaSiN), Tantalum Carbon Nitride (TaCN), Titanium Aluminum (TiAl), Titanium Aluminum Nitride (TiAlN), Tungsten Nitride (WN), metal alloys, and combinations of the foregoing. The gate work function metal layer 122 can be formed by using a suitable process, such as atomic layer deposition, chemical vapor deposition, physical vapor deposition, plating, or a combination of the foregoing. In some embodiments, the gate work function metal layer 122 has a thickness 122t in the range of about 2 nm to about 15 nm. Other materials, formation methods, and thicknesses for the gate work function metal layer 122 are also within the scope of embodiments of the present invention.

The gate metal fill layer 124 may comprise a single metal layer or a stack of metal layers. The stack of metal layers may include metal layers that are different from each other. In some embodiments, the gate metal fill layer 124 may include a suitable conductive material such as Ti, Ag, Al, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, WN, Cu, W, Co, Ni, TiC, TiAlC, TaAlC, metal alloys, and combinations of the foregoing. The gate metal fill layer 124 may be formed by atomic layer deposition, physical vapor deposition, chemical vapor deposition, or other suitable deposition processes. Other materials and formation methods for the gate metal fill layer 124 are also within the scope of embodiments of the present invention.

In some embodiments, the gate cap layer 120 may have a thickness 120t in the range of about 5 nm to about 50 nm, and may protect the gate structure 108 during subsequent processing of the finFET 100 . The gate cap layer 120 may include nitride materials such as silicon nitride, silicon-rich nitride, and silicon oxynitride. Other materials for the gate cap layer 120 are also within the scope of embodiments of the present invention.

Shallow trench isolation regions 112 may provide electrical isolation for adjacent active and passive elements (not shown here) in FinFET 100 that are integrated or deposited on substrate 102 . The shallow trench isolation region 112 may be a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectric materials, and others suitable insulating material. In some embodiments, the shallow trench isolation region 112 may comprise a multi-layer structure. The cross-sectional shapes of the fin structures 104 , the source/drain regions 106 , the gate structures 108 , the spacers 110 and the shallow trench isolation regions 112 are illustrative, but not limited thereto.

Figures 2-6, which provide various exemplary semiconductor structures and fabrication processes, show the formation of spacer structures with air gaps and high rigidity sealing layers in accordance with some embodiments. The high-rigidity sealing layer can also be free of gaps. FIG. 7 is a flow diagram of a method 700 of forming an air gap and a high rigidity sealing layer in a semiconductor structure in accordance with some embodiments of the present invention. Other operations in method 700 may be performed based on the disclosure herein. Furthermore, the operations of method 700 and/or changes may be performed in a different order.

An air gap with a seamless sealing layer can provide the advantage of reducing and/or eliminating damage to air gaps formed between spacer structures. These fabrication processes can be used to form planar semiconductor devices or vertical semiconductor devices, such as fin field effect transistors. In some embodiments, the fabrication processes shown in FIGS. 2-7 may be used to form semiconductor structures similar to the finFET structures described in FIG. 1 . For example, the semiconductor structures shown in FIGS. 2-7 may be similar to the finFET 100 shown in FIG. 1 during different stages of fabrication resulting from tangent A-A'.

Referring to operation 702 of FIG. 7, source/drain regions and gate stacks are formed on a substrate in accordance with some embodiments. FIG. 2 is a schematic cross-sectional view of the semiconductor structure 200 after three adjacent gate structures 208 and two source/drain contacts 230 are formed over the substrate. The substrate may include fin regions 221 . Each gate stack (eg, gate structure 208 ) includes a gate dielectric layer 218 and a gate electrode 216 . A gate dielectric layer 218 may be formed on the sidewall and bottom surface of the gate electrode 216 . A channel region of the semiconductor device (eg, finFET 100 ) may be formed in the fin region 221 and under the gate structure 208 .

The fin region 221 may be a current-carrying semiconductor structure formed on the substrate. For example, the fin region 221 may be similar to the fin region 121 described above in FIG. 1 . In some embodiments, the fin region 221 may comprise a semiconductor material such as germanium, silicon, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, silicon germanium carbide, silicon germanium, phosphorus Gallium arsenide, gallium indium phosphide, gallium indium arsenide, gallium indium arsenide, aluminum indium arsenide and/or aluminum gallium arsenide, any suitable material, and combinations of the foregoing. In some embodiments, the fin regions 221 may be doped with p-type or n-type dopants.

The gate dielectric layer 218 may be formed on the fin region 221 by using a high-k dielectric material. The gate dielectric layer 218 may be deposited by chemical vapor deposition, atomic layer deposition, physical vapor deposition, electron beam evaporation, or other suitable processes. In some embodiments, gate dielectric layer 218 may include a high-k dielectric material, such as HfO ₂ . In some embodiments, gate dielectric layer 218 may include TiO ₂ , HfZrO, Ta ₂ O ₃ , HfSiO ₄ , ZrO ₂ , and ZrSiO ₂ . In some embodiments, the gate dielectric layer 218 may comprise a dielectric layer 118 similar to that described above in FIG. 1 .

Gate electrode 216 may be formed on gate dielectric layer 218 and may comprise a single metal layer or a stack of metal layers. The gate structure 208 may further include a work function layer, and the work function layer is not shown in FIG. 2 for brevity. The stack of metal layers may include metal layers having work functions that are similar to each other or different from each other. In some embodiments, the gate electrode 216 may be formed of a conductive material such as Al, Cu, W, Ti, Ta, TiN, TaN, NiSi, CoSi, Ag, TaC, TaSiN, TaCN, TiAl, TiAlN, WN, metal alloys and a combination of the foregoing. The gate electrode 216 can be formed by using a suitable deposition process, such as atomic layer deposition, chemical vapor deposition, physical vapor deposition, plating, or a combination of the foregoing. Other materials and methods of formation for gate electrode 216 are also within the scope of embodiments of the present invention. In some embodiments, the gate electrode 216 may be formed by using a gate replacement process in which the polysilicon gate is removed and a metal gate electrode is formed at the location after the polysilicon gate is removed.

Spacer structures may be formed on sidewalls of the gate structures 208 . In some embodiments, the gate structures may include gate electrodes, dielectric layers, spacers, any other suitable structures, and may be collectively referred to as gate structures for convenience of description. In some embodiments, spacers 210 and 212 are formed on the sidewalls of gate dielectric layer 218 and the top surface of fin region 221 . Spacer structures are formed on the sidewalls of gate electrode 216 to protect gate dielectric layer 218 and gate electrode 216 during subsequent processing. In some embodiments, spacer 210 may have an L-shaped cross-section with vertical portions formed on the sidewalls of gate dielectric layer 218 and horizontal portions formed on the top surface of fin region 221 . In some embodiments, spacers 210 are formed only on sidewalls of gate dielectric layer 218 . The spacers 210 may be formed by using a dielectric material, such as silicon nitride carbide, silicon nitride, silicon oxide, any suitable dielectric material, and combinations of the foregoing. In some embodiments, for spacers 210 using silicon nitride carbide, the carbon content may be less than about 30%. In some embodiments, the carbon atom content of spacers 210 may be between about 20% and about 30%. Additional spacers, such as spacer 212, may also be formed. For example, spacers 212 may be formed on horizontal portions of spacers 210, on the top surfaces of fin regions 221, or on both. In some embodiments, the spacers 212 may be formed by using a dielectric material, such as silicon. In some embodiments, the material forming spacers 210 and 212 may have a high etch selectivity (eg, greater than about 10) such that when spacers 212 are removed, spacers 210 may remain substantially intact. In some embodiments, spacers 210 and 212 may be formed by using any suitable dielectric material, such as silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon on glass (SOG), Tetraethoxysilane (TEOS), poly(ethylene oxide, PE-oxide), oxides formed by high aspect ratio process (HARP), and combinations of the foregoing. In some implementations For example, spacers 210 and 212 may be formed by using a low-k dielectric material.

Source/drain (S/D) regions 240 may be formed in the fin regions 221 . The source/drain regions 240 may be p-type regions or n-type regions. In some embodiments, the source/drain regions 240 may comprise SiGe and may be doped in-situ with p-type dopants such as boron, indium, and gallium during epitaxial growth. For p-type in-situ doping, p-type doping precursors such as _B2H6 , _BF3 , and other p _- type doping precursors can be used. In some embodiments, the n-type source/drain regions 106 may comprise Si, and may be doped in-situ with n-type dopants such as phosphorous and arsenic during epitaxial growth. For n-type in-situ doping, n _- type doping precursors such as PH3, AsH3, and other n _- type doping precursors can be used. In some embodiments, the source/drain regions 240 are not doped in-situ, and an ion implantation process is performed to doped the source/drain regions 240 . In some embodiments, the source/drain regions 240 may be similar to the source/drain regions 106 described above in FIG. 1 .

Source/drain (S/D) contacts 230 may physically and electrically contact source/drain regions 240 . Source/drain contacts 230 may be formed by depositing conductive material between adjacent gate structures 208 . For example, openings may be formed between spacers 212 to expose underlying source/drain regions 240 . A deposition process can be performed to deposit conductive material in the openings so that electrical connections are formed. In some embodiments, a contact etch stop layer (CESL) 214 may be deposited in the openings prior to depositing the conductive material. Examples of conductive material deposition processes may include physical vapor deposition, sputtering, electroplating, electroless plating, any suitable deposition process, and combinations of the foregoing. After the deposition process, a planarization process may be performed so that the top surfaces of gate electrode 216, spacers 210 and 212, contact etch stop layer 214, and source/drain contacts 230 are substantially coplanar (eg, flat surfaces). In some embodiments, the source/drain contacts 230 may be formed using tungsten, aluminum, cobalt, silver, any suitable conductive material, and combinations of the foregoing.

Similar to the FinFET 100 depicted in FIG. 1, the semiconductor structure 200 may be formed on a substrate with the fin regions 221 protruding from the shallow trench isolation regions. The shallow trench isolation region is not shown in the cross-sectional schematic diagram of the semiconductor structure 200 in FIG. 2 , but for convenience of description, the top surface of the shallow trench isolation region is represented by a dashed line 222 .

Referring to operation 704 of FIG. 7, one or more spacers are removed to form openings between terminals of the semiconductor device, according to some embodiments. 3 is a schematic cross-sectional view of the semiconductor device after removing one or more spacers to form openings. Examples of terminals of a semiconductor device may be gate structures, source/drain structures, or any other suitable structures. The gate structure 208 shown in FIG. 3 may include a gate dielectric layer 218 and a gate electrode 216 . In some embodiments, gate structure 208 may also include spacers 210 . The source/drain structure may include source/drain contacts 230 and contact etch stop layer 214 . In some embodiments, the source/drain structure may further include source/drain regions 240 formed in the fin regions 221 . During operation 704, one or more spacers between the gate electrode 216 and the source/drain contacts 230 may be removed. For example, spacer 212 may be removed to form opening 302 surrounded by spacer 210 and contact etch stop layer 214 . One or more etching processes may be used to remove spacers 212 . In some embodiments, an etch process with high etch selectivity of spacers 212 relative to other structures in semiconductor structure 200 may be used to remove spacers 212 while leaving other exposed structures intact. For example, spacers 212 may be formed by using silicon nitride carbide, and wet etching processes and/or plasma etching may be used to selectively remove spacers 212 .

4A and 4B show schematic cross-sectional views of a fabrication process for forming a high rigidity seal layer using a cyclic deposition/processing process according to some embodiments. 4C-4F show cross-sectional schematic diagrams of forming a high rigidity sealing layer using multiple deposition processes according to some embodiments. Figures 4A-4F are enlarged views of region 304 in Figure 3 . Other structures may be included in the structures shown in Figures 4A-4F, but for the sake of brevity, other structures are not shown.

According to some embodiments, referring to operation 706 of FIG. 7, a sealing layer is deposited on at least the top corners of the opening of the semiconductor device. 4A shows a schematic cross-sectional view of a semiconductor device after depositing an encapsulant on at least a top corner of an opening of the semiconductor device. The encapsulation layer 452 is deposited on the exposed top surfaces of structures in the semiconductor device, such as the gate electrode 216, the gate dielectric layer 218, the source/drain contacts 230, the contact etch stop layer 214, and the top surfaces of other structures. In some embodiments, a sealing layer 452 may also be deposited in the opening 302 . For example, a sealing layer 452 may be deposited on the sidewalls of the spacers 210 and the contact etch stop layer 214 . In some embodiments, a sealing layer 452 may be deposited on the bottom of the opening 302 , such as on the top surface of the horizontal portion of the spacer 210 formed on the fin region 221 . In some embodiments, a sealing layer 452 may also be formed on the fin region 221 if a portion of the top surface of the fin region 221 is exposed between the spacer 210 and the contact etch stop layer 214 . The sealing layer 452 may have horizontal portions 452A formed on the top surfaces of the gate electrode 216, the gate dielectric layer 218, and the source/drain contacts 230 to protect these semiconductor structures from subsequent fabrication processes. For example, the horizontal portion 452A may prevent oxidation of the underlying material during subsequent etching or processing processes. The sealing layer 452 may also include corner portions 452B formed on the spacers 210 and the contact etch stop layer 214 . The top surfaces of the spacer 210 and the contact etch stop layer 214 have rounded corners 410A and 414A, respectively, to facilitate the growth of the corner portion 452B of the sealing layer 452 . The curved surfaces of the rounded corners 410A and 414A may reduce the formation of voids or discontinuities in the sealing layer 452 compared to corners with right angles or sharp edges. Corner portion 452B may have the same profile as the curved surfaces of fillets 410A and 414A.

By adjusting the depth of the sealing layer 452 extending into the opening 302, the sealing layer 452 can affect the volume of the air gap subsequently formed between the terminals of the semiconductor device (eg, the gate electrode 216 and the source/drain contacts 230). In particular, the corner portion 452B of the sealing layer 452 may extend into the opening 302 through the sidewalls formed on the spacer 210 and the contact etch stop layer 214 . Opening 302 may have a height H ₁ and a high aspect ratio (eg, an aspect ratio greater than about 10). By reducing the extension of the corner portion 452B to the opening 302, a larger height _H2 of the air gap 442 can be achieved. A larger ratio of H ₂ to H ₁ may represent a larger volume of air gap 442 in opening 302 .

The sealing layer 452 may be formed by using any suitable dielectric material. In some embodiments, the sealing layer 452 may be formed by using a material that provides sufficient structural strength to support the air gap structure and chemical resistance for protection from subsequent chemical processing. In some embodiments, the sealing layer 452 may include silicon-oxygen or silicon-carbon crosslinks. In some embodiments, the sealing layer 452 may be formed by using free radical chemical vapor deposition, chemical vapor deposition, atomic layer deposition, low pressure chemical vapor deposition, ultra-high vacuum chemical vapor deposition, reduced pressure chemical vapor deposition, physical Vapor deposition, any other suitable deposition process, and combinations of the foregoing. In some embodiments, the sealing layer 452 may be deposited using a free radical chemical vapor deposition process with an ion filter. In some embodiments, the deposition of the sealing layer 452 may include a first operation of flowing the precursor into the deposition chamber. The precursors may provide one or more of the following bond types: silicon-oxygen, silicon-hydrogen, and silicon-carbon. In some embodiments, the precursor is gaseous and can include, for example, tetramethyldisiloxane (TSMDSO), hydrogen, and oxygen. Other suitable precursors may also be included. The hydrogen to oxygen flow ratio may be greater than about 20 to minimize oxidation of the underlying material while promoting the chemical reactions required for deposition. For example, the flow ratio of hydrogen to oxygen may be between about 20 and about 30. The deposition may further comprise a second operation comprising activating the plasma and activating the gaseous precursor to form silicon-oxygen and silicon-carbon crosslinks when the precursor is deposited on the exposed surface. The encapsulant material deposited on the encapsulant layer 452 of the fillets 410A and 414A gradually builds up and eventually coalesces to seal the opening 302 such that the air gap 442 is physically isolated from the environment above the encapsulant layer 452 . Air gap 442 is surrounded by sealing layer 452 , spacers 210 and contact etch stop layer 214 and is in physical contact with sealing layer 452 , spacers 210 and contact etch stop layer 214 . In some embodiments, spacers 210 are formed only on sidewalls of gate dielectric layer 218 , and air gaps 442 may physically contact fin regions 221 .

The height H ₂ of the air gap 442 can be adjusted by changing various deposition parameters of the sealing layer 452 . For example, reducing the deposition rate of sealing layer 452 may increase further stacking of sealing material on the sidewalls into the bottom of opening 302, resulting in air gap 442 having a smaller height _H2 (eg, smaller air gap 442). In some embodiments, the deposition rate may be between about 1 Å/min and about 100 Å/min. In some embodiments, the deposition process may be performed at a deposition rate greater than about 25 Å/min. For example, the deposition process can be performed at a rate between about 25 Å/min and about 35 Å/min. In some embodiments, the deposition rate may be between about 55 Å/min and about 65 Å/min. For example, the deposition rate may be about 60 Å/min. The deposition rate can be adjusted through various deposition parameters. In some embodiments, lower chamber pressure or higher plasma power during deposition may provide higher deposition rates. In some embodiments, the chamber pressure may be between about 0.5 Torr and about 12 Torr. For example, the chamber pressure may be between about 0.5 Torr and about 3 Torr, between about 3 Torr and about 7 Torr, between about 7 Torr and about 12 Torr, and any suitable range/value. As another example, the chamber pressure may be between about 4.5 Torr and about 5.5 Torr, which may provide a deposition rate of about 35 Å/min, while the chamber pressure may be between about 6 Torr and about 7 Torr, which may provide less The deposition rate is around 20 Å/min.

The plasma power level of the deposition process can also affect the deposition rate. For example, during chemical vapor deposition processes, larger plasma power levels can provide larger deposition rates. In some embodiments, the plasma power level may be between about 500W and about 3000W. For example, the plasma power level may be between about 500W and about 1000W, between about 1000W and about 2000W, between about 2000W and about 3000W, and any other suitable power level. In some embodiments, the deposition process may use a radical-triggered chemical reaction with an ion filter.

The density of the sealing layer 452 can also be adjusted through deposition parameters. Increasing the density of the sealing layer 452 may provide greater mechanical support and improved chemical resistance. In some embodiments, the sealing layer 452 may have a density greater than about 2.0 g/cm ³ . For example, the density of the sealing layer 452 may be between about 2.0 g/cm ³ and about 2.2 g/cm ³ . In some embodiments, the density of the sealing layer 452 may be between about 2.2 g/cm ³ and about 3.2 g/cm ³ . In some embodiments, greater densities can be achieved with smaller cavity processing pressures and larger plasma power levels. In some embodiments, the cavity processing pressure may be between about 0.5 Torr and about 12 Torr. For example, the cavity processing pressure may be between about 0.5 Torr and about 3 Torr, between about 3 Torr and about 8 Torr, between about 8 Torr and about 12 Torr, and any other suitable range or value.

The dielectric constant of the sealing layer 452 may be less than about 5. In some embodiments, the sealing layer 452 may have a dielectric constant between about 3.2 and about 5. The smaller dielectric constant of the encapsulation layer 452 allows the terminals of the semiconductor structure 200 to have less parasitic capacitance. In some embodiments, the leakage current in the semiconductor structure 200 may be less than about 1E ⁻⁸ A/cm ² at 2 MV/cm.

According to some embodiments, referring to operation 708 of FIG. 7, a processing process is performed on the deposited sealing layer. FIG. 4B is a schematic cross-sectional view showing the semiconductor device after the processing process.

A treatment process 462 may be performed on the sealing layer 452 to adjust the oxygen content of the deposited sealing material. In some embodiments, the treatment process 462 may increase the oxygen content of the deposited encapsulation material. In some embodiments, the processing process 462 may be performed in an oxygen chamber environment. The oxygen environment promotes the formation of additional Si-O-Si crosslinks in the encapsulant, effectively doping the encapsulant with additional oxygen atoms. In some embodiments, the treatment process 462 can reduce the oxygen content. In some embodiments, processing 462 may be performed in a hydrogen chamber environment. In some embodiments, the processing chamber may contain hydrogen gas at a predetermined pressure. The hydrogen environment facilitates the removal of oxygen atoms from the deposited encapsulant, allowing for the formation of more Si-C-Si crosslinks. In some embodiments, the silicon atomic content of the sealing layer 452 may be between about 25% and about 35%. In some embodiments, the oxygen atomic content of sealing layer 452 may be between about 30% and about 55%. In some embodiments, the carbon atom content of the sealing layer 452 may be between about 10% and about 35%.

The deposition/processing processes described with reference to Figures 4A and 4B are exemplary. In some embodiments, the deposition/treatment process may be performed in a cyclic fashion until the nominal properties of the deposited sealing layer are achieved. For example, more than one cycle including at least one deposition operation and at least one treatment process may be performed until the nominal thickness and quality of the sealing layer 452 is reached. In some embodiments, this cycle is performed only once. In some embodiments, the processing process may be performed in a chamber environment filled with any suitable gas, such as argon, nitrogen, and any suitable gas. In some embodiments, the deposition and/or treatment process may be performed at a temperature between about 200°C and about 700°C. For example, the deposition temperature can be between about 200°C and about 500°C, between about 500°C and about 700°C, and any suitable temperature.

In some embodiments, the sealing layer 452 may be deposited by a bilayer deposition process, as described in Figures 4C-4F. According to some embodiments, as shown in FIG. 4C, a first encapsulant material is deposited on at least corners of the opening of the semiconductor device. The first encapsulation material 412 is deposited on the top surfaces of the gate electrode 216 , the gate dielectric layer 218 , the source/drain contacts 230 and the contact etch stop layer 214 . In some embodiments, the first sealing material 412 may also be deposited in the opening 302 . For example, the first encapsulation material 412 may be deposited on the sidewalls of the spacers 210 and the contact etch stop layer 214 . In some embodiments, the first encapsulation material 412 may be deposited on the bottom of the opening 302 , eg, on the top surface of the horizontal portion of the spacer 210 formed on the fin region 221 . In some embodiments, the first encapsulation material 412 may also be formed on the fin region 221 if a portion of the top surface of the fin region 221 is exposed between the spacer 210 and the contact etch stop layer 214 . The first encapsulation material 412 may include corner portions 412A formed on the spacers 210 and the contact etch stop layer 214 . The top surfaces of the spacer 210 and the contact etch stop layer 214 have rounded corners 410A and 414A, respectively, to facilitate the growth of the corner portion 412A of the first sealing material 412 . The curved surfaces of the rounded corners 410A and 414A may reduce the formation of voids or discontinuities in the first sealing material 412 compared to corners with right angles or sharp edges. The corner portion 412A of the first sealing material 412 may have the same profile as the curved surfaces of the fillets 410A and 414A. The first encapsulant may have horizontal portions 412B formed on the top surfaces of gate electrode 216 , gate dielectric layer 218 , source/drain contacts 230 to protect gate electrode 216 , gate dielectric layer 218 . The source/drain contacts 230 are protected from subsequent manufacturing processes. For example, the horizontal portion 412B may prevent oxidation of the underlying material during subsequent etching or processing processes.

By adjusting the depth of the first sealing material 412 extending into the opening 302 , the first sealing material 412 can affect the volume of the air gap subsequently formed between the gate electrode 216 and the source/drain contacts 230 . In particular, the corner portions 412A of the first sealing material 412 may extend into the openings 302 through the sidewalls formed on the spacers 210 and the contact etch stop layer 214 . The larger extended height H3 _of the corner portion 412A may provide a smaller subsequently formed air gap in the opening 302 (not shown in Figure 4C). For example, _a larger ratio of _H3 to H1 may leave a smaller volume of openings 302 for forming the air gap.

The first encapsulation material 412 may be formed by using any suitable dielectric material. In some embodiments, the first sealing material 412 may be formed by using a material that provides sufficient structural strength to support the air gap structure and chemical resistance for protection from subsequent chemical processing. In some embodiments, the first sealing material 412 may include silicon-oxygen or silicon-carbon crosslinks. In some embodiments, the first encapsulation material 412 may be formed by using free radical chemical vapor deposition, chemical vapor deposition, atomic layer deposition, low pressure chemical vapor deposition, ultra-high vacuum chemical vapor deposition, reduced pressure chemical vapor deposition , physical vapor deposition, any other suitable deposition process, and combinations of the foregoing. In some embodiments, the first encapsulation material 412 may be deposited using a free radical chemical vapor deposition process with an ion filter. In some embodiments, the deposition of the first encapsulation material 412 may include a first operation of flowing the precursor into the deposition chamber. The precursors may provide one or more of the following bond types: silicon-oxygen, silicon-hydrogen, and silicon-carbon. In some embodiments, the precursors are gaseous, such as tetramethyldisiloxane (TSMDSO), hydrogen, and oxygen. Other suitable precursors may also be included. The hydrogen to oxygen flow ratio may be greater than about 20 to minimize oxidation of the underlying material while promoting the chemical reactions required for deposition. For example, the flow ratio of hydrogen to oxygen may be between about 20 and about 30. The deposition may further comprise a second operation comprising activating the plasma and activating the gaseous precursor to form the silicon-oxygen and silicon-carbon crosslinks. The deposition process may include a treatment process of a third operation to reduce the oxygen content of the deposited sealing material. The processing process can be performed in a hydrogen chamber environment. In some embodiments, the processing process may be performed in a chamber environment with any suitable type of gas, such as argon, nitrogen, and any suitable gas. In some embodiments, the deposition process may be performed at a temperature between about 300°C and about 700°C. For example, the deposition temperature can be between about 300°C and about 500°C, between about 500°C and about 700°C, and any other suitable temperature. In some embodiments, the deposition and treatment processes may be performed in a loop, such as a cyclic deposition-treatment process. For example, after the deposition and handling process, another deposition and handling process may be performed until the nominal thickness or quality of the first encapsulation material is reached.

The deposition rate can be adjusted through various deposition parameters. A greater deposition rate may promote greater buildup of the first encapsulation material 412 at the fillets 410A and 414A. A smaller deposition rate may provide a larger extension height H ₃ of the first encapsulant material 412 in the opening 302 . Greater deposition rates can be achieved by adjusting various suitable processing parameters. In some embodiments, the deposition process may be performed at a deposition rate greater than about 25 Å/min. For example, the deposition process can be performed at a rate between about 25 Å/min and about 35 Å/min. In some embodiments, the deposition rate may be between about 55 Å/min and about 65 Å/min. For example, the deposition rate may be about 60 Å/min. In some embodiments, lower chamber pressure or higher plasma power during deposition may provide higher deposition rates. In some embodiments, the chamber pressure may be between about 0.5 Torr and about 12 Torr. For example, the chamber pressure may be between about 0.5 Torr and about 3 Torr, between about 3 Torr and about 7 Torr, between about 7 Torr and about 12 Torr, and any suitable range/value. As another example, the chamber pressure may be between about 4.5 Torr and about 5.5 Torr, which may provide a deposition rate of about 35 Å/min, while the chamber pressure may be between about 6 Torr and about 7 Torr, which may provide less The deposition rate is around 20 Å/min.

The plasma power level used for deposition can also affect the deposition rate. Greater plasma power levels provide greater deposition rates. In some embodiments, the plasma power level may be between about 500W and about 3000W. For example, the plasma power level may be between about 500W and about 1000W, between about 1000W and about 2000W, between about 2000W and about 3000W, and any other suitable power level.

The density of the first encapsulation material 412 can also be adjusted through deposition parameters. Increasing the density of the first sealing material 412 may provide greater mechanical support and improved chemical resistance. In some embodiments, the first sealing material 412 may have a density greater than about 2.0 g/cm ³ . For example, the density of the first sealing material 412 may be between about 2.0 g/cm ³ and about 2.2 g/cm ³ . In some embodiments, the density of the first sealing material 412 may be between about 2.2 g/cm ³ and about 3.2 g/cm ³ . In some embodiments, greater densities can be achieved with smaller cavity processing pressures and larger plasma power levels. In some embodiments, the cavity processing pressure may be between about 0.5 Torr and about 12 Torr. For example, the cavity processing pressure may be between about 0.5 Torr and about 3 Torr, between about 3 Torr and about 8 Torr, between about 8 Torr and about 12 Torr, and any other suitable range or value. In some embodiments, the plasma power level may be between about 500W and about 3000W. For example, the plasma power level may be between about 500W and about 2000W, between about 2000W and about 3000W, and any other suitable range or value. In some embodiments, the deposition process may be performed with an ion filter using a free radical-triggered chemical reaction.

The dielectric constant of the first encapsulation material 412 may be less than about 5. In some embodiments, the first encapsulation material 412 may have a dielectric constant between about 3.2 and about 5. The smaller dielectric constant of the first encapsulation material 412 may allow the terminals of the semiconductor structure 200 to have smaller parasitic capacitances. In some embodiments, the leakage current in the semiconductor structure 200 may be less than about 1E ⁻⁸ A/cm ² at 2 MV/cm.

A selective treatment process may be performed on the first sealing material 412 to further increase the amount of crosslinking inside the first sealing material 412 and/or improve the density of the first sealing material 412 . For example, a hydrogen annealing process may be performed to reduce the oxygen content and form additional Si-C-Si bonds in the first encapsulation material 412. The hydrogen treatment process can also remove chemical by-products, such as _H2O . In some embodiments, the optional treatment process may be performed for less than about 1 minute. For example, the treatment process can be performed for between about 40 seconds and about 1 minute.

A second sealing material may be deposited on the first sealing material and in the opening. FIG. 4D is a schematic cross-sectional view showing the semiconductor device after deposition of the second encapsulation material. The second encapsulation material 432 is deposited on the first encapsulation material 412 , the spacers 210 and a portion of the surface contacting the etch stop layer 214 . The second sealing material 432 may include at least: corner portions 432A deposited on the corner portions 412A of the first sealing material 412, horizontal portions 432B deposited on the horizontal portions 412B of the first sealing material 412, and deposited on the spacers 210 and contacts Vertical portion 432C on the sidewalls of etch stop layer 214 . In some embodiments, the second encapsulant material 432 may be deposited on the bottom of the opening 302 , such as on the top surface of the horizontal portion of the spacer 210 formed on the fin region 221 .

The second encapsulation material 432 may be deposited using any suitable deposition process. For example, the second encapsulation material 432 may be deposited using a chemical vapor deposition process. The semiconductor structure 200 can be loaded into a deposition chamber, and then the encapsulation material is blanket deposited. As the precursor in the deposition chamber moves through the openings formed between the two side corner portions 412A of the first sealing material 412 to be deposited on the exposed surfaces of the openings 302 , the precursors are more stable than the top surface of the horizontal portion 412B. Surface contact with spacers 210 and contact etch stop layer 214 is less likely. Thus, the encapsulant material is deposited at a much lower rate in the portion of the opening 302 below the corner portion 412A. As the sealing material is gradually deposited on the corner portions 412A on both sides of the first sealing material 412 to form the corner portions 432A of the second sealing material 432 , the corner portions 432A deposited above the corner portions 412A will be deposited in the region 440 and the other side. The other corner portion 432A above the one side corner portion 412A is merged. At the region 440 , a gap 450 is formed between adjacent corner portions 432A of the second sealing material 432 .

By adjusting the depth of the second sealing material 432 extending into the opening 302 , the second sealing material 432 can affect the volume of the air gap subsequently formed between the gate electrode 216 and the source/drain contacts 230 . In particular, the vertical portion 432C of the second encapsulation material 432 may extend into the opening 302 by being formed on the sidewalls of the spacer 210 and the contact etch stop layer 214 . The height H ₄ between the lower end of the slit 450 and the bottom surface of the opening 302 is measured. A larger height H ₄ may provide a larger air gap formed between the gate electrode 216 and the source/drain contacts 230 . The height H ₅ between the lower end of the vertical portion 432C and the bottom surface of the opening 302 is measured.

The second sealing material 432 may be formed by using any suitable dielectric material. In some embodiments, the second sealing material 432 may be formed by using a material that provides sufficient strength to support the first sealing material 412 . In some embodiments, the second sealing material 432 may include silicon-oxygen or silicon-carbon crosslinks. In some embodiments, the second sealing material 432 may be formed by using free radical chemical vapor deposition, chemical vapor deposition, atomic layer deposition, low pressure chemical vapor deposition, ultra-high vacuum chemical vapor deposition, reduced pressure chemical vapor deposition , physical vapor deposition, any other suitable deposition process, and combinations of the foregoing. In some embodiments, the second encapsulant material 432 may be deposited using a free radical chemical vapor deposition process with an ion filter. In some embodiments, the deposition of the second encapsulation material 432 may be similar to the deposition of the first encapsulation material 412 . In some embodiments, the second encapsulant 432 may be formed by a chemical vapor deposition process using precursors such as tetramethyldisiloxane (TSMDSO), hydrogen, and oxygen. Other suitable precursors can also be used. The hydrogen to oxygen flow ratio may be greater than about 20 to minimize oxidation of the underlying material while promoting the chemical reactions required for deposition. For example, the flow ratio of hydrogen to oxygen may be between about 20 and about 30. The deposition may further comprise a second operation comprising activating the plasma and activating the gaseous precursor to form the silicon-oxygen and silicon-carbon crosslinks. In some embodiments, the deposition process may be performed at a temperature between about 300°C and about 700°C. For example, the deposition temperature can be between about 300°C and about 450°C, between about 450°C and about 700°C, and any other suitable temperature.

The deposition rate can be adjusted through various deposition parameters. The second encapsulation material 432 may be deposited at a lower deposition rate than the first encapsulation material 412 . In some embodiments, the second sealing material 432 may be a substantially compliant film deposited over the corner portions 412A and horizontal portions 412B of the first sealing material 412 . A larger deposition rate may promote a larger buildup of the second encapsulant material 432 at the corner portion 412A. A smaller deposition rate may provide for a larger extension of the second encapsulation material 432 in the opening 302 . Greater deposition rates can be achieved by adjusting various suitable processing parameters. In some embodiments, the deposition process may be performed at a deposition rate of less than about 30 Å/min. For example, the deposition process can be performed at a rate between about 20 Å/min and about 30 Å/min. In some embodiments, lower chamber pressure or higher plasma power during deposition may provide higher deposition rates. In some embodiments, the chamber pressure may be between about 0.5 Torr and about 12 Torr. For example, the chamber pressure may be between about 0.5 Torr and about 3 Torr, between about 3 Torr and about 7 Torr, between about 7 Torr and about 12 Torr, and any suitable range/value.

The plasma power level used for deposition can also affect the deposition rate. Greater plasma power levels provide greater deposition rates. In some embodiments, the plasma power level may be between about 500W and about 3000W. For example, the plasma power level may be between about 500W and about 1000W, between about 1000W and about 2000W, between about 2000W and about 3000W, and any other suitable power level.

The density of the second encapsulation material 432 can also be adjusted through deposition parameters. Increasing the density of the second sealing material 432 may provide greater mechanical support and improved chemical resistance. In some embodiments, the second sealing material 432 may have a density greater than about 2.0 g/cm ³ . For example, the density of the second sealing material 432 may be between about 2.0 g/cm ³ and about 2.5 g/cm ³ . In some embodiments, the density of the second sealing material 432 may be between about 2.2 g/cm ³ and about 2.5 g/cm ³ . In some embodiments, greater densities can be achieved with smaller cavity processing pressures and larger plasma power levels. In some embodiments, the cavity processing pressure may be between about 0.5 Torr and about 12 Torr. For example, the cavity processing pressure may be between about 0.5 Torr and about 3 Torr, between about 3 Torr and about 8 Torr, between about 8 Torr and about 12 Torr, and any other suitable range or value. In some embodiments, the plasma power level may be between about 500W and about 3000W. For example, the plasma power level may be between about 500W and about 2000W, between about 2000W and about 3000W, and any other suitable range or value. In some embodiments, the deposition process may be performed with an ion filter using a free radical-triggered chemical reaction.

The dielectric constant of the second encapsulation material 432 may be the same or different from that of the first encapsulation material 412 . For example, the second encapsulation material 432 may have a dielectric constant less than about 5. In some embodiments, the second encapsulation material 432 may have a dielectric constant between about 3.2 and about 5. In some embodiments, the leakage current in the semiconductor structure 200 may be less than about 1E ⁻⁸ A/cm ² at 2 MV/cm.

According to some embodiments, a treatment process may be performed on the first and second sealing materials of the sealing layer. FIG. 4E shows a schematic cross-sectional view of the semiconductor device after processing. A processing process 435 may be performed on the second encapsulant material 432 to remove gaps, such as gap 450 . For example, an oxygen annealing process can be performed to physically expand the second encapsulation material 432 and form additional bonds at the gap 450 . During the oxygen annealing process, the Si-C-Si bonds in the second sealing material 432 may become Si-O-Si bonds. In some embodiments, the total carbon atomic ratio of the second encapsulation material 432 may be decreased by between about 5% and about 15%. The oxygen treatment process can be performed for less than about 1 minute. For example, the treatment process may be performed for between about 40 seconds and about 1 minute. In some embodiments, the oxygen flow rate of the treatment process 435 may be between about 1 seem and about 10 seem. For example, the oxygen flow rate can be between about 1 seem and about 3 seem, between about 3 seem and about 5 seem, between about 5 seem and about 10 seem, and any other suitable value. The oxygen annealing process may remove any gaps (eg, gap 450 ), leaving the region 440 containing the second encapsulation material 432 free of any gaps.

FIG. 4F shows a schematic cross-sectional view of the semiconductor device after processing the encapsulation material formed on the asymmetric spacers. As shown in FIG. 4F, the spacers 210 and the contact etch stop layer 214 have different heights along the sidewalls of the gate dielectric layer 218 and the source/drain contacts 230, respectively. For example, spacers 210 and contact etch stop layer 214 may be formed of different materials, and the etch rate of contact etch stop layer 214 may be greater than the spacers in response to one or more spacer etchback processes that form fillets 410A and 414A 210 etch rate. Accordingly, the corner portions 412A formed over the contact etch stop layer 214 may extend down the sidewalls of the source/drain contacts 230 and toward the source/drain regions 240 and the fin regions 221 .

According to some embodiments, referring to operation 710 of FIG. 7 , a planarization process is performed on the high-rigidity sealing layer. FIG. 5 is a schematic cross-sectional view of the semiconductor device after the planarization process. As shown in FIG. 5 , a high rigidity encapsulant 532 is formed on the semiconductor structure 200 to surround air to form an air gap 542 between the terminals of the semiconductor structure 200 and the substrate (eg, the fin region 221 ). In some embodiments, the high-rigidity sealing material 532 is formed of oxygen-doped high-rigidity silicon carbide. In some embodiments, the high rigidity sealing material 532 is a seamless sealing material. The high rigidity sealing material 532 may be formed between the spacers 210 and the contact etch stop layer 214 and contact the spacers 210 and the contact etch stop layer 214 . The high rigidity sealing material 532 may also contact other structures not shown in FIG. 5 . A planarization process may be used to remove the horizontal portion 452A shown in Figure 4B or a portion of the first encapsulation material 412 and the second encapsulation material 432 shown in Figure 4E. The planarization process may continue until the top surfaces of gate electrode 216, gate dielectric layer 218, spacers 210, contact etch stop layer 214, and source/drain contacts 230 are exposed and substantially flush (eg, at the same on flat surface). After the planarization process, the corner portion 412A of the sealing layer 452 or the remaining portions of the first sealing material 412 and the second sealing material 432 may form the high-rigidity sealing material 532 . Air enclosed by the highly rigid encapsulant 532 may form an air gap 542 between the terminals of the semiconductor structure 200 (eg, the gate structure 208 and the source/drain contacts 230). In some embodiments, the air gap 542 may contain different types of air. For example, air gap 542 may include oxygen, hydrogen, helium, argon, nitrogen, any other suitable type of air, and combinations of the foregoing. The smaller deposition rate of the high rigidity sealing material 532 can result in an air gap 542 having a smaller volume. For example, the high rigidity sealing material 532 may be formed by depositing the sealing layer 452 or the first sealing material 412 and the second sealing material 432, and a lower deposition rate may provide an air gap 542 with a smaller height, resulting in a smaller Air gap volume. Since air gap 542 may have a dielectric constant of about 1, the effective dielectric constant of spacer 210 and air gap 542 may be smaller compared to a spacer structure composed of spacers 210 and 212 .

Referring to operation 712 of FIG. 7, dielectric layers and interconnect structures are formed, according to some embodiments. FIG. 6 is a schematic cross-sectional view showing a dielectric layer and an interconnect structure formed on a semiconductor device.

Dielectric layer 620 may be formed on gate electrode 216, gate dielectric layer 218, spacers 210, high rigidity sealing material 532, contact etch stop layer 214, source/drain contacts 230, and other suitable structures. In some embodiments, the dielectric layer 620 may be an etch stop layer. The dielectric layer 620 may be formed by using a low-k dielectric material (eg, a dielectric layer having a dielectric constant less than about 3.9), such as silicon oxide. An inter-layer dielectric (ILD) layer 650 may be formed on the dielectric layer 620 . The interlayer dielectric layer 650 may be formed of a low-k dielectric material. For example, the interlayer dielectric layer 650 may be formed by using silicon oxide. In some embodiments, the dielectric layer 620 and the interlayer dielectric layer 650 may be formed by using chemical vapor deposition, atomic layer deposition, physical vapor deposition, flowable chemical vapor deposition (FCVD), sputtering, any Suitable deposition processes and combinations of the foregoing are formed. Vias may be formed in the interlayer dielectric layer 650 to establish electrical connections from the source/drain contacts 230 and the gate electrode 216 to external circuitry (eg, surrounding circuitry formed over the semiconductor structure 200 ). Gate vias 616 may be formed in the interlayer dielectric layer 650 and extend through the dielectric layer 620 to physically contact the gate electrodes 216 . Similarly, source/drain vias 630 may extend through the interlayer dielectric layer 650 and physically contact the source/drain contacts 230 . Gate vias 616 and source/drain vias 630 may be formed by patterning and etching processes. For example, openings may be formed in the interlayer dielectric layer 650 and through the dielectric layer 620 to expose the gate electrode 216 and the source/drain contacts 230, respectively. A deposition process can be performed to deposit conductive material in the openings so that electrical connections can be established. Examples of deposition processes may be physical vapor deposition, sputtering, electroplating, electroless plating, any suitable deposition process, and combinations of the foregoing. After the deposition process, a planarization process may be performed so that the top surfaces of the interlayer dielectric layer 650, gate vias 616 and source/drain vias 630 may be substantially coplanar (eg, flush). In some embodiments, gate vias 616 and source/drain vias 630 may be formed using tungsten, aluminum, cobalt, silver, any suitable conductive material, and combinations of the foregoing.

The high rigidity encapsulant can also be used as an etch stop layer to facilitate the formation of subsequent structures, or as self-aligned contacts (SACs) for gate electrode 216 and source/drain contacts 230 . In some embodiments, self-aligned contacts may be formed on the top surfaces of gate electrode 216 and/or source/drain contacts 230 . Forming self-aligned contacts with high rigidity encapsulant provides the following advantages: protection against electrical shorts, low leakage current, high uniformity, and good etch resistance. In some embodiments, the self-aligned contacts may also be formed from dielectric materials such as silicon nitride, silicon oxide, silicon oxynitride, silicon oxycarbide, silicon oxynitride, any suitable dielectric material and/or the foregoing combination. Self-aligned contacts can be formed on the gate electrode, on the source/drain contacts, or on both. For clarity, a single self-aligned contact scheme is used to describe semiconductor devices having self-aligned contacts formed on only a single type of terminal (eg, gate electrodes or source/drain contacts). Similarly, a dual self-aligned contact scheme can be used to describe semiconductor devices having self-aligned contacts formed on at least two types of terminals (eg, gate electrodes and source/drain contacts). Figures 8-16 depict various configurations of semiconductor devices, including single self-aligned contact schemes and dual self-aligned contact schemes, with a high rigidity sealing layer formed in the gap and serving as a contact etch stop. In some embodiments, the high-rigidity sealing layer may also be free of gaps through the above-described manufacturing process with reference to FIGS. 4A-4F .

FIG. 8 shows a semiconductor device 800 having a single self-aligned contact scheme formed in gaps between terminals and a high rigidity encapsulation layer, according to some embodiments. The structure shown in Figure 8 is similar to the structure described in Figures 1-6 and is not described in detail here for the sake of simplicity. The semiconductor device 800 may incorporate a single self-aligned contact scheme and include self-aligned contacts formed on the gate electrode 216 or the source/drain contacts 230 . For example, a self-aligned contact 810 may be formed on the top surface of the gate electrode 216, as shown in FIG. In some embodiments, self-aligned contacts 810 may be formed on the top surfaces of source/drain contacts 230 (not shown in FIG. 8). Self-aligned contacts 810 may be formed by etching back a portion of gate electrodes 216 such that a notch is formed on the top of each gate electrode 216 and between the sidewalls of the gate dielectric layer 218 . Dielectric material can be deposited in the recesses to form self-aligned contacts 810 . In some embodiments, the self-aligned contacts 810 can be achieved through the use of silicon oxide, silicon nitride, silicon oxycarbide, silicon oxynitride, silicon oxynitride, any suitable dielectric materials, and combinations of the foregoing. In some embodiments, the self-aligned contacts 810 may be formed prior to forming the high rigidity sealing material 532 . In some embodiments, the self-aligned contacts 810 may be formed after the high rigidity sealing material 532 is formed. The planarization process may be performed so that the top surfaces of the self-aligned contacts 810, gate dielectric layer 218, spacers 210, contact etch stop layer 214, and high rigidity encapsulant 532 are substantially coplanar (eg, on the same plane). Dielectric layer 620, interlayer dielectric layer 650, gate vias 616, and source/drain vias 630 may be formed on the planarized top surface. In some embodiments, gate via 616 may extend through dielectric layer 620 and self-aligned contact 810 and physically contact gate electrode 216 .

FIGS. 9A and 9B show a semiconductor device 900 with a single self-aligned contact scheme between terminals and a high rigidity seal as a contact etch stop and also as a gap seal, according to some embodiments. Figures 9A and 9B show structures similar to those described in Figures 1-8, and for simplicity, are not described in detail here. As shown in FIG. 9A, the high rigidity sealing material 932 may include a first portion 932A formed between the terminals of the semiconductor device 900 and formed in the self-aligned contact 810, the gate dielectric layer 218, the spacers 210, the source electrode /Drain contact 230 and contact second portion 932B on the top surface of etch stop layer 214 . The high rigidity sealing material 932 can be formed by using a method similar to that of FIGS. 4A-4F and 7 described above, and for the sake of simplicity, will not be described in detail here. Air gaps 942 may be formed between the terminals of the semiconductor device 900 , and the size of the air gaps 942 may depend on various factors, such as the deposition rate of the high rigidity sealing material 932 . In some embodiments, the density of the high rigidity sealing material 932 can be adjusted depending on the device design. For example, increasing the density of the high rigidity sealing material 932 may provide greater etch resistance. In some embodiments, the second portion 932B of the high rigidity encapsulation material 932 can be used as a contact etch stop layer for forming subsequent structures, such as vias for the self-aligned contacts 810 and the source/drain contacts 230, as follows This is further described with reference to Figure 9B.

As shown in FIG. 9B , an interlayer dielectric layer 950 may be formed on the second portion 932B of the high rigidity sealing material 932 . The interlayer dielectric layer 950 may be similar to the interlayer dielectric layer 650 described in FIG. 6 . For example, the interlayer dielectric layer 950 may be formed by using silicon oxide. In some embodiments, the interlayer dielectric layer 950 may be formed by using chemical vapor deposition, atomic layer deposition, physical vapor deposition, flowable chemical vapor deposition (FCVD), sputtering, any suitable deposition process, and combinations of the foregoing form. Vias may be formed in the interlayer dielectric layer 950 to establish electrical connections from the source/drain contacts 230 and gate electrodes 216 to external circuitry (eg, surrounding circuitry formed over the semiconductor structure 200). Gate vias 916 may be formed in the interlayer dielectric layer 950 and extend through the second portion 932B of the high rigidity sealing material 932 to physically contact the gate electrodes 216 . Similarly, source/drain vias 930 may extend through the interlayer dielectric layer 950 and physically contact the source/drain contacts 230 . Gate vias 916 and source/drain vias 930 may be formed through patterning and etching processes. For example, openings can be formed in the interlayer dielectric layer 950 to expose the second portion 932B of the underlying high rigidity sealing material 932 through a patterning and etching process. The second portion 932B may serve as a contact etch stop during the process of forming the opening. The high density (eg, greater than about 2.0 g/cm ³ ) of the high rigidity sealing material 932 may provide improved etch resistance. A deposition process may be performed to deposit conductive material in the openings to form gate vias 916 and source/drain vias 930 to establish electrical connections. Examples of deposition processes may be physical vapor deposition, sputtering, electroplating, electroless plating, any suitable deposition process, and combinations of the foregoing. After the deposition process, a planarization process may be performed so that the top surfaces of the interlayer dielectric layer 950, gate vias 916, and source/drain vias 930 may be substantially coplanar (eg, on the same plane). In some embodiments, gate vias 916 and source/drain vias 930 may be formed using tungsten, aluminum, cobalt, silver, any suitable conductive material, and combinations of the foregoing. In some embodiments, gate via 916 may extend through second portion 932B and self-aligned contact 810 and physically contact gate electrode 216 .

Figures 10A-10D show a semiconductor device 1000 with a single self-aligned contact scheme between terminals and a high rigidity seal as a contact etch stop and also as a gap seal, according to some embodiments. The structures shown in Figures 10A-10D are similar to those described in other figures (eg, Figures 2 and 8) and are not described in detail here for simplicity.

10A is a schematic cross-sectional view of a semiconductor device 1000 having terminals and spacers formed between the terminals, according to some embodiments. For example, semiconductor device 1000 may include gate electrode 216 and spacers 210 and 212 . In some embodiments, self-aligned contacts formed by using a high rigidity encapsulant can be formed after the source/drain contacts are formed. In some embodiments, the self-aligned contacts may be formed before the source/drain contacts are formed. The source/drain contacts can be formed by a replacement process, such as removing the dielectric layer and depositing a conductive layer in place of the dielectric layer. As shown in FIG. 10A , a dielectric layer 1020 is formed over the contact etch stop layer 214 and over the source/drain regions 240 . The dielectric layer 1020 may be formed by using materials similar to those used to form the interlayer dielectric layer 650 and the interlayer dielectric layer 950 . For example, the dielectric layer 1020 may be formed by using silicon oxide. Dielectric layer 1020 may be removed and replaced with one or more conductive materials, as further described in FIG. 10B below.

FIG. 10B is a schematic cross-sectional view of the semiconductor device 1000 after forming self-aligned contacts using a highly rigid sealing material and source/drain contacts. As shown in FIG. 10B , source/drain contacts 1030 are formed in place of the dielectric layer 1020 . In some embodiments, the source/drain contacts 1030 are formed by removing the dielectric layer 1020 and performing a deposition process to fill the voids left by the removal of the dielectric layer 1020 . The deposition process may include depositing conductive material until the top surface of the deposited conductive material is flush with the top surfaces of gate dielectric layer 218 and spacers 210 . The conductive material may comprise any suitable conductive material, such as metals, metal alloys, doped semiconductor materials, and/or combinations of the foregoing.

Self-aligned contact 1010 may be formed on gate electrode 216 by using an etch-back process similar to the etch-back process described above with reference to FIG. 8 for forming self-aligned contact 810 . For example, one or more etching processes may be performed to etch back and forth the gate electrode 216 to form openings between the sidewalls of the gate dielectric layer 218 . The high rigidity sealing material can be blanket deposited on the exposed surface and into the opening until the high rigidity sealing material completely fills the opening. A planarization process can be used to remove any excess high rigidity encapsulation material such that the self-aligned contacts 1010 are formed on the top surface of the recessed gate electrodes 216 . Self-aligned contacts 1010 may be formed using methods similar to those described above with reference to Figures 4A-4F. For example, the self-aligned contact 1010 can be formed by using high rigidity silicon carbide doped with oxygen. In some embodiments, the oxygen content of the self-aligned contacts 1010 can be adjusted according to device requirements.

FIG. 10C is a schematic cross-sectional view of the semiconductor device 1000 after a high rigidity encapsulation material is deposited in the gaps between the terminals of the semiconductor device, according to some embodiments. Similar to the process described with reference to FIG. 3 , the spacers 212 may be removed to form openings between the terminals of the semiconductor device 1000 . A high rigidity sealing material 1032 can be deposited in the opening and form the top towards the opening. The formation and properties of the high rigidity sealing material 1032 may be similar to the formation and properties of the high rigidity sealing material 532 described above with reference to FIGS. 4A , 4B and 5 .

According to some embodiments, FIG. 10D is a schematic cross-sectional view of the semiconductor device 1000 after the formation of the dielectric layer and the interconnect structure. As shown in FIG. 10D , the dielectric layer 1020 and the interlayer dielectric layer 1050 may be formed over the self-aligned contacts 1010 , the source/drain contacts 1030 , and other exposed structures of the semiconductor device 1000 . In some embodiments, the dielectric layer 1020 may be a contact etch stop layer. Gate vias 1016 and source/drain vias 1060 may be formed in the interlayer dielectric layer 1050 and extend through the dielectric layer 1020 . In some embodiments, gate vias 1016 may extend through dielectric layer 1020 and self-aligned contacts 1010 and physically contact gate electrodes 216 . In some embodiments, the dielectric layer 1020, the interlayer dielectric layer 1050, the gate vias 1016, and the source/drain vias 1060 may be similar to the dielectric layer 620, the interlayer dielectric layer 650, the gate vias, respectively 616 and source/drain vias 630 and are not described in detail here for simplicity.

Figures 11A and 11B show a semiconductor device 1100 with a single self-aligned contact scheme between terminals and a high rigidity encapsulant as a self-aligned contact, a contact etch stop, and also as a gap seal, according to some embodiments . The structures shown in Figures 11A and 11B are similar to those described in other figures (eg, Figures 8, 9A, 9B, and 10), and are not described in detail here for simplicity.

FIG. 11A is a schematic cross-sectional view of a semiconductor device 1100 having a highly rigid sealing material as self-aligned contacts, a contact etch stop layer, and a gap sealing layer. For example, the high rigidity sealing material 1132 may include a first portion 1132A formed between the terminals of the semiconductor device 1100 and serving as a gap sealing layer to form an air gap. The high rigidity encapsulation material 1132 may include a second portion 1132B formed on the top surfaces of the self-aligned contacts 1010, spacers 210, gate dielectric layer 218, source/drain contacts 1030, and other suitable structures. The first portion 1132A and the second portion 1132B of the high-rigidity sealing material 1132 may be similar to the first portion 932A and the second portion 932B of the high-rigidity sealing material 932 above with reference to FIGS. 9A and 9B , respectively, and for simplicity, are not Describe in detail. The second portion 1132B of the high-rigidity sealing material 1132 can serve as a contact etch stop layer for the subsequent formation of the dielectric layer and interconnect structure. The high rigidity sealing material 1132 can provide the advantages of high etch resistance, low leakage current and high uniformity. In some embodiments, low contamination benefits may also be provided by having self-aligned contacts, contact etch stop layers, and gap seal materials all formed using high rigidity encapsulation materials such as oxygen doped high rigidity silicon carbide, since the In-situ deposition of self-aligned contact and gap sealing material without the need to remove and load semiconductor device 1100 from one cavity to another.

According to some embodiments, FIG. 11B is a schematic cross-sectional view of the semiconductor device 1100 after the formation of the dielectric layer and the interconnect structure. As shown in FIG. 11B , an interlayer dielectric layer 1150 may be formed over the self-aligned contacts 1010 , the source/drain contacts 1030 , and other exposed structures of the semiconductor device 1100 . Gate vias 1116 and source/drain vias 1160 may be formed in the interlayer dielectric layer 1150 and extend through the second portion 1132B of the high rigidity sealing material 1132 . In some embodiments, gate via 1116 may extend through second portion 1132B and self-aligned contact 1010 and may physically contact gate electrode 216 . In some embodiments, ILD 1150 , gate vias 1116 and source/drain vias 1160 may be similar to ILD 650 , gate vias 616 and source/drain vias 630 , respectively , and are not described in detail here for the sake of simplicity.

FIG. 12 shows a semiconductor device 1200 having a dual self-aligned contact scheme between terminals and a high rigidity sealing layer as a gap sealing layer, according to some embodiments. The structure shown in Figure 12 is similar to the structure described in other figures (eg, Figures 2-11B), and for the sake of simplicity, will not be described in detail here. The dual self-aligned contact scheme includes self-aligned contacts formed on more than one type of terminal in the semiconductor device 1200 . For example, self-aligned contacts may be formed on gate electrode 216 . In some embodiments, self-aligned contacts 1210 may be formed on source/drain contacts 230 . Self-aligned contact 1210 may be formed by using materials similar to self-aligned contact 810 . For example, the self-aligned contacts 1210 can be formed by using silicon oxide. The high-rigidity sealing material 532 may be formed between the terminals of the semiconductor device 1200 as a gap sealing layer to form an air gap 1042 surrounded by the high-rigidity sealing material 532 , the spacers 210 and the contact etch stop layer 214 . In some embodiments, self-aligned contacts 1210 may be formed before self-aligned contacts 810 are formed. In some embodiments, the self-aligned contacts 1210 may be formed after the self-aligned contacts 810 are formed. The self-aligned contacts 810 and 1210 may be formed by an etch-back process to recess the terminals of the semiconductor device, followed by a deposition process to deposit a dielectric material on the recessed terminals of the semiconductor device. For example, the self-aligned contacts 1210 can be formed by recessing the source/drain contacts 230 through an etch-back process and depositing a dielectric material on the recessed source/drain contacts 230 . An exemplary semiconductor fabrication process for forming the semiconductor device 1200 may include etching back the gate electrode 216 and depositing a dielectric material on the recessed gate electrode 216 to form self-aligned contacts 810, in the source/drain regions Forming source/drain contacts 230 over 240, forming openings between terminals of semiconductor device 1200, forming high rigidity sealing material 532 in openings, depositing dielectric layer 620, depositing an interlayer dielectric layer on dielectric layer 620 650 , and gate vias 616 and source/drain vias 630 are formed in the interlayer dielectric layer 650 and through the dielectric layer 620 . In some embodiments, gate vias 616 and source/drain vias 630 may extend through self-aligned contacts 810 and 1210, respectively. Other operations may be used to form the semiconductor device 1200, and the order of the operations may be changed.

FIG. 13 shows a semiconductor device 1300 having a dual self-aligned contact scheme between terminals and a high rigidity sealing layer as a gap sealing layer and as a contact etch stop layer, according to some embodiments. The structure shown in FIG. 13 is similar to the structure described in other figures (eg, FIGS. 2-12 ), and is not described in detail here for the sake of simplicity. For example, the high rigidity encapsulant 932 may include a first portion 932A formed between the terminals of the semiconductor device 1300 and a second portion 932B formed on the top surface of the various structures. The second portion 932B may serve as a contact etch stop for forming the gate vias 916 and the source/drain vias 930 . Air gap 942 is surrounded by contact etch stop layer 214 , spacer 210 and high rigidity sealing material 932 . In some embodiments, the high rigidity sealing material 932 may be formed by using a manufacturing method similar to that described with reference to Figures 4A-4F. An exemplary semiconductor fabrication process for forming the semiconductor device 1300 may include etching back the gate electrode 216 and depositing a dielectric material on the recessed gate electrode 216 to form self-aligned contacts 810, in the source/drain regions source/drain contacts 230 are formed over 240, source/drain contacts 230 are etched back and dielectric material is deposited to form self-aligned contacts 1210, openings are formed between the terminals of semiconductor device 1300, in the openings A first portion 932A of the high-rigidity sealing material 932 is formed, and a second portion 932B is formed on the top surface of the terminal, an interlayer dielectric layer 950 is deposited on the high-rigidity sealing material 932, and in the interlayer dielectric layer 950 and through the high-rigidity Encapsulant 932 forms gate vias 916 and source/drain vias 930 . In some embodiments, gate vias 916 and source/drain vias 930 may extend through self-aligned contacts 810 and 1210, respectively. Other operations may be used to form the semiconductor device 1300, and the order of the operations may be changed.

FIG. 14 shows a semiconductor device 1400 having a dual self-aligned contact scheme between terminals and a high rigidity sealing layer as a gap sealing layer and can be used as a self-aligned contact for source/drain contacts, according to some embodiments . The structure shown in FIG. 14 is similar to the structure described in other figures (eg, FIGS. 2-13 ), and is not described in detail here for the sake of simplicity. In some embodiments, the high rigidity sealing material 1032 may be formed by using high rigidity silicon carbide doped with oxygen. In some embodiments, a high rigidity sealing material 1032 may be formed between the terminals of the semiconductor device 1400 . In some embodiments, self-aligned contacts 1460 may be formed on source/drain contacts 1030 . In some embodiments, the self-aligned contacts 1460 may be formed by using a material similar to the high rigidity sealing material 1032 . In some embodiments, self-aligned contacts 1460 may be formed using an etch-back process similar to that described above with reference to Figures 10A-10D. In some embodiments, the high rigidity sealing material 1032 and the self-aligned joints 1460 may be formed during the same manufacturing operation. For example, the source/drain contacts 1030 may be etched back to form notches between the sidewalls of the contact etch stop layer 1030 . One or more spacers between the terminals of the semiconductor device 1400 may be removed to form openings between the terminals. A fabrication process including deposition of high rigidity material and one or more processing steps may be used to deposit high rigidity material in the openings between the terminals and on the recessed source/drain contacts 1030 to form self-aligned contacts 1460 . In some embodiments, the high rigidity sealing material 1032 may be formed using the fabrication methods described above with reference to Figures 4A-4F. An exemplary fabrication process for forming semiconductor device 1400 may include etching back gate electrode 216 and depositing a dielectric material on recessed gate electrode 216 to form self-aligned contact 1010 over source/drain regions 240 Form source/drain contacts 1030, etch back source/drain contacts 1030, form openings between source/drain contacts 1030 and gate electrode 216, deposit high rigidity sealing material to form in openings High rigidity sealing material 1032 and forming self-aligned contacts 1460 on the source/drain contacts 1030, depositing a dielectric layer 1020 on the terminals and the top surface of the high rigidity sealing material 1032, performing a planarization process, depositing an interlayer dielectric electrical layer 1050 , and gate vias 1016 and source/drain vias 1060 are formed in the interlayer dielectric layer 1050 and through the dielectric layer 1020 . In some embodiments, gate vias 1016 and source/drain vias 1060 may extend through self-aligned contacts 1010 and 1460, respectively. Other operations may be used to form the semiconductor device 1400, and the order of the operations may be changed.

FIG. 15 shows a self-aligned contact with a dual self-aligned contact scheme and a high rigidity seal as a gap seal between terminals, source/drain contacts, and a contact etch stop layer, according to some embodiments. Semiconductor device 1500. The structure shown in FIG. 15 is similar to the structure described in other figures (eg, FIGS. 2-14 ) and is not described in detail here for the sake of simplicity. In some embodiments, the high rigidity encapsulation material 1132 may include a first portion 1132A formed between the terminals of the semiconductor device 1500 and a second portion 1132B extending horizontally and formed on top surfaces of the terminals. The terminals may include gate electrode 216 and source/drain contacts 1030 . In some embodiments, high rigidity materials may also be used to form self-aligned joints. For example, the self-aligned contacts 1510 for the source/drain contacts 1030 can be formed by using a high rigidity encapsulation material. In some embodiments, the self-aligned joints 1010 and the high rigidity sealing material 1132 may be formed in the same manufacturing step and composed of the same type of material. For example, the self-aligned contacts 1010 and the high rigidity sealing material 1132 may have approximately the same atomic percentage of oxygen. In some embodiments, the self-aligned joint 1010 and the high rigidity sealing material 1132 may be formed by using high rigidity materials having different compositions. The semiconductor device 1500 applying the dual self-aligned contact scheme may also include a self-aligned contact for the gate electrode 216 . For example, the self-aligned contact 1010 may be formed on the top surface of the gate electrode 216 . The self-aligned contact 1010 can be formed by using a high rigidity sealing material. In some embodiments, the self-aligned contacts 1010 may be formed using dielectric materials such as silicon nitride, silicon oxide, silicon oxynitride, silicon oxycarbide, silicon oxynitride, and any suitable dielectric material. An exemplary fabrication process for forming a semiconductor device 1500 with a dual self-aligned contact scheme and a high rigidity encapsulation material may include, for example, etching back the gate electrode 216, depositing a dielectric material on the recessed gate electrode 216 to form a self-contained gate electrode 216. Align contact 1010, form source/drain contact 1030 over source/drain region 240, etch back to recess source/drain contact 1030, between source/drain contact 1030 and gate An opening is formed between the electrode electrodes 216, a highly rigid sealing material is deposited in the opening and on the recessed source/drain contacts 1030 and the self-aligned contacts 1010, a planarization process is performed, an interlayer dielectric layer 1150 is formed, and Gate vias 1116 and source/drain vias 1160 are formed. In some embodiments, gate vias 1116 and source/drain vias 1160 may extend through self-aligned contacts 1010 and 1510, respectively. Other operations may be used to form the semiconductor device 1500, and the order of the operations may be changed.

FIG. 16 shows a semiconductor device 1600 having a dual self-aligned contact scheme and a high rigidity sealing layer as a gap sealing layer between terminals, a self-aligned contact for gate electrodes, and a contact etch stop layer, according to some embodiments. The structure shown in Fig. 16 is similar to the structure described in other figures (eg, Figs. 2-15), and is not described in detail here for the sake of simplicity. In some embodiments, the high rigidity encapsulation material 1132 may include a first portion 1132A formed between the terminals of the semiconductor device 1600 and a second portion 1132B extending horizontally and formed on the top surfaces of the terminals. In some embodiments, high rigidity materials may also be used to form self-aligned joints. For example, the self-aligned contact 1620 for the gate electrode 216 can be formed by using a high rigidity sealing material. In some embodiments, the self-aligned contacts 1620 and the high-rigidity sealing material 1132 may be formed in the same manufacturing step and composed of the same type of material. For example, the self-aligned contacts 1620 and the high rigidity sealing material 1132 may have approximately the same atomic percentage of oxygen. In some embodiments, the self-aligned contacts 1620 and the high rigidity sealing material 1132 may be formed by using high rigidity materials having different compositions. The semiconductor device 1600 employing the dual self-aligned contact scheme may also include self-aligned contacts for the source/drain contacts 1030 . For example, self-aligned source/drain contacts such as self-aligned contact 1610 may be formed on the top surface of source/drain contact 1030 . The self-aligned contacts 1610 can be formed by using a high rigidity sealing material. In some embodiments, self-aligned contacts 1610 may be formed by using dielectric materials such as silicon nitride, silicon oxide, silicon oxynitride, silicon oxycarbide, silicon oxynitride, and any suitable dielectric material. An exemplary fabrication process for forming a semiconductor device 1600 with a dual self-aligned contact scheme and a high rigidity encapsulation material may include, for example, etching back the gate electrode 216, depositing a high rigidity encapsulation material on the recessed gate electrode 216 to form Self-aligned contact 1620, forming source/drain contact 1030, forming self-aligned contact 1610 on source/drain contact 1030, between source/drain contact 1030 and gate electrode 216 An opening is formed between the openings, a high-rigidity sealing material is deposited in the opening and on the self-aligned contacts 1620 and 1610, a planarization process is performed, an interlayer dielectric layer 1150 is formed, and gate vias 1116 and source/drain vias are formed 1160. Other operations may be used to form the semiconductor device 1600, and the order of the operations may be changed.

Various embodiments of the present invention provide semiconductor devices and methods of fabricating the same to provide simple and cost-effective structures and processes for producing high rigidity encapsulation layers in semiconductor devices. High rigidity sealing layers can be used to seal openings and form air gaps between terminals of semiconductor devices to lower the effective dielectric constant, which in turn can improve device performance. A high rigidity encapsulant can also be formed on the top surface of the semiconductor device terminals as a contact etch stop layer. High rigidity sealing materials can also be used as self-aligned contacts for semiconductor device terminals.

In some embodiments, a semiconductor device includes a first terminal and a second terminal formed on the fin region and a sealing layer formed between the first terminal and the second terminal. The sealing layer includes an oxygen-doped silicon carbide material. The semiconductor device also includes an air gap surrounded by the encapsulation layer, the fin region, and the first and second terminals.

In some other embodiments, wherein the first terminal includes a gate electrode, and the second terminal includes a source/drain contact.

In some other embodiments, wherein the first terminal further comprises: a gate dielectric layer on the sidewall of the gate electrode; and a spacer including the first portion on the sidewall of the gate dielectric layer and the fin region Second part on top surface.

In some other embodiments, wherein the air gap physically contacts the first portion and the second portion of the spacer.

In some other embodiments, wherein the density of the sealing layer is between about 2.0 g/cm ³ and about 3.2 g/cm ³ .

In some other embodiments, wherein the oxygen atomic content of the sealing layer is between about 30% and about 55%.

In some other embodiments, wherein the carbon atom content of the sealing layer is between about 10% and about 35%.

In some other embodiments, the silicon atomic content of the sealing layer is between about 25% and about 35%.

In some other embodiments, wherein the top surfaces of the sealing layer, the first terminal, and the second terminal are substantially coplanar.

In some other embodiments, the semiconductor device further includes a self-aligned contact on the first terminal, wherein the self-aligned contact includes an oxygen-doped silicon carbide material and has a top surface substantially the same as the top surface of the sealing layer. coplanar.

In some embodiments, the semiconductor device includes a gate structure on the fin region. The gate structure includes a gate electrode and a self-aligned contact (SAC) formed on the gate electrode. The self-aligned contacts comprise an oxygen-doped silicon carbide material. The semiconductor device also includes source/drain (S/D) contacts and an encapsulation layer having an oxygen-doped silicon carbide material. The sealing layer further includes a first portion between the gate structure and the source/drain contacts and a second portion on the top surfaces of the self-aligned contacts and the source/drain contacts. Semiconductor devices also include air gaps surrounded by encapsulation layers, fin regions, gate electrodes, and source/drain contacts.

In some other embodiments, wherein the density of the sealing layer is between about 2.0 g/cm ³ and about 3.2 g/cm ³ .

In some other embodiments, wherein the oxygen atomic content of the sealing layer is between about 30% and about 55%.

In some other embodiments, the above-described semiconductor device further includes vias extending through the second portion of the sealing layer and in physical contact with the self-aligned contacts.

In some other embodiments, the above-described semiconductor device further includes a gate dielectric layer and a spacer, wherein the spacer includes a first portion on sidewalls of the gate dielectric layer and a second portion on a top surface of the fin region.

In some embodiments, a method of forming a semiconductor device includes forming an opening over a top surface of a substrate and between a first terminal and a second terminal of the semiconductor device. The method also includes forming a silicon carbide material, forming the silicon carbide material including depositing a first portion of the silicon carbide material in the opening and between the first terminal and the second terminal. The method also includes depositing a second portion of silicon carbide material on the top surfaces of the first and second terminals. The air gap is surrounded by an opening surrounded by the silicon carbide material, the first and second terminals, and the substrate. The method further includes performing an oxygen annealing process on the first and second portions of the deposited silicon carbide material.

In some other embodiments, wherein the first portion of the silicon carbide material is deposited toward the top of the opening.

In some other embodiments, wherein the steps of depositing the first and second portions of the silicon carbide material include flowing tetramethyldisiloxane, hydrogen and oxygen into the deposition chamber.

In some other embodiments, wherein the flow ratio of hydrogen to oxygen is between about 20 and about 30.

In some other embodiments, the above method further comprises: etching the first terminal to recess the first terminal; depositing another silicon carbide material on the recessed first terminal; and subjecting the deposited another silicon carbide material to another Oxygen annealing process.

It is to be understood that the embodiments, rather than the abstract, may be used to interpret the claims. The Summary of the Invention may set forth one or more, but not all, of the exemplary embodiments contemplated and, therefore, is not intended to limit the appended claims.

The foregoing context summarizes the features of many embodiments so that those skilled in the art may better understand the embodiments of the invention from various aspects. It should be understood by those skilled in the art that other processes and structures can be easily designed or modified based on the embodiments of the present invention to achieve the same purpose and/or to achieve the embodiments described herein. the same advantages. Those of ordinary skill in the art should also realize that such equivalent structures do not depart from the spirit and scope of the invention. Various changes, substitutions or modifications may be made to the embodiments of the present invention without departing from the spirit and scope of the invention.

100: FinFET 102: Substrate 104: Fin Structure 106: Source/Drain Regions 108, 208: Gate Structure 110, 210, 212: Spacers 110a, 110b, 110c: Spacer Portion 112: Shallow Trench Isolation Regions 116, 216: Gate electrode 118, 620, 1020: dielectric layer 120: gate cap layer 121, 221: fin region 122: gate work function metal layer 124: gate metal fill layer 200: semiconductor structure 214: contact etch stop layer 218: gate dielectric Layer 222: dashed lines 230, 1030: source/drain contacts 240: source/drain regions 302: openings 304, 440: regions 410A, 414A: fillets 412: first encapsulant 412A, 432A, 452B: corner portions 412B , 432B, 452A: Horizontal part 432: Second sealing material 432C: Vertical part 435, 462: Processing process 442, 542, 942, 1042: Air gap 452: Sealing layer 450: Gap 532, 932, 1032, 1132: High rigidity sealing material 616, 916, 1016, 1116: Gate Vias 630, 930, 1060, 1160: Source/Drain Vias 650, 950, 1050, 1150: Interlayer Dielectric Layer 700: Methods 702, 704, 706, 708, 710, 712: Operations 800, 900, 1000, 1100, 1200, 1300, 1400, 1500, 160 Devices 810, 1010, 1210, 1460, 1510, 1610, 1620: Self-aligned contacts 932A, 1132A: First part 932B, 1132B: Second part _118t , 120t, _122t : Thickness H1, _H2 , H3, H ₄ ,H ₅ : height

The embodiments of the present invention can be better understood according to the following detailed description and the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features in the illustrations are not necessarily drawn to scale. In fact, the dimensions of various components may be arbitrarily enlarged or reduced for clarity of illustration. FIG. 1 is an isometric view of a semiconductor structure in accordance with some embodiments. Figures 2-3, 4A-4F, and 5-6 are schematic cross-sectional views of various partially formed semiconductor structures according to some embodiments. FIG. 7 is a flowchart of a method of forming a double-layer sealing structure in a semiconductor structure according to some embodiments. Figures 8, 9A-9B, 10A-10D, 11A-11B, 12-16 are schematic cross-sectional views of various partially formed semiconductor structures according to some embodiments.

210: Spacer

214: Contact etch stop layer

216: gate electrode

218: gate dielectric layer

221: Fin Area

222: Dotted line

1030: source/drain contacts

240: source/drain region

1132: High rigidity sealing material

1116: gate via hole

1160: Source/Drain Vias

1150: Interlayer dielectric layer

1600: Semiconductor Devices

1610, 1620: Self-aligning contacts

1132A: Part 1

1132B: Part II

Claims (13)

A semiconductor device, comprising: a first terminal and a second terminal formed on a fin region; a sealing layer formed between the first terminal and the second terminal; a spacer on the first terminal and on the fin region; a contact etch stop layer on the second terminal; and an air gap surrounded by the sealing layer, the spacer and the contact etch stop layer, and the air gap physically contacts the sealing layer, The spacer and the contact etch stop layer. The semiconductor device of claim 1, wherein the first terminal includes a gate electrode, and the second terminal includes a source/drain contact. The semiconductor device of claim 2, wherein the first terminal further comprises: a gate dielectric layer on the sidewall of the gate electrode; and the spacer including a gate dielectric layer on the sidewall of the gate electrode The first portion and a second portion on the top surface of the fin region. The semiconductor device of claim 3, wherein the air gap physically contacts the first portion and the second portion of the spacer. The semiconductor device of any one of claims 1 to 4, wherein the sealing layer comprises an oxygen-doped silicon carbide material. The semiconductor device of any one of claims 1 to 4, wherein the top surfaces of the sealing layer, the first terminal, and the second terminal are substantially coplanar. The semiconductor device of any one of claims 1 to 4, further comprising a self-aligned contact on the first terminal, wherein the self-aligned contact comprises an oxygen-doped silicon carbide material and has a top surface The face is substantially coplanar with the top surface of the sealing layer. A semiconductor device, comprising: a gate structure on a fin region, the gate structure comprising: a gate electrode; and a self-aligned contact formed on the gate electrode; a source/drain contacts; a contact etch stop layer contacting the source/drain contacts; a sealing layer comprising: a first portion between the gate structure and the source/drain contacts; and a second portion on the top surfaces of the self-aligned contacts and the source/drain contacts; a spacer on the fin region; and an air gap etched by the sealing layer, the spacer and the contact Stop layers around. The semiconductor device of claim 8, further comprising a via hole extending through the second portion of the sealing layer and in physical contact with the self-aligned contact. The semiconductor device of claim 8 or 9, wherein the spacer comprises a first portion on the sidewall of the gate dielectric layer and a second portion on the top surface of the fin region. A method of forming a semiconductor device, comprising: forming an opening over a top surface of a substrate and between a first terminal and a second terminal of the semiconductor device; and forming an opening in the opening and between the first terminal and the second terminal A silicon carbide material is deposited between the terminals, wherein an air gap is enclosed by the opening surrounded by the silicon carbide material, the first and second terminals and the substrate; performing an oxygen annealing process on the silicon carbide material; and depositing a dielectric layer on the top surfaces of the silicon carbide material, the first terminal and the second terminal. The method of forming a semiconductor device of claim 11, wherein a first portion of the silicon carbide material is deposited toward the top of the opening. The method for forming a semiconductor device of claim 11 or 12, further comprising: etching the first terminal to recess the first terminal; depositing another silicon carbide material on the recessed first terminal; Another silicon carbide material undergoes another oxygen annealing process.

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