TWI759022B - Semiconductor devices and methods for forming the same - Google Patents
Semiconductor devices and methods for forming the same Download PDFInfo
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- TWI759022B TWI759022B TW109145308A TW109145308A TWI759022B TW I759022 B TWI759022 B TW I759022B TW 109145308 A TW109145308 A TW 109145308A TW 109145308 A TW109145308 A TW 109145308A TW I759022 B TWI759022 B TW I759022B
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Classifications
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
- H01L29/4991—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material comprising an air gap
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- H—ELECTRICITY
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
- H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/764—Air gaps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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Abstract
Description
本發明實施例係有關於半導體技術,且特別是有關於半導體裝置及其形成方法。Embodiments of the invention relate to semiconductor technology, and more particularly, to semiconductor devices and methods of forming the same.
積體電路(integrated circuit,IC)產業已經歷了快速成長。在積體電路材料和設計上的技術進步產生了數代積體電路,每一代都比前一代具有更小且更複雜的電路。在積體電路的發展史中,功能密度(即每一晶片區互連的裝置數目)增加,同時幾何尺寸(即製造過程中所產生的最小的組件或線路)縮小。此元件尺寸微縮化的製程提供增加生產效率與降低相關費用的益處。The integrated circuit (IC) industry has experienced rapid growth. Technological advances in integrated circuit materials and design have produced generations of integrated circuits, each generation having smaller and more complex circuits than the previous generation. In the history of integrated circuits, functional density (ie, the number of devices interconnected per wafer area) has increased while geometry size (ie, the smallest component or line produced during fabrication) has shrunk. This process of device size miniaturization provides the benefits of increased production efficiency and reduced associated costs.
在一些實施例中,提供半導體裝置,半導體裝置包含第一端子和第二端子,形成於鰭區上;密封層,形成於第一端子與第二端子之間;間隙壁,位於第一端子和鰭區上;接觸蝕刻停止層,位於第二端子上;以及空氣間隙,被密封層、間隙壁和接觸蝕刻停止層圍繞。In some embodiments, a semiconductor device is provided, the semiconductor device includes a first terminal and a second terminal formed on the fin region; a sealing layer formed between the first terminal and the second terminal; and a spacer between the first terminal and the second terminal on the fin region; a contact etch stop layer on the second terminal; and an air gap surrounded by the sealing layer, the spacers, and the contact etch stop layer.
在一些其他實施例中,提供半導體裝置,半導體裝置包含閘極結構,位於鰭區上,閘極結構包含閘極電極;及自對準接點,形成於閘極電極上;源極/汲極接點;接觸蝕刻停止層,接觸源極/汲極接點;密封層,包含第一部分,位於閘極結構與源極/汲極接點之間;及第二部分,位於自對準接點和源極/汲極接點的頂表面上;間隙壁,位於鰭區上;以及空氣間隙,被密封層、間隙壁和接觸蝕刻停止層圍繞。In some other embodiments, a semiconductor device is provided, the semiconductor device includes a gate structure on the fin region, the gate structure includes a gate electrode; and a self-aligned contact formed on the gate electrode; source/drain contact; contact etch stop layer, contacting source/drain contacts; sealing layer, comprising a first portion, located between the gate structure and the source/drain contact; and a second portion, located at the self-aligned contact and the top surfaces of the source/drain contacts; spacers, on the fin regions; and air gaps, surrounded by a sealing layer, spacers, and contact etch stop layers.
在另外一些實施例中,提供半導體裝置的形成方法,此方法包含在基底的頂表面上方及半導體裝置的第一端子與第二端子之間形成開口;以及在開口中和第一端子與第二端子之間沉積碳化矽材料,其中由碳化矽材料、第一端子和第二端子及基底圍繞的開口圍住空氣間隙;對碳化矽材料進行氧退火製程;以及在碳化矽材料、第一端子和第二端子的頂表面上沉積介電層。In other embodiments, a method of forming a semiconductor device is provided, the method comprising forming an opening over a top surface of a substrate and between a first terminal and a second terminal of the semiconductor device; and forming an opening in the opening and the first terminal and the second terminal depositing silicon carbide material between the terminals, wherein an air gap is enclosed by an opening surrounded by the silicon carbide material, the first and second terminals, and the substrate; performing an oxygen annealing process on the silicon carbide material; and A dielectric layer is deposited on the top surface of the second terminal.
要瞭解的是以下的揭露內容提供許多不同的實施例或範例,以實施提供之主體的不同部件。以下敘述各個構件及其排列方式的特定範例,以求簡化揭露內容的說明。當然,這些僅為範例並非用以限定本發明。例如,以下的揭露內容敘述了將一第一部件形成於一第二部件之上或上方,即表示其包含了所形成的上述第一部件與上述第二部件是直接接觸的實施例,亦包含了尚可將附加的部件形成於上述第一部件與上述第二部件之間,而使上述第一部件與上述第二部件可能未直接接觸的實施例。此外,揭露內容中不同範例可能使用重複的參考符號及/或用字。這些重複符號或用字係為了簡化與清晰的目的,並非用以限定各個實施例及/或所述外觀結構之間的關係。It is to be understood that the following disclosure provides many different embodiments or examples for implementing different components of the provided subject matter. Specific examples of various components and their arrangements are described below in order to simplify the description of the disclosure. Of course, these are only examples and are not intended to limit the present invention. For example, the following disclosure describes that a first part is formed on or over a second part, which means that it includes embodiments in which the formed first part and the second part are in direct contact, and also includes For example, an additional component may be formed between the first component and the second component, and the first component and the second component may not be in direct contact with each other. In addition, different examples in the disclosure may use repeated reference symbols and/or words. These repeated symbols or words are used for the purpose of simplicity and clarity, and are not used to limit the relationship between the various embodiments and/or the appearance structures.
再者,為了方便描述圖式中一元件或部件與另一(複數)元件或(複數)部件的關係,可使用空間相關用語,例如“在...之下”、“下方”、“下部”、“上方”、“上部”及類似的用語。除了圖式所繪示的方位之外,空間相關用語也涵蓋裝置在使用或操作中的不同方位。所述裝置也可被另外定位(例如,旋轉90度或者位於其他方位),並對應地解讀所使用的空間相關用語的描述。Furthermore, for convenience in describing the relationship of one element or component to another (plural) element or (plural) component in the drawings, spatially relative terms such as "under", "under", "under" may be used. ”, “above”, “upper” and similar terms. In addition to the orientation depicted in the drawings, spatially relative terms also encompass different orientations of the device in use or operation. The device may also be otherwise oriented (eg, rotated 90 degrees or at other orientations) and the description of the spatially relative terms used interpreted accordingly.
本文使用的術語“標稱的(nominal)”是指在產品或製程的設計階段期間設定的組件或製程操作的特性或參數的期望值或目標值,以及在期望值以上及/或以下的範圍值。數值的範圍一般為由於製造過程或公差導致的輕微變化。As used herein, the term "nominal" refers to expected or target values for characteristics or parameters of component or process operation set during the design phase of a product or process, as well as ranges of values above and/or below expected values. Values generally range for slight variations due to manufacturing processes or tolerances.
本文使用的術語“大約”、“大致”是指可依據與主體半導體裝置相關連的特定技術節點而改變之給定量的數值。在一些實施例中,基於特定技術節點,術語“大約”、“大致”可指例如在目標值的5%內(例如目標值的±1%、±2%、±3%、±4%、±5%)變化之給定的數值。As used herein, the terms "about" and "approximately" refer to a numerical value by a given amount that may vary depending on the particular technology node associated with the host semiconductor device. In some embodiments, the terms "about", "approximately" may refer to, for example, within 5% of the target value (eg, ±1%, ±2%, ±3%, ±4%, ±4%, ±5%) variation of the given value.
鰭可透過任何合適的方法圖案化。舉例來說,鰭可透過使用一個或多個光微影製程(包含雙重圖案化或多重圖案化製程)來圖案化。一般來說,雙重圖案化或多重圖案化製程結合了光微影和自對準製程,以創造具有較小間距的圖案,舉例來說,此圖案具有比使用單一直接光微影製程可獲得的間距更小的圖案。舉例來說,在一實施例中,犧牲層形成於基底上方並透過使用光微影製程圖案化。間隔物透過使用自對準製程形成於圖案化犧牲層旁邊。接著,移除犧牲層,且可接著使用剩下的間隔物將鰭圖案化。Fins can be patterned by any suitable method. For example, fins can be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. In general, double-patterning or multi-patterning processes combine photolithography and self-alignment processes to create patterns with smaller pitches that, for example, have a Patterns with smaller spacing. For example, in one embodiment, a sacrificial layer is formed over the substrate and patterned by using a photolithography process. Spacers are formed beside the patterned sacrificial layer by using a self-aligned process. Next, the sacrificial layer is removed, and the fins can then be patterned using the remaining spacers.
隨著平面半導體裝置(例如金屬氧化物半導體場效電晶體(metal-oxide-semiconductor field effect transistors,MOSFETs))透過各種技術節點微縮化,已提出了增加裝置密度和速度的其他方法。方法之一為三維場效電晶體的鰭式場效電晶體(fin field effect transistor,finFET),鰭式場效電晶體包含從基底延伸的鰭狀通道的形成。鰭式場效電晶體與傳統的互補金屬氧化物半導體(complementary metal-oxide-semiconductor,CMOS)製程相容,且鰭式場效電晶體的三維結構使其能夠積極地微縮化,同時維持閘極控制並緩和短通道效應。閘極堆疊物用於平面和三維場效電晶體,以控制半導體裝置的導電性。鰭式場效電晶體中包含閘極介電層和閘極電極的閘極堆疊物可透過取代閘極製程形成,其中以金屬閘極結構取代多晶矽犧牲閘極結構。閘極介電層(例如具有介電常數大於約3.9的介電層)形成於通道與閘極電極之間。間隙壁可設置於閘極堆疊物的側壁上,以在製造過程(例如離子佈植、閘極取代製程、磊晶源極/汲極結構形成和其他合適的製程)期間保護閘極結構。空氣間隙可用於取代間隙壁,以降低有效介電常數,進而可減少寄生電容並改善裝置效能。空氣間隙可透過在半導體裝置的端子之間的開口上方沉積密封材料,使得端子之間圍住空氣。密封材料或密封層可作為用以封閉開口的蓋層的結構。由於空氣的介電常數一般小於介電材料,因此可降低有效介電常數。然而,密封材料中的低順應性和低耐蝕性可導致半導體裝置中的缺陷。舉例來說,用於形成互連結構的製造過程(例如用於鰭式場效電晶體裝置的金屬源極/汲極和閘極端子的導通孔)可涉及對端子進行的多個蝕刻和清潔製程,這些蝕刻和清潔製程可透過縫隙蝕刻通過密封材料的一部份,並對空氣間隙造成損壞。損壞的範例可包含密封材料塌陷或將化學溶液困在空氣間隙中。此外,密封材料中的縫隙也可導致物理故障和電性短路。損壞的空氣間隙可導致半導體裝置中的缺陷,並導致低裝置產率,甚至裝置失效。As planar semiconductor devices, such as metal-oxide-semiconductor field effect transistors (MOSFETs), scale through various technology nodes, other approaches to increasing device density and speed have been proposed. One approach is the fin field effect transistor (finFET) of a three-dimensional field effect transistor that includes the formation of fin channels extending from a substrate. FinFETs are compatible with conventional complementary metal-oxide-semiconductor (CMOS) processes, and the three-dimensional structure of FinFETs enables them to be aggressively scaled while maintaining gate control and Alleviate the short channel effect. Gate stacks are used in planar and three-dimensional field effect transistors to control the conductivity of semiconductor devices. A gate stack including a gate dielectric layer and a gate electrode in a finFET can be formed by a replacement gate process, in which a polysilicon sacrificial gate structure is replaced with a metal gate structure. A gate dielectric layer (eg, a dielectric layer having a dielectric constant greater than about 3.9) is formed between the channel and the gate electrode. Spacers may be disposed on the sidewalls of the gate stack to protect the gate structures during fabrication processes such as ion implantation, gate replacement processes, epitaxial source/drain structure formation, and other suitable processes. Air gaps can be used to replace spacers to lower the effective dielectric constant, which in turn can reduce parasitic capacitance and improve device performance. Air gaps may enclose air between the terminals by depositing a sealing material over the openings between the terminals of the semiconductor device. The sealing material or the sealing layer can serve as the structure of the cover layer to close the opening. Since the dielectric constant of air is generally lower than that of dielectric materials, the effective dielectric constant can be lowered. However, low compliance and low corrosion resistance in encapsulation materials can lead to defects in semiconductor devices. For example, fabrication processes for forming interconnect structures, such as vias for metal source/drain and gate terminals of finFET devices, may involve multiple etching and cleaning processes for the terminals , these etching and cleaning processes can etch through a portion of the encapsulant through the crevice and cause damage to the air gap. Examples of damage may include collapse of the sealing material or trapping chemical solutions in air gaps. Additionally, gaps in the sealing material can also lead to physical failures and electrical shorts. Damaged air gaps can lead to defects in semiconductor devices and lead to low device yields and even device failures.
為了解決上述缺點,本揭露提供半導體裝置及其製造方法,以提供在半導體裝置中產生高剛性密封層之簡單且有成本效益的結構和製程。密封層可用於密封開口,並在半導體裝置的端子之間形成空氣間隙,且可用作後續形成結構(例如互連結構)的接觸蝕刻停止層 (contact etch stop layer,CESL)。特別來說,可使用高剛性密封層作為密封材料。舉例來說,可使用摻雜氧的高剛性碳化矽(highly rigid silicon carbide doped with oxygen,HRSCO)作為密封材料。也可形成摻雜氧的高剛性碳化矽作為蝕刻停止層。此外,摻雜氧的高剛性碳化矽層也可形成於半導體裝置的端子之間,且用作自對準接點(self-aligned contacts,SACs)。舉例來說,高剛性密封層也可形成於半導體裝置的端子上。端子可包含源極端子、汲極端子、閘極端子及/或其他合適的結構。To address the above disadvantages, the present disclosure provides a semiconductor device and a method of fabricating the same to provide a simple and cost-effective structure and process for producing a high rigidity sealing layer in a semiconductor device. The sealing layer can be used to seal openings and form air gaps between terminals of the semiconductor device, and can be used as a contact etch stop layer (CESL) for subsequent formation of structures such as interconnect structures. In particular, a high-rigidity sealing layer can be used as the sealing material. For example, highly rigid silicon carbide doped with oxygen (HRSCO) can be used as the sealing material. High rigidity silicon carbide doped with oxygen can also be formed as an etch stop layer. In addition, oxygen-doped high-rigidity silicon carbide layers can also be formed between terminals of semiconductor devices and used as self-aligned contacts (SACs). For example, high rigidity sealing layers may also be formed on terminals of semiconductor devices. The terminals may include source terminals, drain terminals, gate terminals, and/or other suitable structures.
在一些實施例中,高剛性密封層可透過沉積製程及之後的處理製程來形成。舉例來說,可沉積碳化矽層,接著進行氧退火製程,以增加沉積層中的氧含量。可改變各種沉積參數,以調整膜密度,且較大的密度可提供較大的剛性。高剛性密封層可沉積於半導體裝置端子的兩側側壁之間的開口中。高剛性密封層可沉積於開口的側壁並朝向開口的頂部,且沉積製程可持續直到兩側側壁的高剛性密封材料合併以物理接觸,並在兩側側壁之間形成密閉的空間。In some embodiments, the high rigidity sealing layer may be formed through a deposition process followed by a processing process. For example, a silicon carbide layer can be deposited, followed by an oxygen annealing process to increase the oxygen content in the deposited layer. Various deposition parameters can be varied to tune the film density, with greater densities providing greater stiffness. A high rigidity sealing layer may be deposited in the openings between the sidewalls of the semiconductor device terminals. The high-rigidity sealing layer may be deposited on the sidewalls of the opening toward the top of the opening, and the deposition process may continue until the high-rigidity sealing materials on the two sidewalls merge to physically contact and form a closed space between the two sidewalls.
在一些實施例中,增加高剛性密封層的密度可提供較大的抗蝕刻性。在一些實施例中,降低高剛性密封層的沉積速率可改善膜的一致性(例如一致的厚度)。在一些實施例中,高剛性密封層可透過使用合適的沉積製程來沉積,此沉積製程使用合適的前驅物,例如四甲基二矽氧烷(tetramethyldisiloxane,TSMDSO)、氫氣、氧氣和任何其他合適的前驅物。In some embodiments, increasing the density of the high rigidity sealing layer may provide greater etch resistance. In some embodiments, reducing the deposition rate of the high rigidity sealing layer can improve the uniformity (eg, uniform thickness) of the film. In some embodiments, the high rigidity sealing layer can be deposited by using a suitable deposition process using suitable precursors such as tetramethyldisiloxane (TSMDSO), hydrogen, oxygen and any other suitable precursor.
在一些實施例中,高剛性密封層為雙層密封材料,雙層密封材料可透過沉積第一密封材料、沉積第二密封材料,並對沉積的第一和第二密封材料進行至少一處理製程來形成。處理製程在沉積第一密封材料之後進行,在沉積第二密封材料之後進行,或沉積兩者之後都進行。第一和第二密封材料可為介電材料。第一密封材料沉積於開口的兩側側壁的一部分並朝向開口的頂部,且第二密封材料沉積於第一密封材料上及開口中的暴露表面上。第二密封材料沉積於在兩側側壁上的第一密封材料上。第二密封材料的沉積製程持續直到兩側側壁的第二密封材料合併,以在兩側側壁之間形成密閉空間。可對沉積的第一和第二密封材料進行處理製程,以至少透過第二密封材料的擴張來移除縫隙。在一些實施例中,處理製程可為在氧環境中進行的退火製程。在一些實施例中,第一密封材料的沉積速率大於第二密封材料的沉積速率。在一些實施例中,第一和第二密封材料可透過使用前驅物形成,例如四甲基二矽氧烷(TSMDSO)、氫氣、氧氣和任何其他合適的前驅物。In some embodiments, the high-rigidity sealing layer is a double-layered sealing material, and the double-layered sealing material can be formed by depositing a first sealing material, depositing a second sealing material, and performing at least one processing process on the deposited first and second sealing materials to form. The processing sequence is performed after the deposition of the first encapsulation material, after the deposition of the second encapsulation material, or after the deposition of both. The first and second sealing materials may be dielectric materials. A first sealing material is deposited on a portion of both sidewalls of the opening toward the top of the opening, and a second sealing material is deposited on the first sealing material and on exposed surfaces in the opening. The second sealing material is deposited on the first sealing material on both sidewalls. The deposition process of the second sealing material continues until the second sealing materials on the two sidewalls are combined to form a closed space between the two sidewalls. The deposited first and second encapsulant materials may be processed to remove gaps at least through expansion of the second encapsulant material. In some embodiments, the treatment process may be an annealing process performed in an oxygen environment. In some embodiments, the deposition rate of the first sealing material is greater than the deposition rate of the second sealing material. In some embodiments, the first and second encapsulation materials may be formed by using precursors such as tetramethyldisiloxane (TSMDSO), hydrogen, oxygen, and any other suitable precursors.
第1圖為例示性鰭式場效電晶體(fin field effect transistors,finFETs)結構的等角視圖。第2-7圖提供依據一些實施例之各種例示性半導體結構及製造過程,這些製造過程顯示具有空氣間隙和高剛性密封材料的多間隙壁結構的形成。第8-16圖提供用於形成空氣間隙、密封材料、接觸蝕刻停止層和半導體裝置的其他結構的各種結構和製造過程。密封材料和接觸蝕刻停止層可透過使用高剛性密封材料形成,高剛性密封材料提供較大的抗蝕刻性、改善的一致性及較小的漏電流。在一些實施例中,高剛性材料可為摻雜氧的高剛性碳化矽的材料。本文提供的製造過程為例示性的,且可依據本揭露進行替代製程(雖然這些製程未顯示於圖式中)。FIG. 1 is an isometric view of an exemplary fin field effect transistors (finFETs) structure. Figures 2-7 provide various exemplary semiconductor structures and fabrication processes showing the formation of multi-spacer structures with air gaps and high rigidity encapsulation materials in accordance with some embodiments. 8-16 provide various structures and fabrication processes for forming air gaps, encapsulation materials, contact etch stop layers, and other structures of semiconductor devices. The encapsulant and contact etch stop layer can be formed by using a high rigidity encapsulant that provides greater etch resistance, improved uniformity, and less leakage current. In some embodiments, the high stiffness material may be an oxygen doped high stiffness silicon carbide material. The fabrication processes provided herein are exemplary, and alternative processes may be performed in accordance with the present disclosure (although these processes are not shown in the drawings).
第1圖為依據一些實施例之半導體結構的等角視圖。鰭式場效電晶體100可被包含在微處理器、記憶體單元或其他積體電路。第1圖所示的鰭式場效電晶體100用於顯示目的,可未按照比例繪製。鰭式場效電晶體100可包含其他合適結構,例如額外的間隙壁、襯墊層、接觸結構,且為了清楚起見,第1圖未顯示任何其他合適結構。FIG. 1 is an isometric view of a semiconductor structure in accordance with some embodiments.
鰭式場效電晶體100可形成於基底102上,且鰭式場效電晶體100可包含具有鰭區121和源極/汲極區106的鰭結構104、設置於鰭結構104上的閘極結構108、設置於每個閘極結構108的兩側的間隙壁110和淺溝槽隔離(shallow trench isolation,STI)區112。第1圖顯示五個閘極結構108。然而,基於本文所揭露,鰭式場效電晶體100可具有更多或更少的閘極結構。此外,可透過使用其他結構組件(例如源極/汲極接觸結構、閘極接觸結構、導通孔、導線、介電層和保護層)將鰭式場效電晶體100加入至積體電路中,為了清楚起見,省略這些結構組件。The fin
基底102可為半導體材料,例如矽。在一些實施例中,基底102包含結晶矽基底(例如晶圓)。在一些實施例中,基底102包含元素半導體(例如鍺)、化合物半導體(包含碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銻化銦)、合金半導體(包含碳化矽鍺、矽鍺、磷化鎵砷、磷化鎵銦、砷化鎵銦、磷化鎵銦砷、砷化鋁銦及/或砷化鋁鎵或前述之組合。再者,取決於設計需求,基底102可被摻雜(例如p型基底或n型基底)。在一些實施例中,基底102可摻雜p型摻雜物(例如硼、銦、鋁或鎵)或n型摻雜物(例如磷或砷)。The
鰭結構104代表鰭式場效電晶體100的載流結構,且可沿Y軸延伸並通過閘極結構108。鰭結構104可包含在閘極結構108下方的鰭區121的部分以及設置於鰭區121的部分上的源極/汲極區106,源極/汲極區106形成於每個閘極結構108的兩側。鰭結構104的鰭區121在閘極結構108下方的部分(未顯示於第1圖)可延伸至淺溝槽隔離區112之上,且可由對應的閘極結構108環繞。可回蝕刻在閘極結構108兩側的鰭區121,使得源極/汲極區106可磊晶成長在鰭區121被回蝕刻的部分上。
鰭結構104的鰭區121可包含相似於基底102的材料,源極/汲極區106可包含磊晶成長半導體材料。在一些實施例中,磊晶成長的半導體材料與基底102為相同材料。在一些實施例中,磊晶成長的半導體材料包含與基底102不同的材料。磊晶成長的半導體材料可包含半導體材料(例如鍺和矽)、化合物半導體材料(例如砷化鎵和砷化鋁鎵)或半導體合金(例如矽鍺和磷化鎵砷)。用於鰭結構104的其他材料也在本發明實施例的範圍中。
在一些實施例中,源極/汲極區106可透過化學氣相沉積(chemical vapor deposition,CVD)、低壓化學氣相沉積(low pressure CVD,LPCVD)、超高真空化學氣相沉積(ultrahigh vacuum CVD,UHVCVD)、減壓化學氣相沉積(reduced pressure CVD,RPCVD)、合適的化學氣相沉積製程、分子束磊晶(molecular beam epitaxy,MBE)製程、合適的磊晶製程或前述之組合成長。在一些實施例中,源極/汲極區106可透過磊晶沉積/部分蝕刻製程成長,且至少重複一次磊晶沉積/部分蝕刻製程。這種重複的沉積/部分蝕刻製程也被稱為“循環沉積-蝕刻(cyclic deposition-etch,CDE)製程”。在一些實施例中,源極/汲極區106可透過選擇性磊晶成長(selective epitaxial growth,SEG)來成長,其中加入蝕刻氣體,以促進半導體材料選擇性成長於鰭結構的暴露表面上而不成長在絕緣材料(例如淺溝槽隔離區112的介電材料)上。用於磊晶成長源極/汲極區106的其他方法也在本發明實施例的範圍中。In some embodiments, the source/
源極/汲極區106可為p型區或n型區。在一些實施例中,p型源極/汲極區106可包含SiGe,且可在磊晶成長期間使用p型摻雜物(例如硼、銦和鎵)原位摻雜。對於p型原位摻雜,可使用p型摻雜前驅物,例如乙硼烷(B2
H6
)、三氟化硼(BF3
)和其他p型摻雜前驅物。在一些實施例中,n型源極/汲極區106可包含Si,且可在磊晶成長期間使用n型摻雜物(例如磷和砷)原位摻雜。對於n型原位摻雜,可使用n型摻雜前驅物,例如磷化氫(PH3
)、砷化氫(AsH3
)和其他n型摻雜前驅物。在一些實施例中,源極/汲極區106並非原位摻雜,且進行離子佈植製程來摻雜源極/汲極區106。The source/
間隙壁110可包含形成於閘極結構108的側壁上且接觸介電層118的間隙壁部分110a、形成於鰭結構104的側壁上的間隙壁部分110b以及形成作為淺溝槽隔離區112上的保護層的間隙壁部分110c。每個間隙壁部分也可為包含多於一個間隙壁結構的多間隙壁結構。舉例來說,間隙壁部分110a可包含多於一個間隙壁及形成於閘極結構108與鰭結構104之間的空氣間隙。密封材料可形成於空氣間隙上方,以封閉並保護空氣間隙免受後續製造過程影響。為了簡潔起見,空氣間隙和密封材料未顯示於第1圖中。間隙壁110可包含絕緣材料,例如氧化矽、氮化矽、低介電常數材料和前述之組合。間隙壁110可包含有著介電常數小於3.9(例如小於3.5、3和2.8)的低介電常數材料。由於空氣間隙可以具有介電常數約1,所以與使用低介電常數材料形成的間隙壁相比,可以進一步縮小間隙壁110的有效介電常數。間隙壁110的低介電常數材料可透過合適的沉積製程形成,例如原子層沉積(atomic layer deposition,ALD)。在一些實施例中,間隙壁110可透過使用化學氣相沉積、低壓化學氣相沉積、超高真空化學氣相沉積、減壓化學氣相沉積、物理氣相沉積(physical vapor deposition,PVD)、任何其他合適的沉積製程或前述之組合來沉積。在一些實施例中,密封材料可為高剛性材料,例如摻雜氧的高剛性碳化矽。在一些實施例中,密封材料可為多層密封材料,多層密封材料透過在形成於閘極結構108與源極/汲極區106之間的開口的頂部上沉積第一密封材料,接著在第一密封材料上沉積第二密封材料,以形成在開口中具有空氣的密封體來形成。用於間隙壁110的其他材料和厚度也在本本發明實施例的範圍中。The
每個閘極結構108可包含閘極電極116、與閘極電極116相鄰且接觸閘極電極116的介電層118和閘極蓋層120。閘極結構108可透過閘極取代製程形成。Each
在一些實施例中,介電層118可透過使用高介電常數介電材料(例如具有介電常數大於約3.9的介電材料)形成。介電層118可透過化學氣相沉積、原子層沉積、物理氣相沉積、電子束蒸鍍或其他合適的製程形成。在一些實施例中,介電層118可包含氧化矽層、氮化矽層及/或氮氧化矽層、高介電常數介電材料(例如HfO2
、TiO2
、HfZrO、Ta2
O3
、HfSiO4
、ZrO2
和ZrSiO2
)、具有鋰(Li)、鈹(Be)、鎂(Mg)、鈣(Ca)、鍶(Sr)、鈧(Sc)、釔(Y)、鋯(Zr)、鋁(Al)、鑭(La)、鈰(Ce)、鐠(Pr)、釹(Nd)、釤(Sm)、銪(Eu)、釓(Gd)、鋱(Tb)、鏑(Dy)、鈥(Ho)、鉺(Er)、銩(Tm)、鐿(Yb)或鎦(Lu)的氧化物\的高介電常數介電材料或前述之組合。高介電常數介電層可透過原子層沉積及/或其他合適的方法形成。在一些實施例中,介電層118可包含單一層或絕緣材料層的堆疊物。用於介電層118的其他材料和形成方法也在本發明實施例的範圍中。舉例來說,介電層118的一部分形成於水平表面上,例如淺溝槽隔離區112的頂表面上。雖然未顯示於第1圖,但是介電層118也可形成於在閘極電極116下方的鰭區121的頂部和側壁上。在一些實施例中,介電層118也可形成於閘極電極116的側壁與間隙壁部分110a之間,如第1圖所示。在一些實施例中,介電層118具有厚度118t在約1nm至約5nm的範圍中。In some embodiments, the
閘極電極116可包含閘極功函數金屬層122和閘極金屬填充層124。在一些實施例中,閘極功函數金屬層122設置於介電層118上。閘極功函數金屬層122可包含單一金屬層或金屬層的堆疊物。金屬層的堆疊物可包含具有彼此相似或彼此不同的功函數的金屬層。在一些實施例中,閘極功函數金屬層122可包含例如鋁(Al)、銅(Cu)、鎢(W)、鈦(Ti)、鉭(Ta)、氮化鈦(TiN)、氮化鉭(TaN)、矽化鎳(NiSi)、矽化鈷(CoSi)、銀(Ag)、碳化鉭(TaC)、氮化鉭矽(TaSiN)、氮化鉭碳(TaCN)、鈦鋁(TiAl)、氮化鈦鋁(TiAlN)、氮化鎢(WN)、金屬合金和前述之組合。閘極功函數金屬層122可透過使用合適的製程形成,例如原子層沉積、化學氣相沉積、物理氣相沉積、鍍覆或前述之組合。在一些實施例中,閘極功函數金屬層122具有厚度122t在約2nm至約15nm的範圍中。用於閘極功函數金屬層122的其他材料、形成方法和厚度也在本發明實施例的範圍中。The
閘極金屬填充層124可包含單一金屬層或金屬層的堆疊物。金屬層的堆疊物可包含具有彼此不同的金屬層。在一些實施例中,閘極金屬填充層124可包含合適的導電材料,例如Ti、Ag、Al、TiAlN、TaC、TaCN、TaSiN、Mn、Zr、TiN、TaN、Ru、Mo、WN、Cu、W、Co、Ni、TiC、TiAlC、TaAlC、金屬合金和前述之組合。閘極金屬填充層124可透過原子層沉積、物理氣相沉積、化學氣相沉積或其他合適的沉積製程形成。用於閘極金屬填充層124的其他材料和形成方法也在本發明實施例的範圍中。The gate
在一些實施例中,閘極蓋層120可具有厚度120t在約5nm至約50nm的範圍中,且可在鰭式場效電晶體100的後續加工期間保護閘極結構108。閘極蓋層120可包含氮化物材料,例如氮化矽、富矽氮化物和氮氧化矽。用於閘極蓋層120的其他材料也在本發明實施例的範圍中。In some embodiments, the
淺溝槽隔離區112可為鰭式場效電晶體100中整合或沉積於基底102上的相鄰主動和被動元件(未顯示於此)提供電性隔離。淺溝槽隔離區112可為介電材料,例如氧化矽、氮化矽、氮氧化矽、氟摻雜矽酸鹽玻璃(fluorine-doped silicate glass,FSG)、低介電常數介電材料和其他合適的絕緣材料。在一些實施例中,淺溝槽隔離區112可包含多層結構。鰭結構104、源極/汲極區106、閘極結構108、間隙壁110和淺溝槽隔離區112的剖面形狀為顯示性,但不限於此。Shallow
第2-6圖為依據一些實施例,提供各種例示性半導體結構和製造過程,這些圖式顯示具有空氣間隙和高剛性密封層的間隙壁結構的形成。高剛性密封層也可沒有縫隙。第7圖為依據本發明一些實施例,在半導體結構中形成空氣間隙和高剛性密封層的方法700的流程圖。基於本文的揭露,可進行方法700中的其他操作。再者,可以不同順序進行方法700的操作及/或改變操作。Figures 2-6, which provide various exemplary semiconductor structures and fabrication processes, show the formation of spacer structures with air gaps and high rigidity sealing layers in accordance with some embodiments. The high-rigidity sealing layer can also be free of gaps. FIG. 7 is a flow diagram of a
有著無縫隙密封層的空氣間隙可提供降低及/或消除對形成於間隙壁結構之間的空氣間隙造成的損壞的優點。可使用這些製造過程來形成平面半導體裝置或垂直半導體裝置,例如鰭式場效電晶體。在一些實施例中,第2-7圖顯示的製造過程可用於形成相似於第1圖所述之鰭式場效電晶體結構的半導體結構。舉例來說,第2-7圖顯示的半導體結構可相似於第1圖顯示之從切線A-A’所得到的製造的不同階段期間的鰭式場效電晶體100。An air gap with a seamless sealing layer can provide the advantage of reducing and/or eliminating damage to air gaps formed between spacer structures. These fabrication processes can be used to form planar semiconductor devices or vertical semiconductor devices, such as fin field effect transistors. In some embodiments, the fabrication processes shown in FIGS. 2-7 may be used to form semiconductor structures similar to the finFET structures described in FIG. 1 . For example, the semiconductor structures shown in FIGS. 2-7 may be similar to the
依據一些實施例,請參照第7圖的操作702,在基底上形成源極/汲極區和閘極堆疊物。第2圖為三個相鄰的閘極結構208和兩個源極/汲極接點230形成於基底上方之後的半導體結構200的剖面示意圖。基底可包含鰭區221。每個閘極堆疊物(例如閘極結構208)包含閘極介電層218和閘極電極216。閘極介電層218可形成於閘極電極216的側壁和底表面上。半導體裝置的通道區(例如鰭式場效電晶體100)可形成於鰭區221中以及閘極結構208下方。Referring to
鰭區221可為形成於基底上的載流半導體結構。舉例來說,鰭區221可相似於第1圖中上述的鰭區121。在一些實施例中,鰭區221可包含半導體材料,例如鍺、矽、碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦、銻化銦、碳化矽鍺、矽鍺、磷化鎵砷、磷化鎵銦、砷化鎵銦、磷化鎵銦砷、砷化鋁銦及/或砷化鋁鎵、任何合適的材料和前述之組合。在一些實施例中,鰭區221可摻雜p型或n型摻雜物。The
閘極介電層218可形成於鰭區221上,且透過使用高介電常數介電材料形成。閘極介電層218可透過化學氣相沉積、原子層沉積、物理氣相沉積、電子束蒸鍍或其他合適的製程沉積。在一些實施例中,閘極介電層218可包含高介電常數介電材料,例如HfO2
。在一些實施例中,閘極介電層218可包含TiO2
、HfZrO、Ta2
O3
、HfSiO4
、ZrO2
和ZrSiO2
。在一些實施例中,閘極介電層218可包含相似於第1圖中的上述介電層118。The
閘極電極216可形成於閘極介電層218上,且可包含單一金屬層或金屬層的堆疊物。閘極結構208可更包含功函數層,且為了簡潔起見,功函數層不顯示於第2圖中。金屬層的堆疊物可包含具有彼此相似或彼此不同的功函數的金屬層。在一些實施例中,閘極電極216可由導電材料形成,例如Al、Cu、W、Ti、Ta、TiN、TaN、NiSi、CoSi、Ag、TaC、TaSiN、TaCN、TiAl、TiAlN、WN、金屬合金和前述之組合。閘極電極216可透過使用合適的沉積製程形成,例如原子層沉積、化學氣相沉積、物理氣相沉積、鍍覆或前述之組合。用於閘極電極216的其他材料和形成方法也在本發明實施例的範圍中。在一些實施例中,閘極電極216可透過使用閘極取代製程形成,其中移除多晶矽閘極,並在移除多晶矽閘極之後的位置形成金屬閘極電極。
間隙壁結構可形成於閘極結構208的側壁上。在一些實施例中,閘極結構可包含閘極電極、介電層、間隙壁、任何其他合適的結構,且為了方便描述,可被統稱為閘極結構。在一些實施例中,間隙壁210和212形成於閘極介電層218的側壁和鰭區221的頂表面上。間隙壁結構形成於閘極電極216的側壁上,以在後續加工期間保護閘極介電層218和閘極電極216。在一些實施例中,間隙壁210可具有L形剖面,其中有著形成於閘極介電層218的側壁上的垂直部分以及形成於鰭區221的頂表面上的水平部分。在一些實施例中,間隙壁210僅形成於閘極介電層218的側壁上。間隙壁210可透過使用介電材料形成,例如氮碳化矽、氮化矽、氧化矽、任何合適的介電材料和前述之組合。在一些實施例中,對於使用氮碳化矽的間隙壁210,碳原子含量可小於約30%。在一些實施例中,間隙壁210的碳原子含量可在約20%與約30%之間。也可形成額外的間隙壁,例如間隙壁212。舉例來說,間隙壁212可形成於間隙壁210的水平部分上、鰭區221的頂表面上或這兩者上。在一些實施例中,間隙壁212可透過使用介電材料形成,例如矽。在一些實施例中,形成間隙壁210和212的材料可具有高蝕刻選擇性(例如大於約10),使得當移除間隙壁212時,間隙壁210可保持大致完整。在一些實施例中,間隙壁210和212可透過使用任何合適的介電材料形成,例如氮化矽、氮氧化矽、碳化矽、碳氧化矽、玻璃上覆矽(silicon on glass,SOG)、四乙氧基矽烷(tetraethoxysilane,TEOS)、聚乙二醇(poly(ethylene oxide,PE-oxide)、高深寬比製程(high aspect ratio process,HARP)形成的氧化物和前述之組合。在一些實施例中,間隙壁210和212可透過使用低介電常數介電材料形成。Spacer structures may be formed on sidewalls of the
源極/汲極(S/D)區240可形成於鰭區221中。源極/汲極區240可為p型區或n型區。在一些實施例中,源極/汲極區240可包含SiGe,且可在磊晶成長期間使用p型摻雜物(例如硼、銦和鎵)原位摻雜。對於p型原位摻雜,可使用p型摻雜前驅物,例如B2
H6
、BF3
和其他p型摻雜前驅物。在一些實施例中,n型源極/汲極區106可包含Si,且可在磊晶成長期間使用n型摻雜物(例如磷和砷)原位摻雜。對於n型原位摻雜,可使用n型摻雜前驅物,例如PH3
、AsH3
和其他n型摻雜前驅物。在一些實施例中,源極/汲極區240並非原位摻雜,且進行離子佈植製程來摻雜源極/汲極區240。在一些實施例中,源極/汲極區240可相似於第1圖中上述的源極/汲極區106。Source/drain (S/D)
源極/汲極(S/D)接點230可物理及電性接觸源極/汲極區240。源極/汲極接點230可透過沉積導電材料於相鄰閘極結構208之間來形成。舉例來說,開口可形成於間隙壁212之間,以暴露出下方的源極/汲極區240。可進行沉積製程,以在開口中沉積導電材料,使得形成電性連接。在一些實施例中,在沉積導電材料之前,可在開口中沉積接觸蝕刻停止層(contact etch stop layer,CESL)214。導電材料沉積製程的範例可包含物理氣相沉積、濺鍍、電鍍、無電電鍍、任何合適的沉積製程和前述之組合。在沉積製程之後,可進行平坦化製程,使得閘極電極216、間隙壁210和212、接觸蝕刻停止層214以及源極/汲極接點230的頂表面大致共平面(例如平坦表面)。在一些實施例中,源極/汲極接點230可透過使用鎢、鋁、鈷、銀、任何合適的導電材料和前述之組合形成。Source/drain (S/D)
相似於第1圖所描述的鰭式場效電晶體100,半導體結構200可形成於基底上,其中鰭區221從淺溝槽隔離區突出。淺溝槽隔離區未顯示於第2圖的半導體結構200的剖面示意圖中,但是為了方便描述,以虛線222表示淺溝槽隔離區的頂表面。Similar to the
依據一些實施例,請參照第7圖的操作704,移除一個或多個間隙壁,以在半導體裝置的端子之間形成開口。第3圖為在移除一個或多個間隙壁以形成開口之後的半導體裝置的剖面示意圖。半導體裝置的端子的範例可為閘極結構、源極/汲極結構或任何其他合適結構。第3圖所示的閘極結構208可包含閘極介電層218和閘極電極216。在一些實施例中,閘極結構208也可包含間隙壁210。源極/汲極結構可包含源極/汲極接點230和接觸蝕刻停止層214。在一些實施例中,源極/汲極結構可更包含形成於鰭區221中的源極/汲極區240。在操作704期間,可移除在閘極電極216與源極/汲極接點230之間的一個或多個間隙壁。舉例來說,可移除間隙壁212,以形成透過間隙壁210和接觸蝕刻停止層214圍繞的開口302。可使用一個或多個蝕刻製程,以移除間隙壁212。在一些實施例中,可使用間隙壁212相對於半導體結構200中的其他結構具有高蝕刻選擇性的蝕刻製程,以移除間隙壁212,同時保持其他暴露結構完整。舉例來說,間隙壁212可透過使用氮碳化矽形成,且可使用濕蝕刻製程及/或電漿蝕刻,以選擇性移除間隙壁212。Referring to
第4A和4B圖顯示依據一些實施例之使用循環沉積/處理製程形成高剛性密封層的製造過程的剖面示意圖。第4C-4F圖顯示依據一些實施例之使用多沉積製程形成高剛性密封層的剖面示意圖。第4A-4F圖為第3圖的區域304的放大圖。其他結構可被包含在第4A-4F圖所示的結構中,但為了簡潔起見,不顯示其他結構。4A and 4B show schematic cross-sectional views of a fabrication process for forming a high rigidity seal layer using a cyclic deposition/processing process according to some embodiments. 4C-4F show cross-sectional schematic diagrams of forming a high rigidity sealing layer using multiple deposition processes according to some embodiments. Figures 4A-4F are enlarged views of
依據一些實施例,請參照第7圖的操作706,在半導體裝置的開口的至少頂部角落上沉積密封層。第4A圖顯示在沉積密封材料於半導體裝置的開口的至少頂部角落上之後的半導體裝置的剖面示意圖。密封層452沉積於半導體裝置中的結構暴露的頂表面上,例如閘極電極216、閘極介電層218、源極/汲極接點230、接觸蝕刻停止層214和其他結構的頂表面。在一些實施例中,密封層452也可沉積於開口302中。舉例來說,密封層452可沉積於間隙壁210和接觸蝕刻停止層214的側壁上。在一些實施例中,密封層452可沉積於開口302的底部上,例如沉積於間隙壁210形成於鰭區221上的水平部分的頂表面上。在一些實施例中,如果鰭區221的頂表面的一部分暴露於間隙壁210與接觸蝕刻停止層214之間,密封層452也可形成於鰭區221上。密封層452可具有形成於閘極電極216、閘極介電層218、源極/汲極接點230的頂表面上的水平部分452A,以保護這些半導體結構免受後續製造過程影響。舉例來說,水平部分452A可防止下方材料在後續蝕刻或處理製程期間氧化。密封層452也可包含形成於間隙壁210和接觸蝕刻停止層214上的角落部分452B。間隙壁210和接觸蝕刻停止層214的頂表面分別具有圓角410A和414A,以促進密封層452的角落部分452B成長。相較於具有直角或尖銳邊緣的角落,圓角410A和414A的曲面可減少密封層452的空隙或不連續的形成。角落部分452B可與圓角410A和414A的曲面有相同輪廓。According to some embodiments, referring to
透過調整延伸至開口302中的密封層452的深度,密封層452可影響後續形成於半導體裝置的端子(例如閘極電極216與源極/汲極接點230)之間的空氣間隙的體積。特別來說,密封層452的角落部分452B透過形成於間隙壁210和接觸蝕刻停止層214的側壁上可延伸至開口302中。開口302可具有高度H1
和高深寬比(例如深寬比大於約10)。透過減少角落部分452B延伸至開口302,可實現空氣間隙442的較大高度H2
。H2
與H1
的較大比值可代表在開口302中的空氣間隙442具有較大體積。By adjusting the depth of the
密封層452可透過使用任何合適的介電材料形成。在一些實施例中,密封層452可透過使用提供足夠支撐空氣間隙結構的結構強度以及保護免受後續化學製程影響的耐化學性的材料形成。在一些實施例中,密封層452可包含矽-氧或矽-碳交聯。在一些實施例中,密封層452可透過使用自由基化學氣相沉積、化學氣相沉積、原子層沉積、低壓化學氣相沉積、超高真空化學氣相沉積、減壓化學氣相沉積、物理氣相沉積、任何其他合適的沉積製程和前述之組合來沉積。在一些實施例中,密封層452可以離子過濾器使用自由基化學氣相沉積製程來沉積。在一些實施例中,密封層452的沉積可包含將前驅物流入沉積腔體的第一操作。前驅物可提供一個或多個以下接合類型:矽-氧、矽-氫和矽-碳。在一些實施例中,前驅物為氣態,且可包含例如四甲基二矽氧烷(TSMDSO)、氫氣和氧氣。也可包含其他合適的前驅物。氫氣對氧氣的流量比值可大於約20,以最小化下方材料的氧化,同時促進沉積所需的化學反應。舉例來說,氫氣對氧氣的流量比值可在約20與約30之間。沉積可更包含第二操作,第二操作包含活化電漿,且用以活化氣態的前驅物,以在前驅物沉積於暴露表面上時形成矽-氧和矽-碳交聯。沉積於圓角410A和414A的密封層452的密封材料會逐漸堆積,最終合併以密封開口302,使得空氣間隙442與密封層452上方的環境物理隔離。空氣間隙442被密封層452、間隙壁210和接觸蝕刻停止層214圍繞並物理接觸密封層452、間隙壁210和接觸蝕刻停止層214。在一些實施例中,間隙壁210僅形成於閘極介電層218的側壁上,且空氣間隙442可物理接觸鰭區221。The
可透過密封層452的各種沉積參數的改變來調整空氣間隙442的高度H2
。舉例來說,降低密封層452的沉積速率可增加側壁上的密封材料進一步堆疊進入開口302的底部,導致空氣間隙442具有較小的高度H2
(例如較小的空氣間隙442)。在一些實施例中,沉積速率可約1 Å/min與約100 Å/min之間進行。在一些實施例中,沉積製程可在沉積速率大於約25 Å/min來進行。舉例來說,沉積製程可在速率約25 Å/min與約35 Å/min之間進行。在一些實施例中,沉積速率可在約55 Å/min與約65 Å/min之間進行。舉例來說,沉積速率可為約60 Å/min。可透過各種沉積參數調整沉積速率。在一些實施例中,在沉積期間的較小腔體壓力或較大電漿功率可提供較大的沉積速率。在一些實施例中,腔體壓力可在約0.5Torr與約12Torr之間。舉例來說,腔體壓力可在約0.5Torr與約3Torr之間、約3Torr與約7Torr之間、約7Torr與約12Torr之間以及任何合適的範圍/數值。作為另一範例,腔體壓力可在約4.5Torr與約5.5Torr之間,可提供沉積速率在約35 Å/min,而當腔體壓力在約6Torr與約7Torr之間時,可提供較小的沉積速率在約20 Å/min。The height H 2 of the
沉積製程的電漿功率水平也可影響沉積速率。舉例來說,在化學氣相沉積製程期間,較大的電漿功率水平可提供較大的沉積速率。在一些實施例中,電漿功率水平可在約500W與約3000W之間。舉例來說,電漿功率水平可在約500W與約1000W之間、在約1000W與約2000W之間、在約2000W與約3000W之間以及任何其他合適的功率水平。在一些實施例中,沉積製程可使用有著離子過濾器的自由基觸發的化學反應。The plasma power level of the deposition process can also affect the deposition rate. For example, during chemical vapor deposition processes, larger plasma power levels can provide larger deposition rates. In some embodiments, the plasma power level may be between about 500W and about 3000W. For example, the plasma power level may be between about 500W and about 1000W, between about 1000W and about 2000W, between about 2000W and about 3000W, and any other suitable power level. In some embodiments, the deposition process may use a radical-triggered chemical reaction with an ion filter.
密封層452的密度也可透過沉積參數來調整。增加密封層452的密度可提供較大的機械支撐和改善的耐化學性。在一些實施例中,密封層452可具有密度大於約2.0 g/cm3
。舉例來說,密封層452的密度可在約2.0 g/cm3
與約2.2 g/cm3
之間。在一些實施例中,密封層452的密度可在約2.2 g/cm3
與約3.2 g/cm3
之間。在一些實施例中,較大的密度可透過較小腔體加工壓力和較大電漿功率水平來達成。在一些實施例中,腔體加工壓力可在約0.5Torr與約12Torr之間。舉例來說,腔體加工壓力可在約0.5Torr與約3Torr之間、在約3Torr與約8Torr之間、在約8Torr與約12Torr之間以及任何其他合適的範圍或數值。The density of the
密封層452的介電常數可小於約5。在一些實施例中,密封層452可具有介電常數在約3.2與約5之間。密封層452的較小介電常數可使半導體結構200的端子有著較小的寄生電容。在一些實施例中,半導體結構200中的漏電流在2MV/cm可小於約1E-8
A/cm2
。The dielectric constant of the
依據一些實施例,請參照第7圖的操作708,對沉積的密封層進行處理製程。第4B圖為顯示進行處理製程之後的半導體裝置的剖面示意圖。According to some embodiments, referring to
可對密封層452進行處理製程462,以調整沉積的密封材料的氧含量。在一些實施例中,處理製程462可增加沉積的密封材料的氧含量。在一些實施例中,處理製程462可在氧腔體環境中進行。氧環境促進額外的Si-O-Si交聯形成於密封材料中,有效地以額外的氧原子摻雜密封材料。在一些實施例中,處理製程462可減少氧含量。在一些實施例中,處理製程462可在氫腔體環境中進行。在一些實施例中,處理腔體可在預定壓力下含有氫氣。氫環境有利於從沉積的密封材料中移除氧原子,進行形成更多個Si-C-Si交聯。在一些實施例中,密封層452的矽原子含量可在約25%與約35%之間。在一些實施例中,密封層452的氧原子含量可在約30%與約55%之間。在一些實施例中,密封層452的碳原子含量可在約10%與約35%之間。A
參考第4A和4B圖描述的沉積/處理製程為例示性的。在一些實施例中,可以循環的方式進行沉積/處理製程,直到達到沉積密封層的標稱的性質。舉例來說,可進行包含至少一次沉積操作和至少一次處理製程的循環多於一次,直到達到密封層452的標稱的厚度和質量。在一些實施例中,只進行一次此循環。在一些實施例中,處理製程可在填滿任何合適氣體的腔體環境中進行,例如氬、氮和任何合適的氣體。在一些實施例中,沉積及/或處理製程可在溫度約200 °C與約700 °C之間進行。舉例來說,沉積溫度可在約200 °C與約500 °C之間、約500 °C與約700 °C之間以及任何合適的溫度。The deposition/processing processes described with reference to Figures 4A and 4B are exemplary. In some embodiments, the deposition/treatment process may be performed in a cyclic fashion until the nominal properties of the deposited sealing layer are achieved. For example, more than one cycle including at least one deposition operation and at least one treatment process may be performed until the nominal thickness and quality of the
在一些實施例中,密封層452可透過雙層沉積製程沉積,如第4C-4F圖所描述。依據一些實施例,如第4C圖所示,第一密封材料沉積於半導體裝置的開口的至少角落上。第一密封材料412沉積於閘極電極216、閘極介電層218、源極/汲極接點230以及接觸蝕刻停止層214的頂表面上。在一些實施例中,第一密封材料412也可沉積於開口302中。舉例來說,第一密封材料412可沉積於間隙壁210和接觸蝕刻停止層214的側壁上。在一些實施例中,第一密封材料412可沉積於開口302的底部上,例如沉積於間隙壁210形成於鰭區221上的水平部分的頂表面上。在一些實施例中,如果鰭區221的頂表面的一部分暴露於間隙壁210與接觸蝕刻停止層214之間,第一密封材料412也可形成於鰭區221上。第一密封材料412可包含形成於間隙壁210和接觸蝕刻停止層214上的角落部分412A。間隙壁210和接觸蝕刻停止層214的頂表面分別具有圓角410A和414A,以促進第一密封材料412的角落部分412A成長。相較於具有直角或尖銳邊緣的角落,圓角410A和414A的曲面可減少第一密封材料412的空隙或不連續的形成。第一密封材料412的角落部分412A可與圓角410A和414A的曲面有相同輪廓。第一密封材料可具有形成於閘極電極216、閘極介電層218、源極/汲極接點230的頂表面上的水平部分412B,以保護閘極電極216、閘極介電層218、源極/汲極接點230免受後續製造過程影響。舉例來說,水平部分412B可防止下方材料在後續蝕刻或處理製程期間氧化。In some embodiments, the
透過調整延伸至開口302中的第一密封材料412的深度,第一密封材料412可影響後續形成於閘極電極216與源極/汲極接點230之間的空氣間隙的體積。特別來說,第一密封材料412的角落部分412A透過形成於間隙壁210和接觸蝕刻停止層214的側壁上可延伸至開口302中。角落部分412A的較大延伸高度H3
可提供開口302中較小的後續形成的空氣間隙(未顯示於第4C圖中)。舉例來說,H3
對H1
的較大比值可使用於形成空氣間隙的開口302留下較小體積。By adjusting the depth of the
第一密封材料412可透過使用任何合適的介電材料形成。在一些實施例中,第一密封材料412可透過使用提供足夠支撐空氣間隙結構的結構強度以及保護免受後續化學製程影響的耐化學性的材料形成。在一些實施例中,第一密封材料412可包含矽-氧或矽-碳交聯。在一些實施例中,第一密封材料412可透過使用自由基化學氣相沉積、化學氣相沉積、原子層沉積、低壓化學氣相沉積、超高真空化學氣相沉積、減壓化學氣相沉積、物理氣相沉積、任何其他合適的沉積製程和前述之組合來沉積。在一些實施例中,第一密封材料412可以離子過濾器使用自由基化學氣相沉積製程來沉積。在一些實施例中,第一密封材料412的沉積可包含將前驅物流入沉積腔體的第一操作。前驅物可提供一個或多個以下的接合類型:矽-氧、矽-氫和矽-碳。在一些實施例中,前驅物為氣態,例如四甲基二矽氧烷(TSMDSO)、氫氣和氧氣。也可包含其他合適的前驅物。氫氣對氧氣的流量比值可大於約20,以最小化下方材料的氧化,同時促進沉積所需的化學反應。舉例來說,氫氣對氧氣的流量比值可在約20與約30之間。沉積可更包含第二操作,第二操作包含活化電漿,且用以活化氣態的前驅物,以形成矽-氧和矽-碳交聯。沉積製程可包含第三操作的處理製程,以減少沉積的密封材料的氧含量。可在氫腔體環境中進行處理製程。在一些實施例中,處理製程可在具有任何合適類型的氣體的腔體環境中進行,例如氬、氮和任何合適的氣體。在一些實施例中,沉積製程可在溫度約300 °C與約700 °C之間進行。舉例來說,沉積溫度可在約300 °C與約500 °C之間、約500 °C與約700 °C之間以及任何其他合適的溫度。在一些實施例中,沉積和處理製程可在循環中進行,例如循環地沉積-處理製程。舉例來說,沉積和處理製程之後,可進行另一次沉積和處理製程,直到達到第一密封材料的標稱厚度或質量。The
可透過各種沉積參數調整沉積速率。較大的沉積速率可促進第一密封材料412在圓角410A和414A有較大的堆積。較小的沉積速率可提供第一密封材料412在開口302中有著較大的延伸高度H3
。較大的沉積速率可透過調整各種合適的加工參數來達成。在一些實施例中,沉積製程可在沉積速率大於約25 Å/min來進行。舉例來說,沉積製程可在速率約25 Å/min與約35 Å/min之間進行。在一些實施例中,沉積速率可在約55 Å/min與約65 Å/min之間進行。舉例來說,沉積速率可為約60 Å/min。在一些實施例中,在沉積期間的較小腔體壓力或較大電漿功率可提供較大的沉積速率。在一些實施例中,腔體壓力可在約0.5Torr與約12Torr之間。舉例來說,腔體壓力可在約0.5Torr與約3Torr之間、約3Torr與約7Torr之間、約7Torr與約12Torr之間以及任何合適的範圍/數值。作為另一範例,腔體壓力可在約4.5Torr與約5.5Torr之間,可提供沉積速率在約35 Å/min,而當腔體壓力在約6Torr與約7Torr之間時,可提供較小的沉積速率在約20 Å/min。The deposition rate can be adjusted through various deposition parameters. A greater deposition rate may promote greater buildup of the
用於沉積的電漿功率水平也可影響沉積速率。較大的電漿功率水平可提供較大的沉積速率。在一些實施例中,電漿功率水平可在約500W與約3000W之間。舉例來說,電漿功率水平可在約500W與約1000W之間、在約1000W與約2000W之間、在約2000W與約3000W之間以及任何其他合適的功率水平。The plasma power level used for deposition can also affect the deposition rate. Greater plasma power levels provide greater deposition rates. In some embodiments, the plasma power level may be between about 500W and about 3000W. For example, the plasma power level may be between about 500W and about 1000W, between about 1000W and about 2000W, between about 2000W and about 3000W, and any other suitable power level.
第一密封材料412的密度也可透過沉積參數來調整。增加第一密封材料412的密度可提供較大的機械支撐和改善的耐化學性。在一些實施例中,第一密封材料412可具有密度大於約2.0 g/cm3
。舉例來說,第一密封材料412的密度可在約2.0 g/cm3
與約2.2 g/cm3
之間。在一些實施例中,第一密封材料412的密度可在約2.2 g/cm3
與約3.2 g/cm3
之間。在一些實施例中,較大的密度可透過較小腔體加工壓力和較大電漿功率水平來達成。在一些實施例中,腔體加工壓力可在約0.5Torr與約12Torr之間。舉例來說,腔體加工壓力可在約0.5Torr與約3Torr之間、在約3Torr與約8Torr之間、在約8Torr與約12Torr之間以及任何其他合適的範圍或數值。在一些實施例中,電漿功率水平可在約500W與約3000W之間。舉例來說,電漿功率水平可在約500W與約2000W之間、在約2000W與約3000W之間以及任何其他合適的範圍或數值。在一些實施例中,沉積製程可以離子過濾器使用自由基觸發的化學反應來進行。The density of the
第一密封材料412的介電常數可小於約5。在一些實施例中,第一密封材料412可具有介電常數在約3.2與約5之間。第一密封材料412的較小介電常數可使半導體結構200的端子有著較小的寄生電容。在一些實施例中,半導體結構200中的漏電流在2MV/cm可小於約1E-8
A/cm2
。The dielectric constant of the
可對第一密封材料412進行選擇性的處理製程,以更增加第一密封材料412內部交聯的量及/或改善第一密封材料412的密度。舉例來說,可進行氫退火製程,以降低氧含量,並在第一密封材料412中形成額外的Si-C-Si鍵。氫處理製程也可移除化學副產物,例如H2
O。在一些實施例中,可進行選擇性的處理製程小於約1分鐘。舉例來說,可進行處理製程在約40秒與約1分鐘之間。A selective treatment process may be performed on the
第二密封材料可沉積於在第一密封材料上和開口中。第4D圖為顯示在沉積第二密封材料之後的半導體裝置的剖面示意圖。第二密封材料432沉積於第一密封材料412、間隙壁210和接觸蝕刻停止層214的表面的一部分上。第二密封材料432可包含至少:沉積於第一密封材料412的角落部分412A上的角落部分432A、沉積於第一密封材料412的水平部分412B上的水平部分432B以及沉積於間隙壁210和接觸蝕刻停止層214的側壁上的垂直部分432C。在一些實施例中,第二密封材料432可沉積於開口302的底部上,例如沉積於形成於鰭區221上的間隙壁210的水平部分的頂表面上。A second sealing material may be deposited on the first sealing material and in the opening. FIG. 4D is a schematic cross-sectional view showing the semiconductor device after deposition of the second encapsulation material. The
第二密封材料432可透過使用任何合適的沉積製程來沉積。舉例來說,第二密封材料432可透過使用化學氣相沉積製程來沉積。可將半導體結構200裝載至沉積腔體,且之後毯覆式沉積密封材料。隨著沉積腔體中的前驅物移動通過形成於第一密封材料412的兩側角落部分412A之間的開口以沉積於開口302的暴露表面上,相較於水平部分412B的頂表面,前驅物與間隙壁210和接觸蝕刻停止層214的表面接觸具有較小的可能性。因此,密封材料以小很多的速率沉積於開口302在角落部分412A下方的部分中。隨著密封材料逐漸堆積於第一密封材料412的兩側角落部分412A上,以形成第二密封材料432的角落部分432A,沉積於角落部分412A上方的角落部分432A會在區域440與沉積於另一側角落部分412A上方的另一個角落部分432A合併。在區域440處,縫隙450形成於第二密封材料432的相鄰的角落部分432A之間。The
透過調整延伸至開口302中的第二密封材料432的深度,第二密封材料432可影響後續形成於閘極電極216與源極/汲極接點230之間的空氣間隙的體積。特別來說,第二密封材料432的垂直部分432C可透過形成於間隙壁210和接觸蝕刻停止層214的側壁上來延伸至開口302中。測量縫隙450的下端與開口302的底表面之間的高度H4
。較大的高度H4
可提供較大的形成於閘極電極216與源極/汲極接點230之間的空氣間隙。測量在垂直部分432C的下端與開口302的底表面之間的高度H5
。By adjusting the depth of the
第二密封材料432可透過使用任何合適的介電材料形成。在一些實施例中,第二密封材料432可透過使用提供足夠支撐第一密封材料412的強度的材料形成。在一些實施例中,第二密封材料432可包含矽-氧或矽-碳交聯。在一些實施例中,第二密封材料432可透過使用自由基化學氣相沉積、化學氣相沉積、原子層沉積、低壓化學氣相沉積、超高真空化學氣相沉積、減壓化學氣相沉積、物理氣相沉積、任何其他合適的沉積製程和前述之組合來沉積。在一些實施例中,第二密封材料432可以離子過濾器使用自由基化學氣相沉積製程來沉積。在一些實施例中,第二密封材料432的沉積可相似於第一密封材料412的沉積。在一些實施例中,第二密封材料432可透過使用包含例如四甲基二矽氧烷(TSMDSO)、氫氣和氧氣的前驅物的化學氣相沉積製程來形成。也可使用其他合適的前驅物。氫氣對氧氣的流量比值可大於約20,以最小化下方材料的氧化,同時促進沉積所需的化學反應。舉例來說,氫氣對氧氣的流量比值可在約20與約30之間。沉積可更包含第二操作,第二操作包含活化電漿,且用以活化氣態的前驅物,以形成矽-氧和矽-碳交聯。在一些實施例中,沉積製程可在溫度約300 °C與約700 °C之間進行。舉例來說,沉積溫度可在約300 °C與約450 °C之間、約450 °C與約700 °C之間以及任何其他合適的溫度。The
可透過各種沉積參數調整沉積速率。可以比沉積第一密封材料412更小的沉積速率來沉積第二密封材料432。在一些實施例中,第二密封材料432可為大致順應性膜沉積於第一密封材料412的角落部分412A和水平部分412B上方。較大的沉積速率可促進第二密封材料432在角落部分412A有較大的堆積。較小的沉積速率可提供進第二密封材料432在開口302中有著較大的延伸。較大的沉積速率可透過調整各種合適的加工參數來達成。在一些實施例中,沉積製程可在沉積速率小於約30 Å/min來進行。舉例來說,沉積製程可在速率約20 Å/min與約30 Å/min之間進行。在一些實施例中,在沉積期間的較小腔體壓力或較大電漿功率可提供較大的沉積速率。在一些實施例中,腔體壓力可在約0.5Torr與約12Torr之間。舉例來說,腔體壓力可在約0.5Torr與約3Torr之間、約3Torr與約7Torr之間、約7Torr與約12Torr之間以及任何合適的範圍/數值。The deposition rate can be adjusted through various deposition parameters. The
用於沉積的電漿功率水平也可影響沉積速率。較大的電漿功率水平可提供較大的沉積速率。在一些實施例中,電漿功率水平可在約500W與約3000W之間。舉例來說,電漿功率水平可在約500W與約1000W之間、在約1000W與約2000W之間、在約2000W與約3000W之間以及任何其他合適的功率水平。The plasma power level used for deposition can also affect the deposition rate. Greater plasma power levels provide greater deposition rates. In some embodiments, the plasma power level may be between about 500W and about 3000W. For example, the plasma power level may be between about 500W and about 1000W, between about 1000W and about 2000W, between about 2000W and about 3000W, and any other suitable power level.
第二密封材料432的密度也可透過沉積參數來調整。增加第二密封材料432的密度可提供較大的機械支撐和改善的耐化學性。在一些實施例中,第二密封材料432可具有密度大於約2.0 g/cm3
。舉例來說,第二密封材料432的密度可在約2.0 g/cm3
與約2.5 g/cm3
之間。在一些實施例中,第二密封材料432的密度可在約2.2 g/cm3
與約2.5 g/cm3
之間。在一些實施例中,較大的密度可透過較小腔體加工壓力和較大電漿功率水平來達成。在一些實施例中,腔體加工壓力可在約0.5Torr與約12Torr之間。舉例來說,腔體加工壓力可在約0.5Torr與約3Torr之間、在約3Torr與約8Torr之間、在約8Torr與約12Torr之間以及任何其他合適的範圍或數值。在一些實施例中,電漿功率水平可在約500W與約3000W之間。舉例來說,電漿功率水平可在約500W與約2000W之間、在約2000W與約3000W之間以及任何其他合適的範圍或數值。在一些實施例中,沉積製程可以離子過濾器使用自由基觸發的化學反應來進行。The density of the
第二密封材料432的介電常數可相同或不同於第一密封材料412。舉例來說,第二密封材料432可具有介電常數小於約5。在一些實施例中,第二密封材料432可具有介電常數在約3.2與約5之間。在一些實施例中,半導體結構200中的漏電流在2MV/cm可小於約1E-8
A/cm2
。The dielectric constant of the
依據一些實施例,可對密封層的第一和第二密封材料進行處理製程。第4E圖顯示在進行處理製程之後的半導體裝置的剖面示意圖。可對第二密封材料432進行處理製程435,以移除縫隙,例如縫隙450。舉例來說,可進行氧退火製程,使得第二密封材料432物理擴張,並在縫隙450處形成額外鍵結。在氧退火製程期間,在第二密封材料432中的Si-C-Si鍵可變成Si-O-Si鍵。在一些實施例中,第二密封材料432的總碳原子比率可下降約5%與約15%之間。可進行氧處理製程小於約1分鐘。舉例來說,可進行處理製程約40秒與約1分鐘之間。在一些實施例中,處理製程435的氧流量可在約1sccm與約10sccm之間。舉例來說,氧流量可在約1sccm與約3sccm之間、約3sccm與約5sccm之間、約5sccm與約10sccm之間和任何其他合適數值。氧退火製程可移除任何縫隙(例如縫隙450),使得含有第二密封材料432的區域440沒有任何縫隙。According to some embodiments, a treatment process may be performed on the first and second sealing materials of the sealing layer. FIG. 4E shows a schematic cross-sectional view of the semiconductor device after processing. A
第4F圖顯示在對形成於不對稱的間隙壁上的密封材料進行處理製程之後,半導體裝置的剖面示意圖。如第4F圖所示,間隙壁210和接觸蝕刻停止層214分別沿閘極介電層218和源極/汲極接點230的側壁具有不同高度。舉例來說,間隙壁210和接觸蝕刻停止層214可由不同材料形成,且回應於形成圓角410A和414A的一個或多個間隙壁回蝕刻製程,接觸蝕刻停止層214的蝕刻速率可大於間隙壁210的蝕刻速率。因此,形成於接觸蝕刻停止層214之上的角落部分412A可沿源極/汲極接點230的側壁以及朝向源極/汲極區240和鰭區221向下延伸。FIG. 4F shows a schematic cross-sectional view of the semiconductor device after processing the encapsulation material formed on the asymmetric spacers. As shown in FIG. 4F, the
依據一些實施例,請參照第7圖的操作710,對高剛性密封層進行平坦化製程。第5圖為進行平坦化製程之後的半導體裝置的剖面示意圖。如第5圖所示,高剛性密封材料532形成於半導體結構200上,圍住空氣以在半導體結構200的端子與基底(例如鰭區221)之間形成空氣間隙542。在一些實施例中,高剛性密封材料532由摻雜氧的高剛性碳化矽形成。在一些實施例中,高剛性密封材料532為無縫隙密封材料。高剛性密封材料532可形成於間隙壁210與接觸蝕刻停止層214之間並接觸間隙壁210和接觸蝕刻停止層214。高剛性密封材料532也可接觸未顯示於第5圖的其他結構。可使用平坦化製程,以移除第4B圖顯示的水平部分452A或第4E圖顯示的第一密封材料412和第二密封材料432的一部分。可繼續平坦化製程,直到閘極電極216、閘極介電層218、間隙壁210、接觸蝕刻停止層214和源極/汲極接點230的頂表面暴露出來且大致齊平(例如在相同平面上)。在平坦化製程之後,密封層452的角落部分412A或第一密封材料412和第二密封材料432的剩下部分可形成高剛性密封材料532。透過高剛性密封材料532圍住的空氣可在半導體結構200的端子(例如閘極結構208與源極/汲極接點230)之間形成空氣間隙542。在一些實施例中,空氣間隙542可包含不同類型的空氣。舉例來說,空氣間隙542可包含氧、氫、氦、氬、氮、任何其他合適類型的空氣和前述之組合。高剛性密封材料532的較小沉積速率可導致具有較小體積的空氣間隙542。舉例來說,高剛性密封材料532可透過沉積密封層452或第一密封材料412和第二密封材料432形成,且較小的沉積速率可提供具有較小高度的空氣間隙542,導致較小的空氣間隙體積。由於空氣間隙542可具有介電常數約1,因此相較於由間隙壁210和212組成的間隙壁結構,間隙壁210和空氣間隙542的有效介電常數可較小。According to some embodiments, referring to
依據一些實施例,請參照第7圖的操作712,形成介電層和互連結構。第6圖為顯示形成於半導體裝置上的介電層和互連結構的剖面示意圖。Referring to
介電層620可形成於閘極電極216、閘極介電層218、間隙壁210、高剛性密封材料532、接觸蝕刻停止層214、源極/汲極接點230和其他合適的結構上。在一些實施例中,介電層620可為蝕刻停止層。介電層620可透過使用低介電常數介電材料(例如具有介電常數小於約3.9的介電層)形成,例如氧化矽。層間介電(inter-layer dielectric,ILD)層650可形成於介電層620上。層間介電層650可由低介電常數介電材料形成。舉例來說,層間介電層650可透過使用氧化矽形成。在一些實施例中,介電層620和層間介電層650可透過使用化學氣相沉積、原子層沉積、物理氣相沉積、可流動化學氣相沉積(flowable CVD,FCVD)、濺鍍、任何合適的沉積製程和前述之組合形成。導通孔可形成於層間介電層650中,以建立從源極/汲極接點230和閘極電極216至外部電路(例如形成於半導體結構200之上的周圍電路)的電性連接。閘極導通孔616可形成於層間介電層650中,並延伸通過介電層620,以物理接觸閘極電極216。相似地,源極/汲極導通孔630可延伸通過層間介電層650,並物理接觸源極/汲極接點230。閘極導通孔616和源極/汲極導通孔630可透過圖案化和蝕刻製程形成。舉例來說,開口可形成於層間介電層650中並通過介電層620,以分別暴露出閘極電極216和源極/汲極接點230。可進行沉積製程,以沉積導電材料於開口中,使得可建立電性連接。沉積製程的範例可為物理氣相沉積、濺鍍、電鍍、無電電鍍、任何合適的沉積製程和前述之組合。在沉積製程之後,可進行平坦化製程,使得層間介電層650、閘極導通孔616和源極/汲極導通孔630的頂表面可大致共平面(例如齊平)。在一些實施例中,閘極導通孔616和源極/汲極導通孔630可透過使用鎢、鋁、鈷、銀、任何合適的導電材料和前述之組合形成。
高剛性密封材料也可用作蝕刻停止層,以促進後續結構的形成,或用作閘極電極216和源極/汲極接點230的自對準接點(self-aligned contacts,SACs)。在一些實施例中,自對準接點可形成於閘極電極216及/或源極/汲極接點230的頂表面上。使用高剛性密封材料形成自對準接點可提供以下優點:防止電性短路、低漏電流、高一致性和良好的抗蝕刻性。在一些實施例中,自對準接點也可由介電材料形成,例如氮化矽、氧化矽、氮氧化矽、碳氧化矽、氮碳氧化矽、任何合適的介電材料及/或前述之組合。自對準接點可形成於閘極電極上、源極/汲極接點上或兩者上。為了清楚起見,使用單一自對準接點方案來描述具有自對準接點僅形成於單一類型端子(例如閘極電極或源極/汲極接點)上的半導體裝置。相似地,可使用雙重自對準接點方案來描述具有自對準接點形成於至少兩種類型端子(例如閘極電極和源極/汲極接點)上的半導體裝置。第8-16圖描述半導體裝置的各種配置,這些配置包含單一自對準接點方案和雙重自對準接點方案,這些方案具有高剛性密封層形成於間隙中,且作為接觸蝕刻停止層。在一些實施例中,透過參考第4A-4F圖的上述製造過程,高剛性密封層也可不含有縫隙。The high rigidity encapsulant can also be used as an etch stop layer to facilitate the formation of subsequent structures, or as self-aligned contacts (SACs) for
依據一些實施例,第8圖顯示具有形成於端子之間的間隙中的單一自對準接點方案和高剛性密封層的半導體裝置800。第8圖顯示的結構相似於第1-6圖描述的結構,且為了簡單起見,此處不再詳細描述。半導體裝置800可加入單一自對準接點方案,且包含形成於閘極電極216或源極/汲極接點230上的自對準接點。舉例來說,自對準接點810可形成於閘極電極216的頂表面上,如第8圖所示。在一些實施例中,自對準接點810可形成於源極/汲極接點230的頂表面上(未顯示於第8圖中)。自對準接點810可透過回蝕刻閘極電極216的一部分來形成,使得凹口形成於每個閘極電極216的頂部上及閘極介電層218的兩側側壁之間。介電材料可沉積於凹口中,以形成自對準接點810。在一些實施例中,自對準接點810可透過使用氧化矽、氮化矽、碳氧化矽、氮氧化矽、氮碳氧化矽、任何合適的介電材料和前述之組合。在一些實施例中,自對準接點810可在形成高剛性密封材料532之前形成。在一些實施例中,自對準接點810可在形成高剛性密封材料532之後形成。可進行平坦化製程,使得自對準接點810、閘極介電層218、間隙壁210、接觸蝕刻停止層214和高剛性密封材料532的頂表面大致共平面(例如在相同平面上)。介電層620、層間介電層650、閘極導通孔616和源極/汲極導通孔630可形成於平坦化的頂表面上。在一些實施例中,閘極導通孔616可延伸通過介電層620和自對準接點810,並物理接觸閘極電極216。FIG. 8 shows a
依據一些實施例,第9A和9B圖顯示在端子之間具有單一自對準接點方案和高剛性密封層作為接觸蝕刻停止層也可作為間隙密封層的半導體裝置900。第9A和9B圖顯示的結構相似於第1-8圖描述的結構,且為了簡單起見,此處不再詳細描述。如第9A圖所示,高剛性密封材料932可包含形成於半導體裝置900的端子之間的第一部分932A及形成於自對準接點810、閘極介電層218、間隙壁210、源極/汲極接點230和接觸蝕刻停止層214的頂表面上的第二部分932B。高剛性密封材料932可透過使用相似於上述第4A-4F圖和第7圖的方法來形成,且為了簡單起見,此處不再詳細描述。空氣間隙942可形成於半導體裝置900的端子之間,且空氣間隙942的尺寸可取決於各種因素,例如高剛性密封材料932的沉積速率。在一些實施例中,可依據裝置設計調整高剛性密封材料932的密度。舉例來說,增加高剛性密封材料932的密度可提供更大的抗蝕刻性。在一些實施例中,高剛性密封材料932的第二部分932B可用作形成後續結構的接觸蝕刻停止層,例如自對準接點810和源極/汲極接點230的導通孔,如以下參考第9B圖進一步描述。FIGS. 9A and 9B show a
如第9B圖所示,層間介電層950可形成於高剛性密封材料932的第二部分932B上。層間介電層950可相似於第6圖描述的層間介電層650。舉例來說,層間介電層950可透過使用氧化矽形成。在一些實施例中,層間介電層950可透過使用化學氣相沉積、原子層沉積、物理氣相沉積、可流動化學氣相沉積(FCVD)、濺鍍、任何合適的沉積製程和前述之組合形成。導通孔可形成於層間介電層950中,以建立從源極/汲極接點230和閘極電極216到外部電路(例如形成於半導體結構200之上的周圍電路)的電性連接。閘極導通孔916可形成於層間介電層950中,並延伸通過高剛性密封材料932的第二部分932B,以物理接觸閘極電極216。相似地,源極/汲極導通孔930可延伸通過層間介電層950,並物理接觸源極/汲極接點230。閘極導通孔916和源極/汲極導通孔930可透過圖案化和蝕刻製程形成。舉例來說,開口可形成於層間介電層950中,並透過圖案化和蝕刻製程以暴露出下方高剛性密封材料932的第二部分932B。第二部分932B在形成開口的製程期間可作為接觸蝕刻停止層。高剛性密封材料932的高密度(例如大於約2.0 g/cm3
)可提供改善的抗蝕刻性。可進行沉積製程,以在開口中沉積導電材料,以形成閘極導通孔916和源極/汲極導通孔930,以建立電性連接。沉積製程的範例可為物理氣相沉積、濺鍍、電鍍、無電電鍍、任何合適的沉積製程和前述之組合。在沉積製程之後,可進行平坦化製程,使得層間介電層950、閘極導通孔916和源極/汲極導通孔930的頂表面可大致共平面(例如在相同平面上)。在一些實施例中,閘極導通孔916和源極/汲極導通孔930可透過使用鎢、鋁、鈷、銀、任何合適的導電材料和前述之組合形成。在一些實施例中,閘極導通孔916可延伸通過第二部分932B和自對準接點810,並物理接觸閘極電極216。As shown in FIG. 9B , an
依據一些實施例,第10A-10D圖顯示在端子之間具有單一自對準接點方案和高剛性密封層作為接觸蝕刻停止層也可作為間隙密封層的半導體裝置1000。第10A-10D圖顯示的結構相似於其他圖式(例如第2和8圖)描述的結構,且為了簡單起見,此處不再詳細描述。Figures 10A-10D show a
依據一些實施例,第10A圖為具有端子和形成於端子之間的間隙壁的半導體裝置1000的剖面示意圖。舉例來說,半導體裝置1000可包含閘極電極216和間隙壁210和212。在一些實施例中,透過使用高剛性密封材料形成的自對準接點可在形成源極/汲極接點之後形成。在一些實施例中,自對準接點可在形成源極/汲極接點之前形成。源極/汲極接點可透過取代製程形成,例如移除介電層,並沉積導電層取代介電層。如第10A圖所示,介電層1020形成於接觸蝕刻停止層214上及源極/汲極區240之上。介電層1020可透過使用相似於形成層間介電層650和層間介電層950的材料來形成。舉例來說,介電層1020可透過使用氧化矽形成。可移除介電層1020,並以一個或多個導電材料取代介電層1020,如以下第10B圖進一步描述。10A is a schematic cross-sectional view of a
第10B圖為使用高剛性密封材料和源極/汲極接點形成自對準接點之後,半導體裝置1000的剖面示意圖。如第10B圖所示,形成源極/汲極接點1030取代介電層1020。在一些實施例中,源極/汲極接點1030透過移除介電層1020,並進行沉積製程以填充移除介電層1020所留下的空隙來形成。沉積製程可包含沉積導電材料,直到沉積的導電材料的頂表面與閘極介電層218和間隙壁210的頂表面齊平。導電材料可包含任何合適的導電材料,例如金屬、金屬合金、摻雜的半導體材料及/或前述之組合。FIG. 10B is a schematic cross-sectional view of the
自對準接點1010可透過使用回蝕刻製程形成於閘極電極216上,此回蝕刻製程相似於以上參考第8圖所述用於形成自對準接點810的回蝕刻製程。舉例來說,可進行一個或多個蝕刻製程來回蝕刻閘極電極216,以在閘極介電層218的兩側側壁之間形成開口。高剛性密封材料可毯覆式沉積於暴露表面上並進入開口中,直到高剛性密封材料完全填充開口。可使用平坦化製程,以移除任何多餘的高剛性密封材料,使得自對準接點1010形成於凹陷的閘極電極216的頂表面上。自對準接點1010可透過使用相似於以上參考第4A-4F圖所述的方法來形成。舉例來說,自對準接點1010可透過使用摻雜氧的高剛性碳化矽形成。在一些實施例中,可依據裝置需求調整自對準接點1010的氧含量。Self-aligned
依據一些實施例,第10C圖為在高剛性密封材料沉積於半導體裝置的端子之間的間隙中之後,半導體裝置1000的剖面示意圖。相似於參考第3圖所述的製程,可移除間隙壁212,以形成半導體裝置1000的端子之間的開口。高剛性密封材料1032可沉積於開口中,並形成朝向開口的頂部。高剛性密封材料1032的形成和性質可相似於以上參考第4A、4B和5圖所述的高剛性密封材料532的形成和性質。FIG. 10C is a schematic cross-sectional view of the
依據一些實施例,第10D圖為在形成介電層和互連結構之後,半導體裝置1000的剖面示意圖。如第10D圖所示,介電層1020和層間介電層1050可形成於自對準接點1010、源極/汲極接點1030和半導體裝置1000的其他暴露結構上方。在一些實施例中,介電層1020可為接觸蝕刻停止層。閘極導通孔1016和源極/汲極導通孔1060可形成於層間介電層1050中,並延伸通過介電層1020。在一些實施例中,閘極導通孔1016可延伸通過介電層1020和自對準接點1010,並物理接觸閘極電極216。在一些實施例中,介電層1020、層間介電層1050、閘極導通孔1016和源極/汲極導通孔1060可分別相似於介電層620、層間介電層650、閘極導通孔616和源極/汲極導通孔630,且為了簡單起見,此處不再詳細描述。According to some embodiments, FIG. 10D is a schematic cross-sectional view of the
依據一些實施例,第11A和11B圖顯示在端子之間具有單一自對準接點方案和高剛性密封層作為自對準接點、接觸蝕刻停止層,也可作為間隙密封層的半導體裝置1100。第11A和11B圖顯示的結構相似於其他圖式(例如第8、9A、9B和10圖)描述的結構,且為了簡單起見,此處不再詳細描述。Figures 11A and 11B show a
第11A圖為具有高剛性密封材料作為自對準接點、接觸蝕刻停止層和間隙密封層的半導體裝置1100的剖面示意圖。舉例來說,高剛性密封材料1132可包含形成於半導體裝置1100的端子之間且作為間隙密封層以形成空氣間隙的第一部分1132A。高剛性密封材料1132可包含形成於自對準接點1010、間隙壁210、閘極介電層218、源極/汲極接點1030和其他合適的結構的頂表面上的第二部分1132B。高剛性密封材料1132的第一部分1132A和第二部分1132B可分別相似於以上參考第9A和9B圖的高剛性密封材料932的第一部分932A和第二部分932B,且為了簡單起見,此處不再詳細描述。高剛性密封材料1132的第二部分1132B可作為後續形成介電層和互連結構的接觸蝕刻停止層。高剛性密封材料1132可提供高抗蝕刻性、低漏電流和高一致性的優點。在一些實施例中,透過具有自對準接點、接觸蝕刻停止層和間隙密封材料皆使用高剛性密封材料(例如摻雜氧的高剛性碳化矽)形成也可提供低汙染的優點,因為可原位沉積自對準接點和間隙密封材料,而不需要將半導體裝置1100從一個腔體移除並裝載至另一個腔體。FIG. 11A is a schematic cross-sectional view of a
依據一些實施例,第11B圖為形成介電層和互連結構之後,半導體裝置1100的剖面示意圖。如第11B圖所示,層間介電層1150可形成於自對準接點1010、源極/汲極接點1030和半導體裝置1100的其他暴露結構上方。閘極導通孔1116和源極/汲極導通孔1160可形成於層間介電層1150中,並延伸通過高剛性密封材料1132的第二部分1132B。在一些實施例中,閘極導通孔1116可延伸通過第二部分1132B和自對準接點1010,並可物理接觸閘極電極216。在一些實施例中,層間介電層1150、閘極導通孔1116和源極/汲極導通孔1160可分別相似於層間介電層650、閘極導通孔616和源極/汲極導通孔630,且為了簡單起見,此處不再詳細描述。According to some embodiments, FIG. 11B is a schematic cross-sectional view of the
依據一些實施例,第12圖顯示在端子之間具有雙重自對準接點方案和高剛性密封層作為間隙密封層的半導體裝置1200。第12圖顯示的結構相似於其他圖式(例如第2-11B圖)描述的結構,且為了簡單起見,此處不再詳細描述。雙重自對準接點方案包含形成於半導體裝置1200中的多於一個類型的端子上的自對準接點。舉例來說,自對準接點可形成於閘極電極216上。在一些實施例中,自對準接點1210可形成於源極/汲極接點230上。自對準接點1210可透過使用相似於自對準接點810的材料形成。舉例來說,自對準接點1210可透過使用氧化矽形成。高剛性密封材料532可形成於半導體裝置1200的端子之間作為間隙密封層,以形成被高剛性密封材料532、間隙壁210和接觸蝕刻停止層214圍繞的空氣間隙1042。在一些實施例中,自對準接點1210可在形成自對準接點810之前形成。在一些實施例中,自對準接點1210可在形成自對準接點810之後形成。自對準接點810和1210可透過回蝕刻製程以將半導體裝置的端子凹陷,接著以沉積製程在凹陷的半導體裝置的端子上沉積介電材料來形成。舉例來說,自對準接點1210可透過回蝕刻製程以將源極/汲極接點230凹陷,並在凹陷的源極/汲極接點230上沉積介電材料來形成。用於形成半導體裝置1200的例示性的半導體製造過程可包含回蝕刻閘極電極216並在凹陷的閘極電極216上沉積介電材料以形成自對準接點810,在源極/汲極區240上方形成源極/汲極接點230,在半導體裝置1200的端子之間形成開口,在開口中形成高剛性密封材料532,沉積介電層620,在介電層620上沉積層間介電層650,並在層間介電層650中並通過介電層620形成閘極導通孔616和源極/汲極導通孔630。在一些實施例中,閘極導通孔616和源極/汲極導通孔630可分別延伸通過自對準接點810和1210。可使用其他操作來形成半導體裝置1200,且可改變操作的順序。FIG. 12 shows a
依據一些實施例,第13圖顯示在端子之間具有雙重自對準接點方案和高剛性密封層作為間隙密封層且可作為接觸蝕刻停止層的半導體裝置1300。第13圖顯示的結構相似於其他圖式(例如第2-12圖)描述的結構,且為了簡單起見,此處不再詳細描述。舉例來說,高剛性密封材料932可包含形成於半導體裝置1300的端子之間的第一部分932A以及形成於各種結構的頂表面上的第二部分932B。第二部分932B可作為用於形成閘極導通孔916和源極/汲極導通孔930的接觸蝕刻停止層。空氣間隙942被接觸蝕刻停止層214、間隙壁210和高剛性密封材料932圍繞。在一些實施例中,高剛性密封材料932可透過使用相似於參考第4A-4F圖所述的製造方法來形成。用於形成半導體裝置1300的例示性的半導體製造過程可包含回蝕刻閘極電極216並在凹陷的閘極電極216上沉積介電材料以形成自對準接點810,在源極/汲極區240上方形成源極/汲極接點230,回蝕刻源極/汲極接點230並沉積介電材料以形成自對準接點1210,在半導體裝置1300的端子之間形成開口,在開口中形成高剛性密封材料932的第一部分932A,並在端子的頂表面上形成第二部分932B,在高剛性密封材料932上沉積層間介電層950,並在層間介電層950中並通過高剛性密封材料932形成閘極導通孔916和源極/汲極導通孔930。在一些實施例中,閘極導通孔916和源極/汲極導通孔930可分別延伸通過自對準接點810和1210。可使用其他操作來形成半導體裝置1300,且可改變操作的順序。FIG. 13 shows a
依據一些實施例,第14圖顯示在端子之間具有雙重自對準接點方案和高剛性密封層作為間隙密封層且可作為源極/汲極接點的自對準接點的半導體裝置1400。第14圖顯示的結構相似於其他圖式(例如第2-13圖)描述的結構,且為了簡單起見,此處不再詳細描述。在一些實施例中,高剛性密封材料1032可透過使用摻雜氧的高剛性碳化矽形成。在一些實施例中,高剛性密封材料1032可形成於半導體裝置1400的端子之間。在一些實施例中,自對準接點1460可形成於源極/汲極接點1030上。在一些實施例中,自對準接點1460可透過使用相似於高剛性密封材料1032的材料形成。在一些實施例中,自對準接點1460可透過使用相似於以上參考第10A-10D圖所述的回蝕刻製程形成。在一些實施例中,高剛性密封材料1032和自對準接點1460可在相同製造操作期間形成。舉例來說,可回蝕刻源極/汲極接點1030,以在接觸蝕刻停止層1030的兩側側壁之間形成凹口。可移除半導體裝置1400的端子之間的一個或多個間隙壁,以在端子之間形成開口。包含高剛性材料沉積及一個或多個處理製程的製造過程可用於在端子之間的開口中及凹陷的源極/汲極接點1030上沉積高剛性材料,以形成自對準接點1460。在一些實施例中,高剛性密封材料1032可透過使用以上參考第4A-4F圖所述的製造方法來形成。用於形成半導體裝置1400的例示性製造過程可包含回蝕刻閘極電極216並在凹陷的閘極電極216上沉積介電材料以形成自對準接點1010,在源極/汲極區240上方形成源極/汲極接點1030,回蝕刻源極/汲極接點1030,在源極/汲極接點1030與閘極電極216之間形成開口,沉積高剛性密封材料以在開口中形成高剛性密封材料1032及在源極/汲極接點1030上形成自對準接點1460,在端子和高剛性密封材料1032的頂表面上沉積介電層1020,進行平坦化製程,沉積層間介電層1050,並在層間介電層1050中並通過介電層1020形成閘極導通孔1016和源極/汲極導通孔1060。在一些實施例中,閘極導通孔1016和源極/汲極導通孔1060可分別延伸通過自對準接點1010和1460。可使用其他操作來形成半導體裝置1400,且可改變操作的順序。FIG. 14 shows a
依據一些實施例,第15圖顯示具有雙重自對準接點方案和高剛性密封層作為端子之間的間隙密封層、源極/汲極接點的自對準接點及接觸蝕刻停止層的半導體裝置1500。第15圖顯示的結構相似於其他圖式(例如第2-14圖)描述的結構,且為了簡單起見,此處不再詳細描述。在一些實施例中,高剛性密封材料1132可包含形成於半導體裝置1500的端子之間的第一部分1132A以及水平延伸且形成於端子的頂表面上的第二部分1132B。端子可包含閘極電極216和源極/汲極接點1030。在一些實施例中,高剛性材料也可用於形成自對準接點。舉例來說,用於源極/汲極接點1030的自對準接點1510可透過使用高剛性密封材料形成。在一些實施例中,自對準接點1010和高剛性密封材料1132可在相同製造步驟中形成,且由相同類型的材料組成。舉例來說,自對準接點1010和高剛性密封材料1132可具有大致相同的氧原子百分比。在一些實施例中,自對準接點1010和高剛性密封材料1132可透過使用具有不同組成的高剛性材料形成。應用雙重自對準接點方案的半導體裝置1500也可包含用於閘極電極216的自對準接點。舉例來說,自對準接點1010可形成於閘極電極216的頂表面上。自對準接點1010可透過使用高剛性密封材料形成。在一些實施例中,自對準接點1010可透過使用介電材料形成,例如氮化矽、氧化矽、氮氧化矽、碳氧化矽、氮碳氧化矽和任何合適的介電材料。用於形成具有雙重自對準接點方案和高剛性密封材料的半導體裝置1500的例示性製造過程可包含例如回蝕刻閘極電極216,在凹陷的閘極電極216上沉積介電材料以形成自對準接點1010,在源極/汲極區240上方形成源極/汲極接點1030,回蝕刻以將源極/汲極接點1030凹陷,在源極/汲極接點1030與閘極電極216之間形成開口,在開口中及在凹陷的源極/汲極接點1030和自對準接點1010上沉積高剛性密封材料,進行平坦化製程,形成層間介電層1150,並形成閘極導通孔1116和源極/汲極導通孔1160。在一些實施例中,閘極導通孔1116和源極/汲極導通孔1160可分別延伸通過自對準接點1010和1510。可使用其他操作來形成半導體裝置1500,且可改變操作的順序。FIG. 15 shows a self-aligned contact with a dual self-aligned contact scheme and a high rigidity seal as a gap seal between terminals, source/drain contacts, and a contact etch stop layer, according to some embodiments.
依據一些實施例,第16圖顯示具有雙重自對準接點方案和高剛性密封層作為端子之間的間隙密封層、閘極電極的自對準接點及接觸蝕刻停止層的半導體裝置1600。第16圖顯示的結構相似於其他圖式(例如第2-15圖)描述的結構,且為了簡單起見,此處不再詳細描述。在一些實施例中,高剛性密封材料1132可包含形成於半導體裝置1600的端子之間的第一部分1132A以及水平延伸且形成於端子的頂表面上的第二部分1132B。在一些實施例中,高剛性材料也可用於形成自對準接點。舉例來說,用於閘極電極216的自對準接點1620可透過使用高剛性密封材料形成。在一些實施例中,自對準接點1620和高剛性密封材料1132可在相同製造步驟中形成,且由相同類型的材料組成。舉例來說,自對準接點1620和高剛性密封材料1132可具有大致相同的氧原子百分比。在一些實施例中,自對準接點1620和高剛性密封材料1132可透過使用具有不同組成的高剛性材料形成。應用雙重自對準接點方案的半導體裝置1600也可包含用於源極/汲極接點1030的自對準接點。舉例來說,自對準源極/汲極接點(例如自對準接點1610)可形成於源極/汲極接點1030的頂表面上。自對準接點1610可透過使用高剛性密封材料形成。在一些實施例中,自對準接點1610可透過使用介電材料形成,例如氮化矽、氧化矽、氮氧化矽、碳氧化矽、氮碳氧化矽和任何合適的介電材料。用於形成具有雙重自對準接點方案和高剛性密封材料的半導體裝置1600的例示性製造過程可包含例如回蝕刻閘極電極216,在凹陷的閘極電極216上沉積高剛性密封材料以形成自對準接點1620,形成源極/汲極接點1030,在源極/汲極接點1030上形成自對準接點1610,在源極/汲極接點1030與閘極電極216之間形成開口,在開口中及自對準接點1620和1610上沉積高剛性密封材料,進行平坦化製程,形成層間介電層1150,並形成閘極導通孔1116和源極/汲極導通孔1160。可使用其他操作來形成半導體裝置1600,且可改變操作的順序。FIG. 16 shows a
本發明各種實施例提供半導體裝置及其製造方法,以提供在半導體裝置中產生高剛性密封層之簡單且有成本效益的結構和製程。高剛性密封層可用於密封開口,並在半導體裝置的端子之間形成空氣間隙,以降低有效介電常數,進而可改善裝置效能。高剛性密封材料也可形成於半導體裝置端子的頂表面上作為接觸蝕刻停止層。高剛性密封材料也可用作半導體裝置端子的自對準接點。Various embodiments of the present invention provide semiconductor devices and methods of fabricating the same to provide simple and cost-effective structures and processes for producing high rigidity encapsulation layers in semiconductor devices. High rigidity sealing layers can be used to seal openings and form air gaps between terminals of semiconductor devices to lower the effective dielectric constant, which in turn can improve device performance. A high rigidity encapsulant can also be formed on the top surface of the semiconductor device terminals as a contact etch stop layer. High rigidity sealing materials can also be used as self-aligned contacts for semiconductor device terminals.
在一些實施例中,半導體裝置包含形成於鰭區上的第一端子和第二端子以及形成於第一端子與第二端子之間的密封層。密封層包含摻雜氧的碳化矽材料。半導體裝置也包含被密封層、鰭區及第一端子和第二端子圍繞的空氣間隙。In some embodiments, a semiconductor device includes a first terminal and a second terminal formed on the fin region and a sealing layer formed between the first terminal and the second terminal. The sealing layer includes an oxygen-doped silicon carbide material. The semiconductor device also includes an air gap surrounded by the encapsulation layer, the fin region, and the first and second terminals.
在一些其他實施例中,其中第一端子包含閘極電極,且第二端子包含源極/汲極接點。In some other embodiments, wherein the first terminal includes a gate electrode, and the second terminal includes a source/drain contact.
在一些其他實施例中,其中第一端子更包含:閘極介電層,位於閘極電極的側壁上;以及間隙壁,包含在閘極介電層的側壁上的第一部分和在鰭區的頂表面上的第二部分。In some other embodiments, wherein the first terminal further comprises: a gate dielectric layer on the sidewall of the gate electrode; and a spacer including the first portion on the sidewall of the gate dielectric layer and the fin region Second part on top surface.
在一些其他實施例中,其中空氣間隙物理接觸間隙壁的第一部分和第二部分。In some other embodiments, wherein the air gap physically contacts the first portion and the second portion of the spacer.
在一些其他實施例中,其中密封層的密度在約2.0 g/cm3 與約3.2 g/cm3 之間。In some other embodiments, wherein the density of the sealing layer is between about 2.0 g/cm 3 and about 3.2 g/cm 3 .
在一些其他實施例中,其中密封層的氧原子含量在約30%與約55%之間。In some other embodiments, wherein the oxygen atomic content of the sealing layer is between about 30% and about 55%.
在一些其他實施例中,其中密封層的碳原子含量在約10%與約35%之間。In some other embodiments, wherein the carbon atom content of the sealing layer is between about 10% and about 35%.
在一些其他實施例中,其中密封層的矽原子含量在約25%與約35%之間。In some other embodiments, the silicon atomic content of the sealing layer is between about 25% and about 35%.
在一些其他實施例中,其中密封層、第一端子和第二端子的頂表面大致共平面。In some other embodiments, wherein the top surfaces of the sealing layer, the first terminal, and the second terminal are substantially coplanar.
在一些其他實施例中,上述半導體裝置更包含自對準接點,位於第一端子上,其中自對準接點包含摻雜氧的碳化矽材料,且具有頂表面與密封層的頂表面大致共平面。In some other embodiments, the semiconductor device further includes a self-aligned contact on the first terminal, wherein the self-aligned contact includes an oxygen-doped silicon carbide material and has a top surface substantially the same as the top surface of the sealing layer. coplanar.
在一些實施例中,半導體裝置包含位於鰭區上的閘極結構。閘極結構包含閘極電極和形成於閘極電極上的自對準接點(SAC)。自對準接點包含摻雜氧的碳化矽材料。半導體裝置也包含源極/汲極(S/D)接點和具有摻雜氧的碳化矽材料的密封層。密封層更包含位於閘極結構與源極/汲極接點之間的第一部分及位於自對準接點和源極/汲極接點的頂表面上的第二部分。半導體裝置也包含被密封層、鰭區、閘極電極和源極/汲極接點圍繞的空氣間隙。In some embodiments, the semiconductor device includes a gate structure on the fin region. The gate structure includes a gate electrode and a self-aligned contact (SAC) formed on the gate electrode. The self-aligned contacts comprise an oxygen-doped silicon carbide material. The semiconductor device also includes source/drain (S/D) contacts and an encapsulation layer having an oxygen-doped silicon carbide material. The sealing layer further includes a first portion between the gate structure and the source/drain contacts and a second portion on the top surfaces of the self-aligned contacts and the source/drain contacts. Semiconductor devices also include air gaps surrounded by encapsulation layers, fin regions, gate electrodes, and source/drain contacts.
在一些其他實施例中,其中密封層的密度在約2.0 g/cm3 與約3.2 g/cm3 之間。In some other embodiments, wherein the density of the sealing layer is between about 2.0 g/cm 3 and about 3.2 g/cm 3 .
在一些其他實施例中,其中密封層的氧原子含量在約30%與約55%之間。In some other embodiments, wherein the oxygen atomic content of the sealing layer is between about 30% and about 55%.
在一些其他實施例中,上述半導體裝置更包含導通孔,延伸通過密封層的第二部分,並物理接觸自對準接點。In some other embodiments, the above-described semiconductor device further includes vias extending through the second portion of the sealing layer and in physical contact with the self-aligned contacts.
在一些其他實施例中,上述半導體裝置更包含閘極介電層和間隙壁,其中間隙壁包含在閘極介電層的側壁上的第一部分和在鰭區的頂表面上的第二部分。In some other embodiments, the above-described semiconductor device further includes a gate dielectric layer and a spacer, wherein the spacer includes a first portion on sidewalls of the gate dielectric layer and a second portion on a top surface of the fin region.
在一些實施例中,半導體裝置的形成方法包含在基底的頂表面上方及半導體裝置的第一端子與第二端子之間形成開口。此方法也包含形成碳化矽材料,形成碳化矽材料包含在開口中及第一端子與第二端子之間沉積碳化矽材料的第一部分。此方法也包含在第一端子和第二端子的頂表面上沉積碳化矽材料的第二部分。由碳化矽材料、第一端子和第二端子及基底圍繞的開口圍住空氣間隙。此方法更包含對沉積的碳化矽材料的第一部分和第二部分進行氧退火製程。In some embodiments, a method of forming a semiconductor device includes forming an opening over a top surface of a substrate and between a first terminal and a second terminal of the semiconductor device. The method also includes forming a silicon carbide material, forming the silicon carbide material including depositing a first portion of the silicon carbide material in the opening and between the first terminal and the second terminal. The method also includes depositing a second portion of silicon carbide material on the top surfaces of the first and second terminals. The air gap is surrounded by an opening surrounded by the silicon carbide material, the first and second terminals, and the substrate. The method further includes performing an oxygen annealing process on the first and second portions of the deposited silicon carbide material.
在一些其他實施例中,其中碳化矽材料的第一部分沉積朝向開口的頂部。In some other embodiments, wherein the first portion of the silicon carbide material is deposited toward the top of the opening.
在一些其他實施例中,其中沉積碳化矽材料的第一部分和第二部分的步驟包含將四甲基二矽氧烷、氫氣和氧氣流入沉積腔體。In some other embodiments, wherein the steps of depositing the first and second portions of the silicon carbide material include flowing tetramethyldisiloxane, hydrogen and oxygen into the deposition chamber.
在一些其他實施例中,其中氫氣對氧氣的流量比值在約20與約30之間。In some other embodiments, wherein the flow ratio of hydrogen to oxygen is between about 20 and about 30.
在一些其他實施例中,上述方法更包含:蝕刻第一端子,以將第一端子凹陷;在凹陷的第一端子上沉積另一碳化矽材料;以及對沉積的另一碳化矽材料進行另一氧退火製程。In some other embodiments, the above method further comprises: etching the first terminal to recess the first terminal; depositing another silicon carbide material on the recessed first terminal; and subjecting the deposited another silicon carbide material to another Oxygen annealing process.
可以理解的是,實施方式而非發明摘要可用於詮釋請求項。發明摘要可以闡述一個或多個但不是所有考慮的例示性實施例,因此,並不旨在限制附屬請求項。It is to be understood that the embodiments, rather than the abstract, may be used to interpret the claims. The Summary of the Invention may set forth one or more, but not all, of the exemplary embodiments contemplated and, therefore, is not intended to limit the appended claims.
前述內文概述了許多實施例的特徵,使本技術領域中具有通常知識者可以從各個方面更加了解本發明實施例。本技術領域中具有通常知識者應可理解,且可輕易地以本發明實施例為基礎來設計或修飾其他製程及結構,並以此達到相同的目的及/或達到與在此介紹的實施例等相同之優點。本技術領域中具有通常知識者也應了解這些相等的結構並未背離本發明的發明精神與範圍。在不背離本發明的發明精神與範圍之前提下,可對本發明實施例進行各種改變、置換或修改。The foregoing context summarizes the features of many embodiments so that those skilled in the art may better understand the embodiments of the invention from various aspects. It should be understood by those skilled in the art that other processes and structures can be easily designed or modified based on the embodiments of the present invention to achieve the same purpose and/or to achieve the embodiments described herein. the same advantages. Those of ordinary skill in the art should also realize that such equivalent structures do not depart from the spirit and scope of the invention. Various changes, substitutions or modifications may be made to the embodiments of the present invention without departing from the spirit and scope of the invention.
100:鰭式場效電晶體 102:基底 104:鰭結構 106:源極/汲極區 108,208:閘極結構 110,210,212:間隙壁 110a,110b,110c:間隙壁部分 112:淺溝槽隔離區 116,216:閘極電極 118,620,1020:介電層 120:閘極蓋層 121,221:鰭區 122:閘極功函數金屬層 124:閘極金屬填充層 200:半導體結構 214:接觸蝕刻停止層 218:閘極介電層 222:虛線 230,1030:源極/汲極接點 240:源極/汲極區 302:開口 304,440:區域 410A,414A:圓角 412:第一密封材料 412A,432A,452B:角落部分 412B,432B,452A:水平部分 432:第二密封材料 432C:垂直部分 435,462:處理製程 442,542,942,1042:空氣間隙 452:密封層 450:縫隙 532,932,1032,1132:高剛性密封材料 616,916,1016,1116:閘極導通孔 630,930,1060,1160:源極/汲極導通孔 650,950,1050,1150:層間介電層 700:方法 702,704,706,708,710,712:操作 800,900,1000,1100,1200,1300,1400,1500,1600:半導體裝置 810,1010,1210,1460,1510,1610,1620:自對準接點 932A,1132A:第一部分 932B,1132B:第二部分 118t,120t,122t:厚度 H1 ,H2 ,H3 ,H4 ,H5 :高度100: FinFET 102: Substrate 104: Fin Structure 106: Source/Drain Regions 108, 208: Gate Structure 110, 210, 212: Spacers 110a, 110b, 110c: Spacer Portion 112: Shallow Trench Isolation Regions 116, 216: Gate electrode 118, 620, 1020: dielectric layer 120: gate cap layer 121, 221: fin region 122: gate work function metal layer 124: gate metal fill layer 200: semiconductor structure 214: contact etch stop layer 218: gate dielectric Layer 222: dashed lines 230, 1030: source/drain contacts 240: source/drain regions 302: openings 304, 440: regions 410A, 414A: fillets 412: first encapsulant 412A, 432A, 452B: corner portions 412B , 432B, 452A: Horizontal part 432: Second sealing material 432C: Vertical part 435, 462: Processing process 442, 542, 942, 1042: Air gap 452: Sealing layer 450: Gap 532, 932, 1032, 1132: High rigidity sealing material 616, 916, 1016, 1116: Gate Vias 630, 930, 1060, 1160: Source/Drain Vias 650, 950, 1050, 1150: Interlayer Dielectric Layer 700: Methods 702, 704, 706, 708, 710, 712: Operations 800, 900, 1000, 1100, 1200, 1300, 1400, 1500, 160 Devices 810, 1010, 1210, 1460, 1510, 1610, 1620: Self-aligned contacts 932A, 1132A: First part 932B, 1132B: Second part 118t , 120t, 122t : Thickness H1, H2 , H3, H 4 ,H 5 : height
根據以下的詳細說明並配合所附圖式可以更加理解本發明實施例。應注意的是,根據本產業的標準慣例,圖示中的各種部件(feature)並未必按照比例繪製。事實上,可能任意的放大或縮小各種部件的尺寸,以做清楚的說明。 第1圖為依據一些實施例之半導體結構的等角視圖。 第2-3、4A-4F、5-6圖為依據一些實施例之各種部分形成的半導體結構的剖面示意圖。 第7圖為依據一些實施例之半導體結構中的雙層密封結構的形成方法的流程圖。 第8、9A-9B、10A-10D、11A-11B、12-16圖為依據一些實施例之各種部分形成的半導體結構的剖面示意圖。The embodiments of the present invention can be better understood according to the following detailed description and the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features in the illustrations are not necessarily drawn to scale. In fact, the dimensions of various components may be arbitrarily enlarged or reduced for clarity of illustration. FIG. 1 is an isometric view of a semiconductor structure in accordance with some embodiments. Figures 2-3, 4A-4F, and 5-6 are schematic cross-sectional views of various partially formed semiconductor structures according to some embodiments. FIG. 7 is a flowchart of a method of forming a double-layer sealing structure in a semiconductor structure according to some embodiments. Figures 8, 9A-9B, 10A-10D, 11A-11B, 12-16 are schematic cross-sectional views of various partially formed semiconductor structures according to some embodiments.
210:間隙壁 210: Spacer
214:接觸蝕刻停止層 214: Contact etch stop layer
216:閘極電極 216: gate electrode
218:閘極介電層 218: gate dielectric layer
221:鰭區 221: Fin Area
222:虛線 222: Dotted line
1030:源極/汲極接點 1030: source/drain contacts
240:源極/汲極區 240: source/drain region
1132:高剛性密封材料 1132: High rigidity sealing material
1116:閘極導通孔 1116: gate via hole
1160:源極/汲極導通孔 1160: Source/Drain Vias
1150:層間介電層 1150: Interlayer dielectric layer
1600:半導體裝置 1600: Semiconductor Devices
1610,1620:自對準接點 1610, 1620: Self-aligning contacts
1132A:第一部分
1132A:
1132B:第二部分 1132B: Part II
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US16/937,344 | 2020-07-23 | ||
US17/100,533 US11502166B2 (en) | 2019-12-20 | 2020-11-20 | Seal material for air gaps in semiconductor devices |
US17/100,533 | 2020-11-20 |
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