CN113013226A - Semiconductor device and method of forming a semiconductor device - Google Patents

Semiconductor device and method of forming a semiconductor device Download PDF

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Publication number
CN113013226A
CN113013226A CN202011510967.6A CN202011510967A CN113013226A CN 113013226 A CN113013226 A CN 113013226A CN 202011510967 A CN202011510967 A CN 202011510967A CN 113013226 A CN113013226 A CN 113013226A
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China
Prior art keywords
semiconductor device
layer
gate
sac
sealing
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CN202011510967.6A
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Chinese (zh)
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CN113013226B (en
Inventor
梁顺鑫
王振翰
林耕竹
上野哲嗣
陈婷婷
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Priority claimed from US16/937,344 external-priority patent/US11296187B2/en
Priority claimed from US17/100,533 external-priority patent/US11502166B2/en
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN113013226A publication Critical patent/CN113013226A/en
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Abstract

The present invention relates to a semiconductor device including first and second terminals formed on a fin region and an encapsulation layer formed between the first and second terminals. The sealing layer includes a silicon carbide material doped with oxygen. The semiconductor device also includes an air gap surrounded by the sealing layer, the fin region, and the first and second terminals. The invention also relates to a method of forming a semiconductor device.

Description

Semiconductor device and method of forming a semiconductor device
Technical Field
Embodiments of the present application relate to semiconductor devices and methods of forming semiconductor devices.
Background
The semiconductor Integrated Circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have resulted in multiple generations of ICs, each of which has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component or line that can be produced using a fabrication process) has decreased. Such a scaled-down process generally provides benefits by increasing production efficiency and reducing associated costs.
Disclosure of Invention
Some embodiments of the present application provide a semiconductor device, including: a first terminal and a second terminal formed on the fin region; a sealing layer formed between the first terminal and the second terminal, wherein the sealing layer comprises a silicon carbide material doped with oxygen; and an air gap surrounded by the sealing layer, the fin region, and the first and second terminals.
Other embodiments of the present application provide a semiconductor device, including: a gate structure on the fin region, comprising: a gate electrode; and a self-aligned contact (SAC) formed on the gate electrode and including a silicon carbide material doped with oxygen; a source/drain (S/D) contact; a sealing layer comprising the silicon carbide material doped with oxygen, wherein the sealing layer further comprises: a first portion between the gate structure and the source/drain contact; and a second portion on top surfaces of the self-aligned contact and the source/drain contact; and an air gap surrounded by the sealing layer, the fin region, the gate electrode, and the source/drain contacts.
Still further embodiments of the present application provide a method of forming a semiconductor device, comprising: forming an opening over a top surface of a substrate and between a first terminal and a second terminal of the semiconductor device; and forming a silicon carbide material comprising: depositing a first portion of the silicon carbide material in the opening and between the first terminal and the second terminal; depositing a second portion of the silicon carbide material on top surfaces of the first and second terminals, wherein a gas pocket is trapped in the opening surrounded by the silicon carbide material, the first and second terminals, and the substrate; and performing an oxygen annealing process on the deposited first and second portions of the silicon carbide material.
Drawings
Various aspects of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, in accordance with common practice in the industry, various components are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily increased or decreased for clarity of discussion.
Figure 1 is an isometric view of a semiconductor structure according to some embodiments.
Fig. 2-6 are cross-sectional views of semiconductor structures formed in various portions according to some embodiments.
Fig. 7 is a flow chart of a method of forming a two-layer sealing structure in a semiconductor structure according to some embodiments.
Fig. 8-16 are cross-sectional views of semiconductor structures formed in various portions according to some embodiments.
Detailed Description
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the invention. For example, in the following description, forming a first part over a second part may include an embodiment in which the first part and the second part are formed in physical contact, and may also include an embodiment in which an additional part is disposed between the first part and the second part so that the first part and the second part may not be in physical contact. Moreover, the present disclosure may repeat reference numerals and/or characters in the various examples. This repetition does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Also, spatially relative terms, such as "below …," "below …," "lower," "above …," "upper," and the like, may be used herein for ease of description to describe one element or component's relationship to another (or other) element or component as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
As used herein, the term "nominal" refers to a desired or target value, and a range of values above and/or below the desired value, of a characteristic or parameter for a component or process operation that is set during the design phase of the product or process. The range of values is typically due to slight variations in manufacturing processes or tolerances.
The terms "about" and "substantially" as used herein indicate a given number of values that may vary based on the particular technology node associated with the subject semiconductor device. In some embodiments, a given number of values that vary within 5% of the value (e.g., ± 1%, ± 2%, ± 3%, ± 4%, ± 5% of the target value) may be indicated based on the particular technology node.
The fins may be patterned by any suitable method. For example, the fins may be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. Typically, double patterning or multiple patterning processes combine lithographic and self-aligned processes, allowing for the creation of patterns having, for example, pitches smaller than those obtainable using a single direct lithographic process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithographic process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the fin may then be patterned using the remaining spacers.
As planar semiconductor devices, such as metal oxide semiconductor field effect transistors ("MOSFETs"), are scaled down by various technology nodes, other methods of increasing device density and speed have been proposed. One approach is a fin field effect transistor ("finFET") device, which is a three-dimensional FET, that includes the formation of a fin-shaped channel extending from a substrate. Finfets are compatible with conventional Complementary Metal Oxide Semiconductor (CMOS) processes, and their three-dimensional structure enables them to be scaled significantly while maintaining gate control and mitigating short channel effects. Gate stacks are used in planar and three-dimensional FETs to control the conductivity of semiconductor devices. A gate stack including a gate dielectric layer and a gate electrode for a finFET device may be formed by a replacement gate process in which a polysilicon sacrificial gate structure is replaced with a metal gate structure. A gate dielectric layer, such as a high-k dielectric layer (e.g., a dielectric layer having a dielectric constant greater than about 3.9), is formed between the channel and the gate electrode. Spacers may be disposed on sidewalls of the gate stack to protect the gate structure during manufacturing processes, such as ion implantation, gate replacement processes, epitaxial source/drain structure formation, and other suitable processes. Air gaps may be used instead of spacers to reduce the effective dielectric constant, which in turn may reduce parasitic capacitance and improve device performance. An air gap may be formed by depositing a sealing material over the opening between the terminals of the semiconductor device so that the air pockets are trapped between the terminals. The sealing material or layer may be a structure that serves as a lid that closes the opening. Because the dielectric constant of air may be lower than that of the dielectric material, the effective dielectric constant may be reduced. However, low uniformity and low etch resistance in the encapsulation material may lead to defects in the semiconductor device. For example, a manufacturing process for forming interconnect structures (such as vias for metal source/drain and gate terminals of finFET devices) may include multiple etching and cleaning processes performed on the terminals, may etch through portions of the encapsulation material through the seams, and cause damage to the air gaps. Examples of damage include collapse of the sealing material or trapping of chemical solutions in the air gap. In addition, seams in the encapsulant can also lead to physical failures and electrical shorts. The damaged air gap structure can lead to defects in the semiconductor device and result in low device yield and device failure.
In order to solve the above disadvantages, the present invention provides a semiconductor device and a method of manufacturing the same to provide a simple and cost-effective structure and process for manufacturing an encapsulation layer in the semiconductor device. The sealing layer may serve to seal the openings and form air gaps between the terminals of the semiconductor device, and may also serve as a Contact Etch Stop Layer (CESL) for subsequently formed structures, such as interconnect structures. In particular, a high rigidity layer may be used as the sealing material. For example, a highly rigid silicon carbide layer (HRSCO) doped with oxygen may be used as the sealing material. The HRSCO layer may also be formed and used as an etch stop layer. Further, a layer of HRSCO may also be formed on the top surface of the semiconductor device terminals and used as a self-aligned contact (SAC). For example, a high-rigidity layer may be formed on a terminal of the semiconductor device. The terminals may include source terminals, drain terminals, gate terminals, and/or other suitable structures.
In some embodiments, the high rigidity layer may be formed by a deposition process followed by a treatment process. For example, a silicon carbide layer may be deposited followed by an oxygen annealing process to increase the oxygen content in the deposited layer. Various deposition parameters can be varied to tune the density of the film, and greater densities can provide greater stiffness. A high rigidity layer may be deposited in an opening formed between opposing sidewalls of a terminal of a semiconductor device. A highly rigid layer may be deposited on the sidewalls and toward the top of the opening, and the deposition process may continue at least until the highly rigid material from the opposing sidewalls merges into physical contact and forms a closed space between the opposing sidewalls.
In some embodiments, increasing the density of the high stiffness layer may provide greater etch resistance. In some embodiments, reducing the deposition rate of the high stiffness layer may result in improved film uniformity (e.g., uniform thickness). In some embodiments, the high stiffness layer may be deposited using a suitable deposition process using suitable precursors, such as Tetramethyldisiloxane (TSMDSO), hydrogen, oxygen, and any other suitable precursor.
In some embodiments, the high rigidity layer is a two-layer sealing material, which may be formed by depositing a first sealing material, depositing a second sealing material, and performing at least one treatment process on the deposited first and second sealing materials. The treatment process may be performed after the deposition of the first sealing material, after the deposition of the second sealing material, or both. The first and second sealing materials may be dielectric materials. A first encapsulant material is deposited over portions of opposing sidewalls toward a top of the opening, and a second encapsulant material is deposited over the first encapsulant material and over exposed surfaces in the opening. A second encapsulant material is deposited over the first encapsulant material on the opposite sidewall. The deposition process of the second sealing material continues at least until the second sealing material from the opposing sidewalls merges to form a closed space between the opposing sidewalls. The deposited first and second sealing materials may be subjected to a treatment process such that the seams are removed by expansion of at least the second sealing material. In some embodiments, the treatment process may be an annealing process performed in an oxygen ambient. In some embodiments, the first sealing material may be deposited at a greater deposition rate than the second sealing material. In some embodiments, the first and second sealing materials may be formed using precursors such as Tetramethyldisiloxane (TSMDSO), hydrogen, oxygen, and any other suitable precursor.
Fig. 1 is an isometric view of an exemplary fin field effect transistor (finFET) structure. Fig. 2-7 provide various exemplary semiconductor structures and fabrication processes illustrating the formation of a multi-spacer structure with air gaps and a highly rigid encapsulation material, in accordance with some embodiments. Fig. 8-16 provide various structures and fabrication processes for forming air gaps, encapsulation materials, CESL, and other structures of semiconductor devices. The sealing material and CESL may be formed using a highly rigid material that provides, among other things, higher etch resistance, improved uniformity, and lower leakage current. In some embodiments, the high rigidity material may be a material of HRSCO. The manufacturing processes provided herein are exemplary and alternative processes according to the present invention may be implemented (although not shown in these figures).
Figure 1 is an isometric view of a finFET in accordance with some embodiments. FinFET 100 may be included in a microprocessor, memory cell, or other integrated circuit. The view of the finFET 100 in fig. 1 is shown for illustrative purposes and may not be drawn to scale. FinFET 100 may include further suitable structures such as additional spacers, liner layers, contact structures, and any other suitable structures, which are not shown in fig. 1 for clarity.
The FinFET 100 may be formed on a substrate 102, and the FinFET 100 may include a fin structure 104 having a fin region 121 and an S/D region 106, a gate structure 108 disposed on the fin structure 104, spacers 110 disposed on opposite sides of each of the gate structures 108, and Shallow Trench Isolation (STI) regions 112. Fig. 1 shows five gate structures 108. However, based on the disclosure herein, the finFET 100 may have more or fewer gate structures. In addition, the finFET 100 may be incorporated into an integrated circuit by using other structural components (such as S/D contact structures, gate contact structures, conductive vias, conductive lines, dielectric layers, and passivation layers) that are omitted for clarity.
The substrate 102 may be a semiconductor material, such as silicon. In some embodiments, substrate 102 comprises a crystalline silicon substrate (e.g., a wafer). In some embodiments, the substrate 102 comprises: (i) elemental semiconductors such as germanium; (ii) a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, and/or indium antimonide; (iii) an alloy semiconductor including silicon germanium carbide, silicon germanium, gallium arsenide phosphide, indium gallium phosphide, gallium indium arsenide phosphide, aluminum indium arsenide, and/or aluminum gallium arsenide; or (iv) combinations thereof. Further, the substrate 102 may be doped according to design requirements (e.g., a p-type substrate or an n-type substrate). In some embodiments, the substrate 102 may be doped with a p-type dopant species (e.g., boron, indium, aluminum, or gallium) or an n-type dopant species (e.g., phosphorus or arsenic).
The fin structure 104 represents a current-carrying structure of the finFET 100 and may be along the Y-axis and pass through the gate structure 108. The fin structure 104 may include: (i) a portion of fin region 121 located under gate structure 108; and (ii) S/D regions 106 disposed on portions of fin regions 121 formed on opposite sides of each of gate structures 108. A portion of the fin region 121 of the fin structure 104 under the gate structure 108 (not shown in fig. 1) may extend over the STI region 112 and may be wrapped by a corresponding one of the gate structures 108. The fin region 121 on the opposite side of the gate structure 108 may be etched back such that the S/D region 106 may be epitaxially grown on the etched-back portion of the fin region 121.
The fin region 121 of the fin structure 104 may comprise a material similar to the substrate 102. The S/D regions 106 may comprise epitaxially grown semiconductor material. In some embodiments, the epitaxially grown semiconductor material is the same material as the substrate 102. In some embodiments, the epitaxially grown semiconductor material comprises a different material than the substrate 102. The epitaxially grown semiconductor material may include: (i) semiconductor materials such as germanium and silicon; (ii) compound semiconductor materials such as gallium arsenide and aluminum gallium arsenide; or (iii) semiconductor alloys such as silicon germanium and gallium arsenide phosphide. Other materials for fin structure 104 are within the scope of the present invention.
In some embodiments, the S/D regions 106 may be grown by: (i) chemical Vapor Deposition (CVD), such as by low pressure CVD (lpcvd), ultra-high vacuum CVD (uhvcvd), reduced pressure CVD (rpcvd), or suitable CVD processes; (ii) a Molecular Beam Epitaxy (MBE) process; (iii) a suitable epitaxy process; and (iv) combinations thereof. In some embodiments, the S/D region 106 may be grown by an epitaxial deposition/partial etch process, which is repeated at least once. This repeated deposition/partial etch process is also referred to as a "Cyclical Deposition Etch (CDE) process". In some embodiments, the S/D regions 106 may be grown by Selective Epitaxial Growth (SEG), where an etching gas is added to promote selective growth of semiconductor material on exposed surfaces of the fin structure rather than on insulating material (e.g., the dielectric material of the STI regions 112). Other methods of epitaxially growing the S/D regions 106 are within the scope of the present invention.
The S/D regions 106 may be p-type regions or n-type regions. In some embodiments, the p-type S/D regions 106 may comprise SiGe and may be doped in situ with p-type dopants (such as boron, indium, and gallium) during epitaxial growth. For p-type in situ doping, p-type doping precursors such as diborane (B) may be used2H6) Boron trifluoride (BF)3) And other p-type doping precursors. In some embodiments, the n-type S/D regions 106 may comprise Si and may be doped in situ with n-type dopants (such as phosphorous and arsenic) during the epitaxial growth process. For n-type in situ doping, n-type doping precursors such as Phosphine (PH) may be used3) Arsine (AsH)3) And other n-type doping precursors. In some embodiments, the S/D regions 106 are not doped in situ, but rather an ion implantation process is performed to dope the S/D regions 106.
The spacers 110 may include spacer portions 110a formed on sidewalls of the gate structure 108 and in contact with the dielectric layer 118, spacer portions 110b formed on sidewalls of the fin structure 104, and spacer portions 110c formed as a protective layer over the STI regions 106. Each spacer portion may also be a multi-spacer structure comprising more than one spacer structure. For example, the spacer portion 110a may include more than one spacer and an air gap formed between the gate structure 108 and the fin structure 104. A sealing material may be formed over the air gap to close and protect the air gap from subsequent manufacturing processes. For simplicity, the air gaps and sealing material are not shown in fig. 1. The spacers 110 may comprise an insulating material such as silicon oxide, silicon nitride, low-k materials, and combinations thereof. The spacers 110 may have a low-k material with a dielectric constant less than 3.9 (e.g., less than 3.5, 3, and 2.8). Since the air gap may have a dielectric constant of about 1, the effective dielectric constant of the spacer 110 may be further reduced compared to a spacer formed using only a low-k material. The low-k material for the spacers 110 may be formed using a suitable deposition process, such as Atomic Layer Deposition (ALD). In some embodiments, the spacer 110 can be deposited using CVD, LPCVD, UHVCVD, RPCVD, Physical Vapor Deposition (PVD), any other suitable deposition process, and combinations thereof. In some embodiments, the sealing material may be a high rigidity material, such as HRSCO. In some embodiments, the encapsulation material may be a two-layer encapsulation material formed by depositing a first encapsulation material formed on top of the opening between the gate structure 108 and the S/D region 106, followed by deposition of a second encapsulation material on the first encapsulation material to form a housing with air trapped in the opening. Other materials and thicknesses for the spacer 110 and the sealing material are within the scope of the present invention.
Each gate structure 108 may include a gate electrode 116, a dielectric layer 118 adjacent to and in contact with the gate electrode 116, and a gate cap layer 120. The gate structure 108 may be formed by a gate replacement process.
In some embodiments, the dielectric layer 118 may be formed using a high-k dielectric material (e.g., a dielectric material having a dielectric constant greater than about 3.9). Dielectric layer 118 may be formed by CVD, Atomic Layer Deposition (ALD), Physical Vapor Deposition (PVD), e-beam evaporation, or other suitable process. In some embodiments, the dielectric layer 118 may include: (i) a silicon oxide, silicon nitride and/or silicon oxynitride layer, (ii) a high-k dielectric material, such as hafnium oxide (HfO)2)、TiO2、HfZrO、Ta2O3、HfSiO4、ZrO2And ZrSiO2(iii) a high-k dielectric material having oxides of lithium (Li), beryllium (Be), magnesium (Mg), calcium (Ca), strontium (Sr), scandium (Sc), yttrium (Y), zirconium (Zr), aluminum (Al), lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), or lutetium (Lu), or (iv) combinations thereof. The high-k dielectric layer may be formed by ALD and/or other suitable methods. In some embodiments, the dielectric layer 118 may comprise a single layer or a stack of layers of insulating material. Other materials and formation methods for the dielectric layer 118 are within the scope of the present invention. For example, portions of the dielectric layer 118 are formed on horizontal surfaces, such as the top surface of the STI region 112. Although not visible in fig. 1, a dielectric layer 118 may also be formed on the top and sidewalls of fin region 121 under gate electrode 116. In some embodiments, a dielectric layer 1 is also formed between the sidewalls of the gate electrode 116 and the spacer portion 110a18 as shown in figure 1. In some embodiments, the dielectric layer 118 has a thickness 118t in a range from about 1nm to about 5 nm.
The gate electrode 116 may include a gate work function metal layer 122 and a gate metal fill layer 124. In some embodiments, a gate work function metal layer 122 is disposed on the dielectric layer 118. The gate work function metal layer 122 may comprise a single metal layer or a stack of metal layers. The stack of metal layers may comprise metals having work functions similar to or different from each other. In some embodiments, the gate work function metal layer 122 may include, for example, aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), nickel silicide (NiSi), cobalt silicide (CoSi), silver (Ag), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), tantalum carbon nitride (TaCN), titanium aluminum (TiAl), aluminum titanium nitride (TiAlN), tungsten nitride (WN), metal alloys, and combinations thereof. The gate work function metal layer 122 may be formed using a suitable process, such as ALD, CVD, PVD, plating, or combinations thereof. In some embodiments, the gate work function metal layer 122 has a thickness 122t in a range from about 2nm to about 15 nm. Other materials, methods of formation, and thicknesses of the gate work function metal layer 122 are within the scope of the present invention.
The gate metal fill layer 124 may comprise a single metal layer or a stack of metal layers. The stack of metal layers may comprise metals that are different from each other. In some embodiments, the gate metal fill layer 124 may comprise a suitable conductive material, such as Ti, Ag, Al, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, WN, Cu, W, Co, Ni, TiC, TiAlC, TaAlC, metal alloys, and combinations thereof. The gate metal fill layer 124 may be formed by ALD, PVD, CVD, or other suitable deposition process. Other materials and methods of forming the gate metal fill layer 124 are within the scope of the present invention.
In some embodiments, the gate capping layer 120 may have a thickness 120t in a range from about 5nm to about 50nm and may protect the gate structure 108 during subsequent processing of the finFET 100. The gate cap layer 120 may include a nitride material such as silicon nitride, silicon-rich nitride, and silicon oxynitride. Other materials for gate cap layer 120 are within the scope of the present invention.
The STI regions 112 may electrically isolate adjacent active and passive components (not shown here) integrated with the substrate 102 or deposited on the substrate 102 from the finFET 100. STI regions 112 may be of a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, fluorine doped silicate glass (FSG), low-k dielectric material, and other suitable insulating materials. In some embodiments, STI regions 112 may comprise a multi-layer structure. The cross-sectional shapes of the fin structure 104, the S/D region 106, the gate structure 108, the spacers 110, and the STI regions 112 are illustrative and not limiting.
Fig. 2-6 provide various exemplary semiconductor structures and fabrication processes illustrating the formation of a spacer structure with air gaps and a high-rigidity encapsulation layer, according to some embodiments. The high stiffness sealant layer may also be seam free. Fig. 7 is a flow chart of a method 700 of forming an air gap and high rigidity sealing layer in a semiconductor structure according to some embodiments of the invention. Other operations in method 700 may be implemented based on the disclosure herein. Further, the operations of method 700 may be performed in a different order and/or with variations.
Air gaps with seamless sealing layers may provide the benefit of reducing and/or eliminating damage to air gaps formed between spacer structures. The fabrication process may be used to form planar semiconductor devices or vertical semiconductor devices, such as finfets. In some embodiments, the fabrication process shown in fig. 2-7 may be used to form a semiconductor structure similar to the finFET structure described above in fig. 1. For example, the semiconductor structure as shown in fig. 2 may resemble the finFET 100 during different stages of fabrication, as viewed from the cut line a-a' shown in fig. 1.
Referring to operation 702 of fig. 7, source/drain regions and a gate stack are formed on a substrate according to some embodiments. Fig. 2 is a cross-sectional view of the semiconductor structure 200 after three adjacent gate structures 208 and two source/drain contacts 230 are formed over the substrate. The substrate may include a fin region 221. Each gate stack, such as gate structure 208, includes a gate dielectric layer 218 and a gate electrode 216. A gate dielectric layer 218 may be formed on the sidewalls and bottom surface of the gate electrode 216. A channel region for a semiconductor device, such as a finFET, may be formed in the fin region 221 and under the gate structure 208.
Fin region 221 may be a current carrying semiconductor structure formed on a substrate. For example, fin region 221 may be similar to fin region 121 described above in fig. 1. In some embodiments, the fin region 221 may include a semiconductor material such as germanium, silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, indium antimonate, silicon germanium carbide, silicon germanium, gallium arsenide phosphide, gallium indium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, any suitable material, and combinations thereof. In some embodiments, the fin region 221 may be doped with a p-type or n-type dopant species.
A gate dielectric layer 218 may be formed on the fin region 221 and may be formed using a high-k dielectric material. The gate dielectric layer 218 may be deposited by CVD, ALD, PVD, e-beam evaporation, or other suitable process. In some embodiments, the gate dielectric layer 218 may comprise a high-k dielectric material, such as HfO2. In some embodiments, the gate dielectric layer 218 may comprise TiO2、HfZrO、Ta2O3、HfSiO4、ZrO2And ZrSiO2. In some embodiments, the gate dielectric layer 218 may be similar to the dielectric layer 118 described above in fig. 1.
The gate electrode 216 may be formed on the gate dielectric layer 218, and the gate electrode 216 may include a single metal layer or a stack of metal layers. The gate structure 208 may further include a work function layer and is not shown in fig. 2 for simplicity. The stack of metal layers may comprise metals having work functions similar to or different from each other. In some embodiments, the gate electrode 216 may be formed of a conductive material (such as Al, Cu, W, Ti, Ta, TiN, TaN, NiSi, CoSi, Ag, TaC, TaSiN, TaCN, TiAl, TiAlN, WN, metal alloys, and combinations thereof). The gate electrode 216 may be formed using a suitable deposition process, such as ALD, CVD, PVD, plating, and combinations thereof. Other materials and methods of forming gate electrode 216 are within the scope of the present invention. In some embodiments, the gate electrode 216 may be formed using a gate replacement process, wherein a polysilicon gate is removed and a metal gate electrode is formed at the location of the removed polysilicon gate.
Spacer structures may be formed on sidewalls of the gate structure 208. In some embodiments, the gate structure may include a gate electrode, a dielectric layer, a spacer, any other suitable structure, and collectively referred to as a gate structure for ease of reference. In some embodiments, spacers 210 and 212 may be formed on sidewalls of gate dielectric layer 218 and on a top surface of fin region 221. Spacer structures are formed on the sidewalls of the gate electrode 216 to protect the gate dielectric layer 218 and the gate electrode 216 during subsequent processing. In some embodiments, the spacers 210 may have an L-shaped cross-section with vertical portions formed on the sidewalls of the gate dielectric layer 218 and horizontal portions formed on the top surface of the fin region 221. In some embodiments, the spacers 210 are formed only on the sidewalls of the gate dielectric layer 218. The spacers 210 may be formed using a dielectric material, such as silicon carbonitride, silicon nitride, silicon oxide, any suitable dielectric material, and combinations thereof. In some embodiments, the carbon atom content may be less than about 30% for spacers 210 formed using silicon carbonitride. In some embodiments, the carbon atom content of the spacer 210 may be between about 20% and about 30%. Additional spacers, such as spacer 212, may also be formed. For example, spacers 212 may be formed on horizontal portions of spacers 210, on top surfaces of fin regions 221, or on both. In some embodiments, the spacers 212 may be formed using a dielectric material, such as silicon. In some embodiments, the material forming the spacers 210 and 212 may have a high etch selectivity (e.g., greater than about 10), such that the spacers 210 may remain substantially intact when the spacers 212 are removed. In some embodiments, spacers 210 and 212 may be formed using any suitable dielectric material, such as silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, Silicon On Glass (SOG), Tetraethylorthosilicate (TEOS), PE-oxide, HARP-formed oxide, and combinations thereof. In some embodiments, the spacers 210 and 212 may be formed using a low-k dielectric material.
May be in the fin region 221Source/drain (S/D) regions 240 are formed. The S/D region 240 may be a p-type region or an n-type region. In some embodiments, the p-type S/D region 240 may comprise SiGe and may be doped in situ with a p-type dopant species (such as boron, indium, and gallium) during an epitaxial growth process. For p-type in situ doping, p-type doping precursors, such as B, may be used2H6、BF3And other p-type doping precursors. In some embodiments, the n-type S/D region 240 may comprise Si and may be doped in situ with an n-type dopant species (such as phosphorous and arsenic) during the epitaxial growth process. For n-type in situ doping, n-type doping precursors, such as PH, may be used3、AsH3And other n-type doping precursors. In some embodiments, the S/D regions 240 are not doped in situ, and an ion implantation process is performed to dope the S/D regions 240. In some embodiments, the S/D regions may be similar to the S/D regions 160 described above in FIG. 1.
Source/drain (S/D) contacts 230 may be in physical and electrical contact with source/drain regions 240. The S/D contacts 230 may be formed by depositing a conductive material between adjacent gate structures 208. For example, openings may be formed between the spacers 212 to expose the underlying S/D regions 240. A deposition process may be performed to deposit a conductive material in the openings so that electrical connections may be made. In some embodiments, a Contact Etch Stop Layer (CESL)214 may be deposited in the opening prior to the deposition of the conductive material. Examples of conductive material deposition processes may include PVD, sputtering, electroplating, electroless plating, any suitable deposition process, and combinations thereof. A planarization process may be performed after the deposition process such that top surfaces of the gate electrode 216, the spacers 210 and 212, the CESL 214, and the source/drain contacts 230 may be substantially coplanar (e.g., a planar surface). In some embodiments, the S/D contacts 230 may be formed using tungsten, aluminum, cobalt, silver, any suitable conductive material, and combinations thereof.
Similar to the finFET 100 depicted in fig. 1, the semiconductor structure 200 may be formed on a substrate with fin regions 221 protruding from STI regions. The STI region is not visible in the cross-sectional view of the semiconductor structure 200 shown in fig. 2, but for ease of description, the top surface of the STI region is represented by dashed line 222.
Referring to operation 704 of fig. 7, according to some embodiments, one or more spacers are removed to form openings between terminals of the semiconductor device. Fig. 3 is a cross-sectional view of the semiconductor device after removing one or more spacers to form openings. Examples of terminals of the semiconductor device may be a gate structure, an S/D structure, or any other suitable structure. The gate structure 208 shown in fig. 3 may include a gate dielectric layer 218 and a gate electrode 216. In some embodiments, the gate structure 208 may also include spacers 210. The S/D structure may include an S/D contact 230 and a CESL 214. In some embodiments, the S/D structure may further include an S/D region 240 formed in the fin region 221. During operation 704, one or more of the spacers between the gate electrode 216 and the S/D contact 230 may be removed. For example, spacers 212 may be removed to form an opening 302 surrounded by spacers 210 and CESL 214. One or more etching processes may be used to remove the spacers 212. In some embodiments, the spacers 212 may be removed using an etch process in which the spacers 212 have a high etch selectivity relative to other structures in the semiconductor structure 200, while leaving other exposed structures unchanged. For example, silicon carbonitride may be used to form the spacers 212, and a wet etch process and/or a plasma etch may be used to selectively remove the spacers 212.
Fig. 4A and 4B are cross-sectional views illustrating a fabrication process for forming a high-rigidity seam layer using a cyclical deposition/treatment process, according to some embodiments. Fig. 4C-4F are cross-sectional views illustrating a high-rigidity sealing layer formed using a multiple deposition process, according to some embodiments. Fig. 4A to 4F are enlarged views of the region 304 of fig. 3. Other structures may be included in the structures shown in fig. 4A to 4F and are not shown for simplicity.
Referring to operation 706 of fig. 7, a sealing layer is deposited over at least top corners of the opening in the semiconductor device, in accordance with some embodiments. Fig. 4A is a cross-sectional view illustrating the semiconductor device after a sealing material is deposited on at least top corners of the openings in the semiconductor device. An encapsulation layer 452 is deposited on the exposed top surfaces of the structures in the semiconductor device, such as the top surfaces of the gate electrode 216, the gate dielectric layer 218, the S/D contact 230, the CESL 214, and other structures. In some embodiments, a sealing layer 452 may also be deposited in the opening 302. For example, sealing layer 452 may be deposited on sidewalls of spacers 210 and CESL 214. In some embodiments, a sealing layer 452 may be deposited on the bottom of the opening 302, such as on the top surface of the horizontal portion of the spacer 210 formed on the fin region 221. In some embodiments, sealing layer 452 may also be formed on fin region 221 if a portion of the top surface of fin region 221 is exposed between spacers 210 and CESL 214. The sealing layer 452 may have horizontal portions 452A formed on the top surfaces of the gate electrode 216, the gate dielectric layer 218, and the S/D contact 230 to protect these semiconductor structures from subsequent manufacturing processes. For example, the horizontal portion 452A may prevent oxidation of underlying materials during subsequent etching or processing processes. The sealing layer 452 may further include corner portions 452B formed on the spacers 210 and the CESL 214. The top surfaces of the spacer 210 and CESL 214 may have rounded corners 410A and 414A, respectively, to facilitate growth of corner portions 452B of the sealing layer 452. The curved surfaces of the rounded corners 410A and 414A may reduce the formation of voids or discontinuities in the sealing layer 452 as compared to corners having right angles or sharp edges. The corner portions 452B of the sealing layer 452 may contour the curved surfaces of the rounded corners 410A and 414A.
The sealing layer 452 may affect the volume of air gaps subsequently formed between terminals of the semiconductor device (such as the gate electrode 216 and the S/D contact 230) by adjusting the depth of the sealing layer 452 extending into the opening 302. In particular, corner portions 452B of the sealing layer 452 may extend into the openings 302 by being formed on sidewalls of the spacers 210 and CESL 214. Opening 302 may have a depth H1And a high aspect ratio (e.g., an aspect ratio greater than about 10). A greater height H of the air gap 442 may be achieved by reducing the extension of the corner portion 452B into the opening 3022。H2And H1A greater value of the ratio of (a) may indicate a greater volume of air gap 442 in opening 302. In some embodiments, the openings 302 have a height H that may be between about 10nm and about 60nm1. For example, height H1May be between about 15nm and about 55nmBetween about 20nm and about 50nm, or any suitable height value. In some embodiments, the air gap height H2And may be between about 5nm and about 55 nm. For example, height H2May be between about 7nm and about 50nm, between about 10nm and about 45nm, or any suitable height value. In some embodiments, H2And H1May be between about 0.9 and about 2.2. For example, the ratio may be between about 1 and about 2.1, between about 1.05 and about 2, or any suitable ratio.
Any suitable dielectric material may be used to form sealing layer 452. In some embodiments, sealing layer 452 may be formed using a material that provides sufficient mechanical strength to support the air gap structure and chemical resistance to protect from subsequent chemical processes. In some embodiments, sealing layer 452 may include silicon-oxygen or silicon-carbon crosslinks. For example, the sealing layer 452 may be formed using a highly rigid silicon carbide material doped with oxygen. In some embodiments, the sealing layer 452 may be formed using a silicon carbide material. In some embodiments, sealing layer 452 can be deposited using free radical CVD, ALD, LPCVD, UHVCVD, RPCVD, PVD, any other suitable deposition process, and combinations thereof. In some embodiments, the sealing layer 452 may be deposited using a free radical CVD process with an ion filter. In some embodiments, the deposition of the sealing layer 452 may include a first operation of flowing a precursor into the deposition chamber. The precursor may provide one or more of the following binding types: silicon-oxygen, silicon-hydrogen, and silicon-carbon. In some embodiments, the precursor is in a gas phase and may include, for example, Tetramethyldisiloxane (TSMDSO), hydrogen, and oxygen. Other suitable precursors may also be included. The flow rate ratio of hydrogen to oxygen may be greater than about 20 to minimize oxidation of the underlying material while promoting the chemical reactions required for deposition. For example, the flow rate ratio of hydrogen to oxygen may be between about 20 and about 30. The deposition may further include a second operation comprising activating the plasma and for activating the precursors in their vapor phase to form silicon-oxygen and silicon-carbon crosslinks as they are deposited on the exposed surfaces. The sealing material of sealing layer 452 deposited on opposing corners 410A and 414A will gradually build up and eventually merge into sealing opening 302, thereby physically isolating air gap 442 from the environment above sealing layer 452. Air gaps 442 will be surrounded by and in physical contact with sealing layer 452, spacers 210, and CESL 214. In some embodiments, spacers 210 are formed only on the sidewalls of gate dielectric layer 218, and air gaps 442 may be in physical contact with fin region 221.
The height H of the air gap 442 may be adjusted by varying various deposition parameters of the sealing layer 4522. For example, reducing the deposition rate of the sealing layer 452 may increase the accumulation of sealing material on the sidewalls further into the opening 302 toward the bottom thereof, which may result in a lower height H of the air gap 4422(e.g., smaller air gap 442). In some embodiments, the deposition rate may be about
Figure BDA0002846385310000151
And the combination
Figure BDA0002846385310000152
In the meantime. In some embodiments, may be greater than about
Figure BDA0002846385310000153
The deposition rate of (a) performs the deposition process. For example, may be measured by
Figure BDA0002846385310000157
And the combination
Figure BDA0002846385310000154
The deposition process is carried out at a rate in between. In some embodiments, the deposition rate may be about
Figure BDA0002846385310000155
And the combination
Figure BDA0002846385310000156
In the meantime. For example, the deposition rate may be about
Figure BDA0002846385310000158
The deposition rate can be adjusted by various deposition parameters. In some implementationsIn one example, a lower chamber pressure or greater plasma power during deposition can provide a greater deposition rate. In some embodiments, the chamber pressure can be between about 0.5Torr and about 12 Torr. For example, the chamber pressure can be between 0.5Torr and about 3Torr, between about 3Torr and about 7Torr, between about 7Torr and about 12Torr, and any other suitable range or value. As another example, a chamber pressure between about 4.5Torr and about 5.5Torr may provide about
Figure BDA0002846385310000159
While a chamber pressure between about 6Torr and about 7Torr may provide a chamber pressure of about
Figure BDA0002846385310000161
Lower deposition rate.
The plasma power level of the deposition process also affects the deposition rate. For example, greater plasma power levels during a CVD process may provide greater deposition rates. In some embodiments, the plasma power level may be between about 500W and about 3000W. For example, the plasma power level may be between about 500W and about 1000W, between about 1000W and about 2000W, between about 2000W and about 3000W, and at any other suitable power level. In some embodiments, the deposition process may use a radical-triggered chemical reaction with an ion filter.
The density of the sealing layer 452 may also be adjusted by deposition parameters. Increasing the density of sealing layer 452 may provide greater mechanical support and improved chemical resistance. In some embodiments, the sealing layer 452 can have a thickness greater than about 2.0g/cm3The density of (c). For example, the sealing layer 452 may have a density of about 2.0g/cm3And about 3.2g/cm3In the meantime. In some embodiments, the density may be about 2.2g/cm3And about 2.2g/cm3In the meantime. In some embodiments, greater density can be achieved with lower chamber process pressures and higher plasma power levels. In some embodiments, the chamber process pressure can be between about 0.5Torr and about 12 Torr. For example, the chamber process pressure can be between about 0.5Torr and about 3Torr, at aboutBetween about 3Torr and about 8Torr, between about 8Torr and about 12Torr, and any other suitable range or value.
The dielectric constant of the sealing layer 452 may be less than about 5. In some embodiments, sealing layer 452 may have a dielectric constant between about 3.2 and about 5. The lower dielectric constant of the sealing layer 452 may result in a lower parasitic capacitance of the terminals of the semiconductor device 200. In some embodiments, the leakage current in the semiconductor structure 200 may be less than about 1E at 2MV/cm- 8A/cm2。
Referring to operation 708 of fig. 7, according to some embodiments, a treatment process is performed on the deposited sealing layer. Fig. 4B is a sectional view showing the semiconductor device after the treatment process is performed.
A treatment process 462 may be performed on the deposited sealing layer 452 to adjust the oxygen content of the deposited sealing material. In some embodiments, the treatment process 462 may increase the oxygen content in the deposited sealing material. In some embodiments, the treatment process 462 may be performed in an oxygen chamber environment. The oxygen environment helps to form additional Si-O-Si crosslinks in the sealing material, effectively doping the sealing material with additional oxygen atoms. In some embodiments, the treatment process 462 may reduce the oxygen content. In some embodiments, the treatment process 462 may be performed in a hydrogen chamber environment. In some embodiments, the process chamber may contain hydrogen at a predetermined pressure. The hydrogen ambient helps to remove oxygen atoms from the deposited sealing material, thereby allowing more Si-C-Si cross-links to form. In some embodiments, the silicon atom content of sealing layer 452 may be between about 25% and about 35%. In some embodiments, the oxygen atom content of the sealing layer 452 may be between about 30% and about 55%. In some embodiments, the carbon atom content of the sealing layer 452 may be between about 10% and about 35%.
The deposition/treatment processes described with reference to fig. 4A and 4B are exemplary. In some embodiments, the deposition/treatment process may be cycled until the nominal properties of the deposited sealing layer are achieved. For example, a cycle including at least one deposition operation and at least one treatment process may be performed multiple times until a nominal thickness or quality of the sealing layer 452 is achieved. In some embodiments, one cycle may be implemented. In some embodiments, the treatment process may be performed in a chamber environment filled with any suitable type of gas, such as argon, nitrogen, and any suitable gas. In some embodiments, the deposition and/or treatment process may be performed at a temperature between about 200 ℃ and about 700 ℃. For example, the deposition temperature may be between about 200 ℃ and about 500 ℃, between about 500 ℃ and about 700 ℃, and at any suitable temperature.
In some embodiments, the sealing layer 452 may be deposited by a bi-layer deposition process as in fig. 4C-4F. As shown in fig. 4C, a first encapsulant material is deposited over at least the corners of an opening in a semiconductor device, according to some embodiments. A first encapsulant 412 is deposited over the top surfaces of the gate electrode 216, the gate dielectric layer 218, the S/D contact 230, and the CESL 214. In some embodiments, a first sealing material 412 may also be deposited in the opening 302. For example, the first encapsulant material 412 may be deposited on the sidewalls of the spacers 210 and CESL 214. In some embodiments, a first encapsulant material 412 may be deposited on the bottom of the opening 302 (such as on the top surface of the horizontal portion of the spacer 210 formed on the fin region 221). In some embodiments, if a portion of the top surface of the fin region 221 is exposed between the spacer 210 and the CESL 214, a first encapsulation material 412 may also be formed on the fin region 221. The first encapsulant material 412 may include corner portions 412A formed on the spacers 210 and the CESL 214. The top surfaces of the spacer 210 and CESL 214 may have rounded corners 410A and 414A, respectively, to facilitate growth of the corner portions 412A of the first encapsulant material 412. The curved surfaces of the rounded corners 410A and 414A may reduce the formation of voids or discontinuities in the first sealing material 412 as compared to corners having right angles or sharp edges. Corner portions 412A of first encapsulant material 412 may contour the curved surfaces of rounded corners 410A and 414A. The first encapsulation material may have horizontal portions 412B formed on the top surfaces of the gate electrode 216, the gate dielectric layer 218, and the S/D contact 230 to protect them from subsequent manufacturing processes. For example, the horizontal portion 412B may prevent oxidation of underlying materials during subsequent etching or processing processes.
By adjusting the depth of the first encapsulant material 412 extending into the opening 302, the first encapsulant material 412 can affect the volume of the subsequently formed air gap between the gate electrode 216 and the S/D contact 230. In particular, corner portions 412A of the first encapsulant material 412 may extend into the openings 302 by being formed on sidewalls of the spacers 210 and CESL 214. Greater extended depth H of corner portion 412A into opening 3023A smaller subsequently formed air gap (not shown in fig. 4C) may be provided in the opening 302. E.g. H3And H1Larger values of the ratio of (a) may leave less volume in the opening 302 to form an air gap. In some embodiments, the openings 302 have a height H that may be between about 10nm and about 60nm1. For example, height H1May be between about 15nm and about 55nm, between about 20nm and about 50nm, or any suitable height value. In some embodiments, the depth of extension H3And may be between about 2nm and about 11 nm. E.g. depth H3And may be between about 5nm and about 9 nm.
Any suitable dielectric material may be used to form the first encapsulant material 412. In some embodiments, first sealing material 412 may be formed using a material that provides sufficient mechanical strength to support air gap structures and chemical resistance to protect against subsequent chemical processes. In some embodiments, the first sealing material 412 may include silicon-oxygen or silicon-carbon crosslinks. For example, a highly rigid silicon carbide material doped with oxygen may be used to form the first sealing material 412. In some embodiments, the first sealing material 412 may be formed using a silicon carbide material. In some embodiments, first seal material 412 may be deposited using free radical CVD, ALD, LPCVD, UHVCVD, RPCVD, PVD, any other suitable deposition process, and combinations thereof. In some embodiments, the first sealing material 412 may be deposited using a free radical CVD process with an ion filter. In some embodiments, the deposition of the first sealing material 412 may include a first operation of flowing a precursor into the deposition chamber. The precursor may provide one or more of the following binding types: silicon-oxygen, silicon-hydrogen, and silicon-carbon. In some embodiments, the precursor is in a gas phase and may include, for example, Tetramethyldisiloxane (TSMDSO), hydrogen, and oxygen. Other suitable precursors may also be included. The flow rate ratio of hydrogen to oxygen may be greater than about 20 to minimize oxidation of the underlying material while promoting the chemical reactions required for deposition. For example, the flow rate ratio of hydrogen to oxygen may be between about 20 and about 30. The depositing may further include a second operation including activating the plasma and for activating the precursor in its vapor phase to form silicon-oxygen and silicon-carbon crosslinks. The deposition process may include a third operation of the treatment process to reduce the oxygen content from the deposited sealing material. The treatment process may be carried out in a hydrogen chamber environment. In some embodiments, the treatment process may be performed in a chamber environment having any suitable type of gas, such as argon, nitrogen, and any suitable gas. In some embodiments, the deposition process may be performed at a temperature between about 300 ℃ and about 700 ℃. For example, the deposition temperature may be between about 300 ℃ and about 500 ℃, between about 500 ℃ and about 700 ℃, and at any suitable temperature. In some embodiments, the deposition and treatment processes may be performed cyclically, such as a cyclic process deposition-treatment process. For example, the deposition and treatment process may be followed by another deposition and treatment process until a nominal thickness or quality of the first sealing material is achieved.
The deposition rate can be adjusted by various deposition parameters. A greater deposition rate may facilitate greater accumulation of the first encapsulant material at curved surfaces 410A and 414A. The lower deposition rate may provide a greater extended depth H of the first sealing material 412 into the opening 3023. Greater deposition rates can be achieved by adjusting various suitable process parameters. In some embodiments, it may be greater than about
Figure BDA0002846385310000191
The deposition process is carried out at a deposition rate of (a). For example, it may be in the range of about
Figure BDA0002846385310000194
And the combination
Figure BDA0002846385310000192
In betweenThe deposition process is carried out at a rate. In some embodiments, the deposition rate may be about
Figure BDA0002846385310000193
And the combination
Figure BDA0002846385310000195
In the meantime. For example, the deposition rate may be about
Figure BDA0002846385310000196
In some embodiments, a lower chamber pressure or greater plasma power during deposition can provide a greater deposition rate. In some embodiments, the chamber pressure can be between about 0.5Torr and about 12 Torr. For example, the chamber pressure can be between 0.5Torr and about 3Torr, between about 3Torr and about 7Torr, between about 7Torr and about 12Torr, and any other suitable range or value. As another example, a chamber pressure between about 4.5Torr and about 5.5Torr may provide about
Figure BDA0002846385310000197
While a chamber pressure between about 6Torr and about 7Torr may provide a chamber pressure of about
Figure BDA0002846385310000198
Lower deposition rate.
The plasma power level used for deposition also affects the deposition rate. Greater plasma power levels may provide greater deposition rates. In some embodiments, the plasma power level may be between about 500W and about 3000W. For example, the plasma power level may be between about 500W and about 1000W, between about 1000W and about 2000W, between about 2000W and about 3000W, and at any other suitable power level.
The density of the first encapsulant material 412 may also be adjusted by deposition parameters. Increasing the density of the sealing material 412 may provide greater mechanical support and improved chemical resistance. In some embodiments, the first sealing material 412 may have a thickness greater than about 2.0g/cm3The density of (c). For example, a first sealing material412 may have a density of about 2.0g/cm3And about 2.2g/cm3In the meantime. In some embodiments, the density may be about 2.2g/cm3And about 3.2g/cm3In the meantime. In some embodiments, greater density can be achieved with lower chamber process pressures and greater plasma power levels. In some embodiments, the chamber process pressure can be between about 0.5Torr and about 12 Torr. For example, the chamber process pressure can be between about 0.5Torr and about 3Torr, between about 3Torr and about 8Torr, between about 8Torr and about 12Torr, and any other suitable range or value. In some embodiments, the plasma power level may be between about 500W and about 3000W. For example, the plasma power level may be between about 500W and about 2000W, between about 2000W and about 3000W, and any other suitable range or value. In some embodiments, the deposition process may use a radical-triggered chemical reaction with the ion filter.
The dielectric constant of the first encapsulant material 412 may be less than about 5. In some embodiments, the first encapsulant material 412 may have a dielectric constant between about 3.2 and about 5. The lower dielectric constant of the first encapsulant material 412 may result in lower parasitic capacitance of the terminals of the semiconductor device 200. In some embodiments, the leakage current in the semiconductor structure 200 may be less than about 1E at 2MV/cm-8A/cm2。
An optional treatment process may be applied to the first sealing material 412 to further increase the amount of internal cross-linking and/or improve its density. For example, a hydrogen annealing process may be performed to reduce the oxygen content and additional Si-C-Si bonds may be formed in the first seal material 412. The hydrogen treatment process may also remove chemical byproducts, such as H2And O. In some embodiments, the optional treatment process may be performed for less than about 1 min. For example, the treatment process may be performed for between about 40 seconds and about 1 min.
According to some embodiments, a second sealing material may be deposited over the first sealing material and in the opening. Fig. 4D is a cross-sectional view illustrating the semiconductor device after depositing a second sealing material. A second encapsulant 432 is deposited over portions of the surfaces of the first encapsulant 412, the spacers 210, and the CESL 214. Second encapsulant material 432 may include at least: (i) corner portions 432A deposited on corner portions 412A of first encapsulant material 412; (ii) (ii) a horizontal portion 432B deposited on 412B of the first encapsulant material 412, and (iii) a vertical portion 432C deposited on the sidewalls of the spacer 210 and CESL 214. In some embodiments, second encapsulant material 432 may be deposited on the bottom of opening 302 (such as on the top surface of the horizontal portion of spacer 210 formed on fin region 221).
Second encapsulant material 432 may be deposited using any suitable deposition process. For example, second sealing material 432 may be deposited using a CVD process. The semiconductor structure 200 may be loaded into a deposition chamber and then the sealing material blanket deposited. Since the precursor in the deposition chamber must move through the opening formed between the opposing corner portions 412A of the first encapsulant material 412 to be deposited on the exposed surface of the opening 302, the precursor has a lower probability of contacting the surfaces of the spacer 210 and CESL 214 than the top surface of the horizontal portion 412B. Therefore, the sealing material is deposited at a lower rate in the opening 302 below the corner portion 412A. Since the sealing material gradually accumulates on the opposite corner portions 412A of the first sealing material 412 to form the corner portions 432A of the second sealing material 432, the corner portion 432A deposited above one corner portion 412A will merge at the region 440 with the other corner portion 432A deposited above the opposite corner portion 412A. At region 440, a seam 450 is formed between adjacent corner portions 432A of second sealing material 432.
Second encapsulant 432 can affect the volume of the subsequently formed air gap between gate electrode 216 and S/D contact 230 by adjusting the depth of second encapsulant 432 that extends into opening 302. In particular, vertical portions 432C of second sealing material 432 may extend into openings 302 by being formed on sidewalls of spacers 210 and CESL 214. The distance H between the lower end of the seam 450 and the bottom surface of the opening 3024And may be between about 10nm and about 55 nm. E.g. distance H4May be between about 12nm and about 50nm, between about 15nm and about 45nm, or any suitable distance. Greater depth H4Can provideA larger air gap 442 is formed between the gate electrode 216 and the S/D contact 230. Distance H between bottom surfaces of lower closing openings 302 of vertical portions 432C5And may be less than about 45 nm. E.g. distance H5May be between about 10nm and about 40nm, between about 15nm and about 35nm, or any suitable distance. In some embodiments, vertical portion 432C may extend to the bottom of opening 302 and contact the top surface of the horizontal portion of spacer 210.
Second encapsulant material 432 can be formed using any suitable dielectric material. In some embodiments, second sealing material 432 may be formed using a material that provides sufficient bonding strength to first sealing material 412. In some embodiments, second sealing material 432 may include silicon-oxygen or silicon-carbon crosslinks. For example, the second sealing material 432 may be formed using a highly rigid silicon carbide material doped with oxygen. In some embodiments, second encapsulant material 432 may be formed using a silicon carbide material. In some embodiments, second encapsulant material 432 can be deposited using free radical CVD, ALD, LPCVD, UHVCVD, RPCVD, PVD, any other suitable deposition process, and combinations thereof. In some embodiments, second sealing material 432 may be deposited using a free radical CVD process with an ion filter. In some embodiments, the deposition of second encapsulant material 432 may be similar to the deposition process of first encapsulant material 412. In some embodiments, second sealing material 432 may be formed by a CVD process using precursors including, for example, Tetramethyldisiloxane (TSMDSO), hydrogen, and oxygen. Other suitable precursors may also be used. The flow rate ratio of hydrogen to oxygen may be greater than about 20 to minimize oxidation of the underlying material while promoting the chemical reactions required for deposition. For example, the flow rate ratio of hydrogen to oxygen may be between about 20 and about 30. The depositing may further include a second operation including activating the plasma and for activating the precursor in its vapor phase to form silicon-oxygen and silicon-carbon crosslinks. In some embodiments, the deposition process may be performed at a temperature between about 300 ℃ and about 700 ℃. For example, the deposition temperature may be between about 300 ℃ and about 450 ℃, between about 450 ℃ and about 700 ℃, and at any other suitable temperature.
The deposition rate can be adjusted by various deposition parameters. The second encapsulant material 432 may be deposited at a lower deposition rate than the first encapsulant material 412. In some embodiments, second encapsulant material 432 may be a substantially conformal film deposition over corner portions 412A and horizontal portions 412B of first encapsulant material 412. A greater deposition rate may facilitate greater accumulation of the second encapsulant material at the corner portion 412A. A lower deposition rate may provide greater extension of second encapsulant material 432 into opening 302. Greater deposition rates can be achieved by adjusting various suitable process parameters. In some embodiments, may be less than about
Figure BDA0002846385310000221
The deposition rate of (a) performs the deposition process. For example, may be measured by
Figure BDA0002846385310000223
And the combination
Figure BDA0002846385310000222
The deposition process is carried out at a rate in between. In some embodiments, a lower chamber pressure or greater plasma power during deposition can provide a greater deposition rate. In some embodiments, the chamber pressure can be between about 0.5Torr and about 12 Torr. For example, the chamber pressure can be between 0.5Torr and about 3Torr, between about 3Torr and about 7Torr, between about 7Torr and about 12Torr, and any other suitable range or value.
The plasma power level used for deposition also affects the deposition rate. Greater plasma power levels may provide greater deposition rates. In some embodiments, the plasma power level may be between about 500W and about 3000W. For example, the plasma power level may be between about 500W and about 1000W, between about 1000W and about 2000W, between about 2000W and about 3000W, and at any other suitable power level.
The density of the second encapsulant material 432 may also be adjusted by deposition parameters. Increasing the density of second encapsulant material 432 may provide greater mechanical supportAnd improved chemical resistance. In some embodiments, second sealing material 432 may have a thickness greater than about 2.0g/cm3The density of (c). For example, the density of second encapsulant 432 may be about 2.0g/cm3And about 2.2g/cm3In the meantime. In some embodiments, the density may be about 2.2g/cm3And about 3.2g/cm3In the meantime. In some embodiments, greater density can be achieved with lower chamber process pressures and greater plasma power levels. In some embodiments, the chamber process pressure can be between about 0.5Torr and about 12 Torr. For example, the chamber process pressure can be between about 0.5Torr and about 3Torr, between about 3Torr and about 8Torr, between about 8Torr and about 12Torr, and any other suitable range or value. In some embodiments, the plasma power level may be between about 500W and about 3000W. For example, the plasma power level may be between about 500W and about 2000W, between about 2000W and about 3000W, and any other suitable range or value. In some embodiments, the deposition process may use a radical-triggered chemical reaction with an ion filter.
The dielectric constant of the second encapsulant 432 may be the same as or different from that of the first encapsulant 412. For example, second encapsulant material 432 may have a dielectric constant of less than about 5. In some embodiments, second encapsulant material 432 may have a dielectric constant between about 3.2 and about 5. In some embodiments, the leakage current in the semiconductor structure 200 may be less than about 1E at 2MV/cm-8A/cm2。
According to some embodiments, the first and second sealing materials of the sealing layer may be subjected to a treatment process. Fig. 4E is a sectional view showing the semiconductor device after the treatment process is performed. A treatment process 435 may be performed on second encapsulant material 432 to remove seams, such as seam 450. For example, an oxygen annealing process may be performed, causing second sealing material 432 to physically expand and form additional bonds at seam 450. During the oxygen annealing process, portions of the Si-C-Si bonds in second sealing material 432 may become Si-O-Si bonds. In some embodiments, the total carbon atomic ratio of second sealing material 432 may be reduced by between about 5% and about 15%. The oxygen treatment process may be carried out for less than 1 min. For example, the treatment process may be performed for between about 40 seconds and about 1 min. In some embodiments, the oxygen flow rate for the treatment process 435 can be between about 1sccm and about 10 sccm. For example, the oxygen flow rate can be between about 1sccm and about 3sccm, between about 3sccm and about 5sccm, between about 5sccm and about 10sccm, and any other suitable value. The oxygen annealing process may remove any seams, such as seam 450, such that region 440 includes second sealing material 432 without any seams.
Fig. 4F is a sectional view showing the semiconductor device after a treatment process is performed on the sealing material formed on the asymmetric spacer. As shown in fig. 4F, spacers 210 and 214 have different heights along the sidewalls of gate dielectric layer 218 and the S/D contacts, respectively. For example, the spacers 210 and 214 may be formed of different materials, and the etch rate of the spacers 214 may be greater than the etch rate of the spacers 210 in response to one or more spacer etch back processes that form the curved top corners 410A and 414A. Accordingly, the corner portions 412A formed over the spacers 214 may extend down the sidewalls of the source/drain contacts 230 and toward the S/D regions 240 and the fin regions 221.
Referring to operation 710 of fig. 7, a planarization process is performed on the high-rigidity sealing layer, according to some embodiments. Fig. 5 is a cross-sectional view of the semiconductor device after performing a planarization process. As shown in fig. 5, a highly rigid encapsulant 532 is formed over the semiconductor structure 200, trapping air pockets to form air gaps 542 between the terminals of the semiconductor structure 200 and the substrate (such as the fin region 221). In some embodiments, the high rigidity sealing material 532 is formed of HRSCO. In some embodiments, the high rigidity sealing material 532 is a seamless sealing material. A highly rigid sealing material 532 may be formed between and in physical contact with spacer 210 and CESL 214. The high rigidity sealing material 532 may also be in contact with other structures not shown in fig. 5. A planarization process may be used to remove horizontal portion 452A as shown in fig. 4B or portions of first encapsulant material 412 and second encapsulant material 432 as shown in fig. 4E. The planarization process may continue until the top surfaces of the gate electrode 216, the gate dielectric layer 218, the spacers 210, the CESL 214, and the S/D contacts 230 are exposed and substantially flush (e.g., on the same plane). After the planarization process, the corner portion 452A of the sealing layer 452 or the remaining portions of the first and second sealing materials 412 and 432 may form the high-rigidity sealing material 532. The trapped air pockets of the highly rigid encapsulant 532 may form air gaps 542 between the terminals (such as gate structures 208) of the semiconductor structure 200 and the S/D contacts 230. In some embodiments, the gas gap 542 may include different types of gases. For example, the gas gap 542 may include oxygen, hydrogen, helium, argon, nitrogen, any other suitable type of gas, and combinations thereof. The lower deposition rate of the high stiffness sealing material 532 may produce air gaps 542 with smaller volumes. For example, highly rigid encapsulant 532 may be formed by depositing encapsulant 452 or first encapsulant 412 and second encapsulant 432, and a lower deposition rate may provide air gaps 542 with shorter heights, resulting in a smaller air gap volume. Since the air gap 542 may have a dielectric constant of about 1, the effective dielectric constant of the spacer 210 and the air gap 542 may be lower compared to a spacer structure including the spacers 210 and 214.
Referring to operation 712 of fig. 7, a dielectric layer and an interconnect structure are formed, according to some embodiments. Fig. 6 is a cross-sectional view illustrating a dielectric layer and an interconnect structure formed on a semiconductor device.
A dielectric layer 620 may be formed on top surfaces of the gate electrode 216, the gate dielectric layer 218, the spacers 210, the high rigidity sealing material 532, the CESL 214, the S/D contact 230, and other suitable structures. In some embodiments, dielectric layer 620 may be an etch stop layer. Dielectric layer 620 may be formed using a low-k dielectric material, such as silicon oxide, for example, a dielectric layer having a dielectric constant less than about 3.9. An inter-layer dielectric (ILD) layer 650 may be formed on the dielectric layer 620. The ILD layer 650 may be formed of a low-k dielectric material. For example, the ILD layer 650 may be formed using silicon oxide. In some embodiments, dielectric layer 620 and ILD layer 650 may be formed using CVD, ALD, PVD, flowable CVD (fcvd), sputtering, any suitable deposition process, and combinations thereof. Vias may be formed in ILD 650 to establish electrical connections from S/D contacts 230 and gate electrodes 216 to external circuitry, such as peripheral circuitry formed over semiconductor structure 200. A gate via 616 may be formed in ILD 650 and extend through dielectric layer 620 to make physical contact with gate electrode 216. Similarly, the S/D vias 630 may extend through the ILD 650 and make physical contact with the S/D contacts 230. Gate via 616 and S/D via 630 may be formed by a patterning and etching process. For example, openings may be formed in the ILD 650 and through the dielectric layer 620 to expose the gate electrode 216 and the S/D contact 230, respectively. A deposition process may be performed to deposit a conductive material in the openings so that electrical connections may be made. Examples of deposition processes may be PVD, sputtering, electroplating, electroless plating, any suitable deposition process, and combinations thereof. A planarization process may be performed after the deposition process such that the top surfaces of ILD 650, gate via 616, and S/D via 630 may be substantially coplanar (e.g., horizontal). In some embodiments, the gate via 616 and the S/D via 630 may be formed using tungsten, aluminum, cobalt, silver, any suitable conductive material, and combinations thereof.
The highly rigid encapsulation material may also be used as an etch stop layer to facilitate subsequent structure formation or as a self-aligned contact (SAC) for gate electrode 216 and S/D contact 230. In some embodiments, a SAC can be formed on the top surface of gate electrode 216 and/or S/D contact 230. The use of high rigidity sealing materials to form SACs can provide the following benefits, among others: prevention of electrical shorts, low leakage current, high uniformity and good etch resistance. In some embodiments, the SAC may also be formed of a dielectric material (such as silicon nitride, silicon oxide, silicon oxynitride, silicon oxycarbide, silicon oxycarbonitride, any suitable dielectric material, and/or combinations thereof). SACs can be formed on the gate electrode, the S/D contacts, or both. For clarity, a single SAC scheme is used to describe a semiconductor device having SACs formed on only one type of terminal, such as on a gate electrode or an S/D contact. Similarly, the dual SAC scheme may be used to describe a semiconductor device having SACs formed on at least two types of terminals (such as on both gate electrodes and S/D contacts). Fig. 8to 16 describe respective configurations of a semiconductor device including a single SAC scheme and a dual SAC scheme having a high-rigidity sealing layer formed in a gap and also serving as a CESL. In some embodiments, the high-stiffness sealant layer may also not include seams due to the manufacturing process described above in fig. 4A-4F.
Fig. 8 illustrates a semiconductor device 800 having a single SAC scheme and a high rigidity sealing layer formed in the gap between terminals according to some embodiments. For the sake of simplicity, structures similar to those described in fig. 1 to 6 shown in fig. 8 are not described in detail. Semiconductor device 800 may incorporate a single SAC scheme and include a SAC formed on gate electrode 216 or S/D contact 230. For example, a SAC 810 may be formed on the top surface of the gate electrode 216, as shown in fig. 8. In some embodiments, a SAC 810 may be formed on the top surface of the S/D contact 230 (not shown in FIG. 8). SAC 810 may be formed by etching back portions of gate electrodes 216 such that a recess is formed between the top of each gate electrode 216 and the opposing sidewalls of gate dielectric layer 218. A dielectric material may be deposited into the grooves to form SAC 810. In some embodiments, SAC 810 may be formed using silicon oxide, silicon nitride, silicon oxycarbide, silicon oxynitride, silicon oxycarbonitride, any suitable dielectric material, and combinations thereof. In some embodiments, SAC 810 may be formed prior to the formation of high rigidity sealing material 532. In some embodiments, SAC 810 may be formed after high rigidity sealing material 532 is formed. A planarization process may be performed such that top surfaces of the SAC 810, the gate dielectric layer 218, the spacer 210, the CESL 214, and the high rigidity sealing material 532 are substantially coplanar (e.g., on the same plane). A dielectric layer 620, ILD 650, gate via 616 and S/D via 630 may be formed on the planarized top surface. In some embodiments, gate via 616 may extend through dielectric layer 620 and SAC 810 and come into physical contact with gate electrode 216.
Fig. 9A and 9B illustrate a semiconductor device 900 having a single SAC scheme and a high rigidity sealing layer as a CESL and also as a gap sealing layer between terminals, according to some embodiments. For the sake of simplicity, structures similar to those described in fig. 1 to 8 shown in fig. 9A and 9B are not described in detail. As shown in fig. 9A, a high rigidity encapsulant 932 may include a first portion 932A formed between terminals of semiconductor device 900 and a second portion 932B formed on top surfaces of SAC 810, gate dielectric layer 218, spacer 210, S/D contact 230, and CESL 214. The high rigidity sealing material 932 may be formed using methods similar to those described above in fig. 4A to 4F and fig. 7, and will not be described in detail here for the sake of simplicity. Air gaps 942 may be formed between terminals of the semiconductor device 900, and the size of the air gaps 942 may depend on various factors, such as the deposition rate of the high rigidity sealing material 932. In some embodiments, the density of the high rigidity sealing material 932 may be adjusted based on the device design. For example, increasing the density of the high rigidity sealing material 932 may provide, among other things, greater etch resistance. In some embodiments, the second portion 932B of the highly rigid encapsulant 932 may serve as a CESL for forming subsequent structures, such as vias for the SAC 810 and the S/D contacts 230, as further described below with reference to fig. 9B.
As shown in fig. 9B, an ILD layer 950 may be formed on the second portion 932B of the high rigidity sealing material 932B. ILD layer 950 may be similar to ILD layer 650 depicted in fig. 6. For example, ILD layer 950 may be formed using silicon oxide. In some embodiments, ILD layer 950 may be formed using CVD, ALD, PVD, flowable CVD (fcvd), sputtering, any suitable deposition process, and combinations thereof. Vias may be formed in ILD 950 to establish electrical connections from S/D contacts 230 and gate electrodes 216 to external circuitry, such as peripheral circuitry formed over semiconductor structure 200. A gate via 916 may be formed in ILD 650 and extend through second portion 932B of high rigidity encapsulant 932 to make physical contact with gate electrode 216. Similarly, the S/D vias 630 may extend through the ILD 650 and make physical contact with the S/D contacts 230. Gate via 616 and S/D via 630 may be formed by a patterning and etching process. For example, openings may be formed in the ILD 650 and by a patterning and etching process to expose the underlying second portion 932B of the highly rigid encapsulant 932. The second portion 932B may be used as a CESL during the formation process of the opening. High density (e.g., greater than about 2.0 g/cm) of the high rigidity sealing material 9323) Can be used forTo provide improved etch resistance. A deposition process may be performed to deposit conductive material in the openings to form gate vias 916 and S/D vias 930 so that electrical connections may be made. Examples of deposition processes may be PVD, sputtering, electroplating, electroless plating, any suitable deposition process, and combinations thereof. A planarization process may be performed after the deposition process such that the top surfaces of the ILD 950, gate via 916, and S/D via 930 may be substantially coplanar (e.g., on the same plane). In some embodiments, the gate via 916 and the S/D via 930 may be formed using tungsten, aluminum, cobalt, silver, any suitable conductive material, and combinations thereof. In some embodiments, gate via 916 may extend through second portion 932B and SAC 810 and make physical contact with gate electrode 216.
Fig. 10A-10D illustrate a semiconductor device 1000 having a single SAC scheme and a high-rigidity sealing layer as the SAC and also as the gap sealing layer between the terminals, according to some embodiments. For simplicity, structures shown in fig. 10A to 10D similar to those described in other figures (such as fig. 2 and 8) are not described in detail.
Fig. 10A is a cross-sectional view of a semiconductor device 1000 having terminals and spacers formed between the terminals according to some embodiments. For example, the semiconductor device 1000 may include a gate electrode 216 and spacers 210 and 212. In some embodiments, a SAC formed using a high-rigidity sealing material may be formed after forming the S/D contact. In some embodiments, the SAC can be formed prior to the formation of the S/D contact. The S/D contacts may be formed by alternative processes, such as removing the dielectric layer and depositing a conductive instead of the dielectric layer. As shown in fig. 10A, a dielectric layer 1020 is formed on the CESL 214 and over the S/D regions 240. Dielectric layer 1020 may be formed using materials similar to the materials used to form ILD 650 and ILD 950. For example, the dielectric layer 1020 may be formed using silicon oxide. Dielectric layer 1020 may be removed and replaced with one or more conductive materials, as described further below in fig. 10B.
Fig. 10B is a sectional view of the semiconductor device 1000 after forming a SAC using a highly rigid sealing material and an S/D contact. As shown in fig. 10B, S/D contact 1030 is formed in place of dielectric layer 1020. In some embodiments, the S/D contacts are formed by removing dielectric layer 1020 and performing a deposition process to fill the voids left by removing dielectric layer 1020. The deposition process may include depositing a conductive material until a top surface of the deposited conductive material is at least flush with a top surface of the gate dielectric layer 218 and the spacers 210. The conductive material may include any suitable conductive material, such as a metal, metal alloy, doped semiconductor material, and/or combinations thereof.
SAC 1010 may be formed on gate electrode 216 using an etch-back process similar to the etch-back process used to form SAC 810 described above with reference to fig. 8. For example, one or more etching processes may be performed to etch back the gate electrode 216 to form an opening between opposing sidewalls of the gate dielectric layer 218. A high rigidity sealing material may be blanket deposited over the exposed surfaces and into the openings until the high rigidity sealing material completely fills the openings. Any excess high rigidity sealing material may be removed using a planarization process, resulting in SAC 1010 being formed on the top surface of recessed gate electrode 216. The SAC 1010 may be formed using methods similar to those described above with reference to fig. 4A through 4F. For example, HRSCO may be used to form SAC 1010. In some embodiments, the oxygen content of the SAC 1010 may be adjusted according to device requirements. For example, increasing the oxygen content of the SAC 1010 may also provide other benefits.
Fig. 10C is a cross-sectional view of semiconductor device 1000 after depositing a high rigidity sealing material into gaps between terminals of the semiconductor device, according to some embodiments. Similar to the process described with reference to fig. 3, the spacers 212 may be removed to form openings between the terminals of the semiconductor device 1000. A high rigidity sealing material 1032 may be deposited into the opening and formed toward the top of the opening. The formation and properties of the high rigidity sealing material 1032 may be similar to those of the high rigidity sealing material 532 described above in fig. 4A, 4B, and 5.
Fig. 10D is a cross-sectional view of semiconductor device 1000 after forming a dielectric layer and an interconnect structure, in accordance with some embodiments. As shown in fig. 10D, a dielectric layer 1020 and an ILD layer 1050 may be formed over the SAC 1010, S/D contacts 1030, and other exposed structures of the semiconductor device 1000. In some embodiments, dielectric layer 1020 may be CESL. A gate via 1016 and an S/D via 1060 may be formed in ILD 1050 extending through dielectric layer 1020. In some embodiments, gate via 1016 may extend through dielectric layer 1020 and SAC 1010 and make physical contact with gate electrode 216. In some embodiments, dielectric layer 1020, ILD 1050, gate via 1016, and S/D via 1060 may be similar to dielectric layer 620, ILD 650, gate via 616, and S/D via 616, respectively, and are not described in detail herein for simplicity.
Fig. 11A and 11B illustrate a semiconductor device 1100 having a single SAC scheme and a high-rigidity sealing layer as a SAC, CESL, and also as a gap sealing layer between terminals, according to some embodiments. For simplicity, structures shown in fig. 11A and 11B similar to those described in other figures (such as fig. 8, 9A, 9B, and 10) are not described in detail.
Fig. 11A is a cross-sectional view of a semiconductor device 1100 having a highly rigid sealing material as a SAC, CESL, and gap sealing layer. For example, the high-rigidity sealing material 1132 may include a first portion 1132A that is formed between terminals of the semiconductor device 1100 and serves as a gap sealing layer to form the air gap 1142. The highly rigid encapsulant 1132 may include a second portion 1132B formed on the top surface of the SAC 1010, spacer 210, gate dielectric layer 218, S/D contact 1030, and other suitable structures. The first and second portions 1132A, 1132B of the high-rigidity sealing material 1132 may be similar to the first and second portions 932A, 932B of the high-rigidity sealing material 932 described above in fig. 9A and 9B, respectively, and are not described in detail herein for the sake of simplicity. The second portion 1132B of the high-stiffness encapsulant material 1132 may be used as a CESL for subsequent formation of dielectric layers and interconnect structures. The high rigidity sealing material 1132 may also provide the following benefits: high etch resistance, lower leakage current, and high uniformity. In some embodiments, SAC, CESL, and gap seal materials, all formed using highly rigid materials (such as HRSCO), may also provide low contamination benefits, as SAC and gap seal materials may be deposited in situ without removing semiconductor device 1100 from one deposition chamber and loading it into another.
Fig. 11B is a cross-sectional view of semiconductor device 1100 after forming a dielectric layer and interconnect structures, in accordance with some embodiments. As shown in fig. 11B, an ILD layer 1150 may be formed on the SAC 1010, the S/D contact 1030, and other exposed structures of the semiconductor device 1100. A gate via 1116 and an S/D via 1160 extending through the second portion 1132B of the high rigidity sealing material 1132 may be formed in the ILD 1150. In some embodiments, gate via 1116 may extend through dielectric second portion 1132B and SAC 1010, and may be in physical contact with gate electrode 216. In some embodiments, the ILD 1150, gate via 1116 and S/D via 1160 may be similar to ILD 650, gate via 616 and S/D via 616, respectively, and are not described in detail herein for simplicity.
Fig. 12 illustrates a semiconductor device 1200 having a dual SAC scheme and a high rigidity sealing layer as a gap sealing layer between terminals according to some embodiments. For simplicity, structures shown in fig. 12 that are similar to those described in other figures (such as fig. 2-11B) are not described in detail herein. The dual SAC scheme includes SACs formed on more than one type of terminals in the semiconductor device 1200. For example, the SAC 810 may be formed over the gate electrode 216. In some embodiments, a SAC 1210 can be formed on the S/D contact 230. SAC 1210 may be formed using materials similar to SAC 810. For example, the SAC 1210 may be formed using silicon oxide. A high rigidity layer 532 may be formed between terminals of the semiconductor device 1200 as a gap sealing layer to form a gap 1042 surrounded by the high rigidity layer 532, the spacer 210, and the CESL 214. In some embodiments, the SAC 1210 may be formed prior to formation of the SAC 810. In some embodiments, the SAC 1210 may be formed after formation of the SAC 810. SAC 810 and 1210 may be formed by an etch-back process to recess semiconductor device terminals followed by a deposition process to deposit a dielectric material on the recessed semiconductor device terminals. For example, the SAC 1210 may be formed by an etch-back process to recess the S/D contact 230, and a dielectric material is deposited on the recessed S/D contact 230. An exemplary fabrication process for forming semiconductor device 1200 may include: etch back gate electrode 216 and deposit dielectric material on recessed gate electrode 216 to form SAC 810, form S/D contact 230 over S/D region 240, form an opening between terminals of semiconductor device 1200, form high rigidity layer 532 in the opening, deposit dielectric layer 620, deposit ILD layer 650 on dielectric layer 620, and form gate via 616 and S/D via 630 in ILD layer 650 through dielectric layer 620. In some embodiments, the gate vias and the S/D vias may extend through SACs 810 and 1210, respectively. Other operations may be used to form semiconductor device 1200 and the order of the operations may vary.
Fig. 13 illustrates a semiconductor device 1300 having a dual SAC scheme and a high rigidity sealing layer that serves as a gap sealing layer between terminals and also as a CESL, according to some embodiments. For simplicity, structures shown in fig. 13 similar to those described in other figures (such as shown in fig. 2-12) are not described in detail. For example, the high-rigidity sealing material 932 may include a first portion 932A formed between terminals of the semiconductor device 1300 and a second portion 932B formed on a top surface of each structure. The second portion 932B may serve as a CESL for forming the gate via 916 and the S/D via 930. The air gap 942 is surrounded by the CESL 214, the spacer 210, and the highly rigid encapsulant 932. In some embodiments, the high-rigidity sealing material 932 may be formed using a manufacturing method similar to that described with reference to fig. 4A to 4F. An exemplary fabrication process for forming the semiconductor device 1300 may include: etch back gate electrode 216 and deposit dielectric material on recessed gate electrode 216 to form SAC 810, form S/D contact 230 over S/D region 240, etch back S/D contact 230 and deposit dielectric material to form SAC 1210, form an opening between the terminals of semiconductor device 1200, form first portion 932A of high rigidity layer 932 in the opening and form second portion 932B on the top surface of the terminal, deposit ILD layer 950 on high rigidity layer 932, and form gate via 916 and S/D via 930 in ILD layer 950 through high rigidity layer 932. In some embodiments, gate via 916 and S/D via 930 extend through SACs 810 and 1210, respectively. Other operations may be used to form semiconductor device 1300, and the order of the operations may vary.
Fig. 14 shows a semiconductor device 1400 with a dual SAC scheme and a high rigidity sealing layer that serves as a gap sealing layer between terminals and also as a SAC for S/D contacts, according to some embodiments. For simplicity, structures shown in fig. 14 similar to those described in other figures (such as shown in fig. 2-13) are not described in detail. In some embodiments, HRSCO may be used to form high rigidity sealing material 1032. In some embodiments, a high-rigidity sealing material 1032 may be formed between terminals of the semiconductor device 1400. In some embodiments, a SAC 1460 may be formed on S/D contact 1030. In some embodiments, SAC 1460 may be formed using a material similar to high rigidity sealing material 1032. In some embodiments, SAC 1460 may be formed using an etch-back process similar to the etch-back process described above with reference to fig. 10A-10D. In some embodiments, the high rigidity sealing material 1032 and SAC 1460 may be formed during the same manufacturing operation. For example, S/D contact 1030 may be etched back to form a recess between opposing sidewalls of CESL 1030. One or more spacers between the terminals of the semiconductor device 1400 may be removed to form openings between the terminals. A high rigidity material can be deposited in the openings between the terminals and on the recessed S/D contacts 1030 to form the SAC 1460 using a fabrication process that includes depositing the high rigidity material and one or more processing processes. In some embodiments, the high rigidity sealing material 1032 may be formed using a manufacturing method similar to that described with reference to fig. 4A to 4F. An exemplary fabrication process for forming the semiconductor device 1400 may include: etch back gate electrode 216 and deposit dielectric material on recessed gate electrode 216 to form SAC 1010, form S/D contact 1030 over S/D region 240, etch back S/D contact 1030, form an opening between the S/D contact and gate electrode 216, deposit high rigidity material to form high rigidity encapsulant 1032 in the opening and SAC 1460 on S/D contact 1030, deposit dielectric layer 1020 on the top surface of the terminal and high rigidity encapsulant 1032, perform a planarization process, deposit ILD layer 1050, and form gate via 1016 and S/D via 1060 through dielectric layer 1020 in ILD layer 1050. In some embodiments, gate via 1016 and S/D via 1060 extend through SACs 1010 and 1460, respectively. Other operations may be used to form the semiconductor device 1400, and the order of the operations may vary.
Fig. 15 illustrates a semiconductor device 1500 having a dual SAC scheme and a high rigidity sealing layer that functions as: (i) a gap seal layer between the terminals, (ii) SAC for S/D contacts, and (iii) CESL. For simplicity, structures shown in fig. 15 similar to those described in other figures (such as fig. 2-14) are not described in detail. In some embodiments, the high-rigidity sealing material 1132 may include a first portion 1132A formed between the terminals of the semiconductor device 1500 and a second portion 1132B extending horizontally and formed on the top surface of the terminals. The terminal may include a gate electrode 216 and an S/D contact 1030. In some embodiments, high rigidity materials may also be used to form SACs. For example, the SAC 1510 for the S/D contact 1030 may be formed using a high-rigidity sealing material. In some embodiments, SAC 1010 and high-rigidity sealing material 1132 may be formed in the same manufacturing step and composed of substantially the same type of material. For example, the SAC 1010 and the high rigidity sealing material 1132 may have substantially the same atomic percent of oxygen. In some embodiments, the SAC 1010 and the high-rigidity sealing material 1132 may be formed using high-rigidity materials having different compositions. The dual SAC scheme employed by semiconductor device 1500 may also include SAC for gate electrode 216. For example, the SAC 1010 may be formed on the top surface of the gate electrode 216. The SAC 1010 may be formed using a highly rigid sealing material. In some embodiments, the SAC 1010 may be formed using a dielectric material (such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon oxycarbonitride, and any suitable dielectric material). An exemplary manufacturing process of the semiconductor device 1500 having a dual SAC scheme and a high rigidity sealing material may include: for example, etch back to recess gate electrode 216, deposit dielectric material on the recessed gate electrode to form SAC 1010, etch back to recess S/D contact 1030, form an opening between S/D contact 1030 and gate electrode 216, deposit a highly rigid sealing material in the opening and over recessed S/D contact 1030 and SAC 1010, perform a planarization process, form ILD 1150, and form gate via 1116 and S/D via 1160. In some embodiments, the gate via 1116 and the S/D via 1160 may extend through the SACs 1010 and 1510, respectively. Other operations may be used to form semiconductor device 1500 and the order of the operations may be varied.
Fig. 16 shows a semiconductor device 1600 with a dual SAC scheme and a high-rigidity sealing layer that serves as a gap sealing layer between terminals, as a SAC for a gate electrode, and also as a CESL, according to some embodiments. For simplicity, structures shown in fig. 16 similar to those described in other figures (such as fig. 2-15) are not described in detail. In some embodiments, the high-rigidity sealing material 1132 may include a first portion 1132A formed between the terminals of the semiconductor device 1600 and a second portion 1132B extending horizontally and formed on the top surface of the terminals. In some embodiments, high rigidity materials may also be used to form SACs. For example, SAC 1620 for the gate electrode 216 can be formed using a highly rigid sealing material. In some embodiments, SAC 1620 and high-rigidity sealing material 1132 may be formed in the same manufacturing step and composed of substantially the same type of material. For example, the SAC 1620 and the high rigidity sealing material 1132 may have substantially the same atomic percent of oxygen. In some embodiments, SAC 1620 and high-rigidity sealing material 1132 may be formed using high-rigidity materials having different compositions. The dual SAC scheme employed by semiconductor device 1600 may also include SAC for S/D contact 1030. For example, a self-aligned S/D contact (such as SAC 1610) can be formed on the top surface of S/D contact 1030. In some embodiments, the SAC 1610 may be formed using a highly rigid sealing material. In some embodiments, the SAC 1610 may be formed using a dielectric material (such as silicon nitride, silicon oxide, silicon carbide, silicon oxycarbide, silicon oxycarbonitride, and any suitable dielectric material). An exemplary manufacturing process of the semiconductor device 1600 having a dual SAC scheme and a high rigidity sealing material may include: for example, etch back to recess gate electrode 216, depositing a high rigidity sealing material on the recessed gate electrode to form SAC 1620, forming S/D contact 1030, forming SAC 1610 on S/D contact 1030, forming an opening between S/D contact 1030 and gate electrode 216, depositing a high rigidity sealing material in the opening, on SAC 1620 and on SAC 1610, performing a planarization process, forming ILD 1150, and forming gate via 1116 and S/D via 1160. Other operations may be used to form the semiconductor device 1600, and the order of the operations may vary.
Various embodiments of the present invention provide a semiconductor device and a method of manufacturing the same to provide a simple and cost-effective structure and process for producing a high-rigidity sealing layer in a semiconductor device. A highly rigid sealing layer may be used to seal the openings and form air gaps between the terminals of the semiconductor device to reduce the effective dielectric constant, which may improve device performance. A high-rigidity sealing material may also be formed on the top surfaces of the terminals of the semiconductor device as a contact etch stop layer. Highly rigid encapsulation materials may also be used as self-aligned contacts for the terminals of the semiconductor device.
In some embodiments, a semiconductor device includes first and second terminals formed on a fin region and an encapsulation layer formed between the first and second terminals. The sealing layer includes a silicon carbide material doped with oxygen. The semiconductor device also includes an air gap surrounded by the sealing layer, the fin region, and the first and second terminals.
In some embodiments, a semiconductor device includes a gate structure located over a fin region. The gate structure includes a gate electrode and a self-aligned contact (SAC) formed on the gate electrode. The SAC comprises a silicon carbide material doped with oxygen. The semiconductor device also includes source/drain (S/D) contacts and an encapsulation layer having a silicon carbide material doped with oxygen. The sealing layer also includes a first portion located between the gate structure and the S/D contact and a second portion located on the top surface of the SAC and S/D contacts. The semiconductor device also includes an air gap surrounded by the sealing layer, the fin region, the gate electrode, and the S/D contact.
In some embodiments, a method for forming a semiconductor device includes forming an opening over a top surface of a substrate and between first and second terminals of the semiconductor device. The method also includes forming a silicon carbide material including depositing a first portion of the silicon carbide material in the opening and between the first and second terminations. The method also includes depositing a second portion of the silicon carbide material on the top surfaces of the first and second terminations. A bladder is trapped in an opening surrounded by the silicon carbide material, the first and second terminals, and the substrate. The method further includes performing an oxygen annealing process on the first and second portions of the deposited silicon carbide material.
In some embodiments, a semiconductor device, comprises: a first terminal and a second terminal formed on the fin region; a sealing layer formed between the first terminal and the second terminal, wherein the sealing layer comprises a silicon carbide material doped with oxygen; and an air gap surrounded by the sealing layer, the fin region, and the first and second terminals. In some embodiments, the first terminal comprises a gate electrode and the second terminal comprises a source/drain (S/D) contact. In some embodiments, the first terminal further comprises: a gate dielectric layer on sidewalls of the gate electrode; and a spacer comprising a first portion on a sidewall of the gate dielectric layer and a second portion on a top surface of the fin region. In some embodiments, the air gap is in physical contact with the first portion and the second portion of the spacer. In some embodiments, the sealing layer has a density of 2.0g/cm3And 3.2g/cm3In the meantime. In some embodiments, the oxygen atom content of the sealing layer is between 30% and 55%. In some embodiments, the carbon atom content of the sealing layer is between 10% and 35%. In some embodiments, the silicon atom content of the sealing layer is between 25% and 35%. In some embodiments, top surfaces of the sealing layer, the first terminal, and the second terminal are substantially coplanar. In some embodiments, the semiconductor device further comprises: a self-aligned contact (SAC) on the first terminal, wherein the self-aligned contact comprises a silicon carbide material doped with oxygen and has a top surface coplanar with a top surface of the sealing layer.
In some embodiments, a semiconductor device includes: a gate structure on the fin region, comprising: a gate electrode; and self-alignmentA Contact (SAC) formed on the gate electrode and including a silicon carbide material doped with oxygen; a source/drain (S/D) contact; a sealing layer comprising the silicon carbide material doped with oxygen, wherein the sealing layer further comprises: a first portion between the gate structure and the source/drain contact; and a second portion on top surfaces of the self-aligned contact and the source/drain contact; and an air gap surrounded by the sealing layer, the fin region, the gate electrode, and the source/drain contacts. In some embodiments, the sealing layer has a density of 2.0g/cm3And 3.2g/cm3In the meantime. In some embodiments, the oxygen atom content of the sealing layer is between 30% and 55%. In some embodiments, the semiconductor device further comprises: a through-hole extending through a second portion of the sealing layer and in physical contact with the self-aligned contact. In some embodiments, the semiconductor device further comprises: a gate dielectric layer and a spacer, wherein the spacer includes a first portion on a sidewall of the gate dielectric layer and a second portion on a top surface of the fin region.
In some embodiments, a method of forming a semiconductor device includes: forming an opening over a top surface of a substrate and between a first terminal and a second terminal of the semiconductor device; and forming a silicon carbide material comprising: depositing a first portion of the silicon carbide material in the opening and between the first terminal and the second terminal; depositing a second portion of the silicon carbide material on top surfaces of the first and second terminals, wherein a gas pocket is trapped in the opening surrounded by the silicon carbide material, the first and second terminals, and the substrate; and performing an oxygen annealing process on the deposited first and second portions of the silicon carbide material. In some embodiments, the first portion of the silicon carbide material is deposited toward a top of the opening. In some embodiments, depositing the first and second portions of the silicon carbide material includes flowing Tetramethyldisiloxane (TSMDSO), hydrogen, and oxygen into a deposition chamber. In some embodiments, the flow rate ratio of the hydrogen gas to the oxygen gas is between 20 and 30. In some embodiments, the method further comprises: etching the first terminal to recess the first terminal; depositing another silicon carbide material over the recessed first terminal; and performing another oxygen annealing process on the deposited silicon carbide material.
It is to be understood that the detailed description section, and not the abstract, is intended to be used to interpret the claims. The abstract of the disclosure may set forth one or more, but not all contemplated exemplary embodiments, and is therefore not intended to limit the dependent claims.
The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the aspects of the present invention. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present invention, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the appended claims.

Claims (10)

1. A semiconductor device, comprising:
a first terminal and a second terminal formed on the fin region;
a sealing layer formed between the first terminal and the second terminal, wherein the sealing layer comprises a silicon carbide material doped with oxygen; and
an air gap surrounded by the sealing layer, the fin region, and the first and second terminals.
2. The semiconductor device of claim 1, wherein the first terminal comprises a gate electrode and the second terminal comprises a source/drain (S/D) contact.
3. The semiconductor device of claim 2, wherein the first terminal further comprises:
a gate dielectric layer on sidewalls of the gate electrode; and
a spacer comprising a first portion on a sidewall of the gate dielectric layer and a second portion on a top surface of the fin region.
4. The semiconductor device of claim 3, wherein the air gap is in physical contact with the first and second portions of the spacer.
5. The semiconductor device of claim 1, wherein the sealing layer has a density of 2.0g/cm3And 3.2g/cm3In the meantime.
6. The semiconductor device of claim 1, wherein the oxygen atom content of the sealing layer is between 30% and 55%.
7. The semiconductor device of claim 1, wherein the carbon atom content of the sealing layer is between 10% and 35%.
8. The semiconductor device of claim 1, wherein the silicon atom content of the sealing layer is between 25% and 35%.
9. A semiconductor device, comprising:
a gate structure on the fin region, comprising:
a gate electrode; and
a self-aligned contact (SAC) formed on the gate electrode and including a silicon carbide material doped with oxygen;
a source/drain (S/D) contact;
a sealing layer comprising the silicon carbide material doped with oxygen, wherein the sealing layer further comprises:
a first portion between the gate structure and the source/drain contact; and
a second portion on top surfaces of the self-aligned contact and the source/drain contact; and
an air gap surrounded by the sealing layer, the fin region, the gate electrode, and the source/drain contacts.
10. A method of forming a semiconductor device, comprising:
forming an opening over a top surface of a substrate and between a first terminal and a second terminal of the semiconductor device; and
forming a silicon carbide material comprising:
depositing a first portion of the silicon carbide material in the opening and between the first terminal and the second terminal;
depositing a second portion of the silicon carbide material on top surfaces of the first and second terminals, wherein a gas pocket is trapped in the opening surrounded by the silicon carbide material, the first and second terminals, and the substrate; and
performing an oxygen annealing process on the deposited first and second portions of the silicon carbide material.
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US16/937,344 US11296187B2 (en) 2019-12-20 2020-07-23 Seal material for air gaps in semiconductor devices
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US17/100,533 US11502166B2 (en) 2019-12-20 2020-11-20 Seal material for air gaps in semiconductor devices

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