CN113013226B - Semiconductor device and method of forming semiconductor device - Google Patents

Semiconductor device and method of forming semiconductor device Download PDF

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Publication number
CN113013226B
CN113013226B CN202011510967.6A CN202011510967A CN113013226B CN 113013226 B CN113013226 B CN 113013226B CN 202011510967 A CN202011510967 A CN 202011510967A CN 113013226 B CN113013226 B CN 113013226B
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China
Prior art keywords
semiconductor device
layer
gate
terminal
sealing layer
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CN202011510967.6A
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Chinese (zh)
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CN113013226A (en
Inventor
梁顺鑫
王振翰
林耕竹
上野哲嗣
陈婷婷
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Priority claimed from US16/937,344 external-priority patent/US11296187B2/en
Priority claimed from US17/100,533 external-priority patent/US11502166B2/en
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN113013226A publication Critical patent/CN113013226A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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  • Engineering & Computer Science (AREA)
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  • Microelectronics & Electronic Packaging (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
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  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

The invention relates to a semiconductor device including first and second terminals formed on a fin region and a sealing layer formed between the first and second terminals. The sealing layer comprises a silicon carbide material doped with oxygen. The semiconductor device further includes an air gap surrounded by the encapsulation layer, the fin region, and the first and second terminals. The invention also relates to a method of forming a semiconductor device.

Description

Semiconductor device and method of forming semiconductor device
Technical Field
Embodiments of the present application relate to semiconductor devices and methods of forming semiconductor devices.
Background
The semiconductor Integrated Circuit (IC) industry has experienced an exponential growth. Technological advances in IC materials and design have resulted in multi-generation ICs, where each generation has smaller and more complex circuitry than the previous generation. During the development of ICs, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry (i.e., the smallest component or line that can be created using a manufacturing process) has decreased. Such scaled down processes generally provide benefits by improving production efficiency and reducing associated costs.
Disclosure of Invention
Some embodiments of the present application provide a semiconductor device including: a first terminal and a second terminal formed on the fin region; a sealing layer formed between the first terminal and the second terminal, wherein the sealing layer comprises a silicon carbide material doped with oxygen; and an air gap surrounded by the sealing layer, the fin region, and the first and second terminals.
Other embodiments of the present application provide a semiconductor device comprising: a gate structure located on the fin region, comprising: a gate electrode; and a self-aligned contact (SAC) formed on the gate electrode and comprising a silicon carbide material doped with oxygen; source/drain (S/D) contacts; a sealing layer comprising the silicon carbide material doped with oxygen, wherein the sealing layer further comprises: a first portion located between the gate structure and the source/drain contact; and a second portion on top of the self-aligned contacts and the source/drain contacts; and an air gap surrounded by the sealing layer, the fin region, the gate electrode, and the source/drain contact.
Still further embodiments of the present application provide a method of forming a semiconductor device, comprising: forming an opening over a top surface of a substrate and between a first terminal and a second terminal of the semiconductor device; and forming a silicon carbide material, comprising: depositing a first portion of the silicon carbide material in the opening and between the first terminal and the second terminal; depositing a second portion of the silicon carbide material on top of the first and second terminals, wherein a balloon is trapped in the opening surrounded by the silicon carbide material, the first and second terminals, and the substrate; and performing an oxygen anneal process on the deposited first and second portions of the silicon carbide material.
Drawings
The various aspects of the invention are best understood from the following detailed description when read in connection with the accompanying drawings. It should be noted that according to convention in the industry, the various components are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
Fig. 1 is an isometric view of a semiconductor structure according to some embodiments.
Fig. 2-6 are cross-sectional views of semiconductor structures formed in accordance with various portions of some embodiments.
Fig. 7 is a flow chart of a method of forming a double layer seal structure in a semiconductor structure, in accordance with some embodiments.
Fig. 8-16 are cross-sectional views of semiconductor structures formed in accordance with various portions of some embodiments.
Detailed Description
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the invention. For example, in the following description, forming a first component over a second component may include embodiments in which the first component and the second component are formed in physical contact, and may also include embodiments in which additional components are disposed between the first component and the second component, such that the first component and the second component may not be in physical contact. Furthermore, the present invention may repeat reference numerals and/or characters in the various examples. The repetition itself does not dictate a relationship between the various embodiments and/or configurations discussed.
Moreover, spatially relative terms such as "under …," "under …," "lower," "above …," "upper," and the like may be used herein for ease of description to describe one element or component's relationship to another element(s) or component(s) as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
As used herein, the term "nominal" refers to a desired or target value for a characteristic or parameter of a component or process operation, and a range of values above and/or below the desired value, set at a design stage of the product or process. The range of values is typically due to subtle variations in manufacturing processes or tolerances.
The terms "about" and "substantially" as used herein refer to a given number of values that may vary based on the particular technology node associated with the subject semiconductor device. In some embodiments, a given number of values that vary within 5% (e.g., ±1%, ±2%, ±3%, ±4%, ±5%) of the value may be indicated based on a particular technology node.
The fins may be patterned by any suitable method. For example, the fins may be patterned using one or more photolithographic processes, including double patterning or multiple patterning processes. Typically, double patterning or multiple patterning processes combine photolithography and self-aligned processes, allowing creation of patterns with, for example, a pitch smaller than that obtainable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithographic process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed and the remaining spacers may then be used to pattern the fins.
As planar semiconductor devices, such as metal oxide semiconductor field effect transistors ("MOSFETs"), are scaled down through various technology nodes, other approaches to increase device density and speed have been proposed. One approach is a fin field effect transistor ("finFET") device, which is a three-dimensional FET, that includes the formation of a fin-shaped channel extending from a substrate. Finfets are compatible with conventional Complementary Metal Oxide Semiconductor (CMOS) processes, and their three-dimensional structure enables them to scale greatly while maintaining gate control and mitigating short channel effects. Gate stacks are used in planar and three-dimensional FETs to control the conductivity of semiconductor devices. A gate stack including a gate dielectric layer and a gate electrode for a finFET device may be formed by a replacement gate process in which a polysilicon sacrificial gate structure is replaced with a metal gate structure. A gate dielectric layer, such as a high-k dielectric layer (e.g., a dielectric layer having a dielectric constant greater than about 3.9), is formed between the channel and the gate electrode. Spacers may be provided on sidewalls of the gate stack to protect the gate structure during fabrication processes such as ion implantation, gate replacement processes, epitaxial source/drain structure formation, and other suitable processes. An air gap may be used instead of a spacer to reduce the effective dielectric constant, which in turn may reduce parasitic capacitance and improve device performance. An air gap may be formed by depositing a sealing material over the openings between the terminals of the semiconductor device such that the air pockets are trapped between the terminals. The sealing material or the sealing layer may be a structure serving as a cover closing the opening. Since the dielectric constant of air can be lower than that of dielectric materials, the effective dielectric constant can be reduced. However, low uniformity and low etch resistance in the encapsulant material can lead to defects in the semiconductor device. For example, a manufacturing process for forming interconnect structures, such as vias for metal source/drain and gate terminals of finFET devices, may include multiple etching and cleaning processes performed on the terminals, portions through the sealing material may be etched through the seams, and cause damage to the air gaps. Examples of damage include collapse of the sealing material or trapping of chemical solution in the air gap. In addition, seams in the sealing material can also lead to physical failures and electrical shorts. Damaged air gap structures can lead to defects in semiconductor devices and to low device yields and device failures.
In order to solve the above-described drawbacks, the present invention provides a semiconductor device and a method of manufacturing the same to provide a simple and cost-effective structure and process for manufacturing a sealing layer in a semiconductor device. The sealing layer may be used to seal the openings and form air gaps between terminals of the semiconductor device, and may also be used as a Contact Etch Stop Layer (CESL) for subsequently formed structures, such as interconnect structures. In particular, a high-rigidity layer can be used as the sealing material. For example, a high-rigidity silicon carbide layer doped with oxygen (HRSCO) may be used as the sealing material. An HRSCO layer may also be formed and used as an etch stop layer. In addition, a layer of HRSCO may also be formed on the top surface of the semiconductor device terminal and used as a self-aligned contact (SAC). For example, a high-rigidity layer may be formed over a terminal of a semiconductor device. The terminals may include source terminals, drain terminals, gate terminals, and/or other suitable structures.
In some embodiments, the high rigidity layer may be formed by a deposition process followed by a treatment process. For example, a silicon carbide layer may be deposited followed by an oxygen anneal process to increase the oxygen content in the deposited layer. The individual deposition parameters may be varied to adjust the density of the film, and greater densities may provide greater stiffness. A high rigidity layer may be deposited in the openings formed between the opposing sidewalls of the semiconductor device terminals. A high rigidity layer may be deposited on the sidewalls and toward the top of the opening, and the deposition process may continue at least until the high rigidity material from the opposing sidewalls merges into physical contact and a closed space is formed between the opposing sidewalls.
In some embodiments, increasing the density of the high stiffness layer may provide greater etch resistance. In some embodiments, reducing the deposition rate of the high stiffness layer may result in improved film uniformity (e.g., uniform thickness). In some embodiments, the high rigidity layer may be deposited using a suitable deposition process using suitable precursors, such as tetramethyl disiloxane (TSMDSO), hydrogen, oxygen, and any other suitable precursor.
In some embodiments, the high rigidity layer is a bilayer sealing material, which may be formed by depositing a first sealing material, depositing a second sealing material, and performing at least one treatment process on the deposited first and second sealing materials. The treatment process may be performed after the deposition of the first sealing material, after the deposition of the second sealing material, or both. The first and second sealing materials may be dielectric materials. A first sealing material is deposited on the portion of the opposing sidewalls toward the top of the opening and a second sealing material is deposited on the first sealing material and on the exposed surfaces in the opening. A second sealing material is deposited over the first sealing material on the opposite side wall. The deposition process of the second sealing material continues at least until the second sealing material from the opposing sidewalls merges to form a closed space between the opposing sidewalls. A treatment process may be performed on the deposited first and second sealing materials such that the seam is removed by expansion of at least the second sealing material. In some embodiments, the treatment process may be an annealing process performed in an oxygen ambient. In some embodiments, the first sealing material may be deposited at a greater deposition rate than the second sealing material. In some embodiments, the first and second sealing materials may be formed using precursors such as tetramethyl disiloxane (TSMDSO), hydrogen, oxygen, and any other suitable precursor.
Fig. 1 is an isometric view of an exemplary fin field effect transistor (finFET) structure. Fig. 2-7 provide various exemplary semiconductor structures and fabrication processes, illustrating the formation of a multi-spacer structure with air gaps and high rigidity encapsulation material, according to some embodiments. Fig. 8-16 provide various structures and fabrication processes for forming air gaps, encapsulation material, CESL, and other structures of semiconductor devices. The sealing material and CESL may be formed using a highly rigid material that provides, among other things, higher etch resistance, improved uniformity, and lower leakage current. In some embodiments, the high stiffness material may be a HRSCO material. The manufacturing processes provided herein are exemplary and alternative processes according to the present invention may be implemented (although not shown in these figures).
Fig. 1 is an isometric view of a finFET in accordance with some embodiments. FinFET 100 may be included in a microprocessor, memory cell, or other integrated circuit. The view of the finFET 100 in fig. 1 is shown for illustrative purposes and may not be to scale. FinFET 100 may include further suitable structures such as additional spacers, spacer layers, contact structures, and any other suitable structures, which are not shown in fig. 1 for clarity.
FinFET 100 may be formed on substrate 102 and FinFET 100 may include a fin structure 104 having a fin region 121 and an S/D region 106, a gate structure 108 disposed on fin structure 104, spacers 110 disposed on opposite sides of each of gate structures 108, and Shallow Trench Isolation (STI) regions 112. Fig. 1 shows five gate structures 108. However, the finFET 100 may have more or fewer gate structures based on the disclosure herein. In addition, finFET 100 may be incorporated into an integrated circuit by using other structural components that are omitted for clarity, such as S/D contact structures, gate contact structures, conductive vias, wires, dielectric layers, and passivation layers.
The substrate 102 may be a semiconductor material, such as silicon. In some embodiments, the substrate 102 comprises a crystalline silicon substrate (e.g., a wafer). In some embodiments, the substrate 102 includes: (i) elemental semiconductor such as germanium; (ii) A compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, and/or indium antimonide; (iii) Alloy semiconductors including silicon germanium carbide, silicon germanium, gallium arsenide phosphide, indium gallium phosphide, gallium indium arsenide, indium gallium arsenide phosphide, aluminum indium arsenide and/or aluminum gallium arsenide; or (iv) combinations thereof. Further, the substrate 102 may be doped according to design requirements (e.g., a p-type substrate or an n-type substrate). In some embodiments, the substrate 102 may be doped with a p-type dopant species (e.g., boron, indium, aluminum, or gallium) or an n-type dopant species (e.g., phosphorus or arsenic).
The fin structure 104 represents the current carrying structure of the finFET 100 and may be along the Y-axis and through the gate structure 108. The fin structure 104 may include: (i) A portion of fin region 121, underlying gate structure 108; and (ii) S/D regions 106 disposed on portions of fin regions 121 formed on opposite sides of each of gate structures 108. A portion of fin region 121 of fin structure 104 under gate structure 108 (not shown in fig. 1) may extend over STI region 112 and may be surrounded by a corresponding one of gate structures 108. The fin region 121 on the opposite side of the gate structure 108 may be etched back such that the S/D region 106 may be epitaxially grown on the etched back portion of the fin region 121.
Fin region 121 of fin structure 104 may comprise a material similar to substrate 102. The S/D regions 106 may comprise epitaxially grown semiconductor material. In some embodiments, the epitaxially grown semiconductor material is the same material as the substrate 102. In some embodiments, the epitaxially grown semiconductor material includes a different material than the substrate 102. The epitaxially grown semiconductor material may include: (i) semiconductor materials such as germanium and silicon; (ii) Compound semiconductor materials such as gallium arsenide and aluminum gallium arsenide; or (iii) semiconductor alloys such as silicon germanium and gallium arsenide phosphorous. Other materials for fin structure 104 are within the scope of the present invention.
In some embodiments, the S/D regions 106 may be grown by: (i) Chemical Vapor Deposition (CVD), such as by Low Pressure CVD (LPCVD), ultra High Vacuum CVD (UHVCVD), reduced Pressure CVD (RPCVD), or a suitable CVD process; (ii) a Molecular Beam Epitaxy (MBE) process; (iii) a suitable epitaxy process; and (iv) combinations thereof. In some embodiments, the S/D regions 106 may be grown by an epitaxial deposition/partial etch process that is repeated at least once. This repeated deposition/partial etch process is also referred to as a "Cyclical Deposition Etch (CDE) process". In some embodiments, the S/D regions 106 may be grown by Selective Epitaxial Growth (SEG) with an etching gas added to promote selective growth of semiconductor material on exposed surfaces of the fin structure instead of on the insulating material (e.g., dielectric material of the STI regions 112). Other methods of epitaxially growing the S/D regions 106 are within the scope of the invention.
The S/D region 106 may be a p-type region or an n-type region. In some embodiments, the p-type S/D region 106 may comprise SiGe, and may be doped in-situ during epitaxial growth using p-type dopants such as boron, indium, and gallium. For p-type in situ doping, p-type doping precursors such as diborane (B) 2 H 6 ) Boron trifluoride (BF) 3 ) And other p-type doping precursors. In some embodiments, n-type S/D region 106 may include Si and may be doped in-situ during the epitaxial growth process using n-type dopants such as phosphorus and arsenic. For n-type in-situ doping, n-type doping precursors such as phosphine (PH 3 ) Arsine (AsH) 3 ) And other n-type doping precursors. In some embodiments, the S/D region 106 is not doped in situ, but an ion implantation process is performed to dope the S/D region 106.
The spacer 110 may include a spacer portion 110a formed on sidewalls of the gate structure 108 and in contact with the dielectric layer 118, a spacer portion 110b formed on sidewalls of the fin structure 104, and a spacer portion 110c formed as a protective layer over the STI region 106. Each spacer portion may also be a multi-spacer structure comprising more than one spacer structure. For example, the spacer portion 110a may include more than one spacer and an air gap formed between the gate structure 108 and the fin structure 104. A sealing material may be formed over the air gap to close and protect the air gap from subsequent fabrication processes. For simplicity, the air gap and sealing material are not shown in fig. 1. The spacers 110 may comprise an insulating material such as silicon oxide, silicon nitride, a low-k material, and combinations thereof. The spacer 110 may have a low-k material with a dielectric constant less than 3.9 (e.g., less than 3.5, 3, and 2.8). Since the air gap may have a dielectric constant of about 1, the effective dielectric constant of the spacer 110 may be further reduced compared to a spacer formed using only a low-k material. The low-k material for the spacers 110 may be formed using a suitable deposition process, such as Atomic Layer Deposition (ALD). In some embodiments, the spacers 110 may be deposited using CVD, LPCVD, UHVCVD, RPCVD, physical Vapor Deposition (PVD), any other suitable deposition process, and combinations thereof. In some embodiments, the sealing material may be a highly rigid material, such as HRSCO. In some embodiments, the sealing material may be a dual layer sealing material formed by depositing a first sealing material on top of the opening formed between the gate structure 108 and the S/D region 106, followed by deposition of a second sealing material on the first sealing material to form a housing with air trapped in the opening. Other materials and thicknesses for the spacer 110 and sealing material are within the scope of the present invention.
Each gate structure 108 may include a gate electrode 116, a dielectric layer 118 adjacent to and in contact with the gate electrode 116, and a gate cap layer 120. The gate structure 108 may be formed by a gate replacement process.
In some embodiments, the dielectric layer 118 may be formed using a high-k dielectric material (e.g., a dielectric material having a dielectric constant greater than about 3.9). By CVD, atomic Layer Deposition (ALD), physical Vapor Deposition (PVD), electron beam evaporation, or the likeOther suitable processes form dielectric layer 118. In some embodiments, the dielectric layer 118 may include: (i) Silicon oxide, silicon nitride and/or silicon oxynitride layers, (ii) high-k dielectric materials such as hafnium oxide (HfO) 2 )、TiO 2 、HfZrO、Ta 2 O 3 、HfSiO 4 、ZrO 2 And ZrSiO 2 (iii) a high-k dielectric material having oxides of lithium (Li), beryllium (Be), magnesium (Mg), calcium (Ca), strontium (Sr), scandium (Sc), yttrium (Y), zirconium (Zr), aluminum (Al), lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb) or lutetium (Lu), or (iv) combinations thereof. The high-k dielectric layer may be formed by ALD and/or other suitable methods. In some embodiments, the dielectric layer 118 may comprise a single layer or a stack of layers of insulating material. Other materials and methods of formation for dielectric layer 118 are within the scope of the present invention. For example, portions of dielectric layer 118 are formed on horizontal surfaces, such as the top surfaces of STI regions 112. Although not visible in fig. 1, a dielectric layer 118 may also be formed on top of and on the sidewalls of fin region 121 under gate electrode 116. In some embodiments, a dielectric layer 118 is also formed between the sidewalls of the gate electrode 116 and the spacer portion 110a, as shown in fig. 1. In some embodiments, the dielectric layer 118 has a thickness 118t in the range of about 1nm to about 5 nm.
The gate electrode 116 may include a gate work function metal layer 122 and a gate metal fill layer 124. In some embodiments, a gate work function metal layer 122 is disposed on the dielectric layer 118. The gate work function metal layer 122 may comprise a single metal layer or a stack of metal layers. The stack of metal layers may comprise metals having work functions similar to or different from each other. In some embodiments, the gate work function metal layer 122 may include, for example, aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), nickel silicide (NiSi), cobalt silicide (CoSi), silver (Ag), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), tantalum carbon nitride (TaCN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tungsten nitride (WN), metal alloys, and combinations thereof. The gate work function metal layer 122 may be formed using a suitable process such as ALD, CVD, PVD, plating, or a combination thereof. In some embodiments, the gate work function metal layer 122 has a thickness 122t in a range from about 2nm to about 15 nm. Other materials, methods of formation, and thicknesses of the gate work function metal layer 122 are within the scope of the present invention.
The gate metal fill layer 124 may comprise a single metal layer or a stack of metal layers. The stack of metal layers may comprise metals that are different from each other. In some embodiments, the gate metal fill layer 124 may include a suitable conductive material, such as Ti, ag, al, tiAlN, taC, taCN, taSiN, mn, zr, tiN, taN, ru, mo, WN, cu, W, co, ni, tiC, tiAlC, taAlC, metal alloys, and combinations thereof. Gate metal fill layer 124 may be formed by ALD, PVD, CVD or other suitable deposition process. Other materials and methods of forming the gate metal fill layer 124 are within the scope of the invention.
In some embodiments, the gate cap layer 120 may have a thickness 120t in a range from about 5nm to about 50nm, and may protect the gate structure 108 during subsequent processing of the finFET 100. The gate cap layer 120 may include a nitride material such as silicon nitride, silicon-rich nitride, and silicon oxynitride. Other materials for the gate cap layer 120 are within the scope of the present invention.
STI regions 112 may electrically isolate adjacent active and passive components (not shown herein) integrated with substrate 102 or deposited on substrate 102 from finFET 100. STI regions 112 may have dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, fluorine doped silicate glass (FSG), low-k dielectric materials, and other suitable insulating materials. In some embodiments, STI regions 112 may include a multi-layer structure. The cross-sectional shapes of fin structure 104, S/D region 106, gate structure 108, spacer 110, and STI region 112 are illustrative and not limiting.
Fig. 2-6 provide various exemplary semiconductor structures and fabrication processes according to some embodiments, illustrating the formation of spacer structures with air gaps and high rigidity sealing layers. The high rigidity seal layer may also be free of seams. Fig. 7 is a flow chart of a method 700 of forming an air gap and a high rigidity encapsulation layer in a semiconductor structure according to some embodiments of the invention. Based on the disclosure herein, other operations in method 700 may be implemented. Further, the operations of method 700 may be implemented in a different order and/or variation.
An air gap with a seamless sealing layer may provide the benefit of reducing and/or eliminating damage to the air gap formed between the spacer structures. The fabrication process may be used to form planar semiconductor devices or vertical semiconductor devices, such as finfets. In some embodiments, the fabrication process shown in fig. 2-7 may be used to form a semiconductor structure similar to the finFET structure described in fig. 1 above. For example, the semiconductor structure shown in fig. 2 may be similar to the finFET 100 during different stages of fabrication, as viewed from the tangent line A-A' shown in fig. 1.
Referring to operation 702 of fig. 7, source/drain regions and a gate stack are formed on a substrate according to some embodiments. Fig. 2 is a cross-sectional view of semiconductor structure 200 after forming three adjacent gate structures 208 and two source/drain contacts 230 over the substrate. The substrate may include fin regions 221. Each gate stack, such as gate structure 208, includes a gate dielectric layer 218 and a gate electrode 216. A gate dielectric layer 218 may be formed on the sidewalls and bottom surface of the gate electrode 216. A channel region for a semiconductor device, such as a finFET, may be formed in the fin region 221 and under the gate structure 208.
Fin region 221 may be a current carrying semiconductor structure formed on a substrate. For example, fin region 221 may be similar to fin region 121 described above in fig. 1. In some embodiments, fin region 221 may include a semiconductor material such as germanium, silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, indium antimonide, silicon germanium carbide, silicon germanium, gallium arsenide phosphide, gallium indium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, any suitable material, and combinations thereof. In some embodiments, fin region 221 may be doped with a p-type or n-type dopant species.
A gate dielectric layer 218 may be formed over fin region 221 and may be formed using a high-k dielectric material. The gate dielectric layer 218 may be deposited by CVD, ALD, PVD, electron beam evaporation, or other suitable process. In one placeIn some embodiments, the gate dielectric layer 218 may comprise a high-k dielectric material, such as HfO 2 . In some embodiments, the gate dielectric layer 218 may include TiO 2 、HfZrO、Ta 2 O 3 、HfSiO 4 、ZrO 2 And ZrSiO 2 . In some embodiments, the gate dielectric layer 218 may be similar to the dielectric layer 118 described above in fig. 1.
A gate electrode 216 may be formed on the gate dielectric layer 218, and the gate electrode 216 may include a single metal layer or a stack of metal layers. The gate structure 208 may further include a work function layer and is not shown in fig. 2 for simplicity. The stack of metal layers may comprise metals having work functions similar to or different from each other. In some embodiments, the gate electrode 216 may be formed of a conductive material (such as Al, cu, W, ti, ta, tiN, taN, niSi, coSi, ag, taC, taSiN, taCN, tiAl, tiAlN, WN, metal alloys, and combinations thereof). The gate electrode 216 may be formed using a suitable deposition process such as ALD, CVD, PVD, plating, and combinations thereof. Other materials and methods of forming the gate electrode 216 are within the scope of the invention. In some embodiments, the gate electrode 216 may be formed using a gate replacement process, wherein the polysilicon gate is removed and a metal gate electrode is formed at the location of the removed polysilicon gate.
Spacer structures may be formed on sidewalls of the gate structure 208. In some embodiments, the gate structure may include a gate electrode, a dielectric layer, a spacer, any other suitable structure, and are collectively referred to as a gate structure for ease of reference. In some embodiments, spacers 210 and 212 may be formed on sidewalls of gate dielectric layer 218 and on top of fin region 221. Spacer structures are formed on sidewalls of gate electrode 216 to protect gate dielectric layer 218 and gate electrode 216 during subsequent processing. In some embodiments, the spacer 210 may have an L-shaped cross-section with a vertical portion formed on the sidewalls of the gate dielectric layer 218 and a horizontal portion formed on the top surface of the fin region 221. In some embodiments, the spacers 210 are formed only on the sidewalls of the gate dielectric layer 218. The spacers 210 may be formed using a dielectric material such as silicon carbonitride, silicon nitride, silicon oxide, any suitable dielectric material, and combinations thereof. In some embodiments, the carbon atom content may be less than about 30% for spacers 210 formed using silicon carbonitride. In some embodiments, the carbon atom content of the spacer 210 may be between about 20% and about 30%. Additional spacers, such as spacer 212, may also be formed. For example, the spacers 212 may be formed on horizontal portions of the spacers 210, on top surfaces of the fin regions 221, or both. In some embodiments, the spacers 212 may be formed using a dielectric material, such as silicon. In some embodiments, the material forming the spacers 210 and 212 may have a high etch selectivity (e.g., greater than about 10), such that the spacers 210 may remain substantially intact when the spacers 212 are removed. In some embodiments, spacers 210 and 212 may be formed using any suitable dielectric material, such as silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon On Glass (SOG), tetraethylorthosilicate (TEOS), PE-oxide, HARP-formed oxide, and combinations thereof. In some embodiments, spacers 210 and 212 may be formed using a low-k dielectric material.
Source/drain (S/D) regions 240 may be formed in fin region 221. S/D region 240 may be a p-type region or an n-type region. In some embodiments, the p-type S/D region 240 may comprise SiGe, and may be doped in-situ during the epitaxial growth process using p-type dopants such as boron, indium, and gallium. For p-type in situ doping, a p-type doping precursor, such as B, may be used 2 H 6 、BF 3 And other p-type doping precursors. In some embodiments, n-type S/D region 240 may include Si and may be doped in-situ during the epitaxial growth process using n-type dopants such as phosphorus and arsenic. For n-type in situ doping, n-type doping precursors such as PH can be used 3 、AsH 3 And other n-type doping precursors. In some embodiments, the S/D regions 240 are not doped in situ, but an ion implantation process is performed to dope the S/D regions 240. In some embodiments, the S/D regions may be similar to S/D regions 160 described above in fig. 1.
Source/drain (S/D) contacts 230 may be in physical and electrical contact with source/drain regions 240. The S/D contacts 230 may be formed by depositing a conductive material between adjacent gate structures 208. For example, openings may be formed between the spacers 212 to expose the underlying S/D regions 240. A deposition process may be performed to deposit a conductive material in the openings so that electrical connections may be made. In some embodiments, a Contact Etch Stop Layer (CESL) 214 may be deposited in the opening prior to deposition of the conductive material. Examples of conductive material deposition processes may include PVD, sputtering, electroplating, electroless plating, any suitable deposition process, and combinations thereof. A planarization process may be performed after the deposition process such that the top surfaces of gate electrode 216, spacers 210 and 212, CESL 214, and source/drain contacts 230 may be substantially coplanar (e.g., planar surfaces). In some embodiments, the S/D contacts 230 may be formed using tungsten, aluminum, cobalt, silver, any suitable conductive material, and combinations thereof.
Similar to the finFET 100 depicted in fig. 1, the semiconductor structure 200 may be formed on a substrate with fin regions 221 protruding from STI regions. The STI region is not visible from the cross-sectional view of the semiconductor structure 200 shown in fig. 2, but the top surface of the STI region is indicated by a dashed line 222 for ease of description.
Referring to operation 704 of fig. 7, according to some embodiments, one or more spacers are removed to form an opening between terminals of a semiconductor device. Fig. 3 is a cross-sectional view of the semiconductor device after removal of one or more spacers to form an opening. Examples of terminals of the semiconductor device may be gate structures, S/D structures, or any other suitable structures. The gate structure 208 shown in fig. 3 may include a gate dielectric layer 218 and a gate electrode 216. In some embodiments, the gate structure 208 may also include spacers 210. The S/D structure may include S/D contacts 230 and CESL 214. In some embodiments, the S/D structure may further include S/D regions 240 formed in fin region 221. During operation 704, one or more of the spacers between the gate electrode 216 and the S/D contact 230 may be removed. For example, spacer 212 may be removed to form opening 302 surrounded by spacer 210 and CESL 214. The spacers 212 may be removed using one or more etching processes. In some embodiments, the spacers 212 may be removed using an etch process that has a high etch selectivity for the spacers 212 relative to other structures in the semiconductor structure 200, while leaving other exposed structures unchanged. For example, the spacers 212 may be formed using silicon carbonitride, and the spacers 212 may be selectively removed using a wet etch process and/or a plasma etch.
Fig. 4A and 4B are cross-sectional views illustrating a fabrication process for forming a high stiffness seam layer using a cyclical deposition/treatment process, according to some embodiments. Fig. 4C-4F are cross-sectional views illustrating a high rigidity sealing layer formed using a multi-deposition process according to some embodiments. Fig. 4A to 4F are enlarged views of the region 304 of fig. 3. Other structures may be included in the structures shown in fig. 4A to 4F, and are not shown for simplicity.
Referring to operation 706 of fig. 7, a sealing layer is deposited at least over top corners of openings in the semiconductor device, according to some embodiments. Fig. 4A is a cross-sectional view showing the semiconductor device after deposition of a sealing material on at least the top corners of the openings in the semiconductor device. A sealing layer 452 is deposited over exposed top surfaces of structures in the semiconductor device, such as top surfaces of gate electrode 216, gate dielectric layer 218, S/D contacts 230, CESL 214, and other structures. In some embodiments, sealing layer 452 may also be deposited in openings 302. For example, sealing layer 452 may be deposited on sidewalls of spacers 210 and CESL 214. In some embodiments, a sealing layer 452 may be deposited on the bottom of opening 302, such as on the top surface of the horizontal portion of spacer 210 formed on fin region 221. In some embodiments, sealing layer 452 may also be formed on fin region 221 if a portion of the top surface of fin region 221 is exposed between spacer 210 and CESL 214. The sealing layer 452 may have a horizontal portion 452A formed on top of the gate electrode 216, gate dielectric layer 218, and S/D contact 230 to protect these semiconductor structures from subsequent fabrication processes. For example, horizontal portion 452A may prevent oxidation of underlying material during a subsequent etching or treatment process. Sealing layer 452 may also include corner portions 452B formed on spacer 210 and CESL 214. The top surfaces of spacer 210 and CESL 214 may have rounded corners 410A and 414A, respectively, to promote the growth of corner portions 452B of sealing layer 452. The curved surfaces of rounded corners 410A and 414A may reduce the formation of voids or discontinuities in sealing layer 452 as compared to corners having right angles or sharp edges. Corner portions 452B of sealing layer 452 may contour the curved surfaces of rounded corners 410A and 414A.
The sealing layer 452 may affect the volume of the air gap subsequently formed between the terminals of the semiconductor device (such as the gate electrode 216 and the S/D contact 230) by adjusting the depth of the sealing layer 452 extending into the opening 302. In particular, corner portions 452B of sealing layer 452 may extend into openings 302 by being formed on sidewalls of spacers 210 and CESL 214. The opening 302 may have a depth H 1 And high aspect ratios (e.g., aspect ratios greater than about 10). A greater height H of the air gap 442 may be achieved by reducing the extension of the corner portion 452B into the opening 302 2 。H 2 And H is 1 A larger value of the ratio of (a) may indicate a larger air gap 442 volume in the opening 302. In some embodiments, the opening 302 has a height H that may be between about 10nm and about 60nm 1 . For example, height H 1 May be between about 15nm and about 55nm, between about 20nm and about 50nm, or any suitable height value. In some embodiments, the air gap height H 2 May be between about 5nm and about 55 nm. For example, height H 2 May be between about 7nm and about 50nm, between about 10nm and about 45nm, or any suitable height value. In some embodiments, H 2 And H is 1 May be between about 0.9 and about 2.2. For example, the ratio may be between about 1 and about 2.1, between about 1.05 and about 2, or any suitable ratio.
Any suitable dielectric material may be used to form sealing layer 452. In some embodiments, the sealing layer 452 may be formed using a material that provides sufficient mechanical strength to support the air gap structure and chemical resistance to protect from subsequent chemical processes. In some embodiments, sealing layer 452 may include silicon-oxygen or silicon-carbon crosslinks. For example, the sealing layer 452 may be formed using a high-rigidity silicon carbide material doped with oxygen. In some embodiments, sealing layer 452 may be formed using a silicon carbide material. In some embodiments, the sealing layer 452 may be deposited using radicals CVD, CVD, ALD, LPCVD, UHVCVD, RPCVD, PVD, any other suitable deposition process, and combinations thereof. In some embodiments, the sealing layer 452 may be deposited using a radical CVD process with an ion filter. In some embodiments, deposition of the sealing layer 452 may include a first operation of flowing a precursor into the deposition chamber. The precursor may provide one or more of the following binding types: silicon-oxygen, silicon-hydrogen, and silicon-carbon. In some embodiments, the precursor is in a gas phase and may include, for example, tetramethyl disiloxane (TSMDSO), hydrogen, and oxygen. Other suitable precursors may also be included. The flow rate ratio of hydrogen to oxygen may be greater than about 20 to minimize oxidation of the underlying material while promoting the chemical reactions required for deposition. For example, the flow rate ratio of hydrogen to oxygen may be between about 20 and about 30. The deposition may further comprise a second operation comprising activating the plasma and for activating the precursors in their gas phase to form silicon-oxygen and silicon-carbon crosslinks when depositing them on the exposed surface. The sealing material of sealing layer 452 deposited on opposing corners 410A and 414A will gradually accumulate and eventually merge into sealing opening 302, thereby physically isolating air gap 442 from the environment above sealing layer 452. Air gap 442 will be surrounded by and in physical contact with sealing layer 452, spacer 210, and CESL 214. In some embodiments, the spacers 210 are formed only on the sidewalls of the gate dielectric layer 218, and the air gaps 442 may be in physical contact with the fin regions 221.
Height H of air gap 442 may be adjusted by varying various deposition parameters of sealing layer 452 2 . For example, decreasing the deposition rate of the sealing layer 452 may increase the accumulation of sealing material on the sidewalls further toward the bottom thereof into the opening 302, which may result in a lower height H of the air gap 442 2 (e.g., smaller air gap 442). In some embodiments, the deposition rate may be aboutAnd about->Between them. In some embodiments, it may be greater than about +.>Is performed at a deposition rate of (a) a deposition process. For example, about +.>And about->The deposition process is performed at a rate in between. In some embodiments, the deposition rate may be about +.>And about->Between them. For example, the deposition rate may be aboutThe deposition rate may be adjusted by various deposition parameters. In some embodiments, a lower chamber pressure or greater plasma power during deposition may provide a greater deposition rate. In some embodiments, the chamber pressure can be between about 0.5Torr and about 12 Torr. For example, the chamber pressure can be between about 0.5Torr and about 3Torr, between about 3Torr and about 7Torr, between about 7Torr and about 12Torr, and any other suitable range or value. As another example, a chamber pressure between about 4.5Torr and about 5.5Torr may provide about +. >While a chamber pressure between about 6Torr and about 7Torr may provide a deposition rate of about +.>Is a lower deposition rate of (c).
The plasma power level of the deposition process also affects the deposition rate. For example, a greater plasma power level during a CVD process may provide a greater deposition rate. In some embodiments, the plasma power level may be between about 500W and about 3000W. For example, the plasma power level may be between about 500W and about 1000W, between about 1000W and about 2000W, between about 2000W and about 3000W, and at any other suitable power level. In some embodiments, the deposition process may use radical-triggered chemical reactions with ion filters.
The density of the sealing layer 452 may also be adjusted by deposition parameters. Increasing the density of sealing layer 452 may provide greater mechanical support and improved chemical resistance. In some embodiments, sealing layer 452 may have a thickness of greater than about 2.0g/cm 3 Is a density of (3). For example, the density of the sealing layer 452 may be about 2.0g/cm 3 And about 3.2g/cm 3 Between them. In some embodiments, the density may be about 2.2g/cm 3 And about 2.2g/cm 3 Between them. In some embodiments, greater density may be achieved by lower chamber processing pressures and higher plasma power levels. In some embodiments, the chamber processing pressure may be between about 0.5Torr and about 12 Torr. For example, the chamber processing pressure may be between about 0.5Torr and about 3Torr, between about 3Torr and about 8Torr, between about 8Torr and about 12Torr, and any other suitable range or value.
The dielectric constant of the sealing layer 452 may be less than about 5. In some embodiments, sealing layer 452 may have a dielectric constant between about 3.2 and about 5. The lower dielectric constant of the sealing layer 452 may result in lower parasitic capacitance of the terminals of the semiconductor device 200. In some embodiments, the leakage current in the semiconductor structure 200 may be less than about 1E at 2MV/cm - 8 A/cm 2 。
Referring to operation 708 of fig. 7, a treatment process is performed on the deposited sealing layer, according to some embodiments. Fig. 4B is a cross-sectional view showing the semiconductor device after a treatment process is performed.
A treatment process 462 may be performed on the deposited sealing layer 452 to adjust the oxygen content of the deposited sealing material. In some embodiments, the treatment process 462 may increase the oxygen content of the deposited sealing material. In some embodiments, the process 462 may be performed in an oxygen chamber environment. The oxygen environment helps to form additional Si-O-Si crosslinks in the sealing material, effectively doping the sealing material with additional oxygen atoms. In some embodiments, the treatment process 462 may reduce the oxygen content. In some embodiments, the treatment process 462 may be performed in a hydrogen chamber environment. In some embodiments, the process chamber may contain hydrogen at a preset pressure. The hydrogen environment helps to remove oxygen atoms from the deposited sealing material, allowing more Si-C-Si crosslinks to form. In some embodiments, the silicon atom content of sealing layer 452 may be between about 25% and about 35%. In some embodiments, the oxygen atom content of sealing layer 452 may be between about 30% and about 55%. In some embodiments, the carbon atom content of sealing layer 452 may be between about 10% and about 35%.
The deposition/treatment process described with reference to fig. 4A and 4B is exemplary. In some embodiments, the deposition/treatment process may be cycled until the nominal properties of the deposited sealing layer are achieved. For example, a cycle including at least one deposition operation and at least one treatment process may be performed multiple times until a nominal thickness or mass of the sealing layer 452 is achieved. In some embodiments, one cycle may be implemented. In some embodiments, the treatment process may be performed in a chamber environment filled with any suitable type of gas, such as argon, nitrogen, and any suitable gas. In some embodiments, the deposition and/or treatment process may be performed at a temperature between about 200 ℃ and about 700 ℃. For example, the deposition temperature may be between about 200 ℃ and about 500 ℃, between about 500 ℃ and about 700 ℃, and at any suitable temperature.
In some embodiments, the sealing layer 452 may be deposited by a bilayer deposition process as in fig. 4C-4F. As shown in fig. 4C, a first sealing material is deposited over at least the corners of the openings in the semiconductor device, according to some embodiments. A first encapsulation material 412 is deposited on top of gate electrode 216, gate dielectric layer 218, S/D contact 230, and CESL 214. In some embodiments, a first sealing material 412 may also be deposited in the opening 302. For example, first encapsulation material 412 may be deposited on sidewalls of spacers 210 and CESL 214. In some embodiments, a first sealing material 412 may be deposited on the bottom of the opening 302 (such as on the top surface of the horizontal portion of the spacer 210 formed on the fin region 221). In some embodiments, first encapsulation material 412 may also be formed on fin region 221 if a portion of the top surface of fin region 221 is exposed between spacer 210 and CESL 214. The first sealing material 412 may include corner portions 412A formed on the spacers 210 and CESL 214. The top surfaces of the spacers 210 and CESL 214 may have rounded corners 410A and 414A, respectively, to promote the growth of corner portions 412A of the first encapsulation material 412. The curved surfaces of the rounded corners 410A and 414A may reduce the formation of voids or discontinuities in the first sealing material 412 compared to corners having right angles or sharp edges. The corner portion 412A of the first sealing material 412 may contour the curved surfaces of the rounded corners 410A and 414A. The first sealing material may have a horizontal portion 412B formed on top surfaces of the gate electrode 216, the gate dielectric layer 218, and the S/D contact 230 to protect them from a subsequent manufacturing process. For example, the horizontal portion 412B may prevent oxidation of the underlying material during a subsequent etching or treatment process.
By adjusting the depth of the first sealing material 412 extending into the opening 302, the first sealing material 412 may affect the volume of the subsequently formed air gap between the gate electrode 216 and the S/D contact 230. In particular, corner portions 412A of first encapsulation material 412 may extend into openings 302 by being formed on sidewalls of spacers 210 and CESL 214. Greater extension depth H of corner portion 412A into opening 302 3 A smaller subsequently formed air gap (not shown in fig. 4C) may be provided in the opening 302. For example, H 3 And H is 1 A larger value of the ratio of (a) may leave a smaller volume in the opening 302 to form the air gap. In some embodiments, the opening 302 has a height H that may be between about 10nm and about 60nm 1 . For example, height H 1 May be between about 15nm and about 55nm, between about 20nm and about 50nm, or any suitable height value. In some embodiments, the depth of extension H 3 Can be in aboutBetween 2nm and about 11 nm. For example depth H 3 May be between about 5nm and about 9 nm.
The first sealing material 412 may be formed using any suitable dielectric material. In some embodiments, the first sealing material 412 may be formed using a material that provides sufficient mechanical strength to support the air gap structure and chemical resistance to protect from subsequent chemical processes. In some embodiments, the first sealing material 412 may include silicon-oxygen or silicon-carbon crosslinks. For example, the first sealing material 412 may be formed using a high-rigidity silicon carbide material doped with oxygen. In some embodiments, the first sealing material 412 may be formed using a silicon carbide material. In some embodiments, the first sealing material 412 may be deposited using radicals CVD, CVD, ALD, LPCVD, UHVCVD, RPCVD, PVD, any other suitable deposition process, and combinations thereof. In some embodiments, the first sealing material 412 may be deposited using a radical CVD process with an ion filter. In some embodiments, the deposition of the first sealing material 412 may include a first operation of flowing a precursor into the deposition chamber. The precursor may provide one or more of the following binding types: silicon-oxygen, silicon-hydrogen, and silicon-carbon. In some embodiments, the precursor is in a gas phase and may include, for example, tetramethyl disiloxane (TSMDSO), hydrogen, and oxygen. Other suitable precursors may also be included. The flow rate ratio of hydrogen to oxygen may be greater than about 20 to minimize oxidation of the underlying material while promoting the chemical reactions required for deposition. For example, the flow rate ratio of hydrogen to oxygen may be between about 20 and about 30. The deposition may further comprise a second operation comprising activating the plasma and for activating the precursor in its gas phase to form silicon-oxygen and silicon-carbon crosslinks. The deposition process may include a third operation of the treatment process to reduce the oxygen content from the deposited sealing material. The treatment process may be performed in a hydrogen chamber environment. In some embodiments, the processing may be performed in a chamber environment with any suitable type of gas, such as argon, nitrogen, and any suitable gas. In some embodiments, the deposition process may be performed at a temperature between about 300 ℃ and about 700 ℃. For example, the deposition temperature may be between about 300 ℃ and about 500 ℃, between about 500 ℃ and about 700 ℃, and at any suitable temperature. In some embodiments, deposition and treatment processes may be performed in cycles, such as a cyclical process deposition-treatment process. For example, the deposition and treatment process may be followed by another deposition and treatment process until a nominal thickness or mass of the first sealing material is achieved.
The deposition rate may be adjusted by various deposition parameters. A greater deposition rate may facilitate a greater accumulation of the first sealing material at curved surfaces 410A and 414A. A lower deposition rate may provide a greater extension depth H of the first sealing material 412 into the opening 302 3 . A greater deposition rate may be achieved by adjusting the various appropriate processing parameters. In some embodiments, the amount of material may be greater than aboutThe deposition process is performed at a deposition rate of (a). For example, it may be in the order ofAnd about->The deposition process is performed at a rate in between. In some embodiments, the deposition rate may be about +.>And about->Between them. For example, the deposition rate may be about +.>In some embodiments, a lower chamber pressure or greater plasma power during deposition may provide a greater deposition rate. In some embodiments, the chamber pressure can be between about 0.5Torr and about 12 Torr. For example, the chamber pressure can be between 0.5Torr and about 3Torr, between about 3Torr and about 7Torr, between about 7Torr and about 12Torr, and any other suitable rangeCircumference or value. As another example, a chamber pressure between about 4.5Torr and about 5.5Torr may provide about +.>While a chamber pressure between about 6Torr and about 7Torr may provide a deposition rate of about +. >Is a lower deposition rate of (c).
The plasma power level used for deposition also affects the deposition rate. A greater plasma power level may provide a greater deposition rate. In some embodiments, the plasma power level may be between about 500W and about 3000W. For example, the plasma power level may be between about 500W and about 1000W, between about 1000W and about 2000W, between about 2000W and about 3000W, and at any other suitable power level.
The density of the first sealing material 412 may also be adjusted by deposition parameters. Increasing the density of the sealing material 412 may provide greater mechanical support and improved chemical resistance. In some embodiments, the first sealing material 412 may have a weight of greater than about 2.0g/cm 3 Is a density of (3). For example, the first sealing material 412 may have a density of about 2.0g/cm 3 And about 2.2g/cm 3 Between them. In some embodiments, the density may be about 2.2g/cm 3 And about 3.2g/cm 3 Between them. In some embodiments, greater density may be achieved by lower chamber processing pressures and greater plasma power levels. In some embodiments, the chamber processing pressure may be between about 0.5Torr and about 12 Torr. For example, the chamber processing pressure may be between about 0.5Torr and about 3Torr, between about 3Torr and about 8Torr, between about 8Torr and about 12Torr, and any other suitable range or value. In some embodiments, the plasma power level may be between about 500W and about 3000W. For example, the plasma power level may be between about 500W and about 2000W, between about 2000W and about 3000W, and any other suitable range or value. In some embodiments, the deposition process may use radical-triggered and ion filtration Chemical reaction of the reactor.
The dielectric constant of the first encapsulant 412 may be less than about 5. In some embodiments, the first sealing material 412 may have a dielectric constant between about 3.2 and about 5. The lower dielectric constant of the first encapsulant 412 may result in lower parasitic capacitance of the terminals of the semiconductor device 200. In some embodiments, the leakage current in the semiconductor structure 200 may be less than about 1E at 2MV/cm -8 A/cm 2 。
An optional treatment process may be performed on the first sealing material 412 to further increase the amount of internal cross-linking and/or improve the density thereof. For example, a hydrogen annealing process may be performed to reduce the oxygen content and additional Si-C-Si bonds may be formed in the first sealing material 412. The hydrogen treatment process may also remove chemical byproducts, such as H 2 O. In some embodiments, an optional treatment process may be performed for less than about 1 minute. For example, the treatment process may be performed for between about 40s and about 1min.
According to some embodiments, a second sealing material may be deposited over the first sealing material and in the opening. Fig. 4D is a cross-sectional view showing the semiconductor device after the second sealing material is deposited. A second sealing material 432 is deposited over portions of the surfaces of first sealing material 412, spacer 210, and CESL 214. The second sealing material 432 may include at least: (i) A corner portion 432A deposited on the corner portion 412A of the first sealing material 412; (ii) A horizontal portion 432B deposited on 412B of first encapsulation material 412, and (iii) a vertical portion 432C deposited on sidewalls of spacer 210 and CESL 214. In some embodiments, a second sealing material 432 may be deposited on the bottom of the opening 302 (such as on the top surface of the horizontal portion of the spacer 210 formed on the fin region 221).
The second sealing material 432 may be deposited using any suitable deposition process. For example, the second sealing material 432 may be deposited using a CVD process. The semiconductor structure 200 may be loaded into a deposition chamber and then the encapsulation material blanket deposited. Since the precursor in the deposition chamber must move through the openings formed between the opposing corner portions 412A of the first sealing material 412 to deposit on the exposed surfaces of the openings 302, the precursor has a lower likelihood of contacting the surfaces of the spacers 210 and the CESL 214 than the top surfaces of the horizontal portions 412B. Accordingly, the sealing material is deposited at a lower rate in the opening 302 below the corner portion 412A. Since the sealing material gradually accumulates on the opposite corner portions 412A of the first sealing material 412 to form corner portions 432A of the second sealing material 432, the corner portions 432A deposited over one corner portion 412A will merge at the region 440 with the other corner portions 432A deposited over the opposite corner portion 412A. At region 440, a seam 450 is formed between adjacent corner portions 432A of the second sealing material 432.
The second sealing material 432 may affect the volume of the subsequently formed air gap between the gate electrode 216 and the S/D contact 230 by adjusting the depth of the second sealing material 432 extending into the opening 302. In particular, vertical portion 432C of second seal material 432 may extend into opening 302 by being formed on sidewalls of spacer 210 and CESL 214. Distance H between the lower end of seam 450 and the bottom surface of opening 302 4 May be between about 10nm and about 55 nm. For example, distance H 4 May be between about 12nm and about 50nm, between about 15nm and about 45nm, or any suitable distance. Greater depth H 4 A larger air gap 442 may be provided formed between the gate electrode 216 and the S/D contact 230. Distance H between bottom surfaces of lower engagement openings 302 of vertical portion 432C 5 May be less than about 45nm. For example, distance H 5 May be between about 10nm and about 40nm, between about 15nm and about 35nm, or any suitable distance. In some embodiments, the vertical portion 432C may extend to the bottom of the opening 302 and contact the top surface of the horizontal portion of the spacer 210.
The second sealing material 432 may be formed using any suitable dielectric material. In some embodiments, the second sealing material 432 may be formed using a material that provides sufficient bonding strength to the first sealing material 412. In some embodiments, the second sealing material 432 may include silicon-oxygen or silicon-carbon crosslinks. For example, the second sealing material 432 may be formed using a high-rigidity silicon carbide material doped with oxygen. In some embodiments, the second sealing material 432 may be formed using a silicon carbide material. In some embodiments, the second sealing material 432 may be deposited using radicals CVD, CVD, ALD, LPCVD, UHVCVD, RPCVD, PVD, any other suitable deposition process, and combinations thereof. In some embodiments, the second sealing material 432 may be deposited using a radical CVD process with an ion filter. In some embodiments, the deposition of the second sealing material 432 may be similar to the deposition process of the first sealing material 412. In some embodiments, the second sealing material 432 may be formed by a CVD process using a precursor including, for example, tetramethyl disiloxane (TSMDSO), hydrogen, and oxygen. Other suitable precursors may also be used. The flow rate ratio of hydrogen to oxygen may be greater than about 20 to minimize oxidation of the underlying material while promoting the chemical reactions required for deposition. For example, the flow rate ratio of hydrogen to oxygen may be between about 20 and about 30. The deposition may further comprise a second operation comprising activating the plasma and for activating the precursor in its gas phase to form silicon-oxygen and silicon-carbon crosslinks. In some embodiments, the deposition process may be performed at a temperature between about 300 ℃ and about 700 ℃. For example, the deposition temperature may be between about 300 ℃ and about 450 ℃, between about 450 ℃ and about 700 ℃, and at any other suitable temperature.
The deposition rate may be adjusted by various deposition parameters. The second sealing material 432 may be deposited at a lower deposition rate than the first sealing material 412. In some embodiments, the second sealing material 432 may be a substantially conformal film deposition over the corner portions 412A and the horizontal portions 412B of the first sealing material 412. A greater deposition rate may facilitate a greater accumulation of the second sealing material at the corner portions 412A. A lower deposition rate may provide a greater extension of the second sealing material 432 into the opening 302. A greater deposition rate may be achieved by adjusting the various appropriate processing parameters. In some embodiments, may be less than aboutIs performed at a deposition rate of (a) a deposition process. For example, about +.>And about (f)The deposition process is performed at a rate in between. In some embodiments, a lower chamber pressure or greater plasma power during deposition may provide a greater deposition rate. In some embodiments, the chamber pressure can be between about 0.5Torr and about 12 Torr. For example, the chamber pressure can be between about 0.5Torr and about 3Torr, between about 3Torr and about 7Torr, between about 7Torr and about 12Torr, and any other suitable range or value.
The plasma power level used for deposition also affects the deposition rate. A greater plasma power level may provide a greater deposition rate. In some embodiments, the plasma power level may be between about 500W and about 3000W. For example, the plasma power level may be between about 500W and about 1000W, between about 1000W and about 2000W, between about 2000W and about 3000W, and at any other suitable power level.
The density of the second sealing material 432 may also be adjusted by deposition parameters. Increasing the density of the second sealing material 432 may provide greater mechanical support and improved chemical resistance. In some embodiments, the second sealing material 432 may have a weight of greater than about 2.0g/cm 3 Is a density of (3). For example, the second sealing material 432 may have a density of about 2.0g/cm 3 And about 2.2g/cm 3 Between them. In some embodiments, the density may be about 2.2g/cm 3 And about 3.2g/cm 3 Between them. In some embodiments, greater density may be achieved by lower chamber processing pressures and greater plasma power levels. In some embodiments, the chamber processing pressure may be between about 0.5Torr and about 12 Torr. For example, the chamber processing pressure may be between about 0.5Torr and about 3Torr, between about 3Torr and about 8Torr, between about 8Torr and about 12Torr, and any other suitable range or value. In some embodiments, the plasma power level may be between about 500W and about 3000W. For example, the plasma power level may be about 500W and about 2000W Between about 2000W and about 3000W, and any other suitable range or value. In some embodiments, the deposition process may use radical-triggered chemical reactions with ion filters.
The dielectric constant of the second sealing material 432 may be the same as or different from the first sealing material 412. For example, the second encapsulant 432 may have a dielectric constant of less than about 5. In some embodiments, the second encapsulant 432 may have a dielectric constant between about 3.2 and about 5. In some embodiments, the leakage current in the semiconductor structure 200 may be less than about 1E at 2MV/cm -8 A/cm 2 。
According to some embodiments, the treatment process may be performed on the first and second sealing materials of the sealing layer. Fig. 4E is a cross-sectional view showing the semiconductor device after a treatment process is performed. A treatment process 435 may be performed on the second sealing material 432 to remove seams, such as seam 450. For example, an oxygen anneal process may be performed to cause the second sealing material 432 to physically expand and form additional bonds at the seam 450. During the oxygen annealing process, a portion of the Si-C-Si bonds in the second sealing material 432 may become Si-O-Si bonds. In some embodiments, the total carbon atom ratio of the second sealing material 432 may be reduced by between about 5% and about 15%. The oxygen treatment process may be performed for less than 1 minute. For example, the treatment process may be performed for between about 40s and about 1min. In some embodiments, the oxygen flow rate for the treatment process 435 may be between about 1sccm and about 10 sccm. For example, the oxygen flow rate may be between about 1sccm and about 3sccm, between about 3sccm and about 5sccm, between about 5sccm and about 10sccm, and any other suitable value. The oxygen anneal process may remove any seams, such as seam 450, such that region 440 includes second sealing material 432 without any seams.
Fig. 4F is a cross-sectional view showing the semiconductor device after a treatment process is performed on the sealing material formed on the asymmetric spacer. As shown in fig. 4F, spacers 210 and 214 have different heights along the sidewalls of gate dielectric layer 218 and the S/D contacts, respectively. For example, the spacers 210 and 214 may be formed of different materials, and the etch rate of the spacer 214 may be greater than the etch rate of the spacer 210 in response to one or more spacer etch-back processes forming the curved top corners 410A and 414A. Accordingly, corner portions 412A formed over the spacers 214 may extend down the sidewalls of the source/drain contacts 230 and toward the S/D regions 240 and the fin regions 221.
Referring to operation 710 of fig. 7, a planarization process is performed on the high-rigidity seal layer, according to some embodiments. Fig. 5 is a cross-sectional view of the semiconductor device after a planarization process is performed. As shown in fig. 5, a highly rigid encapsulant 532 is formed over the semiconductor structure 200, trapping the air pockets to form an air gap 542 between the terminals of the semiconductor structure 200 and the substrate (such as the fin region 221). In some embodiments, the high rigidity sealing material 532 is formed from HRSCO. In some embodiments, the high rigidity sealing material 532 is a seamless sealing material. A highly rigid sealing material 532 may be formed between and in physical contact with spacer 210 and CESL 214. The high rigidity sealing material 532 may also be in contact with other structures not shown in fig. 5. The horizontal portion 452A as shown in fig. 4B or portions of the first sealing material 412 and the second sealing material 432 as shown in fig. 4E may be removed using a planarization process. The planarization process may continue until the top surfaces of gate electrode 216, gate dielectric layer 218, spacers 210, CESL 214, and S/D contacts 230 are exposed and substantially flush (e.g., on the same plane). After the planarization process, the corner portions 452A of the sealing layer 452 or the remaining portions of the first and second sealing materials 412 and 432 may form a high rigidity sealing material 532. The air pockets trapped by the high rigidity encapsulant 532 may form an air gap 542 between terminals of the semiconductor structure 200 (such as the gate structure 208) and the S/D contacts 230. In some embodiments, the air gap 542 may include different types of gases. For example, air gap 542 may include oxygen, hydrogen, helium, argon, nitrogen, any other suitable type of gas, and combinations thereof. The lower deposition rate of the high stiffness sealing material 532 may result in an air gap 542 having a smaller volume. For example, the high rigidity seal material 532 may be formed by depositing the seal layer 452 or the first and second seal materials 412, 432, and a lower deposition rate may provide the air gap 542 with a shorter height, resulting in a smaller air gap volume. Since the air gap 542 may have a dielectric constant of about 1, the effective dielectric constant of the spacer 210 and the air gap 542 may be lower as compared to a spacer structure including the spacers 210 and 214.
Referring to operation 712 of fig. 7, a dielectric layer and an interconnect structure are formed, according to some embodiments. Fig. 6 is a cross-sectional view showing a dielectric layer and an interconnect structure formed on a semiconductor device.
Dielectric layer 620 may be formed on top of gate electrode 216, gate dielectric layer 218, spacer 210, high rigidity encapsulation material 532, CESL 214, S/D contact 230, and other suitable structures. In some embodiments, dielectric layer 620 may be an etch stop layer. Dielectric layer 620 may be formed using a low-k dielectric material (e.g., a dielectric layer having a dielectric constant less than about 3.9), such as silicon oxide. An interlayer dielectric (ILD) layer 650 may be formed on the dielectric layer 620. ILD layer 650 may be formed of a low-k dielectric material. For example, ILD layer 650 may be formed using silicon oxide. In some embodiments, dielectric layer 620 and ILD layer 650 may be formed using CVD, ALD, PVD, flowable CVD (FCVD), sputtering, any suitable deposition process, and combinations thereof. Vias may be formed in ILD 650 to establish electrical connection from S/D contact 230 and gate electrode 216 to external circuitry, such as peripheral circuitry formed above semiconductor structure 200. A gate via 616 may be formed in ILD 650 and extend through dielectric layer 620 to make physical contact with gate electrode 216. Similarly, S/D vias 630 may extend through ILD 650 and physically contact S/D contacts 230. The gate via 616 and the S/D via 630 may be formed by patterning and etching processes. For example, openings may be formed in ILD 650 and through dielectric layer 620 to expose gate electrode 216 and S/D contact 230, respectively. A deposition process may be performed to deposit a conductive material in the openings so that electrical connections may be made. Examples of deposition processes may be PVD, sputtering, electroplating, electroless plating, any suitable deposition process, and combinations thereof. A planarization process may be performed after the deposition process such that the top surfaces of ILD 650, gate via 616, and S/D via 630 may be substantially coplanar (e.g., horizontal). In some embodiments, the gate via 616 and the S/D via 630 may be formed using tungsten, aluminum, cobalt, silver, any suitable conductive material, and combinations thereof.
The high rigidity seal material may also be used as an etch stop layer to facilitate subsequent structure formation, or as a self-aligned contact (SAC) for the gate electrode 216 and S/D contact 230. In some embodiments, SAC may be formed on top of gate electrode 216 and/or S/D contact 230. The use of a highly rigid sealing material to form a SAC may provide, among other things, the following benefits: preventing electrical shorting, low leakage current, high uniformity, and good etch resistance. In some embodiments, the SAC may also be formed of a dielectric material (such as silicon nitride, silicon oxide, silicon oxynitride, silicon oxycarbide, silicon oxycarbonitride, any suitable dielectric material, and/or combinations thereof). SAC may be formed on the gate electrode, the S/D contact, or both. For clarity, a single SAC scheme is used to describe a semiconductor device with SACs formed on only one type of terminal (such as on a gate electrode or S/D contact). Similarly, a dual SAC scheme may be used to describe a semiconductor device having SACs formed on at least two types of terminals, such as on both gate electrodes and S/D contacts. Fig. 8 to 16 describe respective configurations of the semiconductor device, including a single SAC scheme and a dual SAC scheme having a high rigidity seal layer formed in the gap and also functioning as a CESL. In some embodiments, the high rigidity seal layer may also not include seams due to the manufacturing process described above in fig. 4A-4F.
Fig. 8 illustrates a semiconductor device 800 having a single SAC scheme and a high rigidity sealing layer formed in the gaps between terminals, according to some embodiments. For simplicity, structures similar to those described in fig. 1 to 6 shown in fig. 8 are not described in detail. The semiconductor device 800 may incorporate a single SAC scheme and include a SAC formed on the gate electrode 216 or the S/D contact 230. For example, SAC 810 may be formed on the top surface of gate electrode 216, as shown in fig. 8. In some embodiments, SAC 810 may be formed on the top surface of S/D contact 230 (not shown in fig. 8). SAC 810 may be formed by etching back portions of gate electrodes 216 such that a recess is formed between the top of each gate electrode 216 and the opposing sidewalls of gate dielectric layer 218. A dielectric material may be deposited into the recess to form SAC 810. In some embodiments, SAC 810 may be formed using silicon oxide, silicon nitride, silicon oxycarbide, silicon oxynitride, silicon oxycarbonitride, any suitable dielectric material, and combinations thereof. In some embodiments, SAC 810 may be formed prior to formation of high-rigidity seal material 532. In some embodiments, SAC 810 may be formed after forming high-rigidity seal material 532. A planarization process may be performed such that the top surfaces of SAC 810, gate dielectric layer 218, spacers 210, CESL 214, and high-rigidity encapsulation material 532 are substantially coplanar (e.g., on the same plane). A dielectric layer 620, ILD 650, gate via 616, and S/D via 630 may be formed on the planarized top surface. In some embodiments, gate via 616 may extend through dielectric layer 620 and SAC 810 and become in physical contact with gate electrode 216.
Fig. 9A and 9B illustrate a semiconductor device 900 having a single SAC scheme and a high rigidity sealing layer as CESL and also as a gap sealing layer between terminals, according to some embodiments. For simplicity, structures similar to those described in fig. 1 to 8 shown in fig. 9A and 9B are not described in detail. As shown in fig. 9A, the high rigidity sealing material 932 may include a first portion 932A formed between terminals of the semiconductor device 900 and a second portion 932B formed on top surfaces of the SAC 810, the gate dielectric layer 218, the spacers 210, the S/D contacts 230, and the CESL 214. The high rigidity seal material 932 may be formed using methods similar to those described above in fig. 4A-4F and 7, and will not be described in detail herein for simplicity. An air gap 942 may be formed between the terminals of the semiconductor device 900, and the size of the air gap 942 may depend on various factors, such as the deposition rate of the high rigidity sealing material 932. In some embodiments, the density of the high rigidity seal material 932 may be adjusted based on the device design. For example, increasing the density of the high rigidity seal material 932 may provide, among other things, greater etch resistance. In some embodiments, the second portion 932B of the high-rigidity seal material 932 may be used as a CESL for forming subsequent structures, such as vias for SAC 810 and S/D contacts 230, as described further below with reference to fig. 9B.
As shown in fig. 9B, an ILD layer 950 may be formed on the second portion 932B of the high-rigidity seal material 932B. ILD layer 950 may be similar to ILD layer 650 described in fig. 6. For example, ILD layer 950 may be formed using silicon oxide. In some embodiments, ILD layer 950 may be formed using CVD, ALD, PVD, flowable CVD (FCVD), sputtering, any suitable deposition process, and combinations thereof. Vias may be formed in ILD 950 to establish electrical connection from S/D contact 230 and gate electrode 216 to external circuitry, such as peripheral circuitry formed above semiconductor structure 200. A gate via 916 may be formed in ILD 650 and extend through second portion 932B of high-rigidity seal material 932 to make physical contact with gate electrode 216. Similarly, S/D vias 630 may extend through ILD 650 and physically contact S/D contacts 230. The gate via 616 and the S/D via 630 may be formed by patterning and etching processes. For example, openings may be formed in ILD 650 and through patterning and etching processes to expose underlying second portion 932B of high-rigidity encapsulant 932. The second portion 932B may be used as a CESL during the opening formation process. High density (e.g., greater than about 2.0 g/cm) of the high rigidity seal material 932 3 ) Improved etch resistance may be provided. A deposition process may be performed to deposit a conductive material in the openings to form gate vias 916 and S/D vias 930 so that electrical connections may be made. Examples of deposition processes may be PVD, sputtering, electroplating, electroless plating, any suitable deposition process, and combinations thereof. A planarization process may be performed after the deposition process such that the top surfaces of ILD 950, gate vias 916 and S/D vias 930 may be substantially coplanar (e.g., on the same plane). In some embodiments, the gate vias 916 and the S/D vias 930 may be formed using tungsten, aluminum, cobalt, silver, any suitable conductive material, and combinations thereof. In some embodiments, the gate via 916 may extend through the second portions 932B and SAC 810 and be in physical contact with the gate electrode 216.
Fig. 10A-10D illustrate a semiconductor device 1000 having a single SAC scheme and a high rigidity sealing layer as a SAC and also as a gap sealing layer between terminals, according to some embodiments. For simplicity, structures shown in fig. 10A-10D that are similar to those described in other figures (such as fig. 2 and 8) are not described in detail.
Fig. 10A is a cross-sectional view of a semiconductor device 1000 having terminals and spacers formed between the terminals, in accordance with some embodiments. For example, the semiconductor device 1000 may include a gate electrode 216 and spacers 210 and 212. In some embodiments, SAC formed using a highly rigid sealing material may be formed after the S/D contacts are formed. In some embodiments, SAC may be formed prior to formation of the S/D contacts. The S/D contacts may be formed by alternative processes such as removing the dielectric layer and depositing a conductive replacement dielectric layer. As shown in fig. 10A, a dielectric layer 1020 is formed over CESL 214 and over S/D regions 240. Dielectric layer 1020 may be formed using a material similar to the material used to form ILD 650 and ILD 950. For example, silicon oxide may be used to form dielectric layer 1020. Dielectric layer 1020 may be removed and replaced with one or more conductive materials, as further described below in fig. 10B.
Fig. 10B is a cross-sectional view of the semiconductor device 1000 after formation of a SAC using a highly rigid sealing material and S/D contacts. As shown in fig. 10B, S/D contact 1030 is formed in place of dielectric layer 1020. In some embodiments, the S/D contacts are formed by removing the dielectric layer 1020 and performing a deposition process to fill the voids left by the removal of the dielectric layer 1020. The deposition process may include depositing a conductive material until a top surface of the deposited conductive material is at least flush with top surfaces of the gate dielectric layer 218 and the spacers 210. The conductive material may include any suitable conductive material, such as a metal, a metal alloy, a doped semiconductor material, and/or combinations thereof.
SAC 1010 may be formed on gate electrode 216 using an etch-back process similar to the etch-back process described above with reference to fig. 8 for forming SAC 810. For example, one or more etching processes may be performed to etch back the gate electrode 216 to form openings between opposing sidewalls of the gate dielectric layer 218. A high-rigidity sealing material may be blanket deposited over the exposed surface and into the opening until the high-rigidity sealing material completely fills the opening. Any excess high rigidity seal material may be removed using a planarization process, thereby allowing SAC 1010 to be formed on the top surface of recessed gate electrode 216. SAC 1010 may be formed using methods similar to those described above with reference to fig. 4A-4F. For example, SAC 1010 may be formed using HRSCO. In some embodiments, the oxygen content of SAC 1010 may be adjusted according to device requirements. For example, increasing the oxygen content of SAC 1010 may also provide other benefits.
Fig. 10C is a cross-sectional view of the semiconductor device 1000 after deposition of a highly rigid encapsulant material into gaps between terminals of the semiconductor device, in accordance with some embodiments. Similar to the process described with reference to fig. 3, the spacers 212 may be removed to form openings between terminals of the semiconductor device 1000. A high rigidity seal material 1032 may be deposited into the opening and formed toward the top of the opening. The formation and properties of the high rigidity sealing material 1032 may be similar to the formation and properties of the high rigidity sealing material 532 described above in fig. 4A, 4B, and 5.
Fig. 10D is a cross-sectional view of the semiconductor device 1000 after formation of a dielectric layer and interconnect structures, in accordance with some embodiments. As shown in fig. 10D, a dielectric layer 1020 and an ILD layer 1050 may be formed over SAC 1010, S/D contacts 1030, and other exposed structures of semiconductor device 1000. In some embodiments, dielectric layer 1020 may be CESL. Gate vias 1016 and S/D vias 1060 may be formed in ILD 1050 extending through dielectric layer 1020. In some embodiments, gate via 1016 may extend through dielectric layer 1020 and SAC 1010 and be in physical contact with gate electrode 216. In some embodiments, dielectric layer 1020, ILD 1050, gate via 1016, and S/D via 1060 may be similar to dielectric layer 620, ILD 650, gate via 616, and S/D via 616, respectively, and will not be described in detail herein for simplicity.
Fig. 11A and 11B illustrate a semiconductor device 1100 having a single SAC scheme and a high rigid sealing layer as SAC, CESL, and also as a gap sealing layer between terminals, according to some embodiments. For simplicity, structures shown in fig. 11A and 11B that are similar to those described in other figures (such as fig. 8, 9A, 9B, and 10) are not described in detail.
Fig. 11A is a cross-sectional view of a semiconductor device 1100 having a highly rigid sealing material as SAC, CESL, and gap seal layers. For example, the high rigidity sealing material 1132 may include a first portion 1132A formed between terminals of the semiconductor device 1100 and used as a gap seal layer to form the air gap 1142. The highly rigid sealing material 1132 may include a second portion 1132B formed on top of the SAC 1010, the spacer 210, the gate dielectric layer 218, the S/D contacts 1030, and other suitable structures. The first portion 1132A and the second portion 1132B of the high rigidity seal material 1132 may be similar to the first portion 932A and the second portion 932B of the high rigidity seal material 932 described above in fig. 9A and 9B, respectively, and will not be described in detail herein for the sake of simplicity. The second portion 1132B of the high rigidity encapsulant 1132 may be used as a CESL for subsequent formation of the dielectric layer and interconnect structure. The high rigidity sealing material 1132 may also provide the following benefits: high etch resistance, lower leakage current, and high uniformity. In some embodiments, SAC, CESL, and gap seal materials, all formed using highly rigid materials (such as HRSCO), may also provide the benefit of low contamination, as SAC and gap seal materials may be deposited in situ without removing semiconductor device 1100 from one deposition chamber and loading it into another.
Fig. 11B is a cross-sectional view of the semiconductor device 1100 after formation of a dielectric layer and interconnect structures, in accordance with some embodiments. As shown in fig. 11B, ILD layer 1150 may be formed over SAC 1010, S/D contact 1030, and other exposed structures of semiconductor device 1100. Gate via 1116 and S/D via 1160 may be formed in ILD 1150 extending through second portion 1132B of high rigidity seal material 1132. In some embodiments, the gate via 1116 may extend through the dielectric second portion 1132B and SAC 1010 and may be in physical contact with the gate electrode 216. In some embodiments, ILD 1150, gate via 1116 and S/D via 1160 may be similar to ILD 650, gate via 616 and S/D via 616, respectively, and will not be described in detail herein for simplicity.
Fig. 12 illustrates a semiconductor device 1200 having a dual SAC scheme and a high rigid sealing layer as a gap sealing layer between terminals, according to some embodiments. For simplicity, structures shown in fig. 12 that are similar to those described in other figures (such as fig. 2-11B) are not described in detail herein. The dual SAC scheme includes SACs formed on more than one type of terminal in the semiconductor device 1200. For example, SAC 810 may be formed on gate electrode 216. In some embodiments, a SAC 1210 may be formed on the S/D contact 230. SAC 1210 may be formed using a material similar to SAC 810. For example, SAC 1210 may be formed using silicon oxide. A high rigidity layer 532 may be formed as a gap seal layer between terminals of semiconductor device 1200 to form a gap 1042 surrounded by high rigidity layer 532, spacer 210 and CESL 214. In some embodiments, SAC 1210 may be formed prior to formation of SAC 810. In some embodiments, SAC 1210 may be formed after formation of SAC 810. SAC 810 and 1210 may be formed by an etch back process to recess the semiconductor device terminals, followed by a deposition process to deposit a dielectric material on the recessed semiconductor device terminals. For example, the SAC 1210 may be formed by an etch back process to recess the S/D contact 230 and deposit a dielectric material on the recessed S/D contact 230. An exemplary manufacturing process for forming the semiconductor device 1200 may include: etching back the gate electrode 216 and depositing a dielectric material on the recessed gate electrode 216 to form SAC 810, forming S/D contacts 230 over S/D regions 240, forming openings between terminals of the semiconductor device 1200, forming a high rigidity layer 532 in the openings, depositing a dielectric layer 620, depositing an ILD layer 650 on the dielectric layer 620, and forming gate vias 616 and S/D vias 630 through the dielectric layer 620 in the ILD layer 650. In some embodiments, gate and S/D vias may extend through SAC 810 and 1210, respectively. Other operations may be used to form the semiconductor device 1200 and the order of the operations may vary.
Fig. 13 illustrates a semiconductor device 1300 having a dual SAC scheme and a high rigidity sealing layer that acts as a gap sealing layer between terminals and also as a CESL, according to some embodiments. For simplicity, structures shown in fig. 13 that are similar to those described in other figures (such as those shown in fig. 2-12) are not described in detail. For example, the high rigidity sealing material 932 may include a first portion 932A formed between terminals of the semiconductor device 1300 and a second portion 932B formed on a top surface of each structure. The second portion 932B may be used as a CESL for forming the gate via 916 and the S/D via 930. The air gap 942 is surrounded by the CESL 214, the spacer 210, and the high rigidity seal material 932. In some embodiments, the high rigidity seal material 932 may be formed using manufacturing methods similar to those described with reference to fig. 4A-4F. An exemplary manufacturing process for forming the semiconductor device 1300 may include: etching back the gate electrode 216 and depositing a dielectric material on the recessed gate electrode 216 to form the SAC 810, forming the S/D contact 230 over the S/D region 240, etching back the S/D contact 230 and depositing a dielectric material to form the SAC 1210, forming an opening between the terminals of the semiconductor device 1200, forming a first portion 932A of the high-rigidity layer 932 in the opening and a second portion 932B on the top surface of the terminals, depositing the ILD layer 950 on the high-rigidity layer 932, and forming gate vias 916 and S/D vias 930 through the high-rigidity layer 932 in the ILD layer 950. In some embodiments, gate via 916 and S/D via 930 extend through SAC 810 and 1210, respectively. Other operations may be used to form the semiconductor device 1300, and the order of the operations may vary.
Fig. 14 illustrates a semiconductor device 1400 having a dual SAC scheme and a high rigid sealing layer that acts as a gap sealing layer between terminals and also as a SAC for S/D contacts, according to some embodiments. For simplicity, structures shown in fig. 14 that are similar to those described in other figures (such as those shown in fig. 2-13) are not described in detail. In some embodiments, HRSCO may be used to form the high rigidity seal material 1032. In some embodiments, a highly rigid encapsulant 1032 may be formed between terminals of the semiconductor device 1400. In some embodiments, SAC 1460 may be formed on S/D contact 1030. In some embodiments, SAC 1460 may be formed using a material similar to high rigidity seal material 1032. In some embodiments, SAC 1460 may be formed using an etch-back process similar to the etch-back process described above with reference to fig. 10A-10D. In some embodiments, the high rigidity seal material 1032 and SAC 1460 may be formed during the same manufacturing operation. For example, the S/D contact 1030 may be etched back to form a recess between opposing sidewalls of the CESL 1030. One or more spacers between the terminals of the semiconductor device 1400 may be removed to form openings between the terminals. A fabrication process including deposition of a high rigidity material and one or more treatment processes may be used to deposit the high rigidity material in the openings between the terminals and on the recessed S/D contacts 1030 to form SAC 1460. In some embodiments, the high rigidity sealing material 1032 may be formed using a manufacturing method similar to that described with reference to fig. 4A-4F. An exemplary manufacturing process for forming the semiconductor device 1400 may include: etching back the gate electrode 216 and depositing a dielectric material on the recessed gate electrode 216 to form SAC 1010, forming S/D contacts 1030 over the S/D regions 240, etching back the S/D contacts 1030, forming openings between the S/D contacts and the gate electrode 216, depositing a high stiffness material to form a high stiffness seal material 1032 in the openings and SAC 1460 on the S/D contacts 1030, depositing a dielectric layer 1020 on top of the terminals and the high stiffness seal material 1032, performing a planarization process, depositing an ILD layer 1050, and forming gate vias 1016 and S/D vias 1060 through the dielectric layer 1020 in the ILD layer 1050. In some embodiments, gate via 1016 and S/D via 1060 extend through SAC 1010 and 1460, respectively. Other operations may be used to form the semiconductor device 1400 and the order of the operations may vary.
Fig. 15 illustrates a semiconductor device 1500 with a dual SAC scheme and a high rigid sealing layer that acts as: (i) a gap seal layer between terminals, (ii) SAC for S/D contacts, and (iii) CESL. For simplicity, structures shown in fig. 15 that are similar to those described in other figures (such as fig. 2-14) are not described in detail. In some embodiments, the high rigidity sealing material 1132 may include a first portion 1132A formed between the terminals of the semiconductor device 1500 and a second portion 1132B extending horizontally and formed on the top surfaces of the terminals. The terminals may include gate electrodes 216 and S/D contacts 1030. In some embodiments, a high stiffness material may also be used to form the SAC. For example, SAC 1510 for S/D contacts 1030 may be formed using a highly rigid sealing material. In some embodiments, SAC 1010 and high rigidity seal material 1132 may be formed in the same manufacturing step and composed of substantially the same type of material. For example, SAC 1010 and high rigidity seal material 1132 may have substantially the same atomic percent of oxygen. In some embodiments, SAC 1010 and high-rigidity seal material 1132 may be formed using high-rigidity materials having different compositions. The dual SAC scheme employed by semiconductor device 1500 may also include a SAC for gate electrode 216. For example, SAC 1010 may be formed on the top surface of gate electrode 216. SAC 1010 may be formed using a highly rigid sealing material. In some embodiments, SAC 1010 may be formed using dielectric materials such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon oxycarbonitride, and any suitable dielectric material. An exemplary manufacturing process of the semiconductor device 1500 having the dual SAC scheme and the high rigidity sealing material may include: for example, etching back to recess gate electrode 216, depositing a dielectric material on the recessed gate electrode to form SAC 1010, etching back to recess S/D contact 1030, forming an opening between S/D contact 1030 and gate electrode 216, depositing a highly rigid sealing material in the opening and on recessed S/D contact 1030 and on SAC 1010, performing a planarization process, forming ILD 1150, and forming gate via 1116 and S/D via 1160. In some embodiments, the gate via 1116 and the S/D via 1160 may extend through SAC 1010 and 1510, respectively. Other operations may be used to form the semiconductor device 1500, and the order of the operations may vary.
Fig. 16 illustrates a semiconductor device 1600 with a dual SAC scheme and a high rigid sealing layer that acts as a gap sealing layer between terminals, as a SAC for a gate electrode, and also as a CESL, according to some embodiments. For simplicity, structures shown in fig. 16 that are similar to those described in other figures (such as fig. 2-15) are not described in detail. In some embodiments, the high rigidity sealing material 1132 may include a first portion 1132A formed between terminals of the semiconductor device 1600 and a second portion 1132B extending horizontally and formed on top of the terminals. In some embodiments, a high stiffness material may also be used to form the SAC. For example, SAC 1620 for gate electrode 216 may be formed using a highly rigid sealing material. In some embodiments, SAC 1620 and high rigidity seal material 1132 may be formed in the same manufacturing step and composed of substantially the same type of material. For example, SAC 1620 and high rigidity seal 1132 may have substantially the same atomic percent of oxygen. In some embodiments, SAC 1620 and high-rigidity seal material 1132 may be formed using high-rigidity materials having different compositions. The dual SAC scheme employed by semiconductor device 1600 may also include SACs for S/D contacts 1030. For example, a self-aligned S/D contact (such as SAC 1610) may be formed on the top surface of S/D contact 1030. In some embodiments, SAC 1610 may be formed using a highly rigid sealing material. In some embodiments, SAC 1610 may be formed using dielectric materials such as silicon nitride, silicon oxide, silicon carbide, silicon oxycarbide, silicon oxycarbonitride, and any suitable dielectric material. An exemplary manufacturing process of the semiconductor device 1600 having the dual SAC scheme and the high rigidity sealing material may include: for example, etch back to recess gate electrode 216, deposit a high-rigidity sealing material over the recessed gate electrode to form SAC 1620, form S/D contact 1030, form SAC 1610 over S/D contact 1030, form an opening between S/D contact 1030 and gate electrode 216, deposit a high-rigidity sealing material in the opening, over SAC 1620, and over SAC 1610, perform a planarization process, form ILD 1150, and form gate via 1116 and S/D via 1160. Other operations may be used to form the semiconductor device 1600, and the order of the operations may vary.
Various embodiments of the present invention provide a semiconductor device and a method of manufacturing the same to provide a simple and cost-effective structure and process for producing a high rigidity sealing layer in a semiconductor device. A highly rigid sealing layer may be used to seal the openings and form air gaps between the terminals of the semiconductor device to reduce the effective dielectric constant, which may improve device performance. A highly rigid encapsulant may also be formed over the top surface of the semiconductor device terminals as a contact etch stop layer. The highly rigid encapsulant material may also be used as a self-aligned contact for the terminals of the semiconductor device.
In some embodiments, a semiconductor device includes first and second terminals formed on a fin region and a sealing layer formed between the first and second terminals. The sealing layer comprises a silicon carbide material doped with oxygen. The semiconductor device further includes an air gap surrounded by the encapsulation layer, the fin region, and the first and second terminals.
In some embodiments, the semiconductor device includes a gate structure located over the fin region. The gate structure includes a gate electrode and a self-aligned contact (SAC) formed on the gate electrode. SAC comprises silicon carbide material doped with oxygen. The semiconductor device also includes source/drain (S/D) contacts and a sealing layer having an oxygen doped silicon carbide material. The sealing layer also includes a first portion located between the gate structure and the S/D contact and a second portion located on top of the SAC and S/D contact. The semiconductor device further includes an air gap surrounded by the sealing layer, the fin region, the gate electrode, and the S/D contact.
In some embodiments, a method for forming a semiconductor device includes forming an opening above a top surface of a substrate and between first and second terminals of the semiconductor device. The method also includes forming a silicon carbide material including depositing a first portion of the silicon carbide material in the opening and between the first and second terminals. The method further includes depositing a second portion of silicon carbide material on top surfaces of the first and second terminals. The balloon is trapped in an opening surrounded by the silicon carbide material, the first and second terminals, and the substrate. The method further includes performing an oxygen anneal process on the first and second portions of the deposited silicon carbide material.
In some embodiments, a semiconductor device includes: a first terminal and a second terminal formed on the fin region; a sealing layer formed between the first terminal and the second terminal, wherein the sealing layer comprises a silicon carbide material doped with oxygen; and an air gap surrounded by the sealing layer, the fin region, and the first and second terminals. In some embodiments, the first terminal includes a gate electrode and the second terminal includes a source/drainA pole (S/D) contact. In some embodiments, the first terminal further comprises: a gate dielectric layer on sidewalls of the gate electrode; and a spacer comprising a first portion located on a sidewall of the gate dielectric layer and a second portion located on a top surface of the fin region. In some embodiments, the air gap is in physical contact with the first portion and the second portion of the spacer. In some embodiments, the sealing layer has a density of 2.0g/cm 3 And 3.2g/cm 3 Between them. In some embodiments, the sealing layer has an oxygen atom content between 30% and 55%. In some embodiments, the sealing layer has a carbon atom content between 10% and 35%. In some embodiments, the sealing layer has a silicon atom content between 25% and 35%. In some embodiments, top surfaces of the sealing layer, the first terminal, and the second terminal are substantially coplanar. In some embodiments, the semiconductor device further comprises: a self-aligned contact (SAC) is located on the first terminal, wherein the self-aligned contact comprises an oxygen-doped silicon carbide material and has a top surface coplanar with a top surface of the sealing layer.
In some embodiments, a semiconductor device includes: a gate structure located on the fin region, comprising: a gate electrode; and a self-aligned contact (SAC) formed on the gate electrode and comprising a silicon carbide material doped with oxygen; source/drain (S/D) contacts; a sealing layer comprising the silicon carbide material doped with oxygen, wherein the sealing layer further comprises: a first portion located between the gate structure and the source/drain contact; and a second portion on top of the self-aligned contacts and the source/drain contacts; and an air gap surrounded by the sealing layer, the fin region, the gate electrode, and the source/drain contact. In some embodiments, the sealing layer has a density of 2.0g/cm 3 And 3.2g/cm 3 Between them. In some embodiments, the sealing layer has an oxygen atom content between 30% and 55%. In some embodiments, the semiconductor device further comprises: a via extends through the second portion of the sealing layer and is in physical contact with the self-aligned contact. In one placeIn some embodiments, the semiconductor device further includes: a gate dielectric layer and a spacer, wherein the spacer includes a first portion on a sidewall of the gate dielectric layer and a second portion on a top surface of the fin region.
In some embodiments, a method of forming a semiconductor device includes: forming an opening over a top surface of a substrate and between a first terminal and a second terminal of the semiconductor device; and forming a silicon carbide material, comprising: depositing a first portion of the silicon carbide material in the opening and between the first terminal and the second terminal; depositing a second portion of the silicon carbide material on top of the first and second terminals, wherein a balloon is trapped in the opening surrounded by the silicon carbide material, the first and second terminals, and the substrate; and performing an oxygen anneal process on the deposited first and second portions of the silicon carbide material. In some embodiments, the first portion of the silicon carbide material is deposited toward the top of the opening. In some embodiments, depositing the first portion and the second portion of the silicon carbide material includes flowing tetramethyl disiloxane (TSMDSO), hydrogen, and oxygen into a deposition chamber. In some embodiments, the ratio of the flow rates of the hydrogen to the oxygen is between 20 and 30. In some embodiments, the method further comprises: etching the first terminal to recess the first terminal; depositing another silicon carbide material over the recessed first terminal; and performing another oxygen anneal process on the deposited silicon carbide material.
It should be understood that the detailed description section, rather than the abstract, is intended to be used to interpret the claims. The abstract of the disclosure may set forth one or more, but not all of the contemplated exemplary embodiments, and thus is not intended to limit the dependent claims.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present invention. Those skilled in the art will appreciate that they may readily use the present invention as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the appended claims.

Claims (20)

1. A semiconductor device, comprising:
a first terminal and a second terminal formed on the fin region;
a sealing layer formed between the first terminal and the second terminal, wherein the sealing layer comprises a silicon carbide material doped with oxygen; and
an air gap surrounded by the sealing layer, the fin region, and the first and second terminals,
A self-aligned contact on the first terminal, wherein the self-aligned contact comprises an oxygen-doped silicon carbide material.
2. The semiconductor device of claim 1, wherein the first terminal comprises a gate electrode and the second terminal comprises a source/drain contact.
3. The semiconductor device according to claim 2, wherein the first terminal further comprises:
a gate dielectric layer on sidewalls of the gate electrode; and
a spacer includes a first portion on a sidewall of the gate dielectric layer and a second portion on a top surface of the fin region.
4. The semiconductor device of claim 3, wherein the air gap is in physical contact with the first and second portions of the spacer.
5. The semiconductor device of claim 1, wherein the sealing layer has a density of 2.0g/cm 3 And 3.2g/cm 3 Between them.
6. The semiconductor device of claim 1, wherein the sealing layer has an oxygen atom content between 30% and 55%.
7. The semiconductor device of claim 1, wherein the sealing layer has a carbon atom content between 10% and 35%.
8. The semiconductor device of claim 1, wherein the sealing layer has a silicon atom content between 25% and 35%.
9. The semiconductor device of claim 1, wherein top surfaces of the encapsulation layer, the first terminal, and the second terminal are substantially coplanar.
10. The semiconductor device of claim 1, wherein the self-aligned contact has a top surface that is coplanar with a top surface of the sealing layer.
11. A semiconductor device, comprising:
a gate structure located on the fin region, comprising:
a gate electrode; and
a self-aligned contact formed on the gate electrode and comprising a silicon carbide material doped with oxygen;
source/drain contacts;
a sealing layer comprising the silicon carbide material doped with oxygen, wherein the sealing layer further comprises:
a first portion located between the gate structure and the source/drain contact; and
a second portion on top of the self-aligned contacts and the source/drain contacts; and
an air gap surrounded by the sealing layer, the fin region, the gate electrode, and the source/drain contact.
12. The semiconductor device of claim 11, wherein the sealing layer has a density of 2.0g/cm 3 And 3.2g/cm 3 Between them.
13. The semiconductor device of claim 11, wherein the sealing layer has an oxygen atom content between 30% and 55%.
14. The semiconductor device of claim 11, further comprising: a via extends through the second portion of the sealing layer and is in physical contact with the self-aligned contact.
15. The semiconductor device of claim 11, further comprising: a gate dielectric layer and a spacer, wherein the spacer includes a first portion on a sidewall of the gate dielectric layer and a second portion on a top surface of the fin region.
16. A method of forming a semiconductor device, comprising:
forming an opening over a top surface of a substrate and between a first terminal and a second terminal of the semiconductor device; and
forming a silicon carbide material, comprising:
depositing a first portion of the silicon carbide material in the opening and between the first terminal and the second terminal;
depositing a second portion of the silicon carbide material on top of the first and second terminals, wherein a balloon is trapped in the opening surrounded by the silicon carbide material, the first and second terminals, and the substrate; and
An oxygen anneal process is performed on the deposited first and second portions of the silicon carbide material.
17. The method of claim 16, wherein the first portion of the silicon carbide material is deposited toward a top of the opening.
18. The method of claim 16, wherein depositing the first and second portions of the silicon carbide material comprises flowing tetramethyl disiloxane, hydrogen, and oxygen into a deposition chamber.
19. The method of claim 18, wherein the ratio of flow rates of hydrogen to oxygen is between 20 and 30.
20. The method of claim 16, further comprising:
etching the first terminal to recess the first terminal;
depositing another silicon carbide material over the recessed first terminal; and
another oxygen anneal process is performed on the deposited silicon carbide material.
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US16/937,344 US11296187B2 (en) 2019-12-20 2020-07-23 Seal material for air gaps in semiconductor devices
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