TWI756970B - Level status detector - Google Patents

Abstract

A level status detector includes an input terminal, a voltage drop circuit, a pull-down circuit, a loading circuit, a transistor, a pull-up circuit, a first output terminal, and a second output terminal. The voltage drop circuit is coupled to the input terminal. The pull-down circuit is coupled to the voltage drop circuit and a first reference voltage terminal. The loading circuit is coupled to a second reference voltage terminal . The transistor has a first terminal coupled to the loading circuit, a second terminal coupled to the first reference voltage terminal, and a control terminal coupled to the voltage drop circuit. The pull-up circuit is coupled to the second reference voltage terminal and the voltage drop circuit. The first output terminal is coupled to the first terminal of the transistor for outputting a first status detection signal. The second output terminal is coupled to the voltage drop circuit for outputting a second status detection signal.

Description

Potential state discriminating device

The present invention relates to a potential state judging device, in particular to a potential state judging device capable of judging a floating state.

In the design of electronic circuits, the potential state of a specific node is often judged by a potential state judging device, or the state of a circuit or element related to a specific node is judged. However, in the prior art, the potential state identification device can only determine a specific fixed potential, but cannot determine whether a specific node is in a floating state, thus limiting the application range of the potential state identification device.

An embodiment of the present invention provides a potential state judging device, which includes an input terminal, a voltage drop circuit, a pull-down circuit, a load circuit, a transistor, a pull-up circuit, a first output terminal and a second output terminal.

The voltage drop circuit has a first end and a second end, and the first end of the voltage drop circuit is coupled to the input end. The pull-down circuit has a first end and a second end, the first end of the pull-down circuit is coupled to the second end of the voltage drop circuit, and the second end of the pull-down circuit is coupled to the first reference voltage end. The load circuit has a first end and a second end, and the first end of the load circuit is coupled to the second reference voltage end. The transistor has a first end, a second end and a control end, the first end of the transistor is coupled to the second end of the load circuit, and the second end of the transistor is coupled to the first reference voltage end. The pull-up circuit has a first end and a second end, the first end of the pull-up circuit is coupled to the second reference voltage end, and the second end of the pull-up circuit is coupled to the first end of the voltage drop circuit.

The first output terminal is coupled to the first terminal of the transistor for outputting the first state discrimination signal, and the second output terminal is used for outputting the second state discrimination signal. The control end of the transistor is coupled to the second end of the voltage drop circuit and the second output end is coupled to the first end of the voltage drop circuit, or the control end of the transistor is coupled to the first end of the voltage drop circuit And the second output terminal is coupled to the second terminal of the voltage drop circuit.

The first state discriminating signal and the second state discriminating signal are used to judge the potential state of the input terminal.

100, 200, 300, 400, 500, 600, 700, 800: Potential state discrimination device

110, 410, 510, 810: Voltage drop circuit

120, 420, 520, 820: pull-down circuit

130, 354, 430, 454, 530, 754, 830, 854: Load circuit

140, 440, 540, 840: pull-up circuit

250, 350, 450, 650, 750, 850: Logic circuits

352, 452: Reverse and gate

460, 860: Internal circuit

462, 862: switch circuit

464, 864: functional circuit

752, 852: anti-OR gate

CS1, CS2, CS3: Current Sources

DA, D1, D2, D3: Diodes

DU1, DU2, DU3: Diode unit

I _D : Detection current

I _L1 , I _L2 : load current

IN: input terminal

M1A, M1B, M2, M3, M4, M5, M6A, M6B, M7A, M7B, M8, M9: Transistor

OUT1, OUT2: output terminal

RA, RB, R1, R2, R3: Resistors

VN1, VN2: reference voltage terminals

SIG _D1 , SIG _D2 : Status discrimination signal

SIG _ctrl : control signal

FIG. 1 is a schematic diagram of a potential state discriminating device according to an embodiment of the present invention.

FIG. 2 is a schematic diagram of a potential state judging device according to another embodiment of the present invention.

FIG. 3 is a schematic diagram of a potential state judging device according to another embodiment of the present invention.

FIG. 4 is a schematic diagram of the application of the potential state discriminating device according to an embodiment of the present invention.

FIG. 5 is a schematic diagram of a potential state judging device according to another embodiment of the present invention.

FIG. 6 is a schematic diagram of a potential state judging device according to another embodiment of the present invention.

FIG. 7 is a schematic diagram of a potential state judging device according to another embodiment of the present invention.

FIG. 8 is a schematic diagram of an application of a potential state discriminating device according to another embodiment of the present invention.

FIG. 1 is a schematic diagram of a potential state discriminating device 100 according to an embodiment of the present invention. The potential state discrimination device 100 includes an input terminal IN, an output terminal OUT1 , an output terminal OUT2 , a voltage drop circuit 110 , a pull-down circuit 120 , a load circuit 130 , a transistor M1A, and a pull-up circuit 140 .

The voltage drop circuit 110 has a first terminal and a second terminal, and the first terminal of the voltage drop circuit 110 is coupled to the input terminal IN. When the current passes through the voltage drop circuit 110 , the voltage drop circuit 110 will correspondingly generate a voltage drop between the first end and the second end of the voltage drop circuit 110 .

The pull-down circuit 120 has a first end and a second end. The first end of the pull-down circuit 120 is coupled to the second end of the voltage drop circuit 110 , and the second end of the pull-down circuit 120 is coupled to the reference voltage end VN1 .

The load circuit 130 has a first terminal and a second terminal, and the first terminal of the load circuit 130 is coupled to the reference voltage terminal VN2.

The transistor M1A has a first terminal, a second terminal and a control terminal. The first end of the transistor M1A is coupled to the second end of the load circuit 130 , the second end of the transistor M1A is coupled to the reference voltage end VN1 , and the control end of the transistor M1A is coupled to the second end of the voltage drop circuit 110 end.

The pull-up circuit 140 has a first end and a second end, the first end of the pull-up circuit 140 is coupled to the reference voltage terminal VN2 , and the second end of the pull-up circuit 140 is coupled to the first end of the voltage drop circuit 110 . In some embodiments of the present invention, the voltage provided by the reference voltage terminal VN2 may be higher than the voltage provided by the reference voltage terminal VN1. For example, the voltage provided by the reference voltage terminal VN2 may be, for example, but not limited to, the operating voltage in the system, and the voltage provided by the reference voltage terminal VN1 may be, for example, but not limited to, the ground voltage in the system.

The output terminal OUT1 is coupled to the first terminal of the transistor M1A, and can be used for outputting the state discrimination signal SIG _D1 . The output terminal OUT2 is coupled to the first terminal of the voltage drop circuit 110 , and can be used for outputting the state discrimination signal SIG _D2 . The potential state identification device 100 can output state identification signals SIG _D1 and SIG _D2 of different voltages according to the potential state of the input terminal IN. That is to say, the state determination signals SIG _D1 and SIG _D2 can be used to determine the potential state of the input terminal IN. In some embodiments of the present invention, the input terminal IN can be coupled to a specific node, so as to determine the potential state of the specific node, or to determine the state of a circuit or element related to the specific node.

For example, when the potential state of the input terminal IN is in a _floating state, the detection current _ID will flow through the pull-up circuit 140 and the voltage drop under the condition that the detection current ID of an appropriate magnitude is generated. The circuit 110 and the pull-down circuit 120, the pull-up circuit 140 will correspondingly generate a voltage drop, and the voltage of the output terminal OUT2 can be regarded as the difference between the voltage provided by the reference voltage terminal VN2 and the voltage drop generated by the pull-up circuit 140. At this time, the output The terminal OUT2 will output a state discrimination signal SIG _D2 with a high voltage. The voltage received by the control terminal of the transistor M1A can be regarded as a voltage obtained by dividing the voltage of the output terminal OUT2 by the voltage drop circuit 110 and the pull-down circuit 120. Therefore, the control terminal of the transistor M1A will receive a low voltage, so that Transistor M1A is turned off. In this case, the voltage of the output terminal OUT1 can be regarded as the voltage provided by the reference voltage terminal VN2, so the output terminal OUT1 also outputs the state discrimination signal SIG _D1 with a high voltage.

However, when the potential state of the input terminal IN is in a high voltage state, the voltage received by the control terminal of the transistor _M1A can be regarded as the voltage received by the voltage drop circuit 110 and the pull-down circuit 110 under the condition that the detection current ID of an appropriate magnitude is generated. The circuit 120 divides the high voltage of the input terminal IN, so that the control terminal of the transistor M1A is at a high voltage, so the transistor M1A is turned on. At this time, the voltage of the output terminal OUT1 will be pulled down by the transistor M1A to be close to the voltage provided by the reference voltage terminal VN1 , so the output terminal OUT1 will output the state discrimination signal SIG _D1 with a low voltage. In addition, the voltage of the output terminal OUT2 will be dominated by the high voltage of the input terminal IN, so the output terminal OUT2 will output the state discrimination signal SIG _D2 with a high voltage.

Furthermore, when the potential state of the input terminal _IN is in a low voltage state, the voltage received by the control terminal of the transistor M1A can be regarded as being generated by the voltage drop circuit 110 and the The pull-down circuit 120 divides the low voltage of the input terminal IN, so that the control terminal of the transistor M1A is at a low voltage, so the transistor M1A is turned off. In this case, the voltage of the output terminal OUT1 can be regarded as the voltage provided by the reference voltage terminal VN2, so the output terminal OUT1 will output the state discrimination signal SIG _D1 with a high voltage. In addition, the voltage of the output terminal OUT2 will be dominated by the low voltage of the input terminal IN, so the output terminal OUT2 will output the state discrimination signal SIG _D2 with a low voltage.

In this way, the potential state of the input terminal IN can be determined through the state determination signals SIG _D1 and SIG _D2 . That is to say, when the state discrimination signals SIG _D1 and SIG _D2 are both high voltages, it indicates that the potential state of the input terminal IN is in a floating state. When the state discrimination signals SIG _D1 and SIG _D2 are at different voltages, it indicates that the potential state of the input terminal IN is in a high voltage state or a low voltage state.

The current value of the detection current ID can be designed such that when the potential state of the input terminal _IN is in a high voltage state, the control terminal of the transistor M1A can be boosted to a high enough voltage to turn on the transistor M1A, and the input terminal IN is in a high voltage state. When the potential state of the transistor M1A is in a low voltage state or in a floating state, the control terminal of the transistor M1A can be adjusted to a low voltage to turn off the transistor M1A. In some embodiments of the present invention, the pull-up circuit 140 , the voltage-drop circuit 110 and the pull-down circuit 120 can be appropriately designed to generate the detection current ID of an appropriate _magnitude .

FIG. 2 is a schematic diagram of a potential state discriminating device 200 according to another embodiment of the present invention. The potential state discriminating device 200 and the potential state discriminating device 100 have similar structures and may operate according to similar principles, however, the potential state discriminating device 200 may further include a logic circuit 250 .

The logic circuit 250 can be coupled to the output terminals OUT1 and OUT2 for generating the control signal SIG _ctrl related to the potential state of the input terminal IN according to the state discrimination signals SIG _D1 and SIG _D2 . That is to say, through the logic circuit 250 , the potential state judging device 200 can output the control signal SIG _ctrl of different voltages according to the potential state of the input terminal IN, so as to judge the potential state of the input terminal IN.

FIG. 3 is a schematic diagram of a potential state judging device 300 according to another embodiment of the present invention. The potential state discriminating device 300 and the potential state discriminating device 200 have similar structures and may operate according to similar principles, however, the logic circuit 350 of the potential state discriminating device 300 may include a NAND gate 352 and a load circuit 354 .

The inversion gate 352 has a first input terminal, a second input terminal and an output terminal. The first input terminal of the inversion gate 352 is coupled to the output terminal OUT1, and the second input terminal of the inversion gate 352 is coupled to the output terminal OUT2. The output terminal of the inverse gate 352 is used for outputting the control signal SIG _ctrl .

The load circuit 354 has a first terminal and a second terminal, the first terminal of the load circuit 354 is coupled to the reference voltage terminal VN2 , and the second terminal of the load circuit 354 is coupled to the output terminal of the inverter gate 352 .

The potential state discriminating device 300 can output the control signal SIG _ctrl of different voltages according to the potential state of the input terminal IN. For example, according to FIG. 1, when the potential state of the input terminal IN is in a floating state, the output terminal OUT1 will output a high-voltage state discrimination signal SIG _D1 , and the output terminal OUT2 will output a high-voltage state discrimination signal Signal SIG _D2 . In this way, the output terminal of the inversion gate 352 will output the control signal SIG _ctrl with a low voltage.

In addition, when the potential state of the input terminal IN is in a high voltage state, the output terminal OUT1 outputs a state discrimination signal SIG _D1 with a low voltage, and the output terminal OUT2 outputs a state discrimination signal SIG _D2 with a high voltage. In this way, the output end of the inversion gate 352 will output the control signal SIG _ctrl with a high voltage.

Furthermore, when the potential state of the input terminal IN is in a low voltage state, the output terminal OUT1 outputs a state discrimination signal SIG _D1 with a high voltage, and the output terminal OUT2 outputs a state discrimination signal SIG _D2 with a low voltage. In this way, the output terminal of the inversion gate 352 will also output the control signal SIG _ctrl with a high voltage.

That is to say, the potential state of the input terminal IN can be judged through the control signal SIG _ctrl . In Figure 3, when the control signal SIG _ctrl is at a low voltage, it means that the potential state of the input terminal IN is in a floating state. When the control signal SIG _ctrl is at a high voltage, it indicates that the potential state of the input terminal IN is in a high voltage or a low voltage state. In other embodiments of the present invention, the logic circuit 350 may also utilize other logic operations to generate the control signal SIG _ctrl to meet the actual operation requirements of the system.

FIG. 4 is a schematic diagram of an application of a potential state discriminating device 400 according to an embodiment of the present invention. The potential state discriminating device 400 may be one of the implementations of the potential state discriminating device 300 in FIG. 3 , and may operate according to a similar principle. The potential state discriminating device 400 may include an input terminal IN, an output terminal OUT1 , an output terminal OUT2 , a voltage drop circuit 410 , a pull-down circuit 420 , a load circuit 430 , a transistor M1A, a pull-up circuit 440 and a logic circuit 450 .

The voltage drop circuit 410 may include at least one transistor, at least one diode, at least one resistor, or any combination of the foregoing three, while the pull-down circuit 420 may include at least one transistor, at least one diode, to One less resistor or any combination of the above three. For example, in FIG. 4, the voltage drop circuit 410 may include a resistor RA and a diode DA in series with each other, while the pull-down circuit 420 may include a resistor RB. In other embodiments of the present invention, the diode DA may be replaced by a transistor connected in a diode manner.

In some embodiments of the present invention, the load circuit 430 may include a current source CS1, and the current source CS1 may include at least one transistor, at least one diode, at least one resistor, or any combination of the foregoing three. For example, in Figure 4, current source CS1 may include transistor M2 and resistor R1.

The transistor M2 may be a field effect transistor (Field Effect Transistor, FET). In some embodiments of the present invention, the transistor M2 may be a depletion mode (D-mode) pseudomorphic high electron mobility transistor (PHEMT). The transistor M2 has a first terminal, a second terminal and a control terminal. The first terminal of the transistor M2 is coupled to the first terminal of the load circuit 430 . The resistor R1 has a first end and a second end, the first end of the resistor R1 is coupled to the second end of the transistor M2, and the second end of the resistor R1 can be directly or indirectly coupled to the control end of the transistor M2 and the load circuit The second end of 430. The second end of the resistor R1 is directly coupled to the control end of the transistor M2 and the second end of the load circuit 430, and the voltage of the second end of the load circuit 430 is pulled down (that is, the output end OUT1 has a low voltage at this time. The state discrimination signal SIG _D1 ) is taken as an example, the control terminal of the transistor M2 receives a low voltage, so that the transistor M2 is turned on. The voltage of the second terminal of the transistor M2 can be regarded as the voltage of the output terminal OUT1 minus the voltage difference between the control terminal and the second terminal of the transistor M2. The load current I _L1 flowing through the current source CS1 can be regarded as the voltage of the second terminal of the transistor M2 divided by the resistance value of the resistor R1 . Since the resistance value of the resistor _R1 is inversely proportional to the current value of the load current IL1, the load current _IL1 can be reduced (eg less than 1μA) by selecting a resistor R1 with a large resistance value (eg 1MΩ), thereby reducing the potential Leakage current and power consumption of the state determination device 400 . However, the resistor R1 with a large resistance value will occupy more circuit area of the potential state determination device 400 (for example, the circuit area of the current source CS1 will be increased to 1 times the original circuit area).

To improve the above situation, the current source CS1 may further include a diode unit DU1. The diode unit DU1 has a first end and a second end, the first end of the diode unit DU1 is coupled to the second end of the resistor R1, and the second end of the diode unit DU1 is coupled to the control of the transistor M2 terminal and the second terminal of the load circuit 430 . That is, the second end of the resistor R1 is indirectly coupled to the control end of the transistor M2 and the second end of the load circuit 430 . The diode unit DU1 may include at least one transistor, at least one diode, or any combination of the foregoing two. In some embodiments of the present invention, at least one transistor and/or at least one diode with smaller dimensions may be selected. For example, in Figure 4, diode unit DU1 may include transistor M3 and diode D1. The transistor M3 has a first terminal, a second terminal and a control terminal, and the first terminal of the transistor M3 is coupled to the first terminal of the diode unit DU1. The diode D1 has a first end and a second end, the first end of the diode D1 is coupled to the second end of the transistor M3, and the second end of the diode D1 is coupled to the diode unit DU1 second end. In addition, the transistor M3 may be diode connected. In some embodiments of the present invention, the resistor R1 , the transistor M3 and the diode D1 can be used for current limiting. In this way, when the voltage of the second terminal of the load circuit 430 is pulled down, the control terminal of the transistor M2 receives the low voltage, so that the transistor M2 is turned on. The voltage of the second terminal of the transistor M2 can be regarded as the voltage of the output terminal OUT1 minus the voltage difference between the control terminal and the second terminal of the transistor M2. The load current IL1 flowing through the current source CS1 can be regarded as the voltage at the second end of the transistor _M2 minus the voltage drop generated by the transistor M3 and the diode D1, and then divided by the resistance value of the resistor R1. In other words, compared to using the resistor R1 with a large resistance value to reduce the load current _IL1 (eg, less than 1 μA), by arranging the diode unit DU1 , not only the resistor R1 with a smaller resistance value (eg, less than 1 μA) can be selected 0.4MΩ) to reduce the load current I _L1 (for example, less than 1 μA), and also reduce the circuit area occupied by the current source CS1 in the potential state discrimination device 400 (for example, the circuit area of the current source CS1 will be increased to 0.4 of the original circuit area) times). In other embodiments of the present invention, the diode unit DU1 can be designed according to the required current value of the load current _IL1 .

In some embodiments of the present invention, the pull-up circuit 440 may include a current source CS2, and the current source CS2 may include at least one transistor, at least one diode, at least one resistor, or any combination of the foregoing three. For example, in Figure 4, current source CS2 may include transistor M4 and resistor R2.

Transistor M4 may be an FET. In some embodiments of the present invention, the transistor M4 may be a D-mode PHEMT. The transistor M4 has a first terminal, a second terminal and a control terminal. The first terminal of the transistor M4 is coupled to the first terminal of the pull-up circuit 440 . The resistor R2 has a first terminal and a second terminal, the first terminal of the resistor R2 is coupled to the second terminal of the transistor M4, and the second terminal of the resistor R2 can be directly or indirectly coupled to the control terminal and the pull-up terminal of the transistor M4 the second end of the circuit 440 . The second end of the resistor R2 is directly coupled to the control end of the transistor M4 and the second end of the pull-up circuit 440, and the voltage of the second end of the pull-up circuit 440 is pulled down (that is, the potential of the input end IN at this time). The state is in a low voltage state) as an example, the control terminal of the transistor M4 receives a low voltage, so that the transistor M4 is turned on. The voltage of the second terminal of the transistor M4 can be regarded as the voltage of the input terminal IN minus the voltage difference between the control terminal and the second terminal of the transistor M4. The detection current ID flowing through the current source _CS2 can be regarded as the voltage of the second terminal of the transistor M4 divided by the resistance value of the resistor R2. Since the resistance of the resistor _R2 is inversely proportional to the current value of the detection current ID, the detection current ID can be reduced (eg, less than 1 μA) by selecting a resistor R2 with a large resistance value (eg, 1MΩ), thereby reducing the detection current ID (eg, less than 1 _μA ). The leakage current and power consumption of the potential state determination device 400 are reduced. However, the resistor R2 with a large resistance value will occupy more circuit area of the potential state determination device 400 (for example, the circuit area of the current source CS2 will be increased to 1 times the original circuit area).

To improve the above situation, the current source CS2 may further include a diode unit DU2. The diode unit DU2 has a first end and a second end, the first end of the diode unit DU2 is coupled to the second end of the resistor R2, and the second end of the diode unit DU2 is coupled to the control of the transistor M4 terminal and the second terminal of the pull-up circuit 440 . That is, the second end of the resistor R2 is indirectly coupled to the control end of the transistor M4 and the second end of the pull-up circuit 440 . The diode unit DU2 may include at least one transistor, at least one diode, or any combination of the foregoing two. In some embodiments of the present invention, at least one transistor and/or at least one diode with smaller dimensions may be selected. For example, in Figure 4, diode unit DU2 may include transistor M5 and diode D2. The transistor M5 has a first terminal, a second terminal and a control terminal, and the first terminal of the transistor M5 is coupled to the first terminal of the diode unit DU2. The diode D2 has a first end and a second end, the first end of the diode D2 is coupled to the second end of the transistor M5, and the second end of the diode D2 is coupled to the diode unit DU2 second end. Furthermore, the transistor M5 may be connected in a diode manner. In some embodiments of the present invention, resistor R2, transistor M5 and diode D2 may be used for current limiting. In this way, when the voltage of the second terminal of the pull-up circuit 440 is pulled down, the control terminal of the transistor M4 receives the low voltage, so that the transistor M4 is turned on. The voltage of the second terminal of the transistor M4 can be regarded as the voltage of the input terminal IN minus the voltage difference between the control terminal and the second terminal of the transistor M4. The detection current ID flowing through the current source CS2 can be regarded as the voltage at the second end of the transistor M4 minus the voltage drop generated by the transistor M5 and the diode _D2 , and then divided by the resistance value of the resistor R2. In other words, compared to using the resistor R2 with a large resistance value to reduce the detection current ID (eg, less than 1 _μA ), by arranging the diode unit DU2, not only the resistor R2 with a small resistance value can be selected ( For example, _0.4MΩ ) to reduce the detection current ID (for example, less than 1μA), and also to reduce the circuit area occupied by the current source CS2 in the potential state discrimination device 400 (for example, the circuit area of the current source CS2 will be increased to the original circuit area) 0.4 times). In other embodiments of the present invention, the diode unit _DU2 can be designed according to the required current value of the detection current ID.

Logic circuit 450 may include inverting gate 452 and load circuit 454 . Inverter gate 452 may include transistor M6A and transistor M7A. The transistor M6A has a first terminal, a second terminal and a control terminal. The first terminal of the transistor M6A is coupled to the output terminal of the inverting gate 452 , and the control terminal of the transistor M6A is coupled to the first terminal of the inverting and gate 452 . input. The transistor M7A has a first terminal, a second terminal and a control terminal, the first terminal of the transistor M7A is coupled to the second terminal of the transistor M6A, the second terminal of the transistor M7A is coupled to the reference voltage terminal VN1, and the power The control terminal of the crystal M7A is coupled to the second input terminal of the inverting gate 452 .

In addition, in some embodiments of the present invention, the load circuit 454 may include a current source CS3, and the current source CS3 may include at least one transistor, at least one diode, at least one resistor, or any combination of the foregoing three. For example, in Figure 4, current source CS3 may include transistor M8 and resistor R3.

Transistor M8 may be an FET. In some embodiments of the present invention, the transistor M8 may be a D-mode PHEMT. The transistor M8 has a first terminal, a second terminal and a control terminal. The first terminal of the transistor M8 is coupled to the first terminal of the load circuit 454 . The resistor R3 has a first end and a second end, the first end of the resistor R3 is coupled to the second end of the transistor M8, and the second end of the resistor R3 can be directly or indirectly coupled to the control end of the transistor M8 and the load circuit The second end of 454. The second end of the resistor R3 is directly coupled to the control end of the transistor M8 and the second end of the load circuit 454, and the voltage of the second end of the load circuit 454 is pulled down (that is, the output end of the gate 452 is reversed at this time. Taking the output of the control signal SIG _ctrl with a low voltage as an example, the control terminal of the transistor M8 receives the low voltage, so that the transistor M8 is turned on. The voltage at the second terminal of transistor M8 can be regarded as the voltage at the output terminal of inverting gate 452 minus the voltage difference between the control terminal and the second terminal of transistor M8. The load current _IL2 flowing through the current source CS3 can be regarded as the voltage of the second terminal of the transistor M8 divided by the resistance value of the resistor R3. Since the resistance value of the resistor _R3 is inversely proportional to the current value of the load current IL2, the load current _IL2 can be reduced (eg less than 1μA) by selecting a resistor R3 with a large resistance value (eg 1MΩ), thereby reducing the potential Leakage current and power consumption of the state determination device 400 . However, the resistor R3 with a large resistance value will occupy more circuit area of the potential state determination device 400 (for example, the circuit area of the current source CS3 will be increased to 1 times the original circuit area).

To improve the above situation, the current source CS3 may further include a diode unit DU3. The diode unit DU3 has a first end and a second end, the first end of the diode unit DU3 is coupled to the second end of the resistor R3, and the second end of the diode unit DU3 is coupled to the control of the transistor M8 terminal and the second terminal of the load circuit 454 . That is, the second end of the resistor R3 is indirectly coupled to the control end of the transistor M8 and the second end of the load circuit 454 . The diode unit DU3 may include at least one transistor, at least one diode, or any combination of the foregoing two. In some embodiments of the present invention, at least one transistor and/or at least one diode with smaller dimensions may be selected. For example, in Figure 4, diode unit DU3 may include transistor M9 and diode D3. The transistor M9 has a first terminal, a second terminal and a control terminal, and the first terminal of the transistor M9 is coupled to the first terminal of the diode unit DU3. The diode D3 has a first end and a second end, the first end of the diode D3 is coupled to the second end of the transistor M9, and the second end of the diode D3 is coupled to the diode unit DU3 second end. In addition, the transistor M9 may be connected in a diode manner. In some embodiments of the present invention, resistor R3, transistor M9 and diode D3 may be used for current limiting. In this way, when the voltage of the second terminal of the load circuit 454 is pulled down, the control terminal of the transistor M8 receives the low voltage, so that the transistor M8 is turned on. The voltage at the second terminal of transistor M8 can be regarded as the voltage at the output terminal of inverting gate 452 minus the voltage difference between the control terminal and the second terminal of transistor M8. The load current _IL2 flowing through the current source CS3 can be regarded as the voltage at the second end of the transistor M8 minus the voltage drop generated by the transistor M9 and the diode D3, and then divided by the resistance value of the resistor R3. In other words, compared to using the resistor R3 with a large resistance value to reduce the load current IL2 (eg, less than 1 μA), by arranging the diode unit _DU3 , not only the resistor R3 with a smaller resistance value (eg, less than 1 μA) can be selected 0.4MΩ) to reduce the load current I _L2 (for example, less than 1 μA), and also reduce the circuit area occupied by the current source CS3 in the potential state discrimination device 400 (for example, the circuit area of the current source CS3 will be increased to 0.4 of the original circuit area) times). In other embodiments of the present invention, the diode unit _DU3 can be designed according to the required current value of the load current IL2.

In FIG. 4 , when the potential state of the input terminal IN is in a floating state, the state discrimination signals SIG _D1 and SIG _D2 both have high voltages, so that the transistors M6A and M7A are turned on. The voltage of the output terminal of the inverting gate 452 will be pulled down to be close to the voltage provided by the reference voltage terminal VN1 by the transistors M6A and M7A, so the output terminal of the inverting gate 452 will output the control signal SIG _ctrl with a low voltage.

When the potential state of the input terminal IN is in a high voltage state, the state determination signal SIG _D1 has a low voltage, and the state determination signal SIG _D2 has a high voltage, so that the transistor M6A is turned off and the transistor M7A is turned on. The voltage of the output terminal of the inversion gate 452 can be regarded as the voltage provided by the reference voltage terminal VN2, so the output terminal of the inversion gate 452 will output the control signal SIG _ctrl with a high voltage.

When the potential state of the input terminal IN is in a low voltage state, the state determination signal SIG _D1 has a high voltage, and the state determination signal SIG _D2 has a low voltage, so that the transistor M6A is turned on and the transistor M7A is turned off. The voltage of the output terminal of the inverting gate 452 can be regarded as the voltage provided by the reference voltage terminal VN2, so the output terminal of the inverting gate 452 will also output the control signal SIG _ctrl with a high voltage.

In some embodiments of the present invention, the potential state determination device 400 can provide the control signal SIG _ctrl to the internal circuit 460 for use. In this case, the logic circuit 450 in the potential state discriminating device 400 can be coupled to the internal circuit 460 . Internal circuits 460 may include switch circuits 462 and function circuits 464 . The switch circuit 462 is coupled to the logic circuit 450 , and the function circuit 464 is coupled to the switch circuit 462 . Functional circuitry 464 may be used to perform specific functions. For example, the control signal SIG _ctrl can also be used to switch the operation state of the internal circuit 460 . When the control signal SIG _ctrl has a low voltage, the switch circuit 462 can be turned off, thereby disabling the function circuit 464 . When the control signal SIG _ctrl has a high voltage, the switch circuit 462 can be turned on, thereby enabling the function circuit 464 so that the function circuit 464 can perform a specific function. In some embodiments of the present invention, the potential state discriminating device 400 and the internal circuit 460 may be disposed in the same chip, and the input terminal IN of the potential state discriminating device 400 may be coupled to a specific pin (pin) of the chip. ) to determine the potential state of a specific pin.

In other embodiments of the present invention, the control signal SIG _ctrl output by the potential state judging device 400 may also be used by other circuits in other ways, or act directly with other circuits, and is not limited to controlling the internal circuit 460 .

FIG. 5 is a schematic diagram of a potential state judging device 500 according to another embodiment of the present invention. The potential state discriminating device 500 and the potential state discriminating device 100 have similar structures and operate according to similar principles. The potential state discriminating device 500 may include an input terminal IN, an output terminal OUT1 , an output terminal OUT2 , a voltage drop circuit 510 , a pull-down circuit 520 , a load circuit 530 , a transistor M1B and a pull-up circuit 540 . And the control end of the transistor M1B can be coupled to the first end of the voltage drop circuit 510 , and the output end OUT2 can be coupled to the second end of the voltage drop circuit 510 .

In the embodiment of FIG. 5 , the potential state discriminating device 500 can also output state discriminating signals SIG _D1 and SIG _D2 of different voltages according to the potential state of the input terminal IN. That is to say, the state determination signals SIG _D1 and SIG _D2 can be used to determine the potential state of the input terminal IN. In some embodiments of the present invention, the input terminal IN can be coupled to a specific node, so as to determine the potential state of the specific node, or to determine the state of a circuit or element related to the specific node.

For example, when the potential state of the input terminal IN is in a _floating state, the detection current _ID will flow through the pull-up circuit 540 , the voltage drop circuit 510 and the The pull-down circuit 520 and the pull-up circuit 540 will correspondingly generate a voltage drop. The voltage received by the control terminal of the transistor M1B can be regarded as the difference between the voltage provided by the reference voltage terminal VN2 and the voltage drop generated by the pull-up circuit 540. Therefore, the control terminal of the transistor M1B will receive a high voltage, so that the transistor M1B is turned on. At this time, the voltage of the output terminal OUT1 will be pulled down by the transistor M1B to be close to the voltage provided by the reference voltage terminal VN1 , so the output terminal OUT1 will output the state discrimination signal SIG _D1 with a low voltage. In addition, the voltage of the output terminal OUT2 can be regarded as a voltage obtained by dividing the voltage of the control terminal of the transistor M1B by the voltage drop circuit 510 and the pull-down circuit 520 . Therefore, the output terminal OUT2 also outputs a low-voltage state discrimination signal SIG _D2 .

When the potential state of the input terminal IN is in a high voltage state, the voltage received by the control terminal of the transistor M1B is the high voltage of the input terminal IN, so that the transistor M1B is turned on. At this time, the voltage of the output terminal OUT1 will be pulled down by the transistor M1B to be close to the voltage provided by the reference voltage terminal VN1 , so the output terminal OUT1 will output the state discrimination signal SIG _D1 with a low voltage. When the detection current ID of an appropriate magnitude is generated, the voltage of the output terminal _OUT2 can be regarded as a voltage obtained by dividing the high voltage of the input terminal IN by the voltage drop circuit 510 and the pull-down circuit 520, so that the output terminal OUT2 will output The state discrimination signal SIG _D2 with high voltage.

Furthermore, when the potential state of the input terminal IN is in a low voltage state, the voltage received by the control terminal of the transistor M1B is the low voltage of the input terminal IN, so that the transistor M1B is turned off. In this case, the voltage of the output terminal OUT1 can be regarded as the voltage provided by the reference voltage terminal VN2, so the output terminal OUT1 will output the state discrimination signal SIG _D1 with a high voltage. When the detection current ID of an appropriate magnitude is generated, the voltage of the output terminal _OUT2 can be regarded as a voltage obtained by dividing the low voltage of the input terminal IN by the voltage drop circuit 510 and the pull-down circuit 520, so that the output terminal OUT2 will output The state discrimination signal SIG _D2 has a low voltage.

In this way, the potential state of the input terminal IN can be determined through the state determination signals SIG _D1 and SIG _D2 . That is to say, when the state discrimination signals SIG _D1 and SIG _D2 are both low voltages, it indicates that the potential state of the input terminal IN is in a floating state. When the state discrimination signals SIG _D1 and SIG _D2 are at different voltages, it indicates that the potential state of the input terminal IN is in a high voltage state or a low voltage state.

The current value of the detection current ID can be designed to cause the output terminal _OUT2 to have a high voltage when the potential state of the input terminal IN is in a high voltage state, and the potential state of the input terminal IN is in a low voltage or floating state , the output terminal OUT2 can be caused to have a low voltage. Besides, when the potential state of the input terminal IN is in a floating state, the control terminal of the transistor M1B can also be raised to a high enough voltage to turn on the transistor M1B. In some embodiments of the present invention, the pull-up circuit 540 , the voltage-drop circuit 510 and the pull-down circuit 520 can be appropriately designed to generate the detection current ID of an appropriate _magnitude .

FIG. 6 is a schematic diagram of a potential state judging device 600 according to another embodiment of the present invention. The potential state discriminating device 600 and the potential state discriminating device 500 have similar structures and operate according to similar principles, however, the potential state discriminating device 600 may further include a logic circuit 650 .

The logic circuit 650 can be coupled to the output terminals OUT1 and OUT2 for generating the control signal SIG _ctrl related to the potential state of the input terminal IN according to the state discrimination signals SIG _D1 and SIG _D2 . That is to say, through the logic circuit 650, the potential state judging device 600 can output the control signal SIG _ctrl of different voltages according to the potential state of the input terminal IN, so as to judge the potential state of the input terminal IN.

FIG. 7 is a schematic diagram of a potential state judging device 700 according to another embodiment of the present invention. The potential state discriminating device 700 and the potential state discriminating device 600 have similar structures and operate according to similar principles. However, the logic circuit 750 in the potential state discriminating device 700 may include a NOR gate 752 and a load circuit 754 .

The inverse OR gate 752 has a first input terminal, a second input terminal and an output terminal. The first input terminal of the inverse OR gate 752 is coupled to the output terminal OUT1, and the second input terminal of the inverse OR gate 752 is coupled to the output terminal OUT2. The output terminal of the inverse OR gate 752 can output the control signal SIG _ctrl .

The load circuit 754 has a first terminal and a second terminal, the first terminal of the load circuit 754 is coupled to the reference voltage terminal VN2 , and the second terminal of the load circuit 754 is coupled to the output terminal of the inverse OR gate 752 .

The potential state discriminating device 700 can output the control signal SIG _ctrl of different voltages according to the potential state of the input terminal IN. For example, according to FIG. 5, when the potential state of the input terminal IN is in a floating state, the output terminal OUT1 will output a low-voltage state discrimination signal SIG _D1 , and the output terminal OUT2 will output a low-voltage state discrimination signal Signal SIG _D2 . In this way, the output terminal of the inverse-OR gate 752 will output the control signal SIG _ctrl with a high voltage.

In addition, when the potential state of the input terminal IN is in a high voltage state, the output terminal OUT1 outputs a state discrimination signal SIG _D1 with a low voltage, and the output terminal OUT2 outputs a state discrimination signal SIG _D2 with a high voltage. In this way, the output terminal of the inverse-OR gate 752 will output the control signal SIG _ctrl with a low voltage.

Furthermore, when the potential state of the input terminal IN is in a low voltage state, the output terminal OUT1 outputs a state discrimination signal SIG _D1 with a high voltage, and the output terminal OUT2 outputs a state discrimination signal SIG _D2 with a low voltage. In this way, the output terminal of the inverse OR gate 752 will also output the control signal SIG _ctrl with a low voltage.

That is to say, the potential state of the input terminal IN can be judged through the control signal SIG _ctrl . In FIG. 7, when the control signal SIG _ctrl is at a high voltage, it means that the potential state of the input terminal IN is in a floating state. When the control signal SIG _ctrl is at a low voltage, it indicates that the potential state of the input terminal IN is in a high voltage or a low voltage state. In other embodiments of the present invention, the logic circuit 750 may also use other logic operations to generate the control signal SIG _ctrl to meet the actual operation requirements of the system.

FIG. 8 is a schematic diagram of an application of a potential state judging device 800 according to another embodiment of the present invention. The potential state judging device 800 can be one of the implementations of the potential state judging device 700 in FIG. 7 , and can operate according to a similar principle. The potential state discrimination device 800 may include an input terminal IN, an output terminal OUT1 , an output terminal OUT2 , a voltage drop circuit 810 , a pull-down circuit 820 , a load circuit 830 , a transistor M1B, a pull-up circuit 840 , and a logic circuit 850 . In some embodiments of the present invention, the logic circuit 850 in the potential state identification device 800 can also be coupled to the internal circuit 860 , and the control signal SIG _ctrl can also be used to switch the operation state of the internal circuit 860 .

In the embodiment shown in FIG. 8, the voltage drop circuit 810 and the voltage drop circuit 410 can be constructed in the same structure. In practice, the pull-down circuit 820 can be implemented with the same structure as the pull-down circuit 420 , the load circuit 830 can be implemented with the same structure as the load circuit 430 , and the pull-up circuit 840 can be implemented with the same structure as the pull-up circuit 440 . , and the internal circuit 860 can be implemented with the same structure as the internal circuit 460 , so it is not repeated here.

Logic circuit 850 may include inverse OR gate 852 and load circuit 854 . Inverse OR gate 852 may include transistor M6B and transistor M7B. The transistor M6B has a first terminal, a second terminal and a control terminal. The first terminal of the transistor M6B is coupled to the output terminal of the inverse OR gate 852, the second terminal of the transistor M6B is coupled to the reference voltage terminal VN1, and the power The control terminal of the crystal M6B is coupled to the first input terminal of the inverse-OR gate 852 . The transistor M7B has a first terminal, a second terminal and a control terminal, the first terminal of the transistor M7B is coupled to the first terminal of the transistor M6B, the second terminal of the transistor M7B is coupled to the reference voltage terminal VN1, and the power The control terminal of the crystal M7B is coupled to the second input terminal of the inverse-OR gate 852 . In the embodiment shown in FIG. 8 , the load circuit 854 and the load circuit 454 can be implemented with the same structure, and thus are not described in detail.

In FIG. 8, when the potential state of the input terminal IN is in a floating state, the state discrimination signals SIG _D1 and SIG _D2 both have low voltages, so that the transistors M6B and M7B are turned off. The voltage of the output terminal of the inverse OR gate 852 can be regarded as the voltage provided by the reference voltage terminal VN2, so the output terminal of the inverse OR gate 852 will output the control signal SIG _ctrl with a high voltage.

When the potential state of the input terminal IN is in a high voltage state, the state determination signal SIG _D1 has a low voltage, and the state determination signal SIG _D2 has a high voltage, so that the transistor M6B is turned off and the transistor M7B is turned on. The voltage of the output terminal of the inverse OR gate 852 will be pulled down by the transistor M7B to be close to the voltage provided by the reference voltage terminal VN1 , so the output terminal of the inverse OR gate 852 will output the control signal SIG _ctrl with a low voltage.

When the potential state of the input terminal IN is in a low voltage state, the state determination signal SIG _D1 has a high voltage, and the state determination signal SIG _D2 has a low voltage, so that the transistor M6B is turned on and the transistor M7B is turned off. The voltage of the output terminal of the inverse OR gate 852 will be pulled down by the transistor M6B to be close to the voltage provided by the reference voltage terminal VN1 , so the output terminal of the inverse OR gate 852 will also output the control signal SIG _ctrl with a low voltage.

In some embodiments of the present invention, whether it is the state discrimination signals SIG _D1 and SIG _D2 in Fig. 1 or Fig. 5, or the control signals in Fig. 2, Fig. 3, Fig. 6 or Fig. 7 SIG _ctrl , in addition to judging the potential state of the input terminal IN, can also be used by other circuits, or act directly with other circuits, such as the state judging signals SIG _D1 and SIG _D2 or the control signal SIG _ctrl can be used to control its back-end circuit.

In some embodiments of the present invention, logic circuits may be selectively provided according to different applications or according to system requirements. For example, when the back-end circuit of the potential state judging device is single-ended input, a logic circuit such as Figure 2, Figure 3, Figure 4, Figure 6, Figure 7 or Figure 8 can be provided. And when the back-end circuit of the potential state judging device is a double-terminal input, the logic circuit can be omitted, as shown in FIG. 1 or FIG. 5 .

Transistors M1A, M1B, M3, M5, M9, M6A, M7A, M6B or M7B may be FETs. In some embodiments of the present invention, the transistors M1A, M1B, M3, M5, M9, M6A, M7A, M6B or M7B may be an enhancement mode (E-mode) PHEMT. When the transistor is an E-mode PHEMT and is connected in the form of a diode, the control end of the transistor can be coupled to its first end, such as transistors M3, M5 and M9 in Figure 4 or Figure 8 . However, when the transistor is a D-mode PHEMT and is connected by a diode, the control terminal of the transistor can be coupled to the second terminal thereof. The first terminals of the transistors M1A to M9 may be drain electrodes, the second terminals may be source electrodes, and the control terminals may be gate electrodes. The above transistors can be fabricated using a gallium arsenide (GaAs) process.

To sum up, the device for determining the potential state provided by the embodiments of the present invention can determine the potential state of a specific node, such as whether it is a floating state, a high voltage state or a low voltage state. In this way, it is possible to increase the potential states that can be discriminated, which makes the circuit design more flexible, and also expands the application range of the potential state discriminating device.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.

100: Potential state discrimination device

110: Voltage drop circuit

120: pull-down circuit

130: Load circuit

140: Pull-up circuit

M1A: Transistor

I _D : Detection current

IN: input terminal

OUT1, OUT2: output terminal

SIG _D1 , SIG _D2 : Status discrimination signal

VN1, VN2: reference voltage terminals

Claims (19)

A potential state judging device, comprising: an input end; a voltage drop circuit with a first end coupled to the input end and a second end; a pull-down circuit with a first end coupled to the voltage drop The second end of the circuit and a second end are coupled to a first reference voltage end; a first load circuit has a first end coupled to a second reference voltage end, and a second end; a The first transistor has a first end coupled to the second end of the first load circuit, a second end coupled to the first reference voltage end, and a control end; a pull-up circuit has a A first end is coupled to the second reference voltage end, and a second end is coupled to the first end of the voltage drop circuit; a first output end is coupled to the first end of the first transistor , for outputting a first state discrimination signal; and a second output terminal for outputting a second state discrimination signal, wherein the control terminal of the first transistor is coupled to the second voltage drop circuit terminal and the second output terminal is coupled to the first terminal of the voltage drop circuit, or the control terminal of the first transistor is coupled to the first terminal of the voltage drop circuit and the second output terminal is coupled to the second end of the voltage drop circuit; wherein the first state discriminating signal and the second state discriminating signal are used to judge a potential state of the input end; wherein the voltage drop circuit includes at least one transistor , at least one diode, at least one resistor, or any combination of the foregoing three. The potential state discrimination device of claim 1, wherein the pull-down circuit comprises at least one transistor, at least one diode, at least one resistor, or any combination of the foregoing three items. The potential state judging device of claim 1, wherein the first load circuit includes a first current source. The potential state discrimination device according to claim 3, wherein the first current source comprises at least one transistor, at least one diode, at least one resistor or any combination of the foregoing three items. The electrical potential state judging device of claim 3, wherein the first current source comprises: a second transistor having a first end coupled to the first end of the first load circuit, a second end, and a control terminal; a first resistor with a first terminal coupled to the second terminal of the second transistor, and a second terminal; and a first diode unit with a first terminal coupled The second terminal is connected to the first resistor, and a second terminal is coupled to the control terminal of the second transistor and the second terminal of the first load circuit. The potential state discrimination device of claim 1, wherein the pull-up circuit includes a second current source. The potential state discrimination device of claim 6, wherein the second current source comprises at least one transistor, at least one diode, at least one resistor, or any combination of the foregoing three items. The potential state judging device as claimed in claim 6, wherein the second current source comprises: a third transistor having a first end coupled to the first end of the pull-up circuit, a second end, and a control end; a second resistor having a first end coupled to the third The second end of the transistor, and a second end; and a second diode unit, having a first end coupled to the second end of the second resistor, and a second end coupled to the second end The control terminal of the third transistor and the second terminal of the pull-up circuit. The electrical potential state judging device according to claim 1, further comprising: a logic circuit, coupled to the first output end and the second output end, for judging the signal according to the first state and the second state judging signal A control signal is generated, wherein the control signal is related to the potential state of the input terminal. The electrical potential state judging device as claimed in claim 9, wherein the control terminal of the first transistor is coupled to the second terminal of the voltage drop circuit, and the second output terminal is coupled to the voltage drop When the first end of the circuit is used, the logic circuit includes: an inverting and gate, having a first input end coupled to the first output end, a second input end coupled to the second output end, and an output The terminal is used to output the control signal. The potential state discrimination device of claim 10, wherein the logic circuit further comprises: a second load circuit having a first end coupled to the second reference voltage end, and a second end coupled to the inverter and the output terminal of the gate. The device for determining a potential state of claim 11, wherein the inverter gate comprises: a fourth transistor having a first end coupled to the output end of the inverter gate, a second end, and a The control end is coupled to the first input end of the inverting gate; and a fifth transistor has a first end coupled to the second end of the fourth transistor, and a second end coupled to the fourth transistor The first reference voltage terminal and a control terminal are coupled to the second input terminal of the inverter. The potential state discrimination device as claimed in claim 9, wherein the control terminal of the first transistor is coupled to the first terminal of the voltage drop circuit, and the second output terminal is coupled to the voltage drop At the second end of the circuit, the logic circuit includes: an inverting OR gate, having a first input end coupled to the first output end, a second input end coupled to the second output end, and an output The terminal is used to output the control signal. The electrical potential state judging device of claim 13, wherein the logic circuit further comprises: a second load circuit having a first end coupled to the second reference voltage end, and a second end coupled to the inverter or the output of the gate. The device for determining a potential state of claim 14, wherein the inverse-OR gate comprises: a fourth transistor having a first end coupled to the output end of the inverse-OR gate, and a second end coupled to the inverse-OR gate a first reference voltage terminal, and a control terminal coupled to the first input terminal of the inverse OR gate; and a fifth transistor having a first terminal coupled to the first terminal of the fourth transistor, A second terminal is coupled to the first reference voltage terminal, and a control terminal is coupled to the second input terminal of the inverse OR gate. The potential state discrimination device according to claim 11 or 14, wherein the second load circuit includes a third current source, and the third current source includes at least one transistor, at least one diode, at least one resistor, or the aforementioned three any combination of items. The electrical potential state judging device according to claim 11 or 14, wherein the second load circuit includes a third current source, and the third current source includes: a sixth transistor having a first end coupled to the first The first end, a second end, and a control end of two load circuits; a third resistor having a first end coupled to the second end of the sixth transistor, and a second end; and a third diode unit, having a first end coupled to the second end of the third resistor, and a second end coupled to the control end of the sixth transistor and the second load circuit the second end. The electrical potential state judging device as claimed in claim 9, wherein: the logic circuit is further coupled to an internal circuit, and the control signal is further used to switch an operation state of the internal circuit. The potential state judging device according to claim 1, wherein the potential state of the input terminal includes a floating state.

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