CN1224842C - Joint connection state detecting circuit of integrated circuit - Google Patents
Joint connection state detecting circuit of integrated circuit Download PDFInfo
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- CN1224842C CN1224842C CN 01140952 CN01140952A CN1224842C CN 1224842 C CN1224842 C CN 1224842C CN 01140952 CN01140952 CN 01140952 CN 01140952 A CN01140952 A CN 01140952A CN 1224842 C CN1224842 C CN 1224842C
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Abstract
The present invention relates to a connection state detecting circuit of an integrated circuit pin, which can be used for detecting the connection state of a pin, and the use state of an integrated circuit is correctly determined. The present invention comprise a preset power source resistance, and a preset grounding resistance, a reference bias circuit, a scan bias circuit and a latch unit, wherein the scan bias circuit with the same structure of the reference bias circuit is connected to a pin to be detected. The present invention has the operating principle that the structure of the reference bias circuit coupled with the preset power source resistance and the preset grounding resistance is added to make the structure of the reference bias circuit and the structure of the bias circuit coupled with the pin to be detected keep the same, derivative output signals are respectively compared further to be sent to the latch unit, and thus, the connection state of the pin is judged. The present invention can correctly detect the connection status of pins, and can not judge a wrong state caused by the changes of a power supply.
Description
Technical field
The present invention relates to a kind of testing circuit, particularly a kind of joint connection state testing circuit of integrated circuit.
Background technology
Many integrated circuit (IC) apparatus utilize the connection status of the plug-in resistance of its pin to determine the state of its use, and the keyboard of telephone set is an example.In telephone set, keyboard is that a kind of necessary input is equipped with, and it is also inequality in the telephone system specification requirement of different zone countries, for the elasticity that increases integrated circuit is used, industry promptly utilizes the detection pin of keyboard to be suspended to VDD or to the resistance of GND for a long time, decide the state of selected use in the integrated circuit, to meet different demands, this kind is called resistance and selects (R-Option), the result is shown in following table in its output, under a pin position, can determine three configurations, be respectively and draw (Pull-up) resistance, drop-down (Pull down) resistance and (Floating) state of floating.
| Storage A | Latch B | |
| On draw | 1 | 1 |
| Drop-down | 0 | 0 |
| Float | 1 | 0 |
Then, illustrate the joint connection state testing circuit figure of known integrated circuit with Fig. 1.On this supposition scanning pin 10, hang one to GND resistance R ext (being pull-down state), wherein resistance R ext is about 680K ohm, when we during with SCAN=L, fixed current source I1 is via 12 effects of top current mirror, make the electric current on the plug-in resistance R ext also be I1, this moment, latch A was output as 0 when drop-down in order to meet in the table, must be less than V for the voltage I1*Rext that design scans on the pin 10
TH(the transfer point V of reverser
THBe about 1/2VDD), make latch A be output as low state.So in design, fixed current source I1 can not be too big, to guarantee to scan voltage I1*Rext on the pin 10 less than V
THAnd when SCAN=H, detect the voltage of pin 10 and move low state to, behind two reversers 20,22, latch B is output as low state.
Identical, in the time of will originally detecting on the pin 10 plug-in one to VDD resistance R ext as shown in Figure 2, when SCAN=L, detect the voltage of pin 10 and move high voltage VDD to, so through behind two reversers 14,16, the output of latch A is defined as high state.And during SCAN=H, be output as 1 for making latch B, so the voltage (VDD-I2*Rext) on the scanning pin 10 must be less than V
TH(the transfer point V of reverser
THBe about 1/2VDD), make latch B be output as high state, so in design, fixed current source I2 can not be too big.
And when pin when floating, because the ground material that the dealer uses, still there is a resistance when making floating state, but not an infinitely-great resistance (as shown in Figure 1, this resistance is generally greater than 1M ohm, be different from original Fig. 1 ground connection extension less than 1M Ohmage (about 680K ohm)), if during with VDD=2V, the transfer point V of reverser
TH=1V, can obtain current source I1 this moment, the I2 maximal value is about about 1.5 μ A.If we are during with VDD=5, the transfer point V of reverser then
TH=2.5V, so more than the voltage at pin place must be greater than 2.5V, can guarantee that just latch A is output as 1, but be about 1.5 μ A in current source I1, I2 maximal value, have a resistance (Rext) (approximately greater than 1M ohm, but not under the infinitely-great situation) when adding floating state, the voltage that is created in the pin place will can not surpass 2.5V, thereby the situation of generation misinterpretation (by original 1 interpretation is 0, is pull-down state by actual floating state misjudgement promptly).
Certainly, other application drawings 1 judge that with circuit shown in Figure 2 the integrated circuit (IC) apparatus of joint connection state faces above-mentioned problem too.
Summary of the invention
In view of this, purpose of the present invention promptly in that a kind of joint connection state testing circuit of integrated circuit is provided, can avoid judging by accident the connection status of pin.
According to the present invention, a kind of joint connection state testing circuit of integrated circuit comprises a default source resistance and a default stake resistance, reference bias circuit, the scan bias voltage circuit that has with the reference bias circuit same structure is connected to pin to be measured, and latch.Principle of work of the present invention is to utilize the default source resistance of adding identical with pin to be measured with the structure that default stake resistance couples bias circuit, and then the output signal that it is drawn is respectively compared, and delivers to latch, and then judges the connection status of pin.
A kind of testing circuit provided by the invention, in order to the connection status of the pin of judging integrated circuit, this testing circuit comprises: one first bias circuit; One preset resistance, this preset resistance one end connects this first bias circuit, and the other end is for connecting power supply or ground connection; One second bias circuit couples this pin, and the circuit structure of this second bias circuit is corresponding with this first bias circuit; One comparer, the relatively output of this first bias circuit and this second bias circuit; And a latch, accept the output of this comparer.
For above-mentioned and other purposes of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and in conjunction with the accompanying drawings, be described in detail below:
Description of drawings
Fig. 1 illustrates is the figure of plug-in one to GND resistance R ext on the detection pin of joint connection state testing circuit of known integrated circuit;
Fig. 2 illustrates is the figure of plug-in one to VDD resistance R ext on the detection pin of joint connection state testing circuit of known integrated circuit;
Fig. 3 illustrates is joint connection state testing circuit figure according to a kind of integrated circuit of a preferred embodiment of the present invention;
Illustrate among Fig. 4 and use the joint connection state testing circuit of integrated circuit of the present invention to simulate plug-in resistance to the VDD situation;
Illustrate among Fig. 5 and use the joint connection state testing circuit of integrated circuit of the present invention to simulate plug-in resistance to the GND situation;
The joint connection state testing circuit that illustrates another kind of integrated circuit of the present invention among Fig. 6 is used;
Illustrate extension circuit of the present invention and corresponding sequential chart among Fig. 7; And
Fig. 8 illustrates basic structure of the present invention.
Embodiment
With reference to Fig. 3, it illustrates is preferred embodiment according to the joint connection state testing circuit of a kind of integrated circuit of the present invention.
The joint connection state testing circuit of integrated circuit of the present invention comprises reference bias circuit 30, sweep circuit 32, first latch 34 and second latch 36 as can be seen from Figure.
Comprise in the reference bias circuit 30 that default source resistance 38 is coupled between the VDD and first nmos pass transistor 46, first nmos pass transistor 46 and second nmos pass transistor 48 form one group of current mirror, second nmos pass transistor, 48 serial connections the one PMOS transistor 50.One default stake resistance 42 hold with being coupled to and the 2nd PMOS transistor 52 between, the 2nd PMOS transistor 52 and one group of current mirror of the 3rd PMOS transistor 54 formation, the 3rd PMOS transistor 54 is connected in series the 3rd nmos pass transistor 56.
The sweep circuit 32 that connects pin 60 comprises first gauge tap 62, the 4th nmos pass transistor 64, the 5th nmos pass transistor 66, the 6th PMOS transistor 74, second gauge tap, 68, the four PMOS transistors, 70, the five PMOS transistors 72, the 6th nmos pass transistor 76, and first reverser 78 and second reverser 80.
Wherein, first gauge tap 62 is coupled between pin 60 and the 4th nmos pass transistor 64, and it accepts sweep signal SCAN control.First gauge tap 62 couples the 4th nmos pass transistor 64, the four nmos pass transistors 64 and the 5th nmos pass transistor 66 forms one group of current mirror, the 5th nmos pass transistor 66 serial connections the 6th PMOS transistor 74.Wherein the 6th a PMOS transistor 74 and a PMOS transistor 50 are also formed one group of current mirror.
Second gauge tap 68 is coupled between pin 60 and the 4th PMOS transistor 70, and it accepts reverse sweep signal SCAN control.Second gauge tap 68 couples the 4th PMOS transistor 70, the four PMOS transistors 70 and the 5th PMOS transistor 72 forms one group of current mirror, the 5th PMOS transistor 72 serial connections the 6th nmos pass transistor 76.And the 6th nmos pass transistor 76 is also formed one group of current mirror with the 3rd nmos pass transistor 56.The drain electrode of the 6th nmos pass transistor 76 is connected to the drain electrode of the 5th PMOS transistor 72.
On the path that couples second gauge tap 68, it is identical with second current mirroring circuit 44 that the 4th PMOS transistor 70, the five PMOS transistors 72 and the 6th nmos pass transistor 76 are formed a current mirroring circuit.And the 6th nmos pass transistor 76 and the 3rd nmos pass transistor 56 also form one group of current mirror.
In addition, the input end of first reverser 78 connects the drain electrode of the 6th nmos pass transistor 76, and its output is connected to latch A34, and latch A34 accepts sweep signal SCAN control.The input end of second reverser 80 connects the drain electrode of the 6th PMOS transistor 74, and its output is connected to latch B36, and latch B36 accepts reverse sweep signal SCAN control.
Next the principle of work of circuit shown in Figure 3 is described.
The self-reference bias circuit 30 outputs first reference voltage V
TWith the second reference voltage Vg, produce the first reference current Ir1 and the second reference current Ir2 through the 6th PMOS transistor 74 and the 6th nmos pass transistor 76 respectively.Sweep circuit 32 is connected to pin 60, (for example hang one to GND resistance R ext (being pull-down state) in order to the connection status that detects pin 60, hang one to VDD resistance R ext (being pull-up state) or hanging one to GND resistance R ext ' (floating state), wherein Rext '＞＞Rext), it is by the switching of first gauge tap 62 and second gauge tap 68, draw the first detected state electric current I m1 and the second detected state electric current I m2 respectively, then with the first reference current Ir1 and the second reference current Ir2 relatively after, through reverser 78 and 80, produce one first voltage Vm1 and one second voltage Vm2 respectively.
First latch 34 is accepted the first voltage Vm1, produces first output signal (Latch B).Second latch 36 is accepted the second voltage Vm2, produces one second output signal (Latch A).
As the fixed resistance Rext (for example being 680K) of pin 60 connections one ground connection, during SCAN=L, the connection of plug-in its circuit of resistance R ext is identical with the configuration of default stake resistance (Rrefgnd) 42.That is, when Rext=Rrefgnd, no matter how many magnitudes of voltage of VDD is, electric current behind the current mirror mirror inevitable identical (ignoring passage length modulation (Channel length modulation)), therefore (for example we are set at 1M with Rrefgnd as if Rext＜Rrefgnd, and Rext is fixed as 680K) time, Irext (also being Im2 under the current mirror effect)＞Irefgnd (under the current mirror effect, also being Ir2), the A point is a high state, is output as low state through first reverser 78 at latch B.And work as Rext＞Rrefgnd (under the situation of for example floating, Rext is much larger than 1M, and Rrefgnd is 1M), Irext (also being Im2 under the current mirror effect)＜Irefgnd (under the current mirror effect, also being Ir2), the A point is low state, is output as high state through first reverser 78 at latch B.Such result has improved the problem that may occur under original known configurations in table.
For further reducing default source resistance 38 and default stake resistance 42 resistances, we can adjust as the ratio (fixed proportion) between the M1 of first nmos pass transistor 46 and second nmos pass transistor 48 and the M2 (Aspect Ratio), for example make 10M2=M1, then can allow default source resistance 38 be reduced to 100K by original 1M.Identical way is also applicable to default stake resistance 42, and this practice can reduce resistance at the shared area of chip.
Show the analog result of the plug-in resistance of its pin of circuit shown in Figure 3 to VDD in Fig. 4, wherein resistance value is by 400K～1.2K, and when resistance value during less than 1M, circuit can have been judged a plug-in resistance, and when resistance value during greater than 1M, circuit promptly is judged as floating state.
Show the analog result of the plug-in resistance of its pin of circuit shown in Figure 3 at Fig. 5 to GND, has only 4% error under our the different as can be seen operating voltage, meaning is a circuit for the resolution of plug-in resistance and preset resistance is 4%, on the other hand because built-in resistance also has about 20% drift amount, so resolution is about 25%.
Then, in Fig. 6, illustrate the application of the joint connection state testing circuit of another kind of integrated circuit of the present invention, comprising a reference bias circuit 100, respectively corresponding a plurality of first latchs (for example latch A1, latch A2) of a plurality of sweep circuit (for example SCAN1, SCAN2) and a plurality of second latch (for example latch B1, latch B2).The shared reference bias circuit 100 of wherein a plurality of sweep circuits (for example SCAN1, SCAN2) can be carried out the detection of a plurality of pin situations.
Then, in Fig. 7, illustrate extension circuit of the present invention and corresponding sequential chart.Suppose that the value of Rref can control accurately, the resolution of adding circuit can arrive 4%, therefore we ADC that can design 4bit differentiates 16 state (6.25K, 125K, 187.5K, 250K, 312.5K, 375K, 437.5K, 500K, 562.5K, 625K, 687.5K, 750K, 812.5K, 875K, 937.5K and 1M), as making the 6th PMOS transistor 74 among original Fig. 3 into 16 PMOS transistor AND gates 16 gauge tap A0～A15 among the figure, add that (R0～R15) (latch0～latch15) part is made corresponding circuit modifications with latch at reverser, (cooperation of A0～A15) is added in addition to VDD or to the difference of GND and then can be designed 32 states of differentiating to add gauge tap.Based on differentiating various states, by the detection in repetitiousness interval, the present invention also has can detect the plug-in resistance characteristics of value generally.
Those skilled in the art should be from above-mentioned explanation and accompanying drawing, and it is close comparing Fig. 3 and Fig. 1 part-structure in sweep circuit 32, and therefore realization of the present invention can be compatible with public manufacturing process.
On the other hand, know-why of the present invention is to utilize to add a reference bias circuit, and in this reference bias circuit, the configuration of default source resistance or default stake resistance is identical with the circuit that pin connected that connects plug-in resistance.The output signal that the two is drawn (voltage or electric current) compares again, and then the connection status of decision pin.
Therefore, main spirit of the present invention can be simplified as structure shown in Figure 8.Wherein to connect the line construction that bias circuit A and default stake resistance connect bias circuit A identical for pin 60 line construction that is connected to bias circuit A ' and default source resistance.And then the output signal (curtage) of bias circuit A and bias circuit A ' is delivered to comparer B compare, relatively the result after gives latch C.According to the result of latch C output, can judge the state of pin 60 plug-in resistance.
In certain embodiments, identical if the last pin of application is connected to VDD with the plug-in resistance of GND, then can only use a preset resistance to replace default source resistance and default stake resistance shown in Figure 8, between VDD and GND, switch.
Structure more shown in Figure 8 and circuit shown in Figure 3 are when understanding, bias circuit A among Fig. 8 may comprise two parts, these two parts couple default source resistance and default stake resistance respectively, A ' is corresponding with bias circuit, certainly, may comprise also also among the bias circuit A ' that two parts are corresponding with bias circuit A.
Therefore, the technology of this area should be understood, the characteristics of desiring to illustrate among Fig. 8 are that when pin connects bias circuit A ' be when being connected bias circuit A with default source resistance and making comparisons, and the line construction that pin connected is identical with the line construction that default source resistance is connected.And be when being connected bias circuit A with default stake resistance and making comparisons when pin connects bias circuit A ', the line construction that pin connected is identical with the line construction that default source resistance is connected.If the side circuit of the line construction that uses is identical, then can consider shared.
The joint connection state testing circuit of integrated circuit of the present invention connects corresponding line construction by adding preset resistance, can improve the situation that known technology produces erroneous judgement, the connection status of correct detection pin, the employed state of decision integrated circuit.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; any those skilled in the art; without departing from the spirit and scope of the present invention; when can being used for a variety of modifications and variations, so protection scope of the present invention should be with being as the criterion that the claim scope is defined.
Claims (8)
1. testing circuit, in order to the connection status of the pin of judging integrated circuit, described testing circuit comprises: one first bias circuit; One preset resistance, described preset resistance one end connects described first bias circuit, changeable connection power end of the other end and earth terminal; One second bias circuit couples described pin, and the circuit structure of described second bias circuit is corresponding with described first bias circuit; One comparer, the output of more described first bias circuit and described second bias circuit; And a latch, accept the output of described comparer;
Wherein also comprise current mirroring circuit, cause described comparer with output with described first bias circuit and described second bias circuit.
2. testing circuit as claimed in claim 1, wherein said first bias circuit comprises a transistor.
3. testing circuit, in order to the connection status of the pin of judging integrated circuit, described testing circuit comprises:
One first bias circuit;
One default source resistance, described default source resistance one end connects power supply, and the other end is for connecting described first bias circuit;
One default stake resistance, described default stake resistance one end ground connection, the other end is for connecting described first bias circuit;
One second bias circuit couples described pin, and the circuit structure of described second bias circuit is corresponding with described first bias circuit;
One comparer is in order to the output of more described first bias circuit and described second bias circuit; And
One latch is accepted the output of described comparer;
Wherein also comprise current mirroring circuit, cause described comparer with output with described first bias circuit and described second bias circuit.
4. testing circuit as claimed in claim 3, wherein said first bias circuit comprises a transistor.
5. testing circuit, in order to the connection status of the pin of judging integrated circuit, described testing circuit comprises:
First preset path;
Second preset path;
One default source resistance is coupled between power supply and described first preset path;
One default stake resistance between end and described second preset path with being coupled to;
The first detection path and second is detected the path and is coupled described pin, and it is identical with the described first preset path structure that described first pin detects the path, and it is identical with the described second preset path structure that described second pin detects the path;
First comparer relatively detects the signal that draw in the path from described first preset path and described first, and second comparer, relatively detects the signal that draw in the path from described second preset path and described second; And
One latch is accepted the output of described comparer;
Also comprise: a current mirror, the signal of described first preset path is drawn;
One current mirror is drawn the signal of described second preset path;
One current mirror is drawn described first signal that detects the path;
One current mirror is drawn described second signal that detects the path;
6. testing circuit as claimed in claim 5, wherein said first preset path comprises a transistor.
7. testing circuit as claimed in claim 5, wherein said second preset path comprises a transistor.
8. testing circuit, in order to the connection status of the pin of judging integrated circuit, described testing circuit comprises:
The combination of one first current mirror;
One default source resistance is coupled between described first current mirror combination and the power supply;
The combination of one second current mirror;
One default stake resistance between the combination of end and described second current mirror with being coupled to;
Combination of one the 3rd current mirror and the combination of the 4th current mirror, couple described pin respectively, the structure that described pin connects described the 3rd current mirror combination is identical with the structure that described default source resistance couples described first current mirror combination, and the structure that described pin connects described the 4th current mirror combination is identical with the structure that described default stake resistance connects described second current mirror combination;
The 3rd comparer, the relatively signal of drawing, and the 4th comparer, the relatively signal of drawing from described second current mirror combination and described the 4th current mirror combination from described first current mirror combination and described the 3rd current mirror combination; And
One latch is accepted the output of described comparer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01140952 CN1224842C (en) | 2001-09-27 | 2001-09-27 | Joint connection state detecting circuit of integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01140952 CN1224842C (en) | 2001-09-27 | 2001-09-27 | Joint connection state detecting circuit of integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1410778A CN1410778A (en) | 2003-04-16 |
| CN1224842C true CN1224842C (en) | 2005-10-26 |
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ID=4676032
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 01140952 Expired - Fee Related CN1224842C (en) | 2001-09-27 | 2001-09-27 | Joint connection state detecting circuit of integrated circuit |
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| Country | Link |
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| CN (1) | CN1224842C (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7683607B2 (en) * | 2007-09-25 | 2010-03-23 | Himax Display, Inc. | Connection testing apparatus and method and chip using the same |
| TWI555991B (en) * | 2015-02-11 | 2016-11-01 | 友達光電股份有限公司 | Integrated circuit and method of determining a condition of pin connection of the integrated circuit |
| TWI756970B (en) * | 2020-11-23 | 2022-03-01 | 立積電子股份有限公司 | Level status detector |
| CN113219323A (en) * | 2021-04-29 | 2021-08-06 | 深圳数马电子技术有限公司 | Device and method for testing connectivity of chip pins and readable storage medium |
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2001
- 2001-09-27 CN CN 01140952 patent/CN1224842C/en not_active Expired - Fee Related
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| Publication number | Publication date |
|---|---|
| CN1410778A (en) | 2003-04-16 |
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