CN1664600A - Circuit connecting line conducting test method based on dichotomy - Google Patents

Circuit connecting line conducting test method based on dichotomy Download PDF

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CN1664600A
CN1664600A CN 200510031392 CN200510031392A CN1664600A CN 1664600 A CN1664600 A CN 1664600A CN 200510031392 CN200510031392 CN 200510031392 CN 200510031392 A CN200510031392 A CN 200510031392A CN 1664600 A CN1664600 A CN 1664600A
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line
test
wire net
fault
representative
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CN 200510031392
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CN100367045C (en
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蒋句平
田宝华
苏湘玉
肖立权
刘勇鹏
屈晚霞
徐荣生
罗煜峰
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中国人民解放军国防科学技术大学
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Abstract

The invention discloses a method for measuring the junction circuit conducting based on the dichotomy, which overcomes the problems of lower fault coverage and multitime testing in current measuring method. The technical project is: a) setting a controlling program which is used for measuring the junction circuit conducting on the computer based on the dichotomy; b)when measuring the short-circuiting, dividing the combination formed by junction circuit network to two disjoint sets, any junction network in one set cannot connect with any network in the other set; c) dividing the divided sets until the set has only one connecting line or all connecting lines in the set have short-circuit and the set cannot be divided. Said invention has high fault coverage and high accuracy of fault location.

Description

Circuit connection continuity test method based on dichotomy

Technical field: the present invention relates to the method for computer hardware test, especially complex printed circuit (PCB) is gone up the chip chamber line and utilize boundary scan technique to carry out the method for efficient continuity test.

Background technology: along with the development and the application of large scale integrated circuit, very large scale integration technology, unify structure, the function of circuit board of department of computer science becomes increasingly complex, and conventional measuring technology and means can't have been obtained enough detecting informations and finish test to circuit.After IEEE had announced the IEEE1149.1 boundary scan standard in nineteen ninety, boundary scan technique had obtained developing rapidly and using.Because boundary scan technique can effectively test the function of large scale integrated circuit, microcircuit, complicated PCB and the correctness of line, and cost is relatively low, has obtained computer circle and has supported widely and use.

The basic test method of utilizing boundary scan technique to carry out line continuity test between device is: under test controller control, load test patterns from the boundary scan cell of circuit connection network input end, send " external testing " instruction simultaneously, boundary scan cell by the circuit connection network output reads output valve then, judges according to input, output result whether circuit connection exists interconnect fault in the wire net.

When utilizing boundary scan technique to carry out the test of line conducting failure, the fault coverage of test and localization of fault precision depend on the trouble diagnosibility of test patterns, and the test duration is depended on the length of the number of times and the boundary scan chain of boundary scan testing.For certain test circuit, the length of boundary scan chain is fixed, and the test duration depends primarily on the number of times of test.In actual applications, both require test patterns that the high fault diagnosis ability is arranged, again testing time had been had higher requirement.

The method of testing of utilizing boundary scan technique to carry out the test of line conducting failure has multiple, as counting sequence method, count compensation method, displacement method, W step adaptive method etc.Kautz proposes the counting sequence method the earliest, and the counting sequence method is that every line distributes different numberings in the wire net, and the binary mode of when test line being numbered is applied to the line test lead as test patterns.This method can detect any short trouble, but owing to contain complete 0 and complete 1 test patterns, therefore can not detect stationary state fault and open fault, also exist simultaneously the sign erroneous judgement (when the test patterns of a certain line is identical with the test response sign indicating number of certain class short trouble, will cause when localization of fault, can't determining whether this line is included in this short trouble) obscure (when having a plurality of identical test response sign indicating number, will cause when localization of fault, determining whether there is short circuit between these lines) phenomenon with sign.

Nineteen eighty-two Goel and McMahon have proposed improvement counting sequence method, improvement counting sequence method gets on the basis of counting sequence method except complete 0 and complete 1 test patterns, the method can not only detect all bridging faults, can also detect non-detectable stationary state fault of counting sequence method and open fault, but it is the same with the counting sequence method, there are sign erroneous judgement and sign aliasing, can not accurately locate detected fault.

The count compensation method that Wagner proposes can solve sign erroneous judgement problem, but still there is the sign aliasing in it.Displacement 1 method that Hassan proposes is only method that can solve the sign aliasing in the conventional test methodologies, but because its testing time is identical with the number of wire net to be tested, is difficult to satisfy the requirement of line test to the time in the application of reality.

In the test of reality, each test patterns has all comprised certain detecting information.Therefore, in test, if can utilize the test result of front test patterns to generate the test patterns of back, the test performance that is reached will more be optimized.The main thought of Here it is self-adapting testing method.The W step adaptive testing method that Jarwala and Yau propose at first utilizes improvement counting sequence method that wire net is carried out elementary test; Then the test response sign indicating number is analyzed, identified wire net, at last these lines are applied displacement " 1 " method of testing with same response test patterns.This method can diagnose sign erroneous judgement and sign to obscure fault, has complete diagnosis capability; But under the more situation of fault wiring quantity, the step number of W also can be very big, thereby the test duration is very long.

Therefore it is low to utilize boundary scan technique to carry out the method for testing or the fault coverage of line conducting failure test at present, and a little less than the diagnosis capability, localization of fault is inaccurate; Testing time is many, and the test duration is long.

Summary of the invention: technical matters to be solved by this invention is to overcome the problem that fault coverage is low when utilizing boundary scan technique to carry out the circuit connection continuity test at present, diagnosis capability weak, testing time is more, the test duration is long, proposed a kind of circuit connection continuity test method, made that test is efficient and have than high fault coverage based on dichotomy.

The present invention utilizes boundary scan technique to carry out the circuit connection continuity test, and technical scheme is that circuit under test is connected to test board by test cable, and Devices to test is tested.Test board is by a microcomputer, a limit is swept test card and is formed, circuit connection continuity test control program based on the dichotomy establishment is installed on the microcomputer receives with the converting users data, generate test patterns, test control, and test result is reclaimed and analyzes.It is a PCI plug-in card of making separately that test card is swept on the limit, and major function is to produce corresponding test signal under the control of test control program.The main thought of dichotomy is when short trouble is detected, circuit connection network to be measured is treated as a set, and this set is divided into two disjoint subclass, the fault that can not be short-circuited of the arbitrary wire net in each subclass with the arbitrary wire net in another subclass.Further the subclass of dividing is divided then, there is short trouble each other in all lines that only contain in a line or the subclass up to subclass, till can not dividing again.At this moment, if only contain a line in the subclass, show that then this line less than the fault that is short-circuited with other arbitrary line, is normal; If subclass contains many lines, then these lines be certainly short circuit together, therefore can't divide once more.

The principle that the present invention carries out wire net set division is: the line of the fault that is short-circuited, and the test response sign indicating number of their output terminal output is identical certainly; Export the line of different test response sign indicating numbers, certainly not with their short circuits together.According to this principle, the method that the present invention carries out wire net set division is that wire net set V is once tested, and according to the test response sign indicating number of exporting V is divided into two subclass: the test response sign indicating number is 1 network subset V 1With the test response sign indicating number be 0 network subset V 0And then to V 1And V 0Test respectively, further they are divided into littler subclass (V 11, V 10, V 01, V 00), so go on, up to subclass only contain the test response sign indicating number of all lines in a line or the subclass identical till.Under the worst situation, promptly each division only divides a line to come out from network subset, and then test need be carried out N time altogether, and N is the bar number of the test line that contains among the V; Under the optimal cases,, then only need if all the wire net subset division is become equal-sized two subclass at every turn Inferior.

The fault that the circuit board wire net exists mainly contains stationary state fault, open fault and short trouble.The stationary state fault comprises S-A-1 fault (circuit state is always " 1 ") and S-A-0 fault (circuit state is always " 0 ").Open fault is meant because the fault that the circuit connection open circuit causes.In circuit board, according to different circuit concrete structures, open fault is equivalent to S-A-1 fault or S-A-0 fault.Short trouble is the fault that causes owing to the mutual short circuit of two or more lines, and the related line of fault has identical output state, promptly under different test patterns excitations, has identical answer code.Short trouble mainly comprises two classes: line or logic short circuit and line and logic short circuit.For setting forth conveniently, following content is primarily aimed at line or logic, if concrete circuit structure is line and logic, as long as test patterns upset (promptly in following method of testing, the line of input 1 changes input 0 into, and the line of input 0 changes input 1 into) is got final product.

The present invention has defined two notions: from a certain line n iInput end input 1, from another line n jInput end input 0, if n jOutput terminal be output as 1, then claim n iCan be connected to n jA subclass R for wire net set V if the line among the R can be connected to all lines among the V, claims that then R is the representative of V.

By first notion as can be known, if line n iWith n jBetween have short trouble, n then iMust be connected to n j, vice versa; If n 1, n 2... n kThere is short trouble between this K line, then arbitrary line n i(i=1 ... k) can be connected to this K line, from line n i(i=1 ... k) input end input test sign indicating number 1, no matter remaining line input end imports 0 or 1, and the output terminal of this k line all can export 1.By second notion as can be known, if the line input end input test sign indicating number 1 among the R, then no matter other line input end input 0 or 1 among the V, the capital of all the line output terminals outputs among the V is 1.Therefore, V also is the representative of self.

In order to detect stationary state fault and open fault, the present invention increases by two implicit lines: power supply (VCC) and ground (GND).Clearly, it is 1 line that VCC can represent all state output terminals, promptly has the line of S-A-1 fault and open fault, and it is 0 wire net that GND can represent all state output terminals, promptly has the line of S-A-0 fault.

The detailed process that adopts dichotomy to carry out the line continuity test is:

1, circuit under test is connected to test board by test cable, guarantees to connect correctly, in order to avoid influence the correctness of test result.

2, wire net to be measured and implicit wire net VCC, GND are gathered V as the test wire net, the representative set R of V is V self.

If only contain a line among 3 R, then stop test, test result is as follows:

● if contain among the R and have plenty of VCC, then the line among the wire net set V of R representative exists open fault or S-A-1 fault;

● if contain among the R and have plenty of GND, then there is the S-A-0 fault in the line among the wire net set V of R representative;

● otherwise, there is the bridge joint short trouble between the line among the wire net set V of R representative;

If 4 wire nets representative collection R contains the line of one or more, then R is divided into R 1And R 0Two wire net representative collection, R 1The line number that contains is R 0The line number that contains is | R|-|R 1|.(| R| represents the line number that contains among the wire net collection R)

5, at representative collection R 1The wire net input end input test sign indicating number 1 that contains is at R 0The wire net input end input test sign indicating number 0 that contains, the input end input test sign indicating number 0 of the wire net beyond the representative collection, V tests to the wire net set;

6, according to test result V is divided into two wire nets: the test response value is 1 wire net set V 1With the test response value be 0 wire net set V 0

7, owing to can being included in representative, concentrates the wire net that open fault and stationary state fault take place, therefore to after the V division, and R 1In can contain and not belong to V 1Wire net, R 0In can contain and not belong to V 0Wire net.If there is this situation,, then remove R according to the implication of representative collection 1In do not belong to V 1Line, remove R 0In do not belong to V 0Line.Then to R 1The wire net set V of representative 1And R 0The wire net set V of representative 0

Test respectively.

When network representative collection R being divided,, then to guarantee to divide back VCC and be included in R if VCC is included among the R in the 4th step 1In, send 1 to guarantee that VCC implies in each test; If GND is included among the R, then to guarantees to divide back GND and be included in R 0In, send 0 to guarantee that GND implies in each test.

When network representative collection R is divided, By test execution mode and induction principle as can be known, the size of final network representative collection R is 1 certainly, and test can finish.Consider that the representative collection is the wire net collection V of R, establish and contain I bar line among the V, contain j bar line among the R, then the testing time P that carried out of this method of testing tracing trouble (i j) is:

Thereby Increased VCC and two implicit lines of GND owing to concentrating, so method of testing of the present invention needed testing time when test has the wire net of N bar line is at wire net to be measured Adopt the present invention can reach following technique effect:

1) testing time seldom.To line continuity test arbitrarily, owing to only be that testing time all seldom can be tested fast and effectively to a large amount of wire nets to the simple division of test network set.

2) fault coverage height.This method not only can detect the short trouble of wire net, and can detect the stationary state fault.

3) localization of fault is accurate.The method has been eliminated sign and has been obscured and the sign misjudgment phenomenon, can accurately locate fault.

4) method of testing realizes simply circuit under test to be connected to test board by test cable, and is easy to operate.

Description of drawings:

Fig. 1 is boundary scan technique ultimate principle figure;

Fig. 2 is the circuit connection diagram when adopting the present invention to carry out the line continuity test;

Fig. 3 adopts the present invention to carry out an example of line continuity test;

Fig. 4 is various method of testing performance comparison diagrams.

Embodiment:

Fig. 1 is the ultimate principle figure of boundary scan technique.The main thought of boundary scan technique is by between chip pin and chip internal logical circuit, be to increase the boundary scan cell that constitutes by shift register on the border of chip, realization is set and is read the serial of chip pin state, thereby provides chip-scale, circuit board level so that system-level standard testing framework.As shown in the figure, each boundary scan cell connects into scan chain with serial mode, both can test patterns be imported in the mode of serial by scan input end, and corresponding pin status is set, and realizes the loading of test patterns; Also can carry out the analysis and the processing of data by the test response serial output of scanning output end with system.

Fig. 2 utilizes the present invention to carry out the circuit connection diagram of continuity test.Testing apparatus comprises a test board, a test cable, Devices to test.Test board is by a microcomputer, and the test card composition is swept on a limit, and the circuit connection continuity test program of employing based on the method establishment of dichotomy is installed on the microcomputer.Circuit connection continuity test program major function comprises: reception and converting users data, test patterns generate, test control, test result recovery and analyze.It is a special PCI plug-in card that test card is swept on the limit, produces corresponding boundary scan testing signals under the control of test control program.A boundary scan interface (JTAG) is arranged on the Devices to test, and the boundary scanning device on the equipment is connected into a boundary scan chain.Test card is connected with the boundary scan interface of Devices to test by test cable.

Three subgraph A, B, C are arranged among Fig. 3, be to adopt the present invention to carry out an embodiment of continuity test, as scheme shown in the A, comprise 8 lines in the line set to be tested, S-A-0 fault, line n2 take place in line n1, n4 and n5 short circuit, line n3 open circuit, there is the S-A-1 fault in line n6, line n7 and n8 short circuit.When beginning test, test line set V be n1 ..., n8, VCC, GND}, the representative collection R of V be n1 ... n8, VCC, GND}.The 1st test is divided into R with R 1(comprise VCC, n1, n2, n3, n4) and R 0(comprise n5, n6, n7, n8, GND) two subclass, R 1In line input test sign indicating number 1, R 0In line input test sign indicating number 0.VCC, n2, n3, n4, n5, the test response sign indicating number of n6 is 1, n1, n7, n8, the test response sign indicating number of GND is 0.According to the test response sign indicating number is 1 or 0, and V is divided into two subclass V 1(VCC, n2, n3, n4, n5, n6) and V 0(n1, n7, n8, GND).Because n1 is not at V 1In, so R 1Be adjusted into { VCC, n2, n3, n4}.Equally, because n5, n6 not at V 0In, so R 0Be adjusted into { n7, n8, GND}.As scheme shown in the B, the 2nd time is parallel to (V 1, R 1) and (V 0, R 0) test, with R 1Be divided into R 11(VCC, n2) and R 10(n3, n4), R 0Be divided into R 01(n7) and R 00(n8, GND); R 11And R 01In line input test sign indicating number 1, R 10And R 00In line input test sign indicating number 0.Test result is further with V 1Be divided into V 11(VCC, n2, n3, n4, n5, n6) and V 10, V 10Be sky; With V 0Be divided into V 01(n7, n8) and V 00(n1, GND); Representative collection R 11Further be adjusted into { VCC, n2}, R 01Be adjusted into { n7}, R 00Be adjusted into { GND}, R 10Do not contain any line, get rid of.Because R 01, R 00Only contain a line, so to (V 01, R 01) and (V 00, R 00) end of test (EOT).As scheme C, the 3rd time only to (V 11, R 11) test.R 11Be divided into R 111(VCC) and R 110(n2); After the test with V 11Be divided into V 111(VCC, n3, n6) and V 110(n2, n4, n5).Last test result is: the VCC} representative VCC, and n3, n6}, n3, n6 opens a way or is fixed as 1; { n2} represents { n2, n4, n5}, n2, n4, the short circuit of n5 bridge joint; { n7} represents { n7, n8}, n7, the short circuit of n8 bridge joint; { { n1 is fixed as 0 for n1, GND} in the GND} representative.Therefore, adopt the present invention need only 3 Inferior test just correctly detects the wire net fault and locatees.

Fig. 4 is that various continuity test method performances compare.Need to suppose wire net of test with 1000 lines, utilize every kind of method to test needed testing time, detection failure ability and localization of fault precision situation thereof to be: counting sequence method test 10 times, can not detect persistent fault and open fault, exist sign to obscure and the sign misjudgment phenomenon, can not accurately locate fault; Improve counting sequence method test 10 times, can detect all faults that line exists, but can not accurately locate fault; Count compensation method test 20 times can detect all faults that line exists, but can not accurately locate fault; Displacement 1 (0) method test 1000 times can detect all faults and accurate location that line exists; Unnecessary 10 times of W step adaptive method testing time also can detect all faults and accurate location that line exists; The number of times that utilizes the present invention to test is 10 times, and can detect all faults and accurate location that line exists.As can be seen, the method for testing testing time in all continuity test methods based on dichotomy of the present invention is minimum, the fault coverage height, and localization of fault is accurate, can carry out the circuit connection continuity test preferably.

Claims (5)

1. circuit connection continuity test method based on dichotomy, utilize boundary scan technique to carry out the circuit connection continuity test, it is characterized in that being equipped with on the microcomputer a circuit connection continuity test control program based on the dichotomy establishment, when short trouble is detected, circuit connection network to be measured is treated as a set, and this set is divided into two disjoint subclass, arbitrary wire net in each subclass fault that can not be short-circuited with the arbitrary wire net in another subclass, further the subclass of dividing is divided then, there is short trouble each other in all lines that only contain in a line or the subclass up to subclass, till can not dividing again; At this moment, if only contain a line in the subclass, show that then this line less than the fault that is short-circuited with other arbitrary line, is normal; If subclass contains many lines, then these lines be certainly short circuit together, can't divide once more.
2. the circuit connection continuity test method based on dichotomy as claimed in claim 1 is characterized in that the principle of carrying out wire net set division is: the line of the fault that is short-circuited, and the test response sign indicating number of their output terminal output is identical certainly; Export the line of different test response sign indicating numbers, certainly not with their short circuits together.According to this principle, the method that the present invention carries out wire net set division is that wire net set V is once tested, and according to the test response sign indicating number of exporting V is divided into two subclass: the test response sign indicating number is 1 network subset V 1With the test response sign indicating number be 0 network subset V 0And then to V 1And V 0Test respectively, further they are divided into littler subclass (V 11, V 10, V 01, V 00), so go on, up to subclass only contain the test response sign indicating number of all lines in a line or the subclass identical till.
3. the circuit connection continuity test method based on dichotomy as claimed in claim 1 is characterized in that the present invention has defined two notions: from a certain line n iInput end input 1, from another line n jInput end input 0, if n jOutput terminal be output as 1, then claim n iCan be connected to n jA subclass R for wire net set V if the line among the R can be connected to all lines among the V, claims that then R is the representative of V; By first notion as can be known, if line n iWith n jBetween have short trouble, n then iMust be connected to n j, vice versa; If n 1, n 2... n kThere is short trouble between this K line, then arbitrary line n i(i=1 ... k) can be connected to this K line, from line n i(i=1 ... k) input end input test sign indicating number 1, no matter remaining line input end imports 0 or 1, and the output terminal of this k line all can export 1; By second notion as can be known, if the line input end input test sign indicating number 1 among the R, then no matter other line input end input 0 or 1 among the V, the capital of all the line output terminals outputs among the V is 1, therefore, V also is the representative of self.
4. the circuit connection continuity test method based on dichotomy as claimed in claim 1, it is characterized in that in order to detect stationary state fault and open fault, the present invention increases by two implicit lines: power supply VCC and ground GND, it is 1 line that VCC represents all state output terminals, the line that promptly has S-A-1 fault and open fault, it is 0 wire net that GND represents all state output terminals, promptly has the line of S-A-0 fault.
5. the circuit connection continuity test method based on dichotomy as claimed in claim 1 is characterized in that the detailed process that adopts dichotomy to carry out the line continuity test is:
5.1 circuit under test is connected to test board by test cable, guarantees to connect correctly, in order to avoid influence the correctness of test result;
5.2 wire net to be measured and implicit wire net VCC, GND are gathered V as the test wire net, and the representative set R of V is V self;
If 5.3 only contain a line among the R, then stop test, test result is as follows:
● if contain among the R and have plenty of VCC, then the line among the wire net set V of R representative exists open fault or S-A-1 fault;
● if contain among the R and have plenty of GND, then there is the S-A-0 fault in the line among the wire net set V of R representative;
● otherwise, there is the bridge joint short trouble between the line among the wire net set V of R representative;
5.4 if wire net representative collection R contains the line of one or more, then R is divided into R 1And R 0Two wire net representative collection, R 1The line number that contains is R 0The line number that contains is | R|-|R 1|;
5.5 at representative collection R 1The wire net input end input test sign indicating number 1 that contains is at R 0The wire net input end input test sign indicating number 0 that contains, the input end input test sign indicating number 0 of the wire net beyond the representative collection, V tests to the wire net set;
5.6 according to test result V is divided into two wire nets: the test response value is 1 wire net set V 1With the test response value be 0 wire net set V 0
5.7 because can being included in representative, concentrates the wire net of generation open fault and stationary state fault, after therefore V being divided, and R 1In can contain and not belong to V 1Wire net, R 0In can contain and not belong to V 0Wire net, if there is a this situation,, then remove R according to the implication of representative collection 1In do not belong to V 1Line, remove R 0In do not belong to V 0Line, then to R 1The wire net set V of representative 1And R 0The wire net set V of representative 0Test respectively;
When network representative collection R being divided,, then to guarantee to divide back VCC and be included in R if VCC is included among the R in the 4th step 1In, send 1 to guarantee that VCC implies in each test; If GND is included among the R, then to guarantees to divide back GND and be included in R 0In, send 0 to guarantee that GND implies in each test.
CNB2005100313929A 2005-03-30 2005-03-30 Circuit connecting line conducting test method based on dichotomy CN100367045C (en)

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CN108627716A (en) * 2017-03-22 2018-10-09 株洲中车时代电气股份有限公司 A kind of current transformer complete machine overall process detection coverage ratio analysis method
CN107942187A (en) * 2017-11-21 2018-04-20 北京宇航系统工程研究所 A kind of cable system continuity test method based on constant-current source
CN109031064A (en) * 2018-07-24 2018-12-18 常州同惠电子股份有限公司 High pressure two for wire test instrument divides test method

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