TWI752067B - Semiconductor device and a semiconductor system - Google Patents

Abstract

A semiconductor device includes a first intellectual property block (IP block) which includes a function unit and an interface unit; a first clock control circuit which controls a first clock source; a second clock control circuit which transmits a first clock request to the first clock control circuit, and controls a second clock source which receives a clock signal from the first clock source; and a channel management circuit configured to transmit a second clock request to the second clock control circuit in response to a clock stop request received from the first IP block; wherein the function unit controls an operation of the first IP block, and the interface unit receives a first signal provided from a second IP block electrically connected to the first IP block and provides the first signal to the function unit.

Description

Semiconductor devices and semiconductor systems

The inventive concept relates to a semiconductor device, a semiconductor system, and a method of operating the semiconductor device.

A system-on-chip (SoC) may include one or more intellectual property blocks (IP blocks), a clock management unit (CMU), and a power management unit (power management unit) , PMU). The clock management unit provides clock signals to one or more intellectual property blocks. The clock management unit may not provide clock signals to intellectual property blocks that are not in operation, thereby reducing waste of resources in systems using SoCs.

In order to control the supply of the clock signal, the software can use the special function register (SFR) to control the multiplexing circuit (MUX circuit) and clock division included in the clock management unit. Various clock sources such as clock dividing circuit, short stop circuit, and clock gating circuit. However, software control may be slower than hardware control.

According to an exemplary embodiment of the present inventive concept, there is provided a semiconductor device including: a first intellectual property (IP) block including a functional unit and an interface unit; and a first clock control circuit for controlling a first clock source; a second clock control circuit that transmits a first clock request to the first clock control circuit and controls a second clock source, the second clock originating from the time the first clock source receives a pulse signal; and a channel management circuit configured to transmit a second clock request to the second clock control circuit in response to a clock stop request received from the first intellectual property block; wherein the functional unit The operation of the first intellectual property block is controlled, and the interface unit receives a first signal provided from a second intellectual property block electrically connected to the first intellectual property block and sends the first signal to the provided to the functional unit.

According to an exemplary embodiment of the present inventive concept, there is provided a semiconductor device including: a master intellectual property block operating in response to a first clock signal provided from a clock management unit (CMU); and a slave The property block includes a functional unit and an interface unit, the functional unit operates in response to a second clock signal provided from the clock management unit, and the interface unit is configured to operate from the host at a first point in time The intellectual property block receives the bus operation signal and provides the bus operation signal to the functional unit at a second time point different from the first time point.

According to an exemplary embodiment of the inventive concept, there is provided a semiconductor system including a system-on-chip (SoC) and one or more external devices electrically connected to the system-on-chip, the system-on-chip (SoC) including : a first intellectual property block, including a functional unit and an interface unit; a second intellectual property block, electrically connected to the first intellectual property block; a first clock control circuit, controlling the first clock source; Two clock control circuits, transmitting a first clock request to the first clock control circuit, and controlling a second clock source, the second clock receiving a clock signal from the first clock source; and a channel management circuit that transmits a second clock request to the second clock control circuit in response to a clock stop request received from the first intellectual property block, wherein the functional unit controls the first intellectual property The operation of the property block, and the interface unit receives the first signal provided from the second intellectual property block and provides the first signal to the functional unit.

According to an exemplary embodiment of the present inventive concept, there is provided a method of operating a semiconductor device, the method comprising: receiving a first signal from an autonomous intellectual property block; transmitting to a clock management unit a functional unit for waking up the slave intellectual property block the clock request; after the clock signal is received from the clock management unit from the intellectual property block, a second signal corresponding to the first signal is generated; and the second signal is provided to the described functional unit.

According to an exemplary embodiment of the present inventive concept, there is provided a semiconductor device including: a first intellectual property block including a functional unit and an interface unit; and a second intellectual property block electrically connected to the first intellectual property block an intellectual property block, wherein the interface unit is configured to: receive a first signal from the second intellectual property block when the functional unit is in a sleep state; and when the functional unit wakes up, provide a second signal corresponding to the first signal.

FIG. 1 is a schematic diagram of a semiconductor device according to an exemplary embodiment of the inventive concept.

1 , a semiconductor device 1 according to an exemplary embodiment of the present inventive concept includes a clock management unit (CMU) 100 , intellectual property blocks (IP blocks) 200 and 210 , and a power management unit (PMU) 300 . The semiconductor device 1 according to the exemplary embodiment of the inventive concept may be provided as a system on chip (SoC), but the inventive concept is not limited thereto.

The clock management unit 100 provides clock signals to the intellectual property blocks 200 and 210 . In this embodiment, the clock management unit 100 includes clock components 120 a , 120 b , 120 c , 120 d , 120 e , 120 f , and 120 g , channel management circuits 130 and 132 , and a clock management unit controller 110 . The clock components 120a, 120b, 120c, 120d, 120e, 120f, and 120g generate clock signals to be provided to the intellectual property blocks 200 and 210, and the channel management circuits 130 and 132 are disposed between the clock components 120f and 120g and the A communication channel CH is provided between the intellectual property blocks 200 and 210 to provide a communication channel CH between the clock management unit 100 and the intellectual property blocks 200 and 210 . In addition, the clock management unit controller 110 provides clock signals to the IP blocks 200 and 210 using the clock components 120a, 120b, 120c, 120d, 120e, 120f, and 120g.

In an exemplary embodiment of the inventive concept, the communication channel CH provided by the channel management circuits 130 and 132 may be configured to comply with the ARM ^Ò Low Power Interface (LPI) specification as defined in the ^{ARM Ò LPI Specification} The low power interface (LPI), the Q-channel interface, or the P-channel interface, but the concept of the present invention is not limited to this. For example, the communication channel CH may conform to any communication protocol depending on how the semiconductor device 1 is to be implemented.

Each of clock components 120a, 120b, 120c, 120d, 120e, 120f, and 120g includes clock sources 124a, 124b, 124c, 124d, 124c, 124f, and 124g, and a pair of clock sources 124a, 124b, respectively , 124c, 124d, 124e, 124f, and 124g control the clock control circuits 122a, 122b, 122c, 122d, 122e, 122f, and 122g. The clock sources 124a, 124b, 124c, 124d, 124e, 124f, and 124g may include, for example, multiplexing circuits (MUX circuits), clock division circuits, short stop circuits, clock gating circuits, and the like.

The clock components 120a, 120b, 120c, 120d, 120e, 120f, and 120g have a parent-child relationship with each other. In this embodiment, the clock component 120a is the parent component of the clock component 120b, and the clock component 120b is a child component of the clock component 120a and is the parent component of the clock component 120c. In addition, clock component 120e is the parent component of the two clock components 120f and 120g, and clock components 120f and 120g are child components of clock component 120e. In addition, in this embodiment, the clock component 120a disposed closest to the phase locked loop (PLL) is the root clock component and disposed closest to the intellectual property area Clock components 120f and 120g of blocks 200 and 210 are leaf clock components. Such and clock components are also formed between the clock control circuits 122a, 122b, 122c, 122d, 122e, 122f, and 122g and between the clock sources 124a, 124b, 124c, 124d, 124e, 124f, and 124g The parent-child relationship corresponding to the parent-child relationship of 120a, 120b, 120c, 120d, 120e, 120f, and 120g.

In an embodiment, the clock component 120a is implemented by a phase locked loop controller. In an embodiment, the PLL controller receives the constant or variable frequency signal oscillated by the oscillator OSC and the PLL signal output by the PLL from the oscillator OSC, and outputs the received signal based on a specific condition. one of the two signals. When the component needs the PLL signal, the PLL controller outputs the PLL signal. When the component needs the oscillator signal, the PLL controller outputs the oscillator signal. For example, a phase locked loop controller may be implemented using a ring oscillator or a crystal oscillator. In an embodiment, the clock component 120b is a clock multiplexer unit that receives the first clock signal CLK1 from the first clock component 120a and from an external source (eg, an external clock management unit) Receive the second clock signal CLK2.

The clock control circuits 122a, 122b, 122c, 122d, 122e, 122f, and 122g transmit and receive clock requests (REQs) and their acknowledgements (ACKs) between the parent and child components, and provide clock signals to the smart Property blocks 200 and 210.

For example, if the IP block 200 does not need a clock signal, eg, if the IP block 200 is to be in a sleep state, the clock management unit 100 stops providing the clock signal to the IP block 200 .

For example, under the control of the clock management unit 100 or the clock management unit controller 110 , the channel management circuit 130 transmits the first signal for stopping the supply of the clock signal to the intellectual property block 200 . After the work being processed is completed, upon receiving the first signal, the IP block 200 transmits a second signal to the channel management circuit 130 indicating that the clock signal can be stopped. After receiving the second signal from the IP block 200, the channel management circuit 130 requests the clock component 120f to instruct its parent component to stop providing the clock signal.

As an example, if the communication channel CH provided by the channel management circuit 130 conforms to the Q-channel interface, the channel management circuit 130 transmits to the IP block 200 a The QREQn signal is used as the first signal. After that, the channel management circuit 130 receives, for example, the QACCEPTn signal having the first logic value from the IP block 200 as the second signal. Next, the channel management circuit 130 transmits, for example, a clock request (REQ) having a first logic value to the clock component 120f. In this case, the clock request (REQ) having the first logic value refers to a "clock provision stop request".

Upon receiving a clock request (REQ) having a first logic value from channel management circuit 130 (in other words, a clock supply stop request), clock control circuit 122f instructs clock source 124f (eg, a clock gating circuit) Stop providing the clock signal. Therefore, the IP block 200 may enter sleep mode. During this process, the clock control circuit 122f may provide an ACK with the first logic value to the channel management circuit 130. It should be noted that even if the channel management circuit 130 receives an acknowledgement (ACK) with the first logic value after transmitting the clock supply stop request with the first logic value, it may not be possible to ensure that the clock supply from the clock source 124f is stopped . This is because the above acknowledgement (ACK) may only mean that the clock component 120f that the clock control circuit 122f recognizes as the parent component of the channel management circuit 130 does not have to provide the clock to the channel management circuit 130 .

On the other hand, the clock control circuit 122f of the clock component 120f may transmit a clock request (REQ) having the first logic value to the clock control circuit 122e of its mother clock component 120e. If the IP block 210 does not require a clock signal (eg, when the clock control circuit 122e receives a clock supply stop request from the clock control circuit 122g), the clock control circuit 122e disables the clock source 124e (eg, clock division circuit) to stop providing the clock signal. As a result, IP blocks 200 and 210 may enter sleep mode.

Such operations may be performed similarly for the other clock control circuits 122a, 122b, 122c, and 122d.

In addition, even if the clock control circuit 122f of the clock component 120f transmits a clock request (REQ) with the first logic value to the clock control circuit 122e of its mother clock component 120e, if the IP block 210 is in the running state, Then the clock control circuit 122e may still be unable to disable the clock source 124e. After that, only when the IP block 210 no longer needs the clock signal, the clock control circuit 122e will disable the clock source 124e and transmit the clock request with the first logic value ( REQ). In other words, clock control circuit 122e may disable clock source 124e only when it receives clock provision stop requests from both its sub-clock control circuits 122f and 122g.

When the owners of clock sources 124a, 124b, 124c, 124d, 124e, and 124f are all disabled in the sleep state of IP blocks 200 and 210 and IP block 200 enters the running state, the clock management unit 100 then resumes providing clock signals to IP blocks 200 and 210.

The channel management circuit 130 transmits a clock request (REQ) having a second logic value (eg, a logic high value, hereinafter indicated by H) to the clock control circuit 122f of its parent clock component 120f, and waits for the clock control circuit from the Acknowledgement (ACK) of circuit 122f. Here, the clock request (REQ) having the second logic value refers to a "clock provision request", and the acknowledgement (ACK) of the clock provision request means restarting the clock provision from the clock source 124f pulse. The clock control circuit 122f may not immediately enable the clock source 124f (eg, a clock gating circuit) and therefore waits for a clock signal from its parent component.

Next, the clock control circuit 122f transmits a clock request (REQ) having the second logic value (in other words, a clock supply request) to its mother clock control circuit 122e, and waits for an acknowledgment (ACK) from the clock control circuit 122e ). Such operations may be performed similarly for clock control circuits 122a, 122b, 122c, and 122d.

As a root clock component that has received a clock request (REQ) having a second logic value from clock control circuit 122b, clock control circuit 122a enables clock source 124a (eg, a multiplexer circuit) and sends clock control Circuit 122b transmits an acknowledgement (ACK). When clock sources 124b, 124c, 124d, and 124e are sequentially enabled in this manner, clock control circuit 122e transmits an acknowledgement (ACK) to clock control circuit 122f indicating to resume clocking from clock source 124e. Upon receipt of an acknowledgement (ACK), clock control circuit 122f enables clock source 124f, provides a clock signal to IP block 200, and provides an acknowledgement (ACK) to channel management circuit 130.

In this way, the clock control circuits 122a, 122b, 122c, 122d, 122e, 122f, and 122g operate in a full handshake manner to transmit and receive clock requests ( REQ) and acknowledgement (ACK). As a result, clock control circuits 122a, 122b, 122c, 122d, 122e, 122f, and 122g control clock sources 124a, 124b, 124c, 124d, 124e, 124f, and 124g in hardware, and thus control is provided to the intelligence Clock signals for property blocks 200 and 210.

Clock control circuits 122a, 122b, 122c, 122d, 122e, 122f, and 122g can operate independently to transmit clock requests (REQs) to their parent components or to control clock sources 124a, 124b, 124c, 124d, 124e, 124f , and 124g. In addition, the clock control circuits 122 a , 122 b , 122 c , 122 d , 122 e , 122 f , and 122 g may operate under the control of the clock management unit controller 110 . On the other hand, in an exemplary embodiment of the inventive concept, the clock control circuits 122a, 122b, 122c, 122d, 122e, 122f, and 122g may include finite state machines (FSMs) that The machine controls each of the clock sources 124a, 124b, 124c, 124d, 124e, 124f, and 124g in response to clock requests (REQs) transmitted and received between the parent and child components.

2 and 3 are schematic diagrams of semiconductor devices according to exemplary embodiments of the inventive concept.

2 , in the semiconductor device 1 according to the present embodiment, the intellectual property block 200 and the intellectual property block 210 have a master-slave relationship. In this embodiment, the IP block 200 can be a slave device, and the IP block 210 can be a master device. For example, intellectual property block 210 may include processors, controllers, etc., and intellectual property block 200 may include internal memory devices, external memory interfaces, and the like. The IP block 210 and the IP block 200 may be electrically connected to each other via the bus bar 400 .

In the following, for convenience, the intellectual property block 210 and the intellectual property block 200 will be expressed by the master intellectual property block 210 and the slave intellectual property block 200, respectively.

In an exemplary embodiment of the inventive concept, the type of bus 400 through which the master IP block 210 and the slave IP block 200 can transmit and receive data to and from each other is not particularly limited. It should be noted, however, that a bus to which exemplary embodiments of the present inventive concept may be applied includes, for example, a bus that conforms to a protocol such as the following that does not take into account the operating state of the slave device when the master device and the slave device perform the operation of the bus bar. Row: advanced peripheral bus protocol (APB protocol) and advanced high-performance bus protocol (advanced high-performance bus protocol, AHB protocol). For example, the master IP block 210 may transmit a bus operation signal for data transfer to the slave IP block 200 regardless of whether the slave IP block 200 is currently in a sleep state or a running state.

In an exemplary embodiment of the present inventive concept, the bus operation signals include address signals, data signals, control signals, etc., for the master IP block 210 and the slave IP block 200 to perform bus operation is compulsory. Additionally, the bus operation signal may be provided in various forms depending on the protocol type adopted by the bus 400 . Specific examples thereof will be described later with reference to FIGS. 4 and 9 .

As described above in FIG. 1 , the master IP block 210 and the slave IP block 200 can make clock requests to the clock management unit 100 in a full handshake manner, and can receive clock signals from the clock management unit 100 .

For example, the clock supply request or the clock supply stop request is transmitted from the slave IP block 200 via the channel CH1 formed between the slave IP block 200 and the channel management circuit 130 . Channel management circuit 130 and clock component 120f transmit and receive clock requests (REQ) and acknowledgements (ACK) and control the clock signal ( CLK1 ) provided to slave IP block 200 . As shown in FIG. 1 above, the clock component 120f includes a clock source 124f for generating a clock signal ( CLK1 ), and a clock control circuit 122f for controlling the clock source 124f in hardware.

As in the case of the slave IP block 200 , the master IP block 210 transmits a clock supply request or a clock supply stop request via a channel CH2 formed between the master IP block 210 and the channel management circuit 132 . Clock component 120g and channel management circuit 132 transmit and receive clock requests (REQ) and acknowledgements (ACK) and control the clock signal ( CLK2 ) provided to master IP block 210 . As shown in FIG. 1 above, the clock component 120g includes a clock source 124g for generating the clock signal CLK2, and a clock control circuit 122g for controlling the clock source 124g in hardware.

Subsequently, referring to FIG. 3 , the slave intellectual property block 200 includes a functional unit 202 and an interface unit 204 .

The functional unit 202 controls the original operation of the slave IP block 200 . For example, functional unit 202 corresponds to circuit areas such as internal memory devices and external memory interfaces in which the original functions from IP block 200 are provided.

The interface unit 204 transmits and receives signals to and from the functional unit 202 via the channels 410 and 420 , and provides the signal (eg, the first signal) provided by the autonomous intellectual property block 210 to the functional unit 202 .

The interface unit 204 can receive the operation status signal from the functional unit 202 via the channel 410 . The operational status signal received via channel 410 may include information about the operational status of functional unit 202 . For example, the operation state signal may include information about whether the operation state of the functional unit 202 is a sleep state or a running state.

On the other hand, the interface unit 204 can transmit and receive the second signal to and from the functional unit 202 via the channel 420 . The second signal transmitted and received via the channel 420 includes a signal corresponding to the first signal provided by the autonomous IP block 210 via the bus bar 400 . For example, the second signal may be a signal that transitions from L to H at the second time point to correspond to the first signal that transitions from L to H at the first time point. Here, the second time point may be a time point later than the first time point.

For example, when the IP block 200 is in a sleep state, the first signal provided by the autonomous IP block 210 may change from L to H at the first time point. In this case, after waking up from the IP block 200, the interface unit 204 may include a signal that transitions from L to H at a second time point later than the first time point.

As described above with reference to FIG. 2 , for example, in the event that the bus 400 conforms to the Advanced Peripheral Bus Protocol or the Advanced High Performance Bus Protocol, the master IP block 210 may transmit the bus to the slave IP block 200 Operates the signal regardless of the state of the IP block 200. At this time, if the slave IP block 200 is in a sleep state, the slave IP block 200 may not receive the bus operation signal of the master IP block 210 . In order to avoid this situation, when the main intellectual property block 210 provides the first signal (eg, the bus operation signal), the interface unit 204 can replace the functional unit 202 in the sleep state to receive the first signal at the first time point. a signal. Furthermore, when waking up from the intellectual property block 200, the interface unit 204 may provide the second signal to the functional unit 202, eg, at a second time point. In other words, at the second time point, the interface unit 204 can generate the second signal corresponding to the first signal.

After the autonomous IP block 210 receives the first signal, the interface unit 204 can transmit a clock request to the channel management circuit 130 of the clock management unit 100 to wake up the functional unit 202 of the slave IP block 200 .

As a result, the functional unit 202 can perform the bus operation together with the main IP block 210 according to the second signal received from the interface unit 204 immediately after waking up.

In order to provide such an operation, the functional unit 202 and the interface unit 204 may be driven by different clock signals. The provision of different clock signals may vary according to specific purposes.

FIG. 4 is a schematic diagram illustrating the operation of a semiconductor device according to an exemplary embodiment of the inventive concept.

4 , in the semiconductor device 1 according to the current embodiment, the master IP block 210 and the slave IP block 200 may perform bus operations via a bus 400 conforming to the Advanced Peripheral Bus Protocol. In an exemplary embodiment of the present inventive concept, the master intellectual property block 210 may include an advanced peripheral bus bridge block (APB bridge block) that serves as a , the Advanced High-Performance Bus Protocol) is a medium for data communication with another bus. For this discussion, the functional unit 202 of the intellectual property block 200 will first be assumed to be in a sleep state.

The master IP block 210 can transmit the first signal to the slave IP block 200 to perform bus operation together with the slave IP block 200 . At this time, the main intellectual property block 210 does not consider the operation status of the functional unit 202 . In this embodiment, the first signal transmitted by the master IP block 210 may include signals such as PSEL, PENABLE, PADDR, and PWRITE. Provided in the literature distributed by the company ARM "AMBA ^TM 3 advanced peripheral bus protocol specification v1.0 ^{(AMBA TM 3 APB Protocol v1.0 Specification} ) (ARM IHI 0024B) " the definition and interpretation of these signals, the The full disclosure of the document is incorporated into this case for reference.

The interface unit 204 determines through the channel 410 that the functional unit 202 is currently in a sleep state. When the functional unit 202 is in a sleep state, the interface unit 204 receives the first signal provided by the autonomous intellectual property block 210 .

Next, in order to wake up the functional unit 202 from the IP block 200, the interface unit 204 transmits a clock request to the channel management circuit 130 of the clock management unit 100 via the channel CH1, and can receive an acknowledgement (ACK) from the channel management circuit 130 . The interface unit 204 can check whether the clock signal is provided to the slave IP block 200 by the acknowledgement (ACK) received from the channel management circuit 130 .

After that, the interface unit 204 detects via the channel 410 whether the functional unit 202 has transitioned to the running state. When the functional unit 202 changes to the running state, the interface unit 204 generates a second signal corresponding to the first signal, and provides the generated second signal to the functional unit 202 . Here, the second signal refers to signals such as IP_PSEL, IP_PENABLE, IP_PADDR, and IP_PWRITE. These signals correspond to, for example, PSEL, PENABLE, PADDR, and PWRITE as the first signal.

As a result, after waking up, the functional unit 202 can immediately perform a bus operation conforming to the master IP block 210 and the advanced peripheral bus protocol according to the second signal received from the interface unit 204 .

In addition, the interface unit 204 receives the IP_PREADY signal output from the functional unit 202 of the IP block 200 during the operation of the bus, and can provide the IP_PREADY signal to the main IP block 210 as a PREADY signal conforming to the advanced peripheral bus protocol.

FIG. 5 is a timing chart illustrating the operation of the semiconductor device shown in FIG. 4 according to an exemplary embodiment of the present inventive concept.

Referring to Figure 5, at T1, the functional unit 202 of the slave IP block 200 is in a sleep state.

At T2, the master IP block 210 (eg, the advanced peripheral bus bridging block) begins bus operation while transmitting the PSEL signal to the slave IP block 200, and thereafter, the master IP block 210 at T3 Send the PENABLE signal to the slave IP block 200. The PSEL signal and the PENABLE signal can be provided by the autonomous intellectual property block 210 at a constant clock interval (eg, one clock interval or two clock intervals), and the specific providing content can be determined according to the specific providing purpose.

At T2, upon receiving the PSEL signal of the master IP block 210, the interface unit 204 transmits a clock request to the channel management circuit 130 of the clock management unit 100 via the channel CH1 to wake up the function of the slave IP block 200 unit 202. For example, when the channel CH1 conforms to the Q-channel interface, the interface unit 204 can transmit and receive signals such as QACTIVE, QREQn, and QCCEPTn to and from the channel management circuit 130 . Definitions of these signals can be found in the document "Low Power Interface Specification: ARM Q-Channel and P-Channel Interfaces" (ARM IHI 0068B) distributed by ARM Corporation and explanation, the full disclosure of the document is incorporated into this case for reference.

Around or after T4, the clock PCLK is provided to the functional unit 202 of the slave IP block 200, and the slave IP block 200 performs a wake-up procedure. At this time, the main IP block 210 maintains the PSEL signal and the PENABLE signal equally until the PREADY signal is provided since the IP block 200 .

At or after T5, the interface unit 204 determines that the functional unit 202 wakes up and generates the IP_PSEL signal and the IP_PENABLE signal corresponding to the PSEL signal and the PENABLE signal. The IP_PSEL signal and the IP_PENABLE signal may have the same clock interval (T5 to T6) as the clock interval (T2 to T3) between the PSEL signal and the PENABLE signal. The interface unit 204 also provides the generated IP_PSEL signal and the IP_PENABLE signal to the functional unit 202 .

At or after T6, upon receiving the IP_PSEL signal and the IP_PENABLE signal from the interface unit 204, the functional unit 202 may transmit the PREADY signal to the main IP block 210 via the interface unit 204. For example, the functional unit 202 sends the IP_PREADY signal to the interface unit 204, and the interface unit 204 sends the IP_PREADY signal to the main IP block 210 as the RPEADY signal.

Thereafter, when the bus operation is completed, in order to transfer the functional unit 202 from the IP block 200 to the sleep state, the interface unit 204 may transmit a clock supply stop request to the channel management circuit 130 of the clock management unit 100 via the channel CH1 . As can be seen from T8 to T10, if, for example, the channel CH1 conforms to the Q-channel interface, the interface unit 204 can transmit and receive signals such as QACTIVE, QREQn, and QACCEPTn to and from the channel management circuit 130 .

FIG. 6 is a timing diagram illustrating the operation of the semiconductor device shown in FIG. 4 according to an exemplary embodiment of the present inventive concept.

FIG. 5 illustrates the situation in which the functional unit 202 of the IP block 200 transitions to the sleep state when the bus operation is completed, and FIG. 6 illustrates the situation in which the interface unit 204 further reports to the clock management unit 100 after the bus operation is completed. A scenario where the channel management circuit 130 transmits a clock request (CLKREQ).

For example, at T6, in response to receiving the IP_PSEL signal and the IP_PENABLE signal from the interface unit 204, the functional unit 202 may transmit the PREADY signal to the main IP block 210 via the interface unit 204. For example, the functional unit 202 may transmit the IP_PREADY signal to the interface unit 204, and the interface unit 204 may transmit the IP_PREADY signal to the main IP block 210 as the PREADY signal.

Thereafter, when the bus operation is completed but the slave IP block 200 needs to be operated, the interface unit 204 can autonomously transmit a clock request (CLKREQ) to the channel management circuit 130 of the clock management unit 100 .

Thereafter, when the additional operation is completed, in order to transfer the functional unit 202 of the IP block 200 into a sleep state, the interface unit 204 may transmit the clock supply stop to the channel management circuit 130 of the clock management unit 100 via the channel CH1 ask. As can be seen from T8 to T10, if, for example, the channel CH1 conforms to the Q-channel interface, the interface unit 204 can transmit and receive signals such as QACTIVE, QREQn, and QACCEPTn to and from the channel management circuit 130 .

7 and 8 are schematic diagrams of semiconductor devices according to exemplary embodiments of the inventive concept.

7, in the semiconductor device 1 according to the current embodiment, the intellectual property blocks 200 and 210 and the intellectual property block 220 have a master-slave relationship. In this embodiment, IP blocks 200 and 210 may be slave devices, and IP block 220 may be a master device. The IP block 220 and the IP blocks 200 and 210 can be electrically connected to each other through the bus bar 500 .

In the following, for convenience, the IP block 220 and the IP blocks 200 and 210 will be expressed by the master IP block 220 and the slave IP blocks 200 and 210, respectively.

As described above with reference to FIG. 2 , the type of the busbar 500 is not particularly limited, and the busbar 500 also includes a busbar that conforms to the following agreement: the agreement does not consider when the master device and the slave device perform the busbar operation together (eg, The operating state of the slave device when the bus is operating in the Advanced High Performance Bus Protocol.

Similar to that described with reference to FIG. 1 , the master IP block 220 and the slave IP blocks 200 and 210 make clock requests to the clock management unit 100 and receive clock signals from the clock management unit 100 in a full handshake manner. .

For example, a clock supply request or a clock supply stop request is transmitted from the IP blocks 200 and 210 via the channels CH1 and CH2 formed between the channel management circuits 130 and 132, respectively. Channel management circuits 130 and 132 and clock components 120f and 120g transmit and receive clock requests (REQs) and acknowledgements (ACKs), respectively, and control each of the clock signals (CLK1 and CLK2) to be provided to slaves, respectively. Intellectual Property Blocks 200 and 210. As described above with reference to FIG. 1, clock components 120f and 120g include clock sources 124f and 124g for generating each of clock signals CLK1 and CLK2, and clock sources 124f and 124g, respectively, for controlling in hardware 124g of clock control circuits 122f and 122g.

As in the case of the slave IP blocks 200 and 210, the master IP block 220 transmits a clock supply request or a clock supply stop request via the channel CH3 formed between the master IP block 220 and the channel management circuit 134 . The channel management circuit 134 and the clock component 120h transmit and receive clock requests (REQ) and acknowledgements (ACK), and control the clock signal ( CLK3 ) to be provided to the main IP block 220 . As described with reference to FIG. 7 , the clock component 120h includes a clock source 124h for generating a clock signal ( CLK3 ), and a clock control circuit 122h for controlling the clock source 124h in hardware.

Then, referring to FIG. 8 , the slave intellectual property blocks 200 and 210 respectively include functional units 202 and 212 and interface units 204 and 214 .

Functional units 202 and 212 control the original operation from IP blocks 200 and 210, and interface units 204 and 214 transmit and receive signals to and from functional units 202 and 212 via channels 510, 520, 512, and 522, and will autonomously The first signal provided by the intellectual property block 220 is provided to the functional units 202 and 212 .

Interface units 204 and 214 may receive operational status signals from functional units 202 and 212 via channels 510 and 512, respectively. On the other hand, interface units 204 and 214 can transmit and receive second signals to and from functional units 202 and 212 via channels 520 and 522, respectively. Since the description of the first signal and the second signal is repeated with the description provided with reference to FIG. 3 , they are not repeated here.

When the master IP block 220 provides the first signal, the interface units 204 and 214 receive the first signal on behalf of the functional units 202 and 212 in the sleep state at the first time point. When waking up from the IP blocks 200 and 210 , the interface units 204 and 214 can provide the second signal to the functional units 202 and 212 at the second time point. In other words, at the second time point, the interface units 204 and 214 can generate the second signal corresponding to the first signal.

In addition, after the autonomous intellectual property block 220 receives the first signal, in order to wake up the functional units 202 and 212 from the intellectual property blocks 200 and 210 , the interface units 204 and 214 may report to the channel management circuit 130 of the clock management unit 100 and 132 transmit clock request.

As a result, the functional units 202 and 212 can perform bus operation together with the main IP block 220 immediately after waking up according to the second signal received from the interface units 204 and 214 .

FIG. 9 is a schematic diagram illustrating an operation of a semiconductor device according to an exemplary embodiment of the inventive concept.

9 , in the semiconductor device 1 according to the current embodiment, the master IP block 220 and the slave IP block 200 may perform bus operations via a bus 400 conforming to the Advanced High Performance Bus Protocol. Here, first, the functional unit 202 of the intellectual property block 200 is assumed to be in a sleep state.

The master IP block 220 can transmit the first signal to the slave IP block 200 to perform bus operation together with the slave IP block 200 . At this time, the main intellectual property block 220 does not consider the operation status of the functional unit 202 . In this embodiment, the first signal transmitted by the main IP block 220 may include signals such as HADDR, HWDATA, and HTRANS. In addition, the decoder DEC can receive the input of the HADDR signal and provide the HSEL1 signal to the slave IP block 200 . The decoder DEC can also provide the SEL signal to the multiplexing circuit MUX. For convenience, the HSEL1 signal will also be expressed by the first signal. In distributed by the company ARM "AMBA ^TM 3 lightweight advanced high-performance bus protocol specification v1.0 ^{(AMBA TM 3 AHB-Lite Protocol} v1.0 Specification) (ARM IHI 0033A) " can be found in the literature of these signals Definitions and explanations, the disclosures of the documents are incorporated into this case by reference in their entirety.

The interface unit 204 determines through the channel 510 that the functional unit 202 is currently in a sleep state. When the functional unit 202 is in the sleep state, the interface unit 204 receives the first signal provided by the autonomous intellectual property block 220 .

Next, in order to wake up the functional unit 202 from the IP block 200, the interface unit 204 transmits a clock request to the channel management circuit 130 of the clock management unit 100 via the channel CH1, and can receive an acknowledgement (ACK) from the channel management circuit 130 . The interface unit 204 can check whether the clock signal is provided to the slave IP block 200 by the acknowledgement (ACK) received from the channel management circuit 130 .

After that, the interface unit 204 detects through the channel 510 whether the functional unit 202 has transitioned to the running state. If the functional unit 202 changes to the running state, the interface unit 204 generates a second signal corresponding to the first signal, and provides the generated second signal to the functional unit 202 . Here, the second signal refers to signals such as IP_HADDR, IP_HWDATA, IP_HTRANS, and IP_HSEL1. The signals respectively correspond to signals such as HADDR, HWDATA, HTRANS, and HSEL1 as the first signal.

As a result, after waking up, the functional unit 202 immediately executes the bus operation conforming to the master IP block 220 and the advanced high performance bus protocol in response to the second signal received from the interface unit 204 .

On the other hand, during the operation of the bus, the interface unit 204 receives the IP_HRDATA1 signal and the IP_HREADYOUT1 signal output from the functional unit 202 of the intellectual property block 200, and can use the IP_HRDATA1 signal and the IP_HREADYOUT1 signal as an advanced-compliant signal through the multiplexing circuit (MUX). The HRDATA1 signal and the HREADYOUT1 signal of the peripheral bus protocol are provided to the main intellectual property block 220 as the HRDATA signal and the HREADY signal.

The above disclosure can be similarly applied to achieve the interaction between the master IP block 220 and the slave IP block 210 .

FIG. 10 is a timing chart illustrating the operation of the semiconductor device shown in FIG. 9 according to an exemplary embodiment of the present inventive concept.

Referring to Figure 10, at T1, the functional unit 202 of the slave IP block 200 is in a sleep state.

At T2, the decoder DEC and master IP block 220 begin bus operation while transmitting HSEL and HTRANS to the slave IP block 200.

At or after T2, in response to receiving the HSEL signal and the HTRANS signal of the decoder DEC and the master IP block 220, the interface unit 204 transmits a clock request to the channel management circuit 130 of the clock management unit 100 via the channel CH1 , to wake up functional unit 202 from IP block 200 . For example, when the channel CH1 conforms to the Q-channel interface, the interface unit 204 can transmit and receive signals such as QACTIVE, QREQn, and QCCEPTn to and from the channel management circuit 130 .

The main IP block 220 stores the HSEL signal and the HTRANS signal between T2 and T3. After a clock (eg, slave clock) is provided to the functional unit 202 of the slave IP block 200 during T4, the stored HSEL and HTRANS signals are regenerated into IP_HSEL and IP_HTRANS signals at T5. When a clock (eg, a slave clock) is provided to the functional unit 202 of the slave IP block 200, the slave IP block 200 performs a wake-up procedure.

At T5, upon asserting that the functional unit 202 is awake, the interface unit 204 generates the IP_HSEL signal and the IP_HTRANS signal corresponding to the HSEL signal and the HTRANS signal. The interface unit 204 also provides the generated IP_HSEL signal and IP_HTRANS signal to the functional unit 202 .

At or after T6, upon receiving the IP_HSEL signal and the IP_HTRANS signal from the interface unit 204, the functional unit 202 may transmit the HREADYOUT signal to the multiplexer (MXU) via the interface unit 204, and the multiplexer (MUX) may transmit the HREADYOUT signal to the main The intellectual property block 220 transmits the HREADY signal. For example, the functional unit 202 transmits the IP_HREADYOUT signal corresponding to the HREADYOUT signal to the interface unit 204, and the interface unit 204 may transmit the IP_HREADYOUT signal to the multiplexer (MUX) as the HREADYOUT signal.

Thereafter, when the bus operation is completed, in order to transfer the functional unit 202 from the IP block 200 to the sleep state, the interface unit 204 may transmit a clock supply stop request to the channel management circuit 130 of the clock management unit 100 via the channel CH1 . As can be seen from T8 to T10, for example, if the channel CH1 conforms to the Q channel interface, the interface unit 204 can transmit and receive signals such as QACTIVE, QREQn, and QACCEPTn to and from the channel management circuit 130.

FIG. 11 is a flowchart of a method of operating a semiconductor device according to an exemplary embodiment of the present inventive concept.

3 and 11 , the method of operating a semiconductor device according to the present embodiment includes the following steps.

The interface unit 204 receives the first signal from the IP block 220 ( S1101 ) and transmits the clock request for waking up the function unit 202 of the slave IP block 200 to the clock management unit 100 ( S1103 ).

After receiving the clock signal from the clock management unit 100 from the IP block 200 , in other words, after the interface unit 204 receives an acknowledgement (ACK) corresponding to the clock request from the clock management unit 100 ( S1105 ), the interface The unit 204 generates a second signal corresponding to the first signal (S1107).

After that, the interface unit 204 provides the generated second signal to the functional unit 202 ( S1109 ), so that after the functional unit 202 in the sleep state wakes up, the functional unit 202 can immediately respond to the second signal received from the interface unit 204 The bus operation is performed in conjunction with the main IP block 220.

12 is a block diagram of a semiconductor device and a semiconductor system to which a method of operating the same according to an exemplary embodiment of the present inventive concept can be applied.

12 , a semiconductor device to which a semiconductor device and a method of operating the same according to an exemplary embodiment of the present inventive concept can be applied includes a semiconductor device (system on chip) 1 , a processor 10 , a memory device 20 , and a display device 30 , network device 40 , storage device 50 , and input/output device 60 . The semiconductor device (system chip) 1 , the processor 10 , the memory device 20 , the display device 30 , the network device 40 , the storage device 50 , and the input/output device 60 can transmit and receive data to and from each other via the bus bar 70 .

The intellectual property block within the semiconductor device (system chip) 1 described in the exemplary embodiment of the present inventive concept includes at least one of the following: a memory controller, which controls the memory device 20; and a display controller, which controls the display The device 30; the network controller, which controls the network device 40; the storage controller, which controls the storage device 50; and the input/output controller, which controls the input/output device 60. Additionally, the semiconductor system may further include additional processors that control the devices.

FIGS. 13 to 15 are a semiconductor device and a semiconductor system to which a method of operating the same according to exemplary embodiments of the inventive concept can be applied.

FIG. 13 is a diagram illustrating a tablet PC 1200 , FIG. 14 is a diagram illustrating a laptop computer 1300 , and FIG. 15 illustrates a smartphone 1400 . The semiconductor device according to the exemplary embodiment of the present inventive concept may be used in a tablet personal computer 1200, a laptop computer 1300, a smart phone 1400, and the like.

It should be understood that the semiconductor device according to the exemplary embodiments of the present inventive concept may also be applied to other integrated circuit devices not shown in the drawings.

For example, although only the tablet personal computer 1200 , the laptop computer 1300 , and the smart phone 1400 are described above as application examples of the semiconductor system of the present invention, the semiconductor system of the present invention is not limited thereto.

In an exemplary embodiment of the inventive concept, the semiconductor system may be a computer, an ultra mobile personal computer (UMPC), a workstation, a net-book, a personal digital assistant (personal digital assistant) digital assistant, PDA), portable computer, wireless phone, mobile phone, e-book, portable multimedia player (PMP), portable game console, navigation device, black box (black box), digital cameras, 3D TVs, digital audio recorders, digital audio players, digital picture recorders, digital picture players, digital video recorders, digital video players, etc.

Exemplary embodiments of the inventive concept provide a semiconductor device for performing bus operation in a master-slave relationship of a system in which clock signals are controlled by hardware.

Exemplary embodiments of the inventive concept provide a semiconductor system for performing bus operation in a master-slave relationship of a system in which clock signals are controlled by hardware.

Exemplary embodiments of the inventive concept provide a method for operating a semiconductor device for performing bus operation in a master-slave relationship of a system in which clock signals are controlled by hardware.

While the inventive concept has been specifically described and described with reference to exemplary embodiments of the inventive concept, those of ordinary skill in the art will understand that the inventive concept is not deviated from the spirit and scope of the inventive concept as defined by the following claims Under the conditions, various changes in form and details can be made.

1‧‧‧Semiconductor device 10‧‧‧Processor 20‧‧‧Memory device 30‧‧‧Display device 40‧‧‧Network device 50‧‧‧Storage device 60‧‧‧Input/output device 70, 400 , 500‧‧‧bus bar 100‧‧‧clock management unit 110‧‧‧clock management unit controller 120a‧‧‧clock component/first clock component 120b, 120c, 120d, 120e, 120f, 120g, 120h‧‧‧Clock components 122a, 122b, 122c, 122d, 122e, 122f, 122g, 122h‧‧‧Clock control circuit 124a, 124b, 124c, 124d, 124e, 124f, 124g, 124h‧‧‧ clock source 130, 132, 134‧‧‧Channel management circuit 200‧‧‧IP block/slave IP block 202, 212‧‧‧functional unit 204, 214‧‧‧interface unit 210‧‧‧IP block/ Master IP block/Slave IP block 220‧‧‧IP block/Master IP block 300‧‧‧Power management unit 410, 420, 510, 512, 520, 522, CH1, CH2, CH3‧ ‧‧Channel 1200‧‧‧Tablet PC 1300‧‧‧Laptop 1400‧‧‧Smartphone S1101, S1103, S1105, S1107, S1109‧‧‧Step ACK‧‧‧Confirm CH‧‧‧Communication channel CLK , CLK3‧‧‧clock signal CLK1‧‧‧clock signal/first clock signal CLK2‧‧‧clock signal/second clock signal CLKREQ‧‧‧clock request DEC‧‧‧decoder HADDR, HRDATA , HRDATA1, HRDATA2, HREADY, HREADYOUT, HREADYOUT1, HREADYOUT2, HSEL, HSEL1, HSEL2, HTRANS, HWDATA, IP_PADDR, IP_PENABLE, IP_PSEL, IP_PWRITE, IP_PREADY, IP_HADDR1, IP_HADDR2, IP_HRDATA1, IP_HRDATA2, IP_HREADYOUT, IP_HREADYOUT1, IP_HREADYOUT2, IP_HREADYOUT1, IP_HREADYOUT2 , IP_HSEL2, IP_HTRANS, IP_HWDATA1, IP_HWDATA2, PADDR, PENABLE, PSEL, PWRITE, PREADY, QACCEPTn, QACTIVE, QREQn, SEL‧‧‧Signal MUX‧‧‧Multiplexer circuit OSC‧‧‧Oscillator PCLK‧‧‧clock PLL ‧‧‧Phase-locked loop REQ‧‧‧clock request T1, T2, T3, T4, T5, T6, T7, T8, T9, T10‧‧‧ time points

The above and other features of the inventive concept will become more apparent by explaining in detail exemplary embodiments of the inventive concept with reference to the accompanying drawings, in which:

FIG. 1 is a schematic diagram of a semiconductor device according to an exemplary embodiment of the inventive concept. 2 and 3 are schematic diagrams of semiconductor devices according to exemplary embodiments of the inventive concept. FIG. 4 is a schematic diagram illustrating an operation of a semiconductor device according to an exemplary embodiment of the inventive concept. FIG. 5 is a timing chart illustrating the operation of the semiconductor device shown in FIG. 4 according to an exemplary embodiment of the present inventive concept. FIG. 6 is a timing chart illustrating the operation of the semiconductor device shown in FIG. 4 according to an exemplary embodiment of the present inventive concept. 7 and 8 are schematic diagrams illustrating semiconductor devices according to exemplary embodiments of the inventive concept. FIG. 9 is a schematic diagram illustrating an operation of a semiconductor device according to an exemplary embodiment of the inventive concept. FIG. 10 is a timing chart illustrating the operation of the semiconductor device shown in FIG. 9 according to an exemplary embodiment of the present inventive concept. FIG. 11 is a flowchart of a method of operating a semiconductor device according to an exemplary embodiment of the present inventive concept. 12 is a block diagram of a semiconductor device and a semiconductor system to which a method of operating the same according to an exemplary embodiment of the present inventive concept can be applied. FIGS. 13 , 14 , and 15 are a semiconductor device and a semiconductor system to which a method of operating the same according to an exemplary embodiment of the present inventive concept can be applied.

1‧‧‧Semiconductor device

100‧‧‧Clock Management Unit

110‧‧‧Clock Management Unit Controller

120a‧‧‧Clock Component/First Clock Component

120b, 120c, 120d, 120e, 120f, 120g‧‧‧ clock components

122a, 122b, 122c, 122d, 122e, 122f, 122g‧‧‧ clock control circuit

124a, 124b, 124c, 124d, 124e, 124f, 124g‧‧‧ clock source

130, 132‧‧‧Channel management circuit

200‧‧‧Intellectual Property Block/From Intellectual Property Block

210‧‧‧IP Block/Master IP Block/Slave IP Block

300‧‧‧Power Management Unit

ACK‧‧‧Confirmation

CH‧‧‧communication channel

CLK‧‧‧clock signal

CLK1‧‧‧clock signal/first clock signal

CLK2‧‧‧clock signal/second clock signal

OSC‧‧‧Oscillator

PLL‧‧‧Phase Locked Loop

REQ‧‧‧clock request

Claims (20)

A semiconductor device, comprising: a first intellectual property block (IP block), including a functional unit and an interface unit; a first clock control circuit for controlling a first clock source; a second clock control circuit for reporting to the first clock A clock control circuit transmits a first clock request, controls a second clock source, the second clock receives a clock signal from the first clock source, and directly provides the clock signal to the a first intellectual property block; and a channel management circuit configured to transmit a second clock request to the second clock control circuit in response to a clock stop request received from the first intellectual property block; wherein In response to the clock stop request from the first IP block, the second clock control circuit disables the second clock source and transmits to the first clock control circuit as the The clock of the first clock source provides a request to stop, wherein the functional unit controls the operation of the first intellectual property block, and the interface unit receives the request from a clock electrically connected to the first intellectual property block. The second intellectual property block provides the first signal and provides the first signal to the functional unit. The semiconductor device of claim 1, wherein the interface unit receives information about an operation state of the functional unit of the first intellectual property block, and the operation state includes a sleep state or an operation state . The semiconductor device of claim 1, wherein when the functional unit of the first intellectual property block is in a sleep state, the interface unit receives the data provided by the second intellectual property block. the first signal. The semiconductor device of claim 3, wherein the interface unit transmits the clock stop request to the channel management circuit after receiving the first signal. The semiconductor device of claim 3, wherein after the functional unit of the first intellectual property block wakes up, the interface unit generates a second signal corresponding to the first signal. The semiconductor device of claim 5, wherein after the functional unit of the first intellectual property block wakes up, the interface unit provides the second signal to the functional unit. The semiconductor device of claim 1, wherein the first IP block is a slave device, and the second IP block is a master device. The semiconductor device of claim 1, wherein the first signal includes a bus operation signal. The semiconductor device of claim 8, wherein the bus operation signal includes an address signal, a data signal, or a control signal. The semiconductor device of claim 8, wherein after receiving the first signal from the interface unit, the functional unit of the first intellectual property block and the second intellectual property area Blocks together perform bus operations. A semiconductor device, comprising: a master intellectual property (IP) block, which operates in response to a first clock signal provided from a clock management unit (CMU); and a slave intellectual property block, including a functional unit and an interface unit, the functional unit The interface unit is configured to receive the bus operation signal from the master intellectual property block at a first time point and to operate with the second clock signal provided by the clock management unit The bus operation signal is provided to the functional unit at different second time points, and the clock management unit includes a first clock source for providing the first clock signal, and for providing the second clock a second clock source for signals, and a third clock source for providing a third clock signal to the first clock source and the second clock source, the first clock source being controlled in a first clock control circuit, wherein the first clock signal and the second clock signal are based on the third clock signal, wherein the clock stop request is responsive to the slave IP block , the second clock control circuit disables the second clock source and transmits a clock supply stop request to the third clock control circuit that controls the third clock source. The semiconductor device of claim 11, wherein the interface unit receives information about an operation state of the functional unit, and the operation state includes a sleep state or an operation state. The semiconductor device of claim 11, wherein when the functional unit is in the sleep state, the interface unit receives the bus operation signal from the main intellectual property block. The semiconductor device according to claim 13, wherein the self- After the main intellectual property block receives the bus operation signal, the interface unit transmits a clock request to the clock management unit. The semiconductor device of claim 13, wherein at the second time point when the functional unit wakes up, the interface unit provides the bus operation signal to the functional unit. The semiconductor device of claim 15, wherein after receiving the bus operation signal from the interface unit, the functional unit performs the bus operation together with the main intellectual property block. The semiconductor device of claim 11, wherein the bus operation signal includes an address signal, a data signal, or a control signal. The semiconductor device of claim 11, wherein the master IP block and the slave IP block are in accordance with the Advanced Peripheral Bus Protocol (APB Protocol) or the Advanced High Performance Bus Protocol (AHB Protocol) to transmit and receive data. The semiconductor device of claim 18, wherein the main intellectual property block comprises an advanced peripheral bus bridging block. A semiconductor system, comprising: a system chip (SoC), including: a first intellectual property block (IP block), including a functional unit and an interface unit; a second intellectual property block, electrically connected to the first intellectual property block; a first clock control circuit that controls a first clock source; a second clock control circuit that transmits the first clock to the first clock control circuit a pulse request to control a second clock source, the second clock source receives a clock signal from the first clock source, and directly provides the clock signal to the first intellectual property block; and a channel a management circuit, in response to a clock stop request received from the first intellectual property block, sending a second clock request to the second clock control circuit; one or more external devices electrically connected to the a system chip, wherein in response to the clock stop request from the first IP block, the second clock control circuit disables the second clock source and sends the first clock control circuit to the transmitting a request to stop the clock supply as the first clock source, wherein the functional unit controls the operation of the first intellectual property block, and the interface unit receives the clock provided from the second intellectual property block and provide the first signal to the functional unit.

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