TWI771301B - Semiconductor device and semiconductor system - Google Patents

Abstract

A semiconductor device and a semiconductor system are provided. The semiconductor device includes a first control circuit controlling a first child clock source to receive a clock signal from a parent clock source, a first channel management (CM) circuit transmitting a first clock request to the first control circuit in response to a first clock request received from a first IP block, a second control circuit controlling a second child clock source to receive the clock signal from the parent clock source, a second CM circuit transmitting a second clock request to the second control circuit in response to a second IP clock request received from a second IP block, and a power management unit transmitting a power control command to the first CM circuit and the second CM circuit to control a power state of the first IP block and the second IP block. The first CM circuit and the second CM circuit exchange signals to maintain a master-slave relationship.

Description

Semiconductor devices and semiconductor systems

The present invention relates to a semiconductor device, a semiconductor system, and a method of operating a semiconductor device.

A System-on-Chip (SOC) may contain one or more intellectual property blocks (IP blocks), clock management units (CMUs) and power management units (PMUs) ). The clock management unit provides clock signals to one or more of the IP blocks. In addition, the clock management unit stops supplying clock signals to IP blocks that are no longer executed, thereby making it possible to reduce unnecessary waste of resources in a system using the SoC.

At least one exemplary embodiment of the present invention provides a semiconductor device that performs power management using a master-slave relationship in which clock signal control is managed by hardware.

At least one embodiment of the present invention provides a semiconductor system that performs power management using a master-slave relationship in which clock signal control is managed by hardware.

At least one embodiment of the present invention provides a method of operating a semiconductor device that performs power management using a master-slave relationship in which clock signal control is managed by hardware.

According to an exemplary embodiment of the present invention, a semiconductor device includes a first clock control circuit, a first channel management circuit, a second clock control circuit, a second channel management circuit, and a power management unit (PMU). The PMU can be implemented in a circuit. The first clock control circuit controls the first child clock source to receive a clock signal from the parent clock source. The first channel management circuit transmits the first clock request to the first clock control circuit in response to the first IP block clock request received from the first intellectual property (IP) block. The second clock control circuit controls the second child clock source to receive the clock signal from the parent clock source. The second channel management circuit transmits the second clock request to the second clock control circuit in response to the second IP block clock request received from the second IP block. The power management unit transmits power control commands to the first channel management circuit and the second channel management circuit to control the power states of the first IP block and the second IP block. The first channel management circuit transmits the third clock request to the second channel management circuit, and the second channel management circuit transmits an acknowledgement of receipt of the third clock request to the first channel management circuit to maintain the master-slave relationship.

According to an exemplary embodiment of the present invention, there is provided a semiconductor device including a first channel management circuit, a second channel management circuit, and a power management unit. The first channel management circuit provides the clock signal to the first intellectual property block (IP block). The second channel management circuit receives the clock request from the first channel management circuit and provides the clock signal to the second IP block according to the clock request. A power management unit (PMU) transmits power control commands to the first channel management circuit and the second channel management circuit to control the power states of the first IP block and the second IP block.

According to an exemplary embodiment of the present invention, there is provided a system-on-chip (SoC) including the above-described semiconductor device, a first IP block, and a second IP block. The SoC may further include external devices (eg, memory devices, display devices, network devices, storage devices, and input/output devices), where the SoC controls the external devices.

According to an exemplary embodiment of the present invention, there is provided a method of operating a semiconductor device, the method comprising: a first clock management circuit transmitting a clock request to a second channel management circuit, the first clock management circuit providing a clock signal to the first IP block (IP block); the second clock management circuit provides the clock signal to the second IP block based on the clock request; the second channel management circuit transmits an acknowledgement of receipt of the clock request to the first channel a management circuit; and a second clock management circuit controls a power state of the second IP block based on a power control command received from a power management unit (PMU) circuit.

In order to make the above-mentioned features and advantages of the present invention more obvious and easy to understand, the following embodiments are given and described in detail with the accompanying drawings as follows.

FIG. 1 is a schematic diagram illustrating a semiconductor device according to an exemplary embodiment of the present invention.

Referring to FIG. 1 , a semiconductor device 1 according to an exemplary embodiment of the present invention includes a clock management unit (CMU) 100 , intellectual property blocks (IP blocks) 200 ( IP1 ) and 210 ( IP2 ), and a power management unit (PMU) 300. The CMU can be implemented in a circuit. In the exemplary embodiment, the semiconductor device 1 is implemented as a system-on-chip (SoC), but the scope of the present invention is not limited thereto.

The clock management unit 100 provides clock signals to the IP blocks 200 and 210 . Although the embodiment depicted in Figure 1 shows two IP blocks, the invention is not so limited. For example, in alternate embodiments, there may be additional IP blocks or only a single IP block. In this embodiment, the clock management unit 100 includes clock elements 120a , 120b , 120c , 120d , 120e , 120f and 120g , channel management circuits 130 and 132 , and a clock management unit controller (CMU controller) 110 . Clock elements 120a, 120b, 120c, 120d, 120e, 120f, and 120g generate clock signals to be provided to IP blocks 200 and 210, and channel management circuits 130 and 132 are disposed between clock elements 120f and 120g and IP blocks 200 and 210. 210 to provide a communication channel CH between the clock management unit 100 and the IP blocks 200 and 210 . In addition, the clock management unit controller 110 provides clock signals to the IP blocks 200 and 210 using the clock elements 120a, 120b, 120c, 120d, 120e, 120f and 120g.

In one embodiment, the clock element 120a is implemented by a phase-locked loop (PLL) controller. In one embodiment, the PLL controller receives a constant frequency signal or a variable frequency signal oscillated by the oscillator OSC and a PLL signal output by the PLL from the oscillator OSC, and outputs one of the two received signals based on a certain condition One. When the element requires a PLL signal, the PLL controller outputs the PLL signal. When the element needs an oscillator signal, the PLL controller outputs the oscillator signal. For example, the PLL controller may be implemented using a ring oscillator or a crystal oscillator. In one embodiment, clock element 120b is a clock multiplexer unit that receives a first clock signal CLK1 from first clock element 120a and a second clock signal CLK2 from an external source (eg, an external CMU) .

In an exemplary embodiment of the present invention, the communication channel CH provided by the channel management circuits 130 and 132 is provided to conform to ARM's Low Power Interface (LPI), Q-channel interface (ARC) or P-channel interface, However, the scope of the present invention is not limited to this. For example, a communication channel CH may be provided that conforms to any communication protocol defined according to various purposes.

Clock elements 120a, 120b, 120c, 120d, 120e, 120f, and 120g each contain clock sources 124a, 124b, 124c, 124d, 124e, 124f, and 124g, and control clock sources 124a, 124b, 124c, 124d Clock control circuits (CC) 122a, 122b, 122c, 122d, 122e, 122f and 122g of each of , 124e, 124f and 124g. Clock control sources (CS) 124a, 124b, 124c, 124d, 124e, 124f, and 124g, for example, may include multiplexing circuits (MUX circuits), clock division circuits, shorter stop circuits, or clock Pulse gating circuit. The MUX circuit can be used to receive multiple clock signals as input and select one of the received clock signals as output. A clock division circuit may be used to divide the input clock signal by value to generate a divided clock signal. The value as an instance can be an integer. The clock division circuit can be used to change the frequency of the input clock signal. In one embodiment, the short-circuit stop circuit temporarily sets the clock signal to one logical level (eg, a generally lower level). For example, the clock signal output by the short-circuit stop circuit will include a first period with pulses from the input clock signal, a second period with no pulses (eg, a constant lower level), and then with pulses from the input clock signal The third period of the pulse of the signal. The length of the second period may vary based on the application.

The clock elements 120a, 120b, 120c, 120d, 120e, 120f, and 120g form a parent-child relationship with each other. In this embodiment, clock element 120a is a parent of clock element 120b, and clock element 120b is a child of clock element 120a and a parent of clock element 120c. Also, clock element 120e is the parent of two clock elements 120f and 120g, and clock elements 120f and 120g are children of clock element 120e. The clock element 120a positioned closest to the phase locked loop (PLL) may be referred to as the root clock element, and the clock elements 120f and 120g positioned closest to the IP blocks 200 and 210 may be referred to as leaf clock elements . Such parent-child relationships must also be formed between clock control circuits 122a, 122b, 122c, 122d, 122e, 122f, and 122g based on parent-child relationships between clock elements 120a, 120b, 120c, 120d, 120e, 120f, and 120g, and Formed between clock sources 124a, 124b, 124c, 124d, 124e, 124f and 124g.

Clock control circuits 122b, 122c, 122d, 122e, 122f, and 122g transmit clock request (REQ) signals to the parental clock control circuits. Clock control circuits 122a, 122b, 122c, and 122d receive REQ signals from the child clock control circuits. The clock control circuit 122e receives the REQ signal from each of the two descendant clock control circuits (ie, the clock control circuit 122f and the clock control circuit 122g). Clock control circuits 122f and 122g receive REQ signals from channel management circuits 130 and 132, respectively. Clock control circuits 122a, 122b, 122c, and 122d transmit acknowledgement (ACK) signals to the sub-generation clock control circuits. Clock control circuits 122b, 122c, 122d, and 122e receive the ACK signal from the parental clock control circuit. The clock control circuit 122e transmits the first ACK signal to the clock control circuit 122f, and transmits the second ACK signal to the clock control circuit 122g. The clock control circuit 122f and the clock control circuit 122g transmit the ACK signal to the channel management circuits 130 and 132, respectively. Clock sources 124a , 124b , 124c , 124d , 124e , 124f and 124g provide clock signals to IP blocks 200 and 210 .

For example, if the IP block 200 does not need a clock signal (eg, if the IP block 200 needs to be in a sleep state), the clock management unit 100 stops providing the clock signal to the IP block 200 .

In an exemplary embodiment, the channel management circuit 130 transmits a first signal to the IP block 200 under the control of the clock management unit 100 or the clock management unit controller 110, which instructs to stop providing the clock signal to the IP block 200 . After receiving the first signal, the IP block 200 transmits a second signal to the channel management circuit 130, which indicates that the clock signal can be stopped immediately or after a certain event. For example, the second signal may indicate that the clock signal may be stopped after work (eg, commands, routines, etc.) processed by the IP block 200 is completed. After receiving the second signal from the IP block 200, the channel management circuit 130 requests the clock element 120f corresponding to its parent to stop providing the clock signal. For example, channel management circuit 130 may make this request by sending a REQ signal to clock element 120f.

As an example, if the communication channel CH provided by the channel management circuit 130 conforms to the Q-channel interface, then the channel management circuit 130 treats the QREQn signal having a first logic value (eg, logic low, hereinafter indicated by L) as the first signal Transfer to IP block 200. Afterwards, the channel management circuit 130 receives the QACCEPTn signal having, for example, the first logic value from the IP block 200 as the second signal, and then transmits, for example, the clock request (REQ) having the first logic value to the clock element 120f. In this case, the clock request (REQ) having the first logic value refers to a "clock supply stop request".

After receiving a clock request (REQ) having a first logic value from the channel management circuit 130 (eg, a clock supply stop request), the clock control circuit 122f disables the clock source 124f (eg, a clock gating circuit ) to stop the supply of the clock signal, and thus the IP block 200 can enter the sleep mode. During this process, the clock control circuit 122f may provide the channel management circuit 130 with an ACK signal having a first logic value. It should be noted that although the channel management circuit 130 receives the ACK signal with the first logic value after transmitting the clock supply stop request with the first logic value, it does not ensure that the clock supply is stopped from the clock source 124f. However, the above-mentioned ACK signal means that the clock control circuit 122f recognizes that the clock element 120f, which is the parent of the channel management circuit 130, does not need to additionally provide a clock signal to the channel management circuit 130.

In the exemplary embodiment, clock control circuit 122f of clock element 120f transmits a clock request (REQ) having a first logic value to clock control circuit 122e of clock element 120e corresponding to its parent. If the clock signal is also not required by IP block 210 (eg, when clock control circuit 122e receives a clock stop request from clock control circuit 122g), then clock control circuit 122e disables clock source 124e (eg, when clock pulse division circuit) to stop the supply of the clock signal. Therefore, IP blocks 200 and 210 can enter sleep mode. For example, in this embodiment, clock source 124f does not stop supplying clock signals until it receives an ACK signal with a first logic value from both child clock control circuits 122f and 122g.

Such operations may similarly be performed on the other clock control circuits 122a, 122b, 122c, and 122d.

In the exemplary embodiment, although clock control circuit 122f of clock element 120f transmits a clock request (REQ) signal having a first logic value to the clock control circuit of clock element 120e corresponding to its parent 122e, but the clock control circuit 122e does not disable the clock source 124e if the IP block 210 is in the run state. Afterwards, only when the IP block 210 no longer needs the clock signal, the clock control circuit 122e deactivates the clock source 124e and transmits a clock request (REQ) with the first logic value to the corresponding to its parent The clock control circuit 120d. That is, only when receiving a clock supply stop request from both the clock control circuits 122f and 122g corresponding to the children, the clock control circuit 122e disables the clock source 124e.

In an exemplary embodiment, when all clock sources 124a, 124b, 124c, 124d, 124e, and 124f are disabled during the sleep state of IP blocks 200 and 210 and then IP block 200 enters the run state, clock management unit 100 Resume provides clock signals to IP blocks 200 and 210 .

Channel management circuit 130 transmits a clock request (REQ) signal having a second logic value (eg, logic high, hereinafter indicated by H) to clock control circuit 122f corresponding to its parent's clock element 120f, And wait for an acknowledgement (ACK) from the clock control circuit 122f. Here, the clock request (REQ) having the second logic value is referred to as a "clock supply request", and an acknowledgement (ACK) signal of the clock supply request means that the clock supply has been restored from the clock source 124f. In one embodiment, the clock control circuit 122f does not immediately enable the clock source 124f (eg, a clock gating circuit) and waits for the supply of a clock signal from the parent. In one embodiment, clock control circuit 122f waits until it receives an ACK signal from the parent before enabling clock source 124f.

Next, the clock control circuit 122f transmits a clock request (REQ) having a second logic value (eg, a clock supply request) to the clock control circuit 122e corresponding to its parent, and waits for a signal from the clock control Acknowledgement (ACK) of circuit 122e. Such operations may similarly be performed on clock control circuits 122a, 122b, 122c, and 122d.

Clock control circuit 122a enables clock source 124a (eg, a multiplexer circuit) and transmits an acknowledgement (ACK) signal to clock control circuit 122b that has received from clock control circuit 122b with The root clock element of the clock request (REQ) of the second logic value. When the clock sources 124b, 124c, 124d, 124d, and 124e are sequentially enabled in this manner, the clock control circuit 122e transmits an acknowledgement (ACK) signal to the clock control circuit indicating that the clock supply has been restored from the clock source 124e 122f.

After receiving the acknowledgement (ACK) signal, the clock control circuit 122f enables the clock source 124f, provides the clock signal to the IP block 200, and provides the acknowledgement (ACK) signal to the channel management circuit 130.

In this manner, clock control circuits 122a, 122b, 122c, 122d, 122e, 122f, and 122g execute a full handshake (eg, synchronous handshake). Thus, clock control circuits 122a, 122b, 122c, 122d, 122e, 122f, and 122g control clock sources 124a, 124b, 124c, 124d, 124e, 124f, and 124g in hardware, and control is provided to IP blocks 200 and 210 clock signal.

Clock control circuits 122a, 122b, 122c, 122d, 122e, 122f, and 122g may operate independently to transmit clock request (REQ) signals to parents or to control clock sources 124a, 124b, 124c, 124d, 124e, 124f and 124g, and can operate under the control of the clock management unit controller 110. In an exemplary embodiment of the invention, clock control circuits 122a, 122b, 122c, 122d, 122e, 122f, and 122g comprise finite state machines (FSMs) based on Clock request (REQ) signals exchanged between generations control each of clock sources 124a, 124b, 124c, 124d, 124e, 124f, and 124g.

FIG. 2 is a schematic diagram illustrating a semiconductor device according to an exemplary embodiment of the present invention.

2 , in the semiconductor device 1 according to the embodiment of the present invention, the power management unit 300 transmits a power control command (CMD) to the clock management unit 110 in order to perform power control of the IP blocks 200 and 210 Operates and controls the power states of IP blocks 200 and 210 . In an exemplary embodiment of the present invention, the power control command CMD includes a power down command (D_REQ) to direct the IP blocks 200 and 210 to enter sleep mode. In one embodiment, IP blocks 200 and 210 use less power in sleep mode and more power in normal mode. For example, during sleep mode, the IP block may perform a smaller number of functions than in normal mode.

In an exemplary embodiment of the present invention, IP block 200 and IP block 210 have a master-slave relationship. In one embodiment, IP block 200 is the master device and IP block 210 is the slave device. In this case, IP block 210 (ie, slave) enters sleep mode only when IP block 200 (eg, master) is in sleep mode, and IP block 200 wakes up (eg, exits sleep mode) only after IP block 210 wakes up ). Hereinafter, the operations of the channel management circuit 130 of the IP block 200 and the channel management circuit 132 of the IP block 210 based on such a master-slave relationship will be described in more detail with reference to FIGS. 3 to 5 .

After receiving the power control command CMD from the power management unit 300, the clock management unit controller 110 controls the channel management circuits 130 and 132 based on the power control command CMD, and thereafter the clock management unit controller 110 will acknowledge (ACK) the signal transmitted to the power management unit 300 .

In an exemplary embodiment, the clock management unit controller 110 transmits a power down command (D_REQ) to the channel management circuit 130 responsible for the communication channel with the master IP block 200 and the channel management circuit 130 responsible for the communication channel with the slave IP block 210 circuit 132. After receiving the power down command (D_REQ), channel management circuits 130 and 132 set the value of QREQn to L, which is independent of the value of QACTIVE received from IP blocks 200 and 210 . The channel management circuits 130 and 132 know whether the IP blocks 200 and 210 have entered the sleep mode by checking that the value of QCCEPTn becomes L. In one embodiment, a power down command (D_REQ) has a higher priority than a wakeup command that causes IP blocks 200 and 210 to enter a wakeup mode (ie, leave a sleep mode).

After the channel management circuits 130 and 132 complete operations according to the power down command (D_REQ), only the channel management circuit 130 transmits an acknowledgement (D_ACK) signal of the power down command (D_REQ) to the clock management unit controller 110 .

The channel management circuit 130 responsible for the communication channel with the master IP block 200 and the channel management circuit 132 responsible for the communication channel with the slave IP block 210 exchange clock request (CLK_REQ) signals and acknowledgement (CLK_ACK) signals to form a master-slave relationship.

FIG. 3 is a schematic diagram illustrating an exemplary operation of a semiconductor device according to an exemplary embodiment of the present invention.

Referring to FIG. 3 , the channel management circuits 130 and 132 have a running state (Q_RUN), a sleep mode entry state (Q_CLK_REQ), a sleep state (Q_STOPPED), and a sleep mode exit state (Q_EXIT).

When the idle condition that causes IP blocks 200 and 210 to exit the run state (Q_RUN) is satisfied, the channel management circuits 130 and 132 transition to the sleep mode entry state (Q_CLK_REQ) to set the value of QREQn to L. After that, after checking that the value of QACCEPTn received from the IP blocks 200 and 210 becomes L, the channel management circuits 130 and 132 transition to the sleep state (Q_STOPPED).

Next, when the wake-up condition for waking up the IP blocks 200 and 210 is satisfied, the channel management circuits 130 and 132 transition to the sleep mode exit state (Q_EXIT) to set the value of QREQn to H, and then, after checking the slave IP block 200 After the value of QACCEPTn received by the sum 210 becomes H, the channel management circuits 130 and 132 transition to the running state (Q_RUN).

It should be noted that since the channel management circuit 130 is responsible for the communication channel with the master IP block 200 and the channel management circuit 132 is responsible for the communication channel with the subordinate IP block 210, the channel management circuit 130 and the channel management circuit 132 also have a master-slave relationship. Therefore, the following restrictions may occur.

In an exemplary embodiment, only when the channel management circuit 130 transitions to the sleep state (Q_STOPPED), the channel management circuit 130 provides a signal (CLK_REQ=L) indicating that the supply of the clock signal is to be stopped to the channel management circuit 132 . In one embodiment, the channel management circuit 132 does not transition to the sleep mode entry state (Q_CLK_REQ) when the channel management circuit 130 continuously generates clock requests (CLK_REQ=H) and the idle condition is satisfied. Therefore, in order to transition the channel management circuit 132 into the sleep mode entry state (Q_CLK_REQ), the idle condition for the IP block 210 to enter sleep mode needs to be satisfied, and at the same time, it is necessary to receive from the channel management circuit 130 a signal indicating a stop clock signal signal (CLK_REQ=L). For example, the slave IP block 210 enters sleep mode only when the master IP block 200 is already in sleep mode.

In an exemplary embodiment, channel management circuit 132 sends CLK_ACK=L to channel management circuit 130 after receiving CLK_REQ=L from channel management circuit 130 . In this embodiment, the channel management circuit 132 does not instruct the master IP block 200 to sleep until it receives an acknowledgement from the channel management circuit 132 indicating that the slave IP block 210 has been instructed to sleep (eg, CLK_ACK=L).

In addition, when the channel management circuit 130 in the sleep state (Q_STOPPED) satisfies the wake-up condition, the channel management circuit 130 transmits a clock request (CLK_REQ=H) to the channel management circuit 132 and only receives it from the channel management circuit 132 The channel management circuit 130 transitions to the sleep mode exit state (Q_EXIT) after the acknowledgement (CLK_ACK=H) of the clock request (CLK_REQ=H). When the channel management circuit 132 is in the sleep state (Q_STOPPED), even when the wake-up condition is not satisfied, if a clock request (CLK_REQ=H) is received from the channel management circuit 130, the channel management circuit 132 immediately transitions to sleep mode exit status (Q_EXIT) and transmit an acknowledgment (CLK_ACK=H) to channel management circuit 130 . For example, the master IP block 200 wakes up only after the slave IP block 210 wakes up.

4 is a schematic diagram illustrating an exemplary operation of a semiconductor device according to an exemplary embodiment of the present invention, and FIG. 5 is a schematic diagram illustrating an exemplary operation of a semiconductor device according to an exemplary embodiment of the present invention.

Referring to FIG. 4, in an exemplary embodiment of the present invention, when an IP block contains multiple primary IP blocks and a single subordinate IP block, the first circuit including the channel management circuit 410 responsible for the communication channel with the subordinate IP block is responsible for Multiple clock requests (CLK_REQ1, CLK_REQ2, and CLK_REQ3) are received in channel management circuits 400, 402, and 404 for communication channels with multiple primary IP blocks. For example, the first circuit may include OR gate and channel management circuit 410

In this embodiment, the first circuit receives multiple clock requests (CLK_REQ1, CLK_REQ2, and CLK_REQ3) and performs an OR logic operation on the multiple clock requests (CLK_REQ1, CLK_REQ2, and CLK_REQ3) to generate a single clock request (OR_CLK_REQ) . In other words, the slave IP needs to be woken up when only one of the multiple master IPs generates a clock request. For example, if CLK_REQ1 has a logic H, then even though CLK_REQ2 and CLK_REQ3 are logic L, since they are ORed with each other, the channel management circuit 410 interprets the result as a need to wake up the slave IP.

Referring to FIG. 5, in an exemplary embodiment of the present invention, if an IP block contains a single primary IP block and multiple subordinate IP blocks, then a second circuit containing the channel management circuit 400 responsible for the communication channel with the primary IP block is responsible for the secondary IP block. Multiple acknowledgments (CLK_ACK1, CLK_ACK2, and CLK_ACK3) are received in channel management circuits 410, 412, and 414 of the communication channel with multiple slave IP blocks. For example, the second circuit may include AND gates and channel management circuit 400 .

In this embodiment, the second circuit receives multiple acknowledgments (CLK_ACK1, CLK_ACK2, and CLK_ACK3) and performs AND logic operations on the multiple acknowledgments (CLK_ACK1, CLK_ACK2, and CLK_ACK3) to generate a single acknowledgment (AND_CLK_ACK). For example, wake up the master IP only when all multiple slave IPs are woken up. For example, if any of CLK_ACK1, CLK_ACK2, and CLK_ACK is a logic L, then since they are AND logic with each other, the channel management circuit 410 interprets the result as not needing to wake up the primary IP.

FIG. 6 is a timing diagram illustrating an exemplary operation of a semiconductor device according to an exemplary embodiment of the present invention.

Referring to FIG. 6 , the main IP block 200 in the active state (IP1=H) at T1 begins to enter the sleep mode at T2, and transitions to the sleep state (IP1=L) at T3. Therefore, the channel management circuit 130 of the master IP block 200 provides a signal (CLK_REQ=L) instructing to stop the clock supply to the channel management circuit 132 of the slave IP block 210, thereby inducing the slave IP block 210 to enter the sleep mode.

Therefore, the dependent IP block 210 begins to enter sleep mode at T4 and transitions to sleep state at T7 (IP2=L). As mentioned above, in order to wake up the master IP block 200 later, the slave IP block 210 needs to be woken up first.

However, when the power down command (D_REQ) is received from the clock management unit controller 110 at T6, although the slave IP block 210 enters sleep mode in the interval from T4 to T7, due to the priority of the power down command (D_REQ) The order is higher than the wakeup command received from the master IP block 200 (eg, clock request (CLK_REQ=H)), so after T6, the channel management circuit 132 of the slave IP block 210 ignores the channel management circuit 130 from the master IP block 200 Received clock request (CLK_REQ).

Therefore, when the master IP block 200 satisfies the wake-up condition at T5 and waits for the wake-up of the slave IP block 210 with the QACTIVE value of H, since the path management circuit 132 of the slave IP block 210 ignores the path management from the master IP block 200 The clock request (CLK_REQ) received by the circuit 130, may lock up without waking up both the master IP block 200 and the slave IP block 210.

7 and 8 are schematic diagrams illustrating semiconductor devices according to exemplary embodiments of the present invention.

7 and 8 , in order to prevent the occurrence of the lockup described with reference to FIG. 6 in the semiconductor device according to the exemplary embodiment of the present invention, the channel management circuit 130 of the main IP block 200 transmits a grant signal (GRANT_D_REQ) to The channel management circuit 132 of the slave IP block 210 . The grant signal (GRANT_D_REQ) is a signal that determines whether to operate the channel management circuit 132 based on a power control command (eg, a power-down command (D_REQ)) in consideration of a master-slave relationship.

In an exemplary embodiment, the slave IP block is based on a signal derived from the power down command (D_REQ) received from the clock management unit controller 110 and the grant signal (S_D_REQ) received from the channel management circuit 130 of the master IP block 200 . The channel management circuit 132 of 210 performs a power down operation. For example, channel management circuit 132 may include the AND gate shown in FIG. 8 that receives D_REQ and GRANT_D_REQ, and performs an AND logic operation on D_REQ and GRANT_D_REQ to obtain a grant signal (S_D_REQ).

Therefore, in the case where the slave IP block 210 receives a power down command (D_REQ) from the clock management unit controller 110 but needs to wake up the master IP block 200, the slave IP block 210 wakes up. In an exemplary embodiment, when a state in which the master IP block 200 can perform a power-down operation is transmitted to the slave IP block 210 as a grant signal (GRANT_D_REQ), the slave IP block 210 is subjected to the interruption by ensuring that the master IP block 200 is not awake Electricity.

When the power down of the IP blocks 200 and 210 has been completed, only the channel management circuit 130 transmits an acknowledgement (D_ACK) of the power down command (D_REQ) to the clock management unit controller 110 .

FIG. 9 is a timing diagram illustrating an exemplary operation of a semiconductor device according to an exemplary embodiment of the present invention.

Referring to FIG. 9 , the main IP block 200 in the running state (IP1=H) at T1 begins to enter the sleep mode at T2, and transitions to the sleep state (IP1=L) at T3. Therefore, the channel management circuit 130 of the master IP block 200 provides a signal (CLK_REQ=L) instructing to stop the clock supply to the channel management circuit 132 of the slave IP block 210, thereby inducing the slave IP block 210 to enter the sleep mode.

Therefore, the dependent IP block 210 starts entering sleep mode at T4 and transitions to sleep state at T7 (IP2=L). As mentioned above, in order to wake up the master IP block 200 later, the slave IP block 210 needs to be woken up first.

When a power down command (D_REQ) is received from the clock management unit controller 110 at T6, although the slave IP block 210 enters sleep mode in the interval from T4 to T7, the power down command (D_REQ) has a higher priority than A wake-up command (eg, a clock request (CLK_REQ=H)) received from the primary IP block 200 . However, since the channel management circuit 130 does not transmit the grant signal (GRANT_D_REQ) to the channel management circuit 130, after T6, the channel management circuit 132 of the slave IP block 210 does not ignore the reception from the channel management circuit 130 of the master IP block 200 the clock request (CLK_REQ).

Therefore, when the master IP block 200 satisfies the wake-up condition at T5 and waits for the wake-up of the slave IP block 210 with the QACTIVE value of H, based on the clock request (CLK_REQ) received from the channel management circuit 130 of the master IP block 200, The channel management circuit 132 of the slave IP block 210 wakes up in the interval T9 to T10.

After that, in the channel management circuit 130, after the grant signal (GRANT_D_REQ) is transmitted to the channel management circuit 132 at T11, the power-off operation of the subordinate IP block 210 is performed.

10 and 11 are schematic diagrams illustrating semiconductor devices according to exemplary embodiments of the present invention.

10 and 11 , in order to prevent the occurrence of the lockup described with reference to FIG. 6 in the semiconductor device according to the exemplary embodiment of the present invention, the channel management circuit 132 of the slave IP block 210 receives a transmission from the master IP block 200 QACTIVE signal (first active signal) to channel management circuit 130 .

This embodiment is based on a master-slave relationship, in which the restriction on the slave IP block 210 that needs to be woken up first before the master IP block 200 is woken up is loose. Accordingly, each of the channel management circuits 130 and 132 receives power down commands (D_REQ1 and D_REQ2) from the clock management unit controller 110 and transmits acknowledgments (D_ACK1 and D_ACK2) to the clock management after power down has been performed unit 110.

In an exemplary embodiment, based on the QACTIVE signal (the first active signal) transmitted from the master IP block 200 to the channel management circuit 130 and the QACTIVE signal (the second active signal) received from the slave IP block 210 , the slave IP block The channel management circuit 132 of 210 performs a power down operation. For example, the channel management circuit performs a power down operation based on the signal (S_QACTIVE) which is passed through the QACTIVE signal (first active signal) transmitted from the master IP block 200 to the channel management circuit 130 and the slave slave Obtained by performing an OR logic operation on the QACTIVE signal (the second active signal) received by the IP block 210 . For example, the channel management circuit 132 may include the OR gate shown in FIG. 11 that performs the OR operation.

Therefore, in the case where the slave IP block 210 receives a power down command (D_REQ) from the clock management unit controller 110 but needs to wake up the master IP block 200, the slave IP block wakes up.

FIG. 12 is a schematic diagram illustrating a semiconductor device according to an exemplary embodiment of the present invention.

FIG. 12 differs from FIG. 7 in that the power management unit 300 directly transmits a power down command (D_REQ) to the channel management circuits 130 and 132 in order to perform the power control operations of the IP blocks 200 and 210 and control the IP blocks 200 and 210 power state.

Therefore, based on the power-down command (D_REQ) received from the power management unit 300 and the grant signal (GRANT_D_REQ) received from the channel management circuit 130 of the master IP block 200, the channel management circuit 132 of the slave IP block 210 performs a power-down operation. For example, based on a signal (S_D_REQ) obtained by performing AND logical operations on a power down command (D_REQ) received from the power management unit 300 and a grant signal (GRANT_D_REQ) received from the channel management circuit 130 of the main IP block 200 , the channel management circuit performs a power-down operation.

Therefore, in the case where the slave IP block 210 receives a power down command (D_REQ) from the power management unit 300 but needs to wake up the master IP block 200, the slave IP block 210 wakes up. In an exemplary embodiment, when a state in which the master IP block 200 can perform a power-down operation is transmitted to the slave IP block 210 as a grant signal (GRANT_D_REQ), the slave IP block 210 is performed by ensuring that the master IP block 200 is not awake. Power off.

When the power down of the IP blocks 200 and 210 has been completed, only the channel management circuit 130 transmits an acknowledgement (D_ACK) of the power down command (D_REQ) to the power management unit 300 .

13 is a schematic diagram illustrating a semiconductor device according to an exemplary embodiment of the present invention.

FIG. 13 differs from FIG. 10 in that the power management unit 300 directly transmits a power down command (D_REQ) to the channel management circuits 130 and 132 in order to perform the power control operations of the IP blocks 200 and 210 and control the IP blocks 200 and 210 power state.

Each of channel management circuits 130 and 132 receives power down commands (D_REQ1 and D_REQ2) from power management unit 300 and transmits acknowledgments (D_ACk1 and D_ACK2) to power management unit 300 after power down has been performed.

Based on the QACTIVE signal (first active signal) transmitted from the master IP block 200 to the channel management circuit 130 and the QACTIVE signal (second active signal) received from the slave IP block 210 , the channel management circuit 132 of the slave IP block 210 performs Power off operation. For example, the channel management circuit 132 performs a power down operation based on the signal (S_QACTIVE) which is passed between the QACTIVE signal (first active signal) transmitted from the main IP block 200 to the channel management circuit 130 and the slave Obtained by performing an OR logic operation on the QACTIVE signal (second active signal) received by the slave IP block 210 .

Therefore, in the case where the slave IP block 210 receives a power down command (D_REQ) from the clock management unit controller 110 but needs to wake up the master IP block 200, the slave IP block wakes up.

14 is a block diagram of a semiconductor system for which a semiconductor device and a method of operating a semiconductor device according to some embodiments of the present invention are applicable.

14 , the semiconductor system includes a semiconductor device (SoC) 1 , a processor 10 , a memory device 20 , a display device 30 , a network device 40 , a storage device 50 , and an input/output device 60 . The semiconductor device (SoC) 1 , the processor 10 , the memory device 20 , the display device 30 , the network device 40 , the storage device 50 and the input/output device 60 may transmit and receive data to and from each other through the bus bar 70 .

The IP blocks inside the semiconductor device (SoC) 1 described in various embodiments of the present invention include a memory controller that controls the memory device 20 , a display controller that controls the display device 30 , and a network that controls the network device 40 . At least one of a controller, a storage controller that controls the storage device 50 , and an input-output controller that controls the input-output device 60 . The semiconductor system may further include an additional processor 10 that controls these devices.

15 to 17 are exemplary semiconductor systems for which semiconductor devices and methods of operation of semiconductor devices in accordance with some embodiments of the present invention are applicable.

FIG. 15 is a diagram illustrating a tablet personal computer (PC) 1200 , FIG. 16 is a diagram illustrating a laptop computer 1300 , and FIG. 17 is a diagram illustrating a smartphone 1400 . The semiconductor device according to various embodiments of the present invention may be used in a tablet PC 1200 , a laptop computer 1300 , or a smart phone 1400 . However, since the semiconductor device can also be used in various other devices and integrated circuit devices not shown, the present invention is not limited thereto.

In some embodiments of the present invention, the semiconductor system may be provided as a computer such as an ultra mobile PC (UMPC), workstation, netbook, personal digital assistants (PDA), portable computer, wireless Telephones, mobile phones, e-book readers, portable multimedia players (PMP), portable game consoles, navigation devices, black boxes, digital cameras, 3D TVs, digital audio recorders, digital audio players , digital picture recorder, digital picture player, digital video recorder or digital video player.

Although the present invention has been disclosed above by the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, The protection scope of the present invention shall be determined by the scope of the appended patent application.

1‧‧‧System Chip; 10‧‧‧Processor; 20‧‧‧Memory Device; 30‧‧‧Display Device; 40‧‧‧Network Device; 50‧‧‧Storage Device; 60‧‧‧Input/ Output device; 70‧‧‧bus; 100‧‧‧clock management unit; 110‧‧‧CMU controller; 120a‧‧‧clock element; 120b‧‧‧clock element; ;120d‧‧‧clock component;120e‧‧‧clock component;120f‧‧‧clock component;120g‧‧‧clock component;122a‧‧‧clock control circuit;122b‧‧‧clock control circuit ;122c‧‧‧Clock Control Circuit; 122d‧‧‧Clock Control Circuit; 122e‧‧‧Clock Control Circuit; 122f‧‧‧Clock Control Circuit; 122g‧‧‧Clock Control Circuit; 124a‧‧‧ 124b‧‧‧Clock Source; 124c‧‧‧Clock Source; 124d‧‧‧Clock Source; 124e‧‧‧Clock Source; 124f‧‧‧Clock Source; 124g‧‧‧Clock Source Source; 130‧‧‧Channel Management Circuit; 132‧‧‧Channel Management Circuit; 200‧‧‧IP Block; 210‧‧‧IP Block; 300‧‧‧Power Management Unit; 402‧‧‧Channel management circuit; 404‧‧‧Channel management circuit; 410‧‧‧Channel management circuit; 412‧‧‧Channel management circuit; 414‧‧‧Channel management circuit; ‧‧Laptop Computer; 1400‧‧‧Smart Phone; OSC‧‧‧Oscillator; ‧Clock request; ACK‧‧‧Clock request confirmation; CLK‧‧‧clock signal; CLK1‧‧‧first clock signal; CLK2‧‧‧second clock signal; CM‧‧‧channel management circuit ;PMU‧‧‧Power Management Unit; CMD‧‧‧Power Control Command; D_REQ, D_REQ1, D_REQ2‧‧‧Power-Down Command; D_ACK, D_ACK1, D_ACK2‧‧‧Power-Down Command Confirmation; , OR_CLK_REQ‧‧‧ clock request; CLK_ACK, CLK_ACK1, CLK_ACK2, CLK_ACK3, AND_CLK_ACK‧‧‧ clock request confirmation; QREQn, QACCEPTn, QACTIVE‧‧‧ signal; Q_RUN‧‧‧ running state; Q_CLK_REQ‧‧‧ sleep mode Enter state; Q_STOPPED‧‧‧ sleep state; Q_EXIT‧‧‧ sleep mode exit state; T1~T16‧‧‧ time point; GRANT_D_REQ‧‧‧authorization signal; S_D_REQ‧‧‧signal number/authorization signal; S_QACTIVE‧‧‧ signal.

FIG. 1 is a schematic diagram illustrating a semiconductor device according to an exemplary embodiment of the present invention. FIG. 2 is a schematic diagram illustrating a semiconductor device according to an exemplary embodiment of the present invention. FIG. 3 is a schematic diagram illustrating an exemplary operation of a semiconductor device according to an exemplary embodiment of the present invention. FIG. 4 is a schematic diagram illustrating an exemplary operation of a semiconductor device according to an exemplary embodiment of the present invention. FIG. 5 is a schematic diagram illustrating an exemplary operation of a semiconductor device according to an exemplary embodiment of the present invention. FIG. 6 is a timing diagram illustrating an exemplary operation of a semiconductor device according to an exemplary embodiment of the present invention. 7 and 8 are schematic diagrams illustrating semiconductor devices according to exemplary embodiments of the present invention. FIG. 9 is a timing diagram illustrating an exemplary operation of a semiconductor device according to an exemplary embodiment of the present invention. 10 and 11 are schematic diagrams illustrating semiconductor devices according to exemplary embodiments of the present invention. FIG. 12 is a schematic diagram illustrating a semiconductor device according to an exemplary embodiment of the present invention. 13 is a schematic diagram illustrating a semiconductor device according to an exemplary embodiment of the present invention. 14 is a block diagram of a semiconductor system to which a semiconductor device and a method of operating a semiconductor device according to at least one embodiment of the present invention are applicable. 15 to 17 are exemplary semiconductor systems for which semiconductor devices and methods of operation of semiconductor devices according to some embodiments of the present invention are applicable.

1: System chip

100: clock management unit

110: CMU Controller

120a, 120b, 120c, 120d, 120e, 120f, 120g: clock elements

122a, 122b, 122c, 122d, 122e, 122f, 122g: clock control circuit

124a, 124b, 124c, 124d, 124e, 124f, 124g: clock source

130: Channel management circuit

132: Channel management circuit

200: IP Block

210: Intellectual Property Block

300: Power Management Unit

OSC: Oscillator

PLL: Phase Locked Loop

CC: Clock Control Circuit

CM: Channel Management Circuit

CS: clock source

REQ: clock request

ACK: Acknowledgement of the clock request

CLK: clock signal

CLK1: The first clock signal

CLK2: The second clock signal

Claims (20)

A semiconductor device comprising: a first clock control circuit that controls a first child clock source to receive a clock signal from a parent clock source; a first channel management circuit that responds to a clock signal from a first IP block The received first IP block clock request transmits the first clock request to the first clock control circuit; the second clock control circuit controls the second child clock source from the parent clock receiving the clock signal at the source; a second channel management circuit that transmits a second clock request to the second clock control circuit in response to a second IP block clock request received from the second IP block a power management unit that transmits power control commands to the first channel management circuit and the second channel management circuit to control the power states of the first IP block and the second IP block, wherein all the first channel management circuit transmits a third clock request to the second channel management circuit, and the second channel management circuit transmits an acknowledgement of receipt of the third clock request to the first channel management circuit to maintain the master-slave relationship. The semiconductor device of claim 1, wherein the first channel management circuit transmits an authorization signal to the second channel management circuit and the second channel management circuit is based on the power control command and the Authorize signal operations. The semiconductor device of claim 2, wherein the second channel management circuit controls the second channel based on a resultant signal obtained by performing AND logical operations on the power control command and the grant signal The power state of the IP block. The semiconductor device of claim 2, wherein the first channel management circuit transmits an acknowledgement of the reception of the power control command to the power management unit. The semiconductor device of claim 1, wherein the second channel management circuit receives a first active signal transmitted through the first IP block to the first channel management circuit, wherein the first An active signal indicates whether the first IP block has woken up. The semiconductor device of claim 5, wherein the second channel management circuit is based on a signal transmitted through the first active signal and through the second IP block to the second channel management circuit The power state of the second IP block is controlled by a result signal obtained by performing an OR logic operation on a second active signal, wherein the second active signal indicates whether the second IP block has woken up. The semiconductor device of claim 5, wherein the first channel management circuit and the second channel management circuit transmit an acknowledgement of the reception of the power control command to the power management unit. The semiconductor device of claim 1, wherein the first IP block is a master device and the second IP block is a slave device. The semiconductor device of claim 8, wherein said second IP block enters sleep mode only when said first IP block is already in sleep mode, and wherein said second IP block enters sleep mode only when said second IP block is already in sleep mode. After having woken up the first IP block wakes up. The semiconductor device of claim 1, wherein the power management unit transmits the power control command to a clock management unit controller, and the clock management unit controller controls based on the power control command The first channel management circuit or the second channel management circuit and then transmits an acknowledgement of receipt of the power control command to the power management unit. A semiconductor device comprising: a first channel management circuit that controls the output of a clock signal to a first IP block; a second channel management circuit that receives a clock request from the first channel management circuit and according to the a clock request control clock signal output to a second IP block; and a power management unit that transmits power control commands to the first channel management circuit and the second channel management circuit to control the first IP block with and the power state of the second IP block. The semiconductor device of claim 11, wherein the second channel management circuit transmits an acknowledgement of receipt of the clock request to the first channel management circuit. The semiconductor device of claim 11, wherein the first channel management circuit transmits an authorization signal to the second channel management circuit and the second channel management circuit is based on the power control command and the Authorize signal operations. The semiconductor device of claim 13, wherein the second channel management circuit controls the second channel based on a resultant signal obtained by performing AND logical operations on the power control command and the grant signal The power state of the IP block. The semiconductor device of claim 13, wherein the first channel management circuit transmits an acknowledgement of the reception of the power control command to the power management unit. The semiconductor device of claim 11, wherein the second channel management circuit receives a first active signal transmitted to the first channel management circuit through the first IP block, wherein the first An active signal indicates whether the first IP block has woken up. The semiconductor device of claim 11, wherein the power management unit transmits the power control command to a clock management unit controller, and The clock management unit controller controls the first channel management circuit or the second channel management circuit based on the power control command, and then transmits an acknowledgement of receipt of the power control command to the power management unit . A semiconductor system comprising: a system chip including the semiconductor device according to claim 1; the first IP block; and the second IP block. The semiconductor system of claim 18, further comprising an external device, wherein the external device includes at least one of a memory device, a display device, a network device, a storage device, and an input/output device, and the The system chip controls the external device. The semiconductor system of claim 19, wherein the first IP block or the second IP block includes a memory controller that controls the memory device, a display control that controls the display device one of a controller, a network controller that controls the network device, a storage controller that controls the storage device, and an input-output controller that controls the input-output device.

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