TWI750074B - Defect analysis method of semiconductor device and electonic device - Google Patents

Abstract

A defect analysis method of a semiconductor device and an electronic device are provided. The defect analysis method includes follows steps. A test area in the semiconductor device is divided into a plurality of blocks according to a direction. A M defect addresses of defects in each block is recorded to obtain a defect address group corresponding to each block, and a number of defects in each block is counted to obtain a defect count value corresponding to each block. It is determined in sequence whether the defect count value corresponding to a block-to-be-processed is less than or equal to M and the defect count value is not zero to determine whether the block-to-be-processed is set as a selected block. It is determined whether the defective address group corresponding to the block adjacent to the selected block has a same compared address. The compared address is recorded as a first-direction defect type in the test area to analyze a defect distribution in the test area.

Description

Defect analysis method of semiconductor device and electronic device

The present invention relates to a defect detection and classification technology for memory devices in a semiconductor manufacturing process, and more particularly to a defect analysis method of semiconductor devices and electronic devices for analyzing defects in semiconductor devices.

In the semiconductor industry, how to ensure that the manufactured semiconductor components (such as semiconductor wafers and dies) have consistently high quality is becoming more and more important. Semiconductor testing can be used to determine the defect type on the semiconductor component and the position distribution of these defects on the semiconductor component. The memory device manufactured by the semiconductor manufacturing process has a plurality of memory cells, and each memory cell has coordinates or a character line and bit line number used to indicate the position, so that the semiconductor test will determine each cell through electrical testing. Whether each memory cell fails and forms a defect. These defects can be represented by the aforementioned coordinate or character line and bit line numbers to show their corresponding positions.

Semiconductor testing can generate the aforementioned defect locations through full bitmap technology. However, the full bitmap technology (or full bitmap approach) will depend on the size of the semiconductor components and generate huge amounts of data that are difficult to store or process, so that marking these defects and presenting the positions of these defects will be difficult to store or process. It will consume a lot of computing resources and take up a lot of storage space to be completed very slowly. In detail, during semiconductor testing, the corresponding defect address and input/output pin information are generated for each memory cell defect through the aforementioned coordinates. Many defect types (such as defective input/output pins, bit lines (BL) or word lines (WL)) require the defects of these memory cells to be marked or displayed on the wafer Only after the corresponding position can be known or judged. Although the defect location can be obtained relatively quickly by reducing the number/precision/completeness of defects, but there is still another part of the defect location unknown, which may lead to misjudgment of the defect form on the semiconductor component .

The present invention provides a defect analysis method for semiconductor devices and an electronic device for analyzing defects in semiconductor devices. Through a small number of address comparisons, the more frequently occurring defect forms (for example, bit line (BL) defect forms, word defects) can be judged. Element line (WL) defect form, cross (cross) defect form), thereby saving the calculation time of defect analysis.

The defect analysis method of a semiconductor device according to an embodiment of the present invention includes the following steps. Divide a test area in a semiconductor device into a plurality of first blocks according to a first direction; record M first defect addresses of defects in each first block to obtain the corresponding first block A first defect address group of, and count the number of defects in each first block to obtain a first defect count value corresponding to each first block, where M is a positive integer; determine in order Whether the first defect count value corresponding to a first block to be processed in each first block is less than or equal to the M and not zero, and whether the first defect count corresponding to the first block to be processed is When the first defect count value is less than or equal to the M and not zero, the first block to be processed is set as a selected first block; the first blocks adjacent to the selected first block are determined Whether there is the same compared first address in the first defective address group corresponding to a block, and determine whether the first blocks adjacent to the selected first block have the same Whether the number is greater than a first predetermined adjacent value; and, the first address groups corresponding to the first blocks adjacent to the selected first block have the same When the first address is compared and the number of adjacent first blocks is greater than the first predetermined adjacent value, the compared first address is recorded as a first in the test area One-directional defect form to analyze the defect distribution in the test area.

The electronic device for analyzing defects in a semiconductor device according to an embodiment of the present invention includes a defect detection device and a defect analysis device. The defect detection device is used for judging defects in the semiconductor device to generate defect information. The defect analysis device is coupled to the defect detection device. The defect analysis device includes a processor. The processor records the M first defect addresses of the defects in each first block according to the defect information to obtain a first defect address group corresponding to each first block, and counts each first zone The number of the defects in the block obtains a first defect count value corresponding to each first block, where M is a positive integer. The processor sequentially determines whether the first defect count corresponding to a first block to be processed in each first block is less than or equal to the M and not zero, and is corresponding to the second block to be processed When the first defect count value of is less than or equal to the M and not zero, the first block to be processed is set as a selected first block. The processor determines whether the first defective address group corresponding to the first blocks adjacent to the selected first block has the same compared first address, and determines whether the first address is the same as the first defective address group. Select whether the number of the first blocks adjacent to the first block is greater than a first predetermined adjacent value. The first address groups corresponding to the first blocks adjacent to the selected first block have the same compared first address and the adjacent first address groups When the number of a block is greater than the first predetermined adjacent value, the processor records the compared first address as a first direction defect form in the test area to analyze the defects in the test area distributed.

Based on the above, the embodiment of the present invention uses the word line direction and the bit line direction of the memory layout to divide the test area into multiple blocks, and uses the selected area corresponding to the relatively small defect count in each block Block and the defect address group corresponding to this selected block are used to classify other blocks adjacent to this selected block in the form of defects. Therefore, through a small number of address comparisons, the more frequently occurring defect forms can be judged (For example, bit line (BL) defect form, word line (WL) defect form, cross defect form), and the defect form of the compared address can be recorded from the aforementioned comparison to determine the cross The occurrence point of the defect form (ie, the corresponding address of the cross defect form). In this way, the embodiment of the present invention can save the calculation time of defect analysis through the aforementioned method.

FIG. 1 is a block diagram of an electronic device 100 for analyzing defects in a semiconductor device according to an embodiment of the present invention. As shown in FIG. 1, the electronic device 100 is used to determine defects in the semiconductor component 105 and analyze these defects, thereby reducing the probability of these defects due to the semiconductor manufacturing process, and improving the yield of the semiconductor device in the manufacturing process. The semiconductor member 105 is an element constituting a semiconductor device, and is, for example, a wafer.

The electronic device 100 mainly includes a defect detection device 110 and a defect analysis device 120. The defect detection device 110 is used to detect defects in each unit (for example, semiconductor die) in the semiconductor component 105 (wafer), and provide information on whether each unit in the semiconductor component 105 is defective. The semiconductor die of this embodiment is used as a memory device, and is implemented by using a predetermined memory layout.

The defect detection device 110 is used for judging defects in the semiconductor component 105 to generate defect information. In this embodiment, the defect detection device 110 can be a testing machine for defect sampling for the semiconductor component 105, and the defect sampling rate of the defect detection device 110 can be determined according to the needs of the person applying this embodiment. In some embodiments, the defect sampling rate of the defect detection device 110 may be proportional sampling. For example, one may be selected from the corresponding positions of multiple word line/bit line numbers to determine whether there is a defect. For example, choose one from the corresponding positions of the 4 word line/bit line numbers to determine whether there is a defect, so that the sampling rate is 1/4. This embodiment can also use different defect sampling rates for different areas of the semiconductor component 105. For example, a part of the test area uses a 1/4 sampling rate to detect defects, and another part of the test area uses a 1/8 sampling rate. Detect defects.

The defect analysis device 120 mainly includes a processor 130 and a memory 140. The memory 140 is controlled by the processor 130 for temporarily storing the information provided by the defect detection device 110 and for temporarily storing the intermediate information required by the defect analysis method according to the embodiment of the present invention. The defect detection device 110 of this embodiment can be implemented by a testing machine, and although the defect analysis device 120 is separated from the defect detection device 110 in this embodiment, those who apply this embodiment can also use the defect analysis device 120 as a test machine. The defect detection device 110 of the machine is implemented. In other words, the processor 130 of the defect analysis device 120 can be implemented by the arithmetic unit (eg, central processing unit, microprocessor, etc.) in the defect detection device 110, and the memory 140 of the defect analysis device 120 can be implemented by the defect detection device. The data storage device in the device 110 is implemented.

The processor 130 of this embodiment divides the test area in the semiconductor component into a plurality of blocks through the defect analysis method described in the embodiment of the present invention, and uses the defect corresponding to the relatively small defect count in each block. The selected block and the defect address group corresponding to this selected block are used to classify other blocks adjacent to this selected block in the form of defects, so that more frequent defects can be judged by a relatively small number of addresses Form (for example, bit line (BL) defect form, word line (WL) defect form, cross defect form), and the defect form of the compared address can be recorded from the aforementioned comparison to determine The occurrence point of the cross defect form (ie, the corresponding address of the cross defect form). The defect analysis method described in the embodiment of the present invention will be described in detail below.

2 is a schematic diagram of the test area 210 and related statistical information in the semiconductor component 105 according to the first embodiment of the present invention. The semiconductor component 105 of this embodiment is an example of a memory device. The test area 210 is a partial area where the defect inspection device 110 of FIG. 1 inspects the semiconductor component 105. The semiconductor component 105 described in this embodiment is a wafer body, so the overall test area of the semiconductor component 105 may be spliced into a circular saw-tooth shape. However, for the convenience of description, this embodiment takes the rectangular test area 210 in FIG. 2 as an example.

The test area 210 of this embodiment is divided into multiple units. The "unit" can be a die or a part of a wafer defined by the application of this embodiment. In this embodiment, each cell (take cell 215 in FIG. 2 as an example) corresponds to 128 character lines (marked as "WL×128" in FIG. 2) and 16 bit lines (marked as "BL×16 in FIG. 』). The number of word lines and the number of bit lines corresponding to each cell can be adjusted by those applying this embodiment according to their needs. In other words, a person applying this embodiment can selectively adjust the number of memory cells in the semiconductor component 105 expressed in each unit.

In this embodiment, the wiring direction of the word line WL in the memory layout is used as the first direction to divide the test area 210 in the semiconductor component into a plurality of first blocks 220-1 to 220-4. Each first block 220-1~220-4 is composed of multiple units. In FIG. 2, the X-axis direction is an example of the wiring direction of the word line WL. Those applying this embodiment can selectively adjust the number of the first block in the test block according to their needs. Here, the four first blocks 220-1~220-4 are taken as examples.

On the other hand, this embodiment also uses the wiring direction of the bit line BL in the memory layout as the second direction to divide the test area 210 into a plurality of second blocks 230-1 to 230-16. In FIG. 2, the Y-axis direction is an example of the wiring direction of the bit line BL. Each second block 230-1~230-16 is composed of multiple units. The wiring direction (first direction) of the word line WL and the wiring direction (second direction) of the bit line BL are not parallel to each other. In detail, the first direction and the second direction are perpendicular to each other. Those applying this embodiment can selectively adjust the number of second blocks in the test block according to their needs. Here, 16 second blocks 230-1~230-16 are taken as examples.

The field 240 in FIG. 2 is used to indicate the first defect count values CR1 to CR4 corresponding to the first blocks 220-1 to 220-4. The first defect count values CR1 to CR4 are used to count the number of defects in the first blocks 220-1 to 220-4, respectively. For example, if there is 1 defect in the first block 220-1, the first defect count value CR1 is "1"; the first defect count values CR2 and CR4 are also the same as the first defect count value CR1, respectively representing the first block There is 1 defect in 220-2 and 220-4; there are 2 defects in the first block 220-3, the first defect count value CR4 is "2".

The column 250 in FIG. 2 is used to indicate the second defect count values CC1 to CC16 corresponding to the second blocks 230-1 to 230-16. The second defect count values CC1 to CC16 are used to count the number of defects in the second blocks 230-1 to 230-16, respectively. For example, if there are no defects in the second block 230-1, the second defect count value CC1 is "0"; the second defect count values CC2~CC8, CC10~CC16 are also "0", indicating the first block There are no defects in 230-2~230-8 and 230-10~230-16; there are 512 defects in the second block 220-9, the second defect count value CC9 is "512". Moreover, for the convenience of description, the defect BLT1 in the form of a bit line defect and the defect PT1 in the form of a single point defect are depicted on the test area 210 in FIG. 2.

FIG. 3 is a flowchart illustrating a defect analysis method of a semiconductor device according to the first embodiment of the present invention. The defect analysis method described in FIG. 3 may be executed by the processor 130 in FIG. 1. 2 and FIG. 3 at the same time, in step S310, the processor of FIG. 1 according to the first direction (for example, the wiring direction of the word line WL) to divide the test area 210 in the semiconductor component 105 into a plurality of first Blocks (for example, the first blocks 220-1~220-4). In this embodiment, the first direction is the wiring direction of the character lines in the memory layout (represented by the X-axis direction in FIG. 2) as an example. Therefore, this embodiment uses the X-axis direction in FIG. It is divided into the first blocks 220-1~220-4.

In step S320, the processor of FIG. 1 records the M first defect addresses of the defects in each first block 220-1~220-4 to obtain the corresponding first block 220-1~220-4 The first defect address group, and the processor in Figure 1 counts the number of defects in each first block 220-1~220-4 to obtain the first block corresponding to each first block 220-1~220-4 Defect count value CR1~CR4. M is a positive integer. The column 240 in FIG. 2 is used to display the first defect count values CR1 to CR4 corresponding to each of the first blocks 220-1 to 220-4.

The value of "M" in this embodiment is determined by the person applying this embodiment, and the value of "M" can be determined by the average or maximum value of the number of defects that frequently occur in semiconductor testing, so as to record each One block 220-1 to 220-4 corresponds to the number of addresses in the first defective address group, which can prevent the number of addresses recorded in the first defective address group from being too many. In other words, there are at most M addresses in the first defective address group corresponding to each of the first blocks 220-1 to 220-4. The value of "M" in this embodiment is, for example, "3".

It is assumed here that the test area 210 of FIG. 2 has a defect BLT1 in the form of a bit line defect and a defect PT1 in the form of a single point defect. Both the first defect address of this embodiment and the compared first address described in step S330 are presented by the number of bit lines. For example, the defect BLT1 appears on the bit line labeled 140, so the first address AC140 is represented as the address of the defect BLT1; the defect PT1 appears on the bit line labeled 130, so the first address AC130 is represented as a defect The address of PT1. In addition, this embodiment does not need to record the label information of the defects BLT1 and PT1 on the character line.

Therefore, based on the description of step S320 and the defects BLT1 and PT1 in FIG. 2, the first defect address group corresponding to the first block 220-1 records a defect address (here set as AC140), and The first defect count value CR1 corresponding to the first block 220-1 is "1". The first defect address group corresponding to the first block 220-2 records a defect address (here set to AC140), and the first defect count CR2 corresponding to the first block 220-2 is " 1". The first defect address group corresponding to the first block 220-3 records two defect addresses (here set to AC130, AC140), and the first defect count value corresponding to the first block 220-3 CR3 is "2". The first defect address group corresponding to the first block 220-4 records a defect address (here set to AC140), and the first defect count CR4 corresponding to the first block 220-4 is " 1".

In step S330, the processor of FIG. 1 sequentially determines whether the first defect count corresponding to the first block to be processed in each of the first blocks 220-1 to 220-4 is less than or equal to M (this embodiment is "3") and not zero. And, when the first defect count value corresponding to the first block to be processed is less than or equal to M and not zero, the processor of FIG. 1 sets the first block to be processed as the selected first block, and proceeds to step S340 . Here, for example, assuming that the first block to be processed is the first block 220-1, the processor in FIG. 1 determines whether the first defect count value CR1 corresponding to the first block 220-1 is less than or equal to M and not zero . Since the first defect count value CR1 ("1") in FIG. 1 is less than or equal to M ("3") and is not zero, the first block 220-1 is set as the selected first block. In contrast, when the first defect count value corresponding to the first block is greater than M or the aforementioned first defect count value is zero, it means that the block to be processed will not be set as the selected first block. Step S330 proceeds to step S335 to determine whether the first block to be processed is the last first block. If the first block to be processed is not the last first block, proceed from step S335 to step S337, use the next first block as the first block to be processed, and perform step S330 again to determine the next first block Whether the block is the first block selected. If the block to be processed is the last first block, in step S335, proceed to step S339 to end the defect analysis method.

In step S340, the processor of FIG. 1 determines whether the first defective address group corresponding to the first blocks adjacent to the selected first block (take the first block 220-1 as an example) is Have the same compared first address, and the processor in Figure 1 determines whether the number of these first blocks adjacent to the selected first block (first block 220-1) is greater than the first preset Adjacent value. The "first preset neighbor value" of this embodiment is used to determine whether there are multiple cells in the adjacent first block that have multiple defects with continuity and extensibility, and whether these defects are along the second The direction (for example, the wiring direction of the bit line BL, and the Y-axis direction in FIG. 2 is taken as an example) is generated to determine whether it is the first direction defect form (this embodiment uses "bit line defect form" as an example) . In other words, the "first preset adjacent value" can be used to determine whether there are multiple first blocks all connected with defects, and the number of adjacent first blocks must be greater than or equal to the "first preset adjacent value" Value" to judge it as a bit line defect form. In this embodiment, the "first preset neighbor value" is set to 3. Those who apply this embodiment can adjust the first preset neighbor value according to their needs.

The first address groups corresponding to the first blocks adjacent to the selected first block (first block 220-1) have the same compared first address and are adjacent When the number of connected first blocks is greater than the first predetermined neighboring value, the process proceeds from step S340 to step S350, and the processor of FIG. 1 records the first compared first address as the first direction defect in the test area 210 form. Since the aforementioned first direction is the wiring direction of the word line, and it is known from the judgment of the aforementioned steps S330~350 that the first addresses with multiple defects are all the same (that is, the adjacent first block Corresponding first address groups have the same compared first address), it can be known that multiple defects arranged in the wiring direction of bit lines have occurred in the test area 210. Therefore, this embodiment will The addresses of these defects (that is, the aforementioned first address after comparison) are recorded as the first-direction defect form in the test area (that is, the "bit line defect form"). In this way, the multiple defects arranged in the wiring direction of the bit line can be marked as the first direction defect form ("bit line defect form") through the steps in FIG. Address comparison can determine the form of defects that occur more frequently, thereby saving computing time for defect analysis.

In contrast, the first address groups corresponding to the first blocks adjacent to the selected first block (first block 220-1) do not have the same compared first bit Address, or when the number of adjacent first blocks is less than the aforementioned first preset adjacent value, it means that the adjacent first blocks do not have multiple connected defects, or that these defects If the connection length is not enough to determine that it is the aforementioned first direction defect form ("bit line defect form"), then from step S340 to step S335 to determine whether the block to be processed is the last first block. If it is not the last first block, proceed from step S335 to step S337, use the next first block as the first block to be processed, and perform step S330 again to determine whether the next first block is selected The first block. If the block to be processed is the last first block, in step S335, proceed to step S339 to end the defect analysis method.

Therefore, in the present embodiment of the present invention, the number and location of defects in the semiconductor manufacturing process of a fab (FAB) can be obtained by the aforementioned defect analysis method in the current wafer test, thereby generating a defect wafer map to display the aforementioned fab semiconductor. The distribution state of the defects in the process can produce the actual positions of the aforementioned defects on the wafer.

Here, FIG. 2 is used to describe in detail the related details of "the first blocks adjacent to the selected first block" in the aforementioned steps S330 to S350. In this embodiment, "these first blocks adjacent to the first block 220-1" refer to the first blocks 220-2, 220-3, and 220-4, and the first block 220-1~ 220-4 are adjacent to each other, and the number of adjacent first regions 220-1 to 220-4 is 4. Therefore, the processor of FIG. 1 determines in step S340 whether the first defect location groups corresponding to the first blocks 220-2 to 220-4 adjacent to the first block 220-1 have the same address (That is, the first address AC140), and it is found that the first address AC140 is all recorded in the first defect location group corresponding to the first blocks 220-2 to 220-4, so the experience of this embodiment is compared The first address is the first address AC140. The processor of FIG. 1 also determines in step S340 that the number of adjacent first regions 220-1 to 220-4 is 4, which is greater than the aforementioned first preset adjacent value ("3"). Therefore, in this embodiment, the compared first address (AC140) is recorded as the first direction defect form ("bit line defect form") in the test area.

In the foregoing embodiment, the wiring direction of the word line WL is used as the first direction, the blocks 220-1 to 220-4 are used as the first block, and the bit line defect form is used as the first direction defect form, that is, The defect analysis method of the foregoing embodiment is used to determine the defect of the bit line defect form. In addition, in other embodiments consistent with the present invention, those applying this embodiment can also regard the wiring direction of the bit line as the first direction, the blocks 230-1 to 230-16 as the aforementioned first blocks, and the words The element line defect form is used as the first direction defect form to implement the steps in FIG. 3, so that other embodiments can use the compared first address as the character line defect form in the test area, that is, the defect of the previous embodiment The analysis method is used to judge the defects in the form of character line defects.

4 is a schematic diagram of a test area 410 and related statistical information in a semiconductor component according to a second embodiment of the present invention. For the convenience of description, only the blocks 230-1~230-16 and the corresponding defect count values CC1~CC16 and the defect count values CR1~CR4 are shown in the test area 410 in Fig. 4, and the defect count values CR1~CR4 are respectively 151, 0, 0, and 0. The field 440 in FIG. 4 is used to indicate the defect count values CR1 to CR4 corresponding to the blocks classified according to the X-axis direction. The field 450 in FIG. 4 is used to indicate the blocks 230-1 to 230-16 distinguished according to the Y-axis direction and the corresponding defect count values CC1 to CC16. The defect count values CC1~CC16 are used to count the number of defects in the blocks 230-1~230-16, respectively.

In addition, the defects WLT1 and WLT2 in the form of character line defects are shown as examples on the test area 410 in FIG. 4. It is assumed here that the test area 410 in FIG. 4 has two defects WLT1 and WLT2 in the form of character line defects. The first defect address in this embodiment and the compared first address described in step S330 in FIG. 3 are all presented by the number of word lines. For example, the defect WLT1 appears on the character line labeled 61, so the address AR61 is represented as the address of the defect WLT1; the defect WLT2 appears on the character line labeled 120, so the address AR120 is represented as the address of the defect WLT2 .

Referring to FIGS. 3 and 4 at the same time, in step S310, the processor divides the test area 410 in the semiconductor component 105 into a plurality of first blocks according to the first direction (for example, the wiring direction of the bit line BL) (For example, blocks 230-1~230-16). In this embodiment, the first direction is the routing direction of bit lines in the memory layout (represented by the Y-axis direction in FIG. 2) as an example. Therefore, this embodiment is along the Y-axis direction in FIG. The area 410 is divided into first blocks 230-1 to 230-16.

In step S320, the processor records the M defect addresses of the defects in each block 230-1~230-16 to obtain the defect address group corresponding to each block 230-1~230-16, and processes The device counts the number of defects in each block 230-1~230-16 to obtain the defect count value CC1~CC16 corresponding to each block 230-1~230-16. The column 450 in FIG. 4 is used to display the defect count values CC1 to CC16 corresponding to the respective blocks 230-1 to 230-16. For example, the defect address group corresponding to the blocks 230-1 to 230-6 is an empty set, because no defects are found in the blocks 230-1 to 230-6. The defect address group corresponding to the blocks 230-7~230-16 is (AR61, AR120), because there are defects WLT1, WLT2 in the blocks 230-7~230-16, and the defective WLT1 bit is in the use of the word line The numbered address is AR61, and the defective WLT2 is located at the address AR120 that is represented by the number of word lines.

In step S330, the processor sequentially determines whether the defect count corresponding to the block to be processed in each block 230-1 to 230-16 is less than or equal to M ("3" in this embodiment) and not zero . When the defect count value corresponding to the block to be processed is greater than M or the aforementioned defect count value is zero, it means that the block to be processed will not be set as a selected block. Therefore, from step S330 to steps S335 and S337, The processing block is moved to the next block, and step S330 is performed again to determine whether the block to be processed is the selected block. In this embodiment, since the defect count values CC1 to CC6 corresponding to the blocks 230-1 to 230-6 are all 0, the block to be processed is moved to the next block 230-7 as the block to be processed . Since the defect count value CC7 (value "2") corresponding to the block to be processed (block 230-7) is less than or equal to M ("3" in this embodiment) and not zero, block 230-7 Set as the selected block.

In step S340, the processor determines whether the defective address groups corresponding to the blocks adjacent to the selected block (using block 230-7 as an example) have the same compared addresses, and processes The detector determines whether the number of blocks adjacent to the selected block (block 230-7) is greater than the preset adjacent value. The "preset neighboring value" of this embodiment is used to determine whether there are multiple defects in adjacent blocks that have multiple cells with continuity and extensibility, and whether these defects are distributed along the character line WL The line direction is generated to determine whether it is a character line defect form. In other words, the "default adjacent value" can be used to determine whether multiple blocks have connected defects, and the number of adjacent blocks must be greater than or equal to the "default adjacent value" to determine whether it is Character line defect form. In this embodiment, the "default neighboring value" is set to 3. Those who apply this embodiment can adjust the default neighboring value according to their needs.

The processor of this embodiment determines the defect address corresponding to the block (for example, block 230-7~230-16) adjacent to the selected block (block 230-7) in FIG. 4 in step S340 There are the same compared addresses in the group, namely addresses AR61 and AR120. In addition, the processor also determines in step S340 that the number of blocks (blocks CC7~CC16) adjacent to the selected block (block 230-7) ("10") is greater than the preset adjacent value (" 3』). Therefore, from step S340 to step S350, the processor records the aforementioned compared addresses (addresses AR61 and AR120) as a specific defect form (ie, a character line defect form) in the test area 410.

In another embodiment of the present invention, a defect analysis method can also be used to determine whether there is a defect in the form of a character line defect based on the first block 220-1 to 220-4 corresponding to the first direction, and based on the second direction. Corresponding to the second blocks 230-1 to 230-16 to determine whether there is a defect in the form of a bit line defect. Even after judging that there are defects in the form of bit line defects and defects in the form of word line defects, the intersection of the aforementioned defect in the form of bit line defects and the defect in the form of word line defects can be recorded. In order to test the cross defect forms in the area, the calculation time for judging the defect forms of the defect is greatly reduced and the calculation resources are saved.

FIG. 5 is a schematic diagram of a test area 510 and related statistical information in a semiconductor component according to a third embodiment of the present invention. The field 540 in FIG. 5 is used to indicate the defect count values CR1 to CR4 corresponding to the first blocks 220-1 to 220-4 classified according to the X-axis direction. The field 550 in FIG. 5 is used to indicate the second blocks 230-1 to 230-16 distinguished according to the Y-axis direction and the corresponding defect count values CC1 to CC16. The defect count values CR1~CR4, CC1~CC16 are used to count the number of defects in the blocks 220-1~220-4, 230-1~230-16, respectively.

For the convenience of explanation, it is assumed here that the test area 510 of FIG. 5 has two defects WLT1, WLT2 in the form of word line defects, three defects BLT1, BLT2, BLT3 in the form of bit line defects, and two defects PT1 in the form of single point defects. , PT2 is taken as an example, and is shown on the test area 510 in FIG. 5. In this embodiment, the first defective address and the compared first address are all represented by the number of the bit line, and the second defective address and the compared second address are represented by the number of the word line . For example, the defect BLT1 in Figure 5 appears on the bit line labeled 83, so the address AC83 is represented as the first defect address of the defect BLT1; the defect BLT2 in Figure 5 appears on the bit line labeled 90, so the address AC90 represents It is the first defect address of the defect BLT2; the defect BLT3 in FIG. 5 appears on the bit line labeled 95, so the address AC95 is represented as the first defect address of the defect BLT3. Figure 5 Defect WLT1 appears on the character line labeled 400, so the address AR400 is represented as the second defect address of the defect WLT1; Figure 5 Defect WLT2 appears on the character line labeled 502, so the address AR502 is represented as a defect The address of the first defect of WLT2. Figure 5 Defect PT1 appears at the intersection of the bit line labeled 100 and the character line labeled 390, so the address (AC100, AR390) is represented as the address of the defect PT1; Figure 5 Defect PT2 appears at the intersection of the label 130 The intersection of the bit line and the character line labeled 510, so the address (AC130, AR510) is represented as the address of the defect PT2. Therefore, in this embodiment, the first defect count value CR1~CR3 is set to "3", the first defect count value CR4 is set to "88", the second defect count value CC1~CC2, CC11~CC16 is set to "0", The second defect count value CC3~CC5, CC9~CC10 are set to "2", the second defect count value CC6 is set to "521" and the second defect count value CC7~CC8 is set to "3".

6A and 6B are flowcharts illustrating a defect analysis method of a semiconductor device according to another embodiment of the invention. Step S300 in FIG. 6A is each step S310 to step S350 in the defect analysis method described in FIG. The selected first block corresponding to the relatively small first defect count value CR1~CR4 in 1~220-4 and the first defect address group corresponding to the selected first block are compared with the selected first block The first blocks 220-1 to 220-4 adjacent to the first block are classified in the first direction defect form (this embodiment is "bit line defect form"). Those who apply this embodiment can refer to the aforementioned Figure 2 Similar to the embodiment in FIG. 3, details are not repeated here.

The main difference between step S300 in FIG. 6A and the defect analysis method described in FIG. 3 is that if it is determined in step S335 to be the last first block, step S335 in FIG. 6A proceeds to step S605 in FIG. For example, "Bit line routing direction") to use the selected second block corresponding to the relatively small second defect count value CC1~CC16 in each second block 230-1~230-16, and The defect address group corresponding to the selected second block is used to perform defect forms on the second blocks 230-1~230-16 adjacent to the selected second block (in this embodiment, "character line Defect form") classification.

After step S300 in FIG. 6A, the first defect address groups corresponding to the adjacent first blocks 220-1 to 220-3 in FIG. 5 are the first addresses AC83, AC90, and AC95, so the first addresses AC83, AC90 , AC95 is the first address after comparison. The first blocks 220-1 to 220-3 are also adjacent to the first block 220-4. However, since the first defect count value CC4 "88" corresponding to the first block 220-4 is higher than the M "3", this embodiment will ignore the first defect corresponding to the first block 220-4. The address group, and it is determined that the second defective address group corresponding to the first block 220-4 already contains the first compared first address. In this way, the processor records the aforementioned compared first addresses (ie, the first addresses AC83, AC90, AC95) as the first direction defect form ("bit line defect form") in the test area 510.

Here, each step S610 to step S650 in step S605 in FIG. 6B will be described in detail. In step 610, the processor divides the test area 510 of FIG. 5 into a plurality of second blocks (eg, blocks 230-1 to 230-16) according to the second direction (the wiring direction of the bit line). In this embodiment, the first direction (the wiring direction of the word lines) and the second direction (the wiring direction of the bit lines) are not parallel to each other. In step S620, the processor records the N second defect addresses of the defects in each second block 230-1~230-16 to obtain the defect bits corresponding to each second block 230-1~230-16 Address groups, and the processor counts the number of defects in each second block 230-1~230-16 to obtain the second defect count value CC1~CC16 corresponding to each second block 230-1~230-16 . N is a positive integer. The value of "N" in this embodiment is determined by the person applying this embodiment, and the value of "N" can be determined by the average or maximum value of the number of defects that frequently occur in semiconductor testing, so as to record each The number of addresses in the second defective address group corresponding to the two blocks 230-1 to 230-16 can avoid too many addresses recorded in the second defective address group.

Through step S620, the second defect address group corresponding to the second block 230-1~230-2, 230-11~230-16 is an empty set; the second block 230-3~230-5, 230- The second defect address group corresponding to 9~230-10 is the second address AR400 (defect WLT1), AR502 (defect WLT2); because of the second defect count value CC6 "521" corresponding to the second block 230-6 It is higher than the N "3", so this embodiment will ignore the second defect address group corresponding to the second block 230-6 and directly identify the second defect address group corresponding to the second block 230-6 The address group already contains the compared second address; the second defective address group corresponding to the second block 230-7 is the second address AR390 (defect PT1), AR400 (defect WLT1), AR502 (defect WLT2) ); The second defect address group corresponding to the second block 230-8 is the second address AR400 (defect WLT1), AR502 (defect WLT2), AR510 (defect PT2).

In step S630, the processor sequentially determines whether the second count value of the defect corresponding to the second block to be processed in each of the second blocks 230-1 to 230-16 is less than or equal to N (this embodiment is "3 』) and not zero. When the second defect count value corresponding to the second block to be processed is greater than N or the aforementioned second defect count value is zero, it means that the second block to be processed will not be set as the selected second block. From step S630 to steps S635 and S637, the second block to be processed is moved to the next second block, and step S630 is performed again to determine whether the second block to be processed is the selected second block. In this embodiment, since the second defect count values CC1~CC2 corresponding to the second blocks 230-1~230-6 are all 0, the second block to be processed is moved to the next block 230-3 Take it as the block to be processed. Since the defect count value CC3 (the value "2") corresponding to the block to be processed in FIG. 5 (block 230-3) is less than or equal to N ("3" in this embodiment) and not zero, the second area Block 230-3 is set as the selected second block.

In step S640, the processor determines whether the second defective address groups corresponding to the second blocks adjacent to the selected second block (block 230-3) have the same compared second block Two addresses, and the processor determines whether the number of the second blocks adjacent to the selected second block (block 230-3) is greater than the second predetermined adjacent value. The "second preset neighbor value" in this embodiment is used to determine whether there are multiple defects in adjacent blocks that have multiple cells with continuity and extensibility, and whether these defects are along the character line WL The wiring direction is generated, so as to determine whether it is in the form of a character line defect. In this embodiment, the "second preset neighbor value" is set to 3. Those who apply this embodiment can adjust the second preset neighbor value according to their needs.

The processor of this embodiment determines in step S640 that the blocks (for example, the second blocks 230-3~230-10) adjacent to the selected second block (block 230-3) in FIG. 5 The corresponding defective address groups have the same compared addresses, that is, the second addresses AR400 and AR502. In addition, the processor also determines the number of second blocks (second blocks 230-3~230-10) adjacent to the selected second block (block 230-3) in step S640 ("8 ") is greater than the second preset adjacent value ("3"). Therefore, from step S640 to step S650, the processor records the aforementioned compared second addresses AR400 and AR502 as the second direction defect form ("character line defect form") in the test area 510.

After performing step S300 and step S605, it proceeds to step S690, and the processor also compares the first address (the first address AC83, AC90, AC95 in this embodiment) that was compared in step S300 with the second At least one intersection position where the addresses (the second addresses AR400 and AR502 in this embodiment) intersect is recorded as the form of the intersection defect in the test area 510. In this embodiment, there are a total of 6 intersections (AC83, AR400), (AC90, AR400), (AC95, AR400), (AC83, AR502), (AC90, AR502) and (AC95, AR502) at the aforementioned intersection. In this embodiment, these intersections are recorded as defects in the form of intersection defects.

In summary, the embodiment of the present invention uses the word line direction and the bit line direction of the memory layout to divide the test area into a plurality of blocks, and uses the smaller defect count values corresponding to each block The selected block and the defect address group corresponding to the selected block are used to classify other blocks adjacent to the selected block in the form of defects, so through a small number of address comparisons, more frequent occurrences can be judged Defect form (for example, bit line (BL) defect form, word line (WL) defect form, cross defect form), and can be judged by recording the defect form of the compared address from the foregoing comparison The occurrence point of the cross defect form (ie, the corresponding address of the cross defect form). In this way, the embodiment of the present invention can save the calculation time of defect analysis through the aforementioned method.

100: Electronic devices that analyze defects in semiconductor devices 105: Semiconductor components 110: Defect detection device 120: Defect analysis device 130: processor 140: memory 210, 410, 510: test area for semiconductor components 215: Unit 240, 250, 440, 450, 540, 550: field 220-1~220-4: the first area/area 230-1~230-16: second area/area S300, S310~S350, S605~S609: Steps of the defect analysis method of semiconductor devices CR1~CR4: first defect count value/defect count value CC1~CC16: second defect count value/defect count value WL: Character line BL: bit line PT1~PT2, BLT1~BLT3, WLT1~WLT2: defects AC130, AC140, AC83, AC90, AC95: first address/address AR61, AR120, AR400, AR502: second address/address X: X axis direction Y: Y axis direction

FIG. 1 is a block diagram of an electronic device for analyzing defects in a semiconductor device according to an embodiment of the present invention. 2 is a schematic diagram of a test area and related statistical information in a semiconductor component according to the first embodiment of the present invention. FIG. 3 is a flowchart illustrating a defect analysis method of a semiconductor device according to an embodiment of the present invention. 4 is a schematic diagram of a test area and related statistical information in a semiconductor component according to a second embodiment of the present invention. FIG. 5 is a schematic diagram of a test area and related statistical information in a semiconductor component according to a third embodiment of the present invention. 6A and 6B are flowcharts illustrating a defect analysis method of a semiconductor device according to another embodiment of the invention.

S310~S350: The steps of the defect analysis method of semiconductor devices

Claims (10)

A defect analysis method of a semiconductor device includes: Dividing a test area in a semiconductor component into a plurality of first blocks according to a first direction; Record M first defect addresses of defects in each first block to obtain a first defect address group corresponding to each first block, and count the number of defects in each first block To obtain a first defect count value corresponding to each first block, where M is a positive integer; Determine in sequence whether the first defect count value corresponding to a first block to be processed in each first block is less than or equal to the M and not zero, and is corresponding to the first block to be processed Setting the first block to be processed as a selected first block when the first defect count value is less than or equal to the M and not zero; Determine whether the first defective address groups corresponding to the first blocks adjacent to the selected first block have the same compared first address, and determine whether it is the same as the first defective address group Whether the number of the first blocks adjacent to the selected first block is greater than a first predetermined adjacent value; and The first address groups corresponding to the first blocks adjacent to the selected first block have the same compared first address, and the adjacent ones When the number of the first blocks is greater than the first predetermined adjacent value, the compared first address is recorded as a first direction defect form in the test area to analyze the defect distribution in the test area . The defect analysis method as described in claim 1, further including: Dividing the test area into a plurality of second blocks according to a second direction, wherein the first direction and the second direction are not parallel to each other; Record N second defect addresses of defects in each second block to obtain a second defect address group corresponding to each second block, and count the number of these defects in each second block To obtain a second defect count value corresponding to each second block, where N is a positive integer; Determine in sequence whether the second defect count corresponding to a second block to be processed in each second block is less than or equal to the N and not zero, and whether the second defect count corresponding to the second block to be processed is Setting the second block to be processed as a selected second block when the second defect count value is less than or equal to the N and not zero; Determine whether the second defective address groups corresponding to the second blocks adjacent to the selected second block have the same compared second address, and determine whether it is the same as the selected second address. Whether the number of the second blocks adjacent to the two blocks is greater than a second predetermined adjacent value; and The second address groups corresponding to the second blocks adjacent to the selected second block have the same compared second address, and the adjacent first When the number of the two blocks is greater than the second predetermined adjacent value, the compared second address is recorded as a second direction defect form in the test area. The defect analysis method according to claim 2, wherein the at least one first defect address and the compared first address are used to indicate the number of wiring of the defects in the first area in the second direction , The at least one second defect address and the compared second address are used to indicate the number of the defect in the second area wired in the first direction, The defect analysis method also includes: A cross position where the compared first address meets the compared second address is recorded as a cross defect form in the test area. The defect analysis method according to claim 2, wherein the first direction is a wiring direction of at least one character line in a memory layout, and the second direction is a wiring direction of at least one bit line in the memory layout direction. The defect analysis method according to claim 4, wherein the semiconductor component is a memory device using the memory layout, and the at least one first defect address and the compared first address use the at least one bit The number of the element line is presented, and the at least one second defect address and the compared second address are presented using the number of the at least one character line. An electronic device for analyzing defects in a semiconductor device, including: A defect detection device for judging a defect in a semiconductor component to generate defect information; and A defect analysis device coupled to the defect detection device, wherein the defect analysis device includes a processor, The processor divides a test area in the semiconductor component into a plurality of first blocks according to a first direction, The processor records the M first defect addresses of defects in each first block according to the defect information to obtain a first defect address group corresponding to each first block, and counts each first defect address group The number of the defects in the block to obtain a first defect count value corresponding to each first block, where M is a positive integer, The processor sequentially determines whether the first defect count value corresponding to a first block to be processed in each first block is less than or equal to the M and not zero, and in the first block to be processed When the corresponding first defect count value is less than or equal to the M and not zero, the first block to be processed is set as a selected first block, The processor determines whether the first defective address group corresponding to the first blocks adjacent to the selected first block has the same compared first address, and determines Whether the number of the first blocks adjacent to the selected first block is greater than a first predetermined adjacent value, The first address groups corresponding to the first blocks adjacent to the selected first block have the same compared first address and the adjacent first address groups When the number of a block is greater than the first predetermined adjacent value, the processor records the compared first address as a first direction defect form in the test area to analyze the defects in the test area distributed. The electronic device according to claim 6, wherein the processor further divides the test area into a plurality of second blocks according to a second direction, wherein the first direction and the second direction are not parallel to each other, The processor records the N second defect addresses of defects in each second block to obtain a second defect address group corresponding to each second block, and counts the number of these in each second block The number of defects to obtain a second defect count corresponding to each second block, where N is a positive integer, The processor sequentially determines whether the second defect count corresponding to a second block to be processed in each second block is less than or equal to the N and not zero, and in the second block to be processed When the corresponding second defect count value is less than or equal to the N and not zero, the second block to be processed is set as a selected second block, The processor judges whether the second defective address group corresponding to the second blocks adjacent to the selected second block has the same compared second address, and judges the same Whether the number of the second blocks adjacent to the selected second block is greater than a second predetermined adjacent value, The second address groups corresponding to the second blocks adjacent to the selected second block have the same compared second address, and the adjacent first When the number of the two blocks is greater than the second predetermined adjacent value, the processor records the compared second address as a second direction defect form in the test area. The electronic device according to claim 7, wherein the at least one first defect address and the compared first address are used to indicate the number of wiring of the defects in the first area in the second direction, The at least one second defect address and the compared second address are used to indicate the numbered position of the defect in the second area that is routed in the first direction, The processor also records a cross position where the compared first address and the compared second address meet as a cross defect form in the test area. The electronic device according to claim 7, wherein the first direction is a wiring direction of at least one character line in a memory layout, and the second direction is a wiring direction of at least one bit line in the memory layout . The electronic device according to claim 9, wherein the semiconductor component is a memory device using the memory layout, and the at least one first defect address and the compared first address use the at least one bit The number of the line is presented, and the at least one second defect address and the compared second address are presented using the number of the at least one character line.

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