JP2004077564A - Judging system for mask defect and method for judging mask defect - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a judging system for mask defects and a method for judging mask defects by which the conditions for judging mask defects can be optimized and the detection sensitivity of a mask defect detecting device can be optimized. <P>SOLUTION: The system includes: a layout design block 1 to layout a plurality of mask defects with different insertion positions and sizes on an inspection photomask; a measuring block 7 to measure the electric characteristics of a semiconductor device on which mask defects are transferred from the inspection photomask and to obtain the failure map indicating positions of semiconductor devices showing electric failure; and a calculating block 17 of judging conditions to compare the coordinate values of the layout of the mask defects with the coordinate values of the position in the failure map and to total the mask defects inducing electric failure in terms of the size to calculate the judging conditions for mask defects. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to defect management of a photomask, and more particularly to a mask defect determination system and a mask defect determination method for a photomask.
[0002]
[Prior art]
Various shapes and sizes of mask defects are introduced on a photomask for manufacturing a semiconductor device by a photomask manufacturing process. These mask defects may be transferred from the photomask and affect not only the pattern of the semiconductor device but also the electrical characteristics of the semiconductor device. In the manufacture and management of photomasks, mask defects that cause electrical failure in semiconductor devices are not allowed. Therefore, in a mask defect inspection performed by a mask defect inspection apparatus for a photomask, when a mask defect formed on a photomask is transferred to a semiconductor device, it is important that a mask defect determination condition to determine that an electrical defect is caused is caused. Become. For example, when the mask defect determination condition for the mask defect size is made strict and the detection sensitivity is increased, a mask defect having a smaller size is detected by the mask defect inspection apparatus. In this case, there is almost no oversight of a mask defect that causes an electrical failure in the semiconductor device. However, there is a high possibility that the mask defect inspection device has excessive detection sensitivity. When the production control of the photomask is performed under the mask defect determination condition with excessive detection sensitivity, the yield is reduced, the production cost is increased, and the production period is prolonged. In addition, a mask defect inspection apparatus with high detection sensitivity that meets excessively severe mask defect determination conditions is required, and equipment costs increase. Conversely, if the mask defect determination conditions are relaxed, it is highly possible that a mask defect that causes a defect in a semiconductor device is overlooked in a mask defect inspection of a manufactured photomask, and a defective photomask is provided for semiconductor device manufacturing. As a result, the manufacturing yield of the semiconductor device is reduced, the manufacturing cost is increased, and the manufacturing period is prolonged. Conventionally, mask defect determination conditions have been obtained by simulation. However, the reliability of the mask defect determination condition determined by the simulation is not high, and as a result, the mask defect inspection apparatus has been operated in a state where the detection sensitivity is excessive.
[0003]
[Problems to be solved by the invention]
As described above, in mask defect inspection of a photomask, it is difficult to optimize a mask defect determination condition of a mask defect that causes an electrical failure in a semiconductor device and to optimize a detection sensitivity of a mask defect inspection apparatus. Met.
[0004]
An object of the present invention is to solve such problems and to provide a mask defect determination system and a mask defect determination method for a photomask that can optimize mask defect determination conditions and optimize detection sensitivity of a mask defect device. I do.
[0005]
[Means for Solving the Problems]
In order to solve the above problems, a first feature of the present invention is (a) a layout design block for arranging a plurality of mask defects having different insertion positions and sizes on an inspection photomask; A measurement block that measures the electrical characteristics of the semiconductor device to which the defect has been transferred and obtains a defect map indicating the position of the semiconductor device indicating an electrical defect; and (c) the arrangement coordinates of the mask defect and the position of the defect map The gist of the present invention is a mask defect determination system including a determination condition calculation block that compares coordinate values and tabulates mask defects that cause electrical failure with respect to size to calculate a mask defect determination condition.
[0006]
According to the first aspect of the present invention, it is possible to provide a mask defect determination system capable of optimizing a mask defect determination condition and optimizing a detection sensitivity of a mask defect device.
[0007]
A second feature of the present invention is that (a) a step of forming a mask drawing data by inserting a plurality of program defects having different insertion positions and sizes into layout data of a semiconductor device, and (b) a mask of a plurality of program defects. Calculating the position coordinates on the drawing data to create program defect information; and (c) producing an inspection photomask having a mask defect in which the program defect has been transferred from the mask drawing data, and measuring the size of the mask defect. And (d) fabricating a semiconductor device having a device defect in which a mask defect has been transferred from an inspection photomask, measuring the electrical characteristics of the semiconductor device, and forming a defect map indicating the position of the electrically defective semiconductor device. The step of creating and (e) comparing the program defect information with the position coordinate value of the defect map, And summarized in that a defect by summing the size is a mask defect determination process and a step of calculating a mask defect determination conditions.
[0008]
According to the second feature of the present invention, it is possible to provide a mask defect determination method capable of optimizing a mask defect determination condition and optimizing a detection sensitivity of a mask defect device.
[0009]
In the first and second aspects of the present invention, a mask defect occurring on a product photomask for newly manufacturing a semiconductor device product can be determined based on a mask defect determination condition. In addition, the relationship between the size of a new mask defect placed on a new photomask and the dimensional change rate of a new semiconductor device pattern caused by the new mask defect is calculated, and the dimensional change rate corresponding to the mask defect determination condition is calculated. Calculating the mask defect determination condition of a new photomask based on the relationship between the dimensional change rate of the pattern of the new semiconductor device caused by the new mask defect and the mask of the semiconductor device photomask by different design rules and processes. Defect judgment conditions can be easily calculated by simulation. Further, it is preferable that the mask defects are respectively arranged in circuit portions that are electrically independent from each other in a circuit including a semiconductor device. In addition, a danger point where the circuit operation is likely to fluctuate due to a change in the pattern shape of the circuit composed of the semiconductor device and a danger point where the pattern of the semiconductor device is likely to have a defective shape are extracted. Simulation of the output signal of a circuit in the case where a dangerous portion in which the device pattern is likely to have a defective shape becomes an electrical defect, and determining an electrical defect in the dangerous portion based on the output signal simulates a semiconductor device that is randomly arranged. A similar effect can be obtained for a photomask for use. Further, by detecting a device defect corresponding to the mask defect of the semiconductor device to which the mask defect has been transferred from the inspection photomask, and calculating the optimum sensitivity of the wafer defect inspection apparatus using the mask defect determination condition, the wafer defect inspection is performed. The detection sensitivity of the device can be grasped quantitatively, and the optimum detection sensitivity can be set. Further, by previously calculating the corresponding coordinate values of the coordinates of the inspection photomask and the semiconductor device, the correspondence between the mask defect and the defect map can be simplified.
[0010]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, first and second embodiments of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the shape and the plane size, the ratio of the thickness of each layer, and the like are different from actual ones. Therefore, specific thicknesses and dimensions should be determined in consideration of the following description. In addition, it is needless to say that the drawings include portions having different dimensional relationships and ratios.
[0011]
(First Embodiment)
In the first embodiment of the present invention, a semiconductor memory product having a regular repeating pattern will be described as an example of a semiconductor device.
[0012]
As shown in FIG. 1, a mask defect determination system according to a first embodiment of the present invention includes: a layout design block 1 for creating mask drawing data of a photomask based on layout data of a semiconductor device; Is transferred to a light-shielding film made of metal or the like on a transparent substrate surface made of quartz or the like to perform a mask defect inspection block 3 of a photomask manufactured, and a semiconductor device is formed by transferring a photomask pattern onto a wafer. Wafer defect inspection block 5 for performing a device defect inspection of a semiconductor device manufactured by a manufacturing process; measurement block 7 for measuring an electrical characteristic of a semiconductor device formed on a wafer; layout data and measurement of layout design block 1 A mask defect determination condition is calculated from the electrical measurement result of block 7 and the calculated mask is determined. And a determination condition calculation block 9 for outputting Recessed determination condition in the mask defect inspection blocks 3 and wafer defect inspection block 5.
[0013]
The layout design block 1 includes a layout design editing device 11 and a program defect storage unit 13. The layout design editing apparatus 11 outputs mask drawing data for producing a photomask created from the layout data of the semiconductor memory to a pattern drawing apparatus for a photomask such as an electron beam (EB) drawing apparatus. Further, the layout design / editing apparatus 11 arranges a plurality of types and sizes of program defects in the semiconductor memory layout to artificially introduce mask defects on the inspection photomask, and arranges the arranged program defects on the mask drawing pattern. The coordinate values are stored in the program defect storage unit 13 as program defect information. Further, the layout design / editing apparatus 11 converts the coordinate values of the program defect on the mask drawing pattern into the coordinate system of the inspection photomask on which the mask drawing pattern is transferred, and the wafer (semiconductor substrate) on which the semiconductor memory pattern is transferred from the inspection photomask. And the result is added to the program defect information stored in the program defect storage unit 13 and stored.
[0014]
The mask defect inspection block 3 includes a mask defect inspection device 17, a mask defect storage unit 19, and a mask defect optimum sensitivity calculation unit 21. The mask defect inspection apparatus 17 performs a mask defect inspection of a photomask manufactured based on mask drawing data. Further, the mask defect inspection apparatus 17 stores the result of the mask defect inspection performed on the inspection photomask in the mask defect storage unit 19 in order to grasp the mask defect detection sensitivity. The mask defect optimum sensitivity calculation unit 21 compares the coordinates of the mask defect stored in the mask defect storage unit 19 with the program defect included in the program defect information stored in the program defect storage unit 13, and calculates the mask defect detection sensitivity. Is calculated.
[0015]
The wafer defect inspection block 5 includes a wafer defect inspection device 23, a wafer defect storage unit 25, and a wafer defect optimum sensitivity calculation unit 27. The wafer defect inspection device 23 performs a device defect inspection of the semiconductor memory formed on the wafer using the produced photomask. Further, the wafer defect inspection device 23 stores the device defect inspection result for the semiconductor memory manufactured using the inspection photomask in the wafer defect storage unit 25 in order to grasp the device detection sensitivity. The wafer defect optimum sensitivity calculation unit 27 compares the coordinates of the device defect stored in the wafer defect storage unit 25 and the program defect included in the program defect information stored in the program defect storage unit 13 to obtain the wafer defect detection sensitivity. Is calculated.
[0016]
The pattern dimension measuring device 15 measures the size of a mask pattern or a mask defect of a photomask and the size of a device defect of a semiconductor memory, and stores them in addition to the program defect information stored in the program defect storage unit 13.
[0017]
The measurement block 7 includes an electric tester 29, a shape classification device 31, and an electric test result storage unit 33. The electric tester 29 measures electric characteristics of the manufactured semiconductor memory cell array. In addition, for a semiconductor memory manufactured using the inspection photomask, the electrical tester 29 acquires a bit address of a memory cell indicating an electrical failure as a fail bitmap. The shape classifying device 31 classifies the fail bit map obtained by the electrical tester 29 into a defective shape, and stores the classified fail bit map in the electrical test result storage unit 33.
[0018]
The determination condition calculation block 9 includes a mask defect determination condition calculation unit 35, a display unit 37, a mask defect determination condition conversion unit 39, and a process simulator 41. The mask defect determination condition calculation unit 35 compares the program defect information stored in the program defect storage unit 13 with the classification fail bit map stored in the electrical test result storage unit 33, and determines whether an electrical failure has occurred on the semiconductor device. Then, the type and size of the program defect causing the error are extracted, and the result is displayed on the display unit 37. Further, the mask defect determination condition conversion unit 39 calculates a dimensional change rate of the defect based on a comparison between the sizes of the mask defect and the device defect. The process simulator 41 and the mask defect determination condition conversion unit 39 determine mask defect determination conditions in different design rules and processes based on the calculated dimensional change rates.
[0019]
In the first embodiment of the present invention, first, a semiconductor device manufacturing process is performed using an inspection photomask manufactured by intentionally inserting a program defect into layout data. Correspondence is made between the map of the electrical failure obtained from the electrical characteristic measurement of the manufactured semiconductor device and the program defect, and the mask defect determination condition is determined.
[0020]
According to the mask defect determination system according to the first embodiment of the present invention, it is possible to derive the type and size of a mask defect of a photomask that causes an electrical failure in a semiconductor device, so that the optimum mask defect determination is performed. Conditions can be determined.
[0021]
In the photomask defect determination method according to the first embodiment of the present invention, for example, as shown in FIG. 3, program defects are classified according to the arrangement location. FIG. 3A shows a program defect 101a formed in the center of the space of the wiring pattern 105 in a line and space pattern of a semiconductor memory, and is referred to as a defect type A. FIG. 3B shows a program defect 101b formed at the center of the line of the wiring pattern 105, and is referred to as a defect type B. FIG. 3C shows a program defect 101c formed so as to be in contact with the line pattern in a space portion of the wiring pattern 105, and is referred to as a defect type C. FIG. 3D shows a program defect 101d which is arranged at a line portion of the wiring pattern 105 so as to be in contact with the line end, and is referred to as a defect type D. Further, the defect types A to D corresponding to the program defects 101a to 101d are classified according to their sizes. For example, as shown in FIG. 4, defect types A to D are classified into six types of program defect sizes 1 to 6, and 24 types of defect types A1 to A6, B1 to B6, C1 to C6, and D1 to D6. Is done.
[0022]
Here, the shapes of the defect types on the photomask include a black defect to which an unnecessary pattern is added, such as defect types A and C, and a pattern in which the pattern is partially missing, such as defect types B and D. White defects. A black defect does not form an image on a wafer unless there is a wiring pattern around it, or becomes an isolated pattern even if it forms an image. However, if there is a wiring pattern in the vicinity, the wiring size on the wafer increases. If the white defect is in a wiring pattern having a large width, it will only make a hole in the wiring on the wafer, but if it is located at the end of the wiring pattern, it will reduce the wiring size on the wafer. In FIG. 3, both the program defect and the black defect and the white defect are arranged at the center of the wiring pattern and at a position in contact with the end of the wiring pattern, but may be arranged at an intermediate point between the center and the end of the wiring pattern. That is, of course. Furthermore, although the outer shape is described as a square, other shapes such as a rectangle, a circle, and an ellipse may be used, and it is a matter of course that these various outer shapes may be mixed.
[0023]
As described above, a plurality of program defects are created by changing the defect type and the defect size. Since the size of a program defect generated on a layout and the size of a mask defect formed on a photomask from the program defect are generally different, the size of the program defect needs to be set to a sufficiently wide range. As shown in FIG. 5, a program defect 101 including defect types A1 to A6, B1 to B6, C1 to C6, and D1 to D6 is placed on a chip area 107 of a semiconductor memory layout, and the respective program defects 101 Insert so that there is no electrical interference. For example, one program defect 101 is inserted into one word line or bit line pattern of a semiconductor memory. Further, the insertion positions of the program defects 101 are set at a sufficient interval of, for example, 100 μm or more on the semiconductor device so that shortage failure does not cause shortage of power supply capacity and the like and can be recognized as individual defects. As shown in FIG. 5, the program defects 101 are arranged, for example, on a diagonal line of a chip area 107 on a semiconductor memory layout.
[0024]
In addition, the layout design editing apparatus 11 calculates in advance the coordinate system conversion to the mask defect inspection apparatus 17, the wafer defect inspection apparatus 23, and the electrical tester 29 for the position of the program defect 101 on the mask drawing data. . The coordinate systems of the mask defect inspection device 17 and the wafer defect inspection device 23 are both XY coordinate systems. For example, as shown in FIG. 5, the position coordinates of the program defect 101 are determined using the position of the lower left corner of the chip area 107 where the program defect 101 is arranged as the origin.
[0025]
As shown in FIG. 6, the inspection photomask 113 is formed by arranging a chip region 117 having a mask defect and a chip region 119 having no mask defect in which the mask defects 111 are arranged. The mask defect 111 formed from the defect type A1 of the program defect 101 is, for example, (x _A1 , Y _A1 ).
[0026]
For example, it is assumed that a stepper having a reduction ratio of 4: 1 is used as the exposure apparatus. As shown in FIG. 7A, the pattern of the inspection photomask 113 is transferred to the shot area on the wafer 123 in a step-and-repeat reduced to a quarter. As a result, the plurality of chips 127 having device defects and the chips 129 having no device defects are arranged in pairs. Therefore, the coordinates of the wafer defect inspection device 23 determine the chip position coordinates of each device defect chip 127 within the wafer, using, for example, one of the device defect chips 127 at the upper right end of the wafer 123 as the origin chip. As in the case of the mask defect 111, the coordinates of the device defect 121 in the chip 127 having the device defect are determined using the position of the lower left corner of the chip 127 having the device defect as the origin. For example, as shown in FIG. 7B, the coordinates of the device defect 121a formed from the defect type A1 of the program defect 101 are obtained. In the coordinate system of the wafer defect inspection apparatus 23, the coordinate of the origin of the i-th device defect chip 127i is (X _i , Y _i ). The coordinates of the device defect 121a in the chip 127i having the device defect are (x _A1 / 4, y _A1 / 4), the device defect 121a of the i-th device defective chip 127i in the wafer 123 has the coordinates (x _A1 / 4 + X _i , Y _A1 / 4 + Y _i ).
[0027]
On the other hand, the electric tester 29 uses a bitmap coordinate system representing addresses of a memory. The positions of the memory cells of the memory cell array arranged in a matrix on the chip 127 having the device defect or the chip 129 having no device defect are designated by the row address and the column address of the memory cell array. Since the position of the program defect 101 is not completely one-to-one converted to the bitmap coordinate system, an allowable range is provided as necessary, and specified by, for example, two or three row and column addresses surrounding the program defect 101. Is done.
[0028]
The fail bit map obtained from the electrical measurement result of the electrical tester 29 is classified by the shape classification device 31 into a failure classification mode according to the shape such as a bit defect, a row defect, a column defect, a cross defect, or a block defect. The classification fail bitmap classified in the failure classification mode has a start address and an end address, and expresses a position and a size. Here, the bit failure is a failure classification mode caused by, for example, a defect of the memory cell capacitor, the row failure and the column failure are caused by a defect of the row wiring and the column wiring, and the cross failure is caused by a defect of the MOS transistor gate. On the other hand, the block failure is a failure classification mode due to a cause other than the target process.
[0029]
For example, in a semiconductor memory manufactured using an inspection photomask 113 for forming a gate oxide film, for example, a mask defect 111 is transferred to form a device defect 121 in a gate oxide film of a MOS transistor of a memory cell, and the MOS transistor operates. Suppose that it becomes bad. In a MOS transistor of a memory cell, a gate electrode is connected in a matrix by, for example, a row wiring and a drain electrode is connected by a column wiring. Therefore, as shown in FIG. 8A, the shape of the appearing electrical failure is a cross-shaped fail bit map centered on the defective memory cell 135 of the MOS transistor with the operation failure. As shown in FIG. 8B, the classification fail bit map is represented by a start address RS and an end address RE of a row address, and a start address CS and an end address CE of a column address. Therefore, the defect classification mode to be subjected to the mask defect inspection differs depending on the layer or location where the program defect is created, and the defect classification mode that is not likely to be caused by the mask defect 111 of the inspection photomask 113 is deleted from the shape classification result.
[0030]
A method of determining a photomask defect according to the first embodiment of the present invention will be described with reference to FIG. 1 by taking a semiconductor memory as an example and following the procedures of steps S201 to S211 in FIG.
[0031]
(A) In step S201, the layout design / editing device 11 artificially inserts a program defect into the memory cell array portion of the layout data of the semiconductor memory product whose operation has been confirmed.
[0032]
(B) In step S202, mask drawing data for producing an inspection photomask is created from the layout data into which the program defect 101 shown in FIG. 5 has been inserted. As the mask drawing data, a chip layout with a program defect in which the program defect 101 is arranged and a chip layout without a program defect without a program defect are prepared.
[0033]
(C) In step S203, the layout design editing apparatus 11 converts the position of the program defect 101 on the mask drawing data into the coordinate system of the mask defect inspection apparatus 17, the wafer defect inspection apparatus 23, and the electrical tester 29, respectively. Is calculated in advance. The calculation results of the coordinate conversion to each of the mask defect inspection device 17, the wafer defect inspection device 23, and the electrical tester 29 performed in advance for each program defect 101 are stored in the program defect storage unit 13 as the program defect information. .
[0034]
(D) In step S204, the inspection photomask 113 is manufactured in a mask manufacturing process based on the mask drawing data. An EB drawing device or the like is used for drawing the inspection photomask 113. For example, mask drawing data of a chip layout with a program defect and a chip layout without a program defect are transferred onto a resist on the surface of a light-shielding film made of a metal such as chromium (Cr) formed on a transparent substrate made of quartz or the like. . The light-shielding film is selectively removed by selective etching such as reactive ion etching (RIE) using the transferred resist pattern as a mask, and as shown in FIG. 117 and a chip region 119 without a mask defect are formed, and an inspection photomask 113 is manufactured.
[0035]
(E) In step S205, the size of the mask defect 111 formed on the inspection photomask 113 is measured by the pattern dimension measuring device 15. To specify the location of the mask defect 111 caused by the program defect 101 on the inspection photomask 113, the pattern dimension measuring device 15 acquires program defect information from the program defect storage unit 13. The measured size of the mask defect 111 on the inspection photomask 113 is stored in the program defect storage unit 13 in addition to the program defect information. The size of the mask defect 111 may not be measured due to the relationship between the mask manufacturing process and the resolution of the pattern dimension measuring device 15. In that case, it is not necessary to enter the size in the program defect information.
[0036]
(F) In step S206, using the inspection photomask 113, a semiconductor device manufacturing process including a memory cell capacitor forming process, a metal oxide semiconductor (MOS) transistor forming process, a wiring process, and the like is performed. It is formed on the wafer 123. Here, except for the process in which the inspection photomask 113 to be inspected is used, a normal product photomask for manufacturing a semiconductor memory is used.
[0037]
(G) In step S207, in the test step of inspecting the electrical characteristics of the semiconductor memory product formed on the wafer 123, the electrical tester 29 creates a fail bitmap indicating the address of the electrically defective memory cell. You. The fail bit map may be created for a chip having a device defect having a device defect 121 caused by the program defect 101, and it is not necessary to create a fail bit map for a chip having no device defect.
[0038]
(H) In step S208, the obtained fail bitmap is classified by the shape classification device 31 into a failure classification mode according to the shape. The classification fail bitmap classified in the failure classification mode is stored in the electrical test result storage unit 33 as a classification fail bitmap.
[0039]
(I) In step S209, the mask defect determination condition calculation unit 35 compares the coordinates of the mask defect 111 and the classification fail bit map acquired from the program defect storage unit 13 and the electrical test result storage unit 33. Since the coordinate values of the fail bitmap in the coordinate system are stored in the program defect 101 in advance in step S203, coordinate conversion is not required. Normally, as shown in FIG. 7, there are a plurality of chips 127 having a device defect on the wafer 123, and the coordinates of all the chips 127 having a device defect are compared. If it is determined in the coordinate comparison that there is a classification fail bitmap at the location of the mask defect 111, a flag is set for the mask defect 111.
[0040]
(V) In step S210, the mask defect determination condition calculation unit 35 counts the mask defects 111 for which the flag is raised in the coordinate comparison for each defect type, calculates an electrical failure rate, and generates a size histogram for each defect type. Created. For example, FIG. 9A shows the relationship between the actual size of the mask defect 111 on the inspection photomask 113 and the electrical failure rate for the defect type A, and FIG. .
[0041]
(G) In step S211, the size of the mask defect that causes an electrical failure in the semiconductor memory formed on the wafer 123 is specified based on the size histogram calculated by the mask defect determination condition calculation unit 35. For example, for the defect types A and B, as shown in FIG. 9A or 9B, the mask defect size W at which the defect rate becomes completely zero. _CA Or W _CB Are obtained, and these values are used as mask defect determination conditions. Information such as a size histogram and a mask defect determination condition for each defect type is displayed on the display unit 37. Further, by changing exposure conditions such as an exposure amount and a focus in the transfer process of the inspection photomask 113 in step S206, and repeating steps S207 to S210, a mask defect determination condition in consideration of a change in the exposure condition is calculated. .
[0042]
The inspection and management of the mask defect of the manufactured product photomask is performed by applying the mask defect determination condition calculated in this way. The inspection sensitivity of the mask defect inspection apparatus 17 is optimized so that a mask defect larger than the mask defect size in the mask defect determination condition can be detected. The mask defect detected on the product photomask is re-inspected using an optical microscope or the like by using the mask defect inspection device 17 having the optimized inspection sensitivity, and the review is performed. Based on the review, the detected mask defects are classified into correctable mask defects and uncorrectable mask defects. The uncorrectable mask defect includes, for example, a mask defect generated at a corner of a mask pattern. A product photomask having only a mask defect that can be repaired is repaired using a photomask repair device, and a product photomask having an uncorrectable defect is discarded as a defective product.
[0043]
According to the mask defect determination method according to the first embodiment of the present invention, it is possible to determine an optimum mask defect determination condition for a mask defect of a photomask that causes an electrical failure in a semiconductor device.
[0044]
Next, the method of quantifying the mask defect inspection sensitivity and the method of setting the optimum sensitivity according to the first embodiment of the present invention will be described with reference to FIGS. 1 and 6 according to the procedure of steps S221 to S224 shown in FIG. I do.
[0045]
(A) In step S221, the mask defect inspection device 17 inspects the inspection photomask 113 manufactured as described above for the mask defect 111. The mask defect inspection result is stored in the mask defect storage unit 19. The mask defect inspection and the storage of the mask defect inspection result are performed for the same inspection photomask 113 a plurality of times.
[0046]
(B) In step S222, the mask defect optimum sensitivity calculation unit 21 compares the coordinates of the mask defect inspection result obtained by the mask defect inspection device 17 with the program defect acquired from the program defect information in the program defect storage unit 13. .
[0047]
(C) In step S223, a size histogram of the detection rate of the mask defect 111 calculated for each defect type with respect to the actual size of the mask defect 111 on the inspection photomask 113 is created. The created size histogram is displayed on the display unit 37.
[0048]
(D) In step S224, the detection sensitivity for the mask defect size of the mask defect inspection device 17 is quantitatively grasped based on the calculated size histogram. Further, the calculated size histogram is compared with the mask defect determination condition calculated by the mask defect determination method according to the first embodiment of the present invention, and the detection sensitivity of the mask defect inspection device 17 is examined. For example, when a mask defect with a size larger than the mask defect determination condition is not detected, “insufficient detection sensitivity” is used. When a mask defect with a size smaller than the mask defect determination condition is detected, “excessive detection sensitivity” is used. If the size of the detection mask defect is the same as that of the detection mask defect, it is determined that “detection sensitivity is optimal”. If the detection sensitivity is insufficient, readjustment of the mask defect inspection device 17 is performed, or development of the mask defect inspection device 17 is performed. If the detection sensitivity is excessive, there is no adverse effect on the semiconductor device, but the yield of the product photomask may be reduced, so that the detection sensitivity of the mask defect inspection device 17 is reduced.
[0049]
According to the method for quantifying the mask defect inspection sensitivity and the method for setting the optimum sensitivity according to the first embodiment of the present invention, the detection sensitivity of the mask defect inspection apparatus can be quantitatively grasped, and the optimum detection sensitivity can be set. Can be.
[0050]
Next, the quantification of the detection sensitivity and the optimum sensitivity setting of the wafer defect inspection apparatus 23 according to the first embodiment of the present invention will be described with reference to FIGS. 1 and 7 and steps S231 to S234 shown in FIG. It will be explained according to the procedure.
[0051]
(A) In step S231, the wafer defect inspection device 23 inspects the device defect 121 of the semiconductor device formed on the wafer 123. Usually, the device defect 121 is greatly deformed from the mask defect 111 by the semiconductor device manufacturing process. For example, a pattern which is transferred from the defect type A such as an isolated mask defect 111 between the wiring patterns 115 shown in FIG. As shown in (b), the device defect 121 is absorbed by the wiring 125 to form a projection. In addition, a concave portion is formed in the wiring 125 from the defect type B in which a hole is formed in the wiring pattern. The device defect size is the wiring width W of the wiring 125. _L Indicates the maximum or minimum wiring width fluctuated due to a device defect. _D As | W _L -W _D | The device defect inspection is performed by comparing the chip 127 with a device defect and the chip 129 without a device defect. The wafer defect inspection result is stored in the wafer defect storage unit 25. The wafer defect inspection and the storage of the wafer inspection defect result are performed a plurality of times for the semiconductor memory of the same wafer 123.
[0052]
(B) In step S232, the wafer defect optimum sensitivity calculation unit 27 compares the coordinates of the wafer defect inspection result obtained by the wafer defect inspection device 23 with the program defect acquired from the program defect information in the program defect storage unit 13. .
[0053]
(C) In step S233, a size histogram of the detection rate of the device defect 121 calculated for each defect type is created for the actual size of the device defect 121 of the semiconductor device on the wafer 123. The created size histogram is displayed on the display unit 37.
[0054]
(D) In step S234, the detection sensitivity for the device defect size of the wafer defect inspection apparatus 23 is quantitatively grasped based on the calculated size histogram. Further, the calculated size histogram is compared with the mask defect determination condition calculated by the mask defect determination method according to the first embodiment of the present invention, and the detection sensitivity of the wafer defect inspection device 23 is examined. For example, when the device defect 121 corresponding to the mask defect 111 having a size larger than the mask defect determination condition is not detected, “insufficient detection sensitivity” is detected, and the device defect corresponding to the mask defect smaller than the mask defect determination condition is detected. In this case, “excessive detection sensitivity” is determined, and when the mask defect determination condition and the size of the mask defect corresponding to the detected device defect are the same, it is determined that “detection sensitivity is optimal”. If the detection sensitivity is insufficient, readjustment of the wafer defect inspection device 23 is performed, or development of the wafer defect inspection device 23 is performed. If the detection sensitivity is excessive, the detection sensitivity of the wafer defect inspection device 23 is reduced.
[0055]
According to the method for quantifying the wafer defect detection sensitivity and the method for setting the optimum sensitivity according to the first embodiment of the present invention, the detection sensitivity of the wafer defect inspection apparatus can be grasped quantitatively and the optimum detection sensitivity can be set. Can be.
[0056]
According to the first embodiment of the present invention, it is possible to derive the type and size of a mask defect that causes an electrical defect in a wafer and determine the optimum mask defect determination condition. Further, it is possible to quantify the defect detection rates of the mask defect inspection device and the wafer defect inspection device. By optimizing the conditions for judging mask defects that are too severe, it can be expected to improve the yield of product photomasks, shorten the turn around time (TAT), and reduce the manufacturing cost. In addition, by optimizing the conditions for determining a mask defect that is too loose, a product photomask that causes electrical failure in a semiconductor device formed on a wafer can be extracted by inspection.
[0057]
(Application example)
An application example of the first embodiment of the present invention is a method of converting the mask defect determination conditions of the photomask defect determination method described above into mask defect determination conditions in different design rules and processes. The other parts are the same as those of the first embodiment, and the duplicated description will be omitted.
[0058]
A method of converting a mask defect determination condition according to an application of the first embodiment of the present invention will be described according to the procedure of steps S241 to S244 in FIG. As described in the first embodiment, it is assumed that the mask defect size of the inspection photomask 113 and the device defect size of the semiconductor memory manufactured by the inspection photomask 113 have already been measured by the pattern dimension measuring device 15. . Here, the semiconductor device manufacturing process already performed using the inspection photomask 113 is described as “process A”, and the semiconductor device manufacturing process performed according to a new design rule is described as “process B”.
[0059]
Mask defect size W _m Is defined as the square root of the area of the mask defect 111 formed on the inspection photomask 113. The dimensional change rate ε is defined as a rate at which the pattern size of the semiconductor device changes due to the device defect 121. For example, a description will be given using a defect type A shown in FIG. 13A. As shown in FIG. _L Is the defective wiring width W due to the device defect 121. _D And a swelling shape. Device defect size | W _L -W _D | Defines the dimensional change rate ε (%) as
ε = (| W _L − W _D ｜ / W _L ) ・ 100 (1)
Is represented by
[0060]
(A) First, in step S241 in FIG. 12, the mask defect determination condition conversion unit 39 uses the mask defect size W for each mask defect type. _m And the dimensional change rate ε are calculated. For example, for the defect type A, as shown in FIG. _m And a graph of the dimensional change rate ε are created.
[0061]
(B) In step S242, the relationship between the mask defect determination condition (spec) of the process A and the dimensional variation rate ε is calculated. Mask defect size W shown in FIG. _m1 Is the mask defect determination condition size W already determined. _CA (See FIG. 9A), and the mask defect size W _m1 Is the critical dimension variation rate ε corresponding to ₁ It becomes. That is, the dimensional change rate ε is equal to the critical dimensional change rate ε. ₁ Larger means that the semiconductor device becomes electrically defective.
[0062]
(C) In step S243, for the process B, the relationship between the mask defect size and the dimensional variation rate is calculated by the process simulator 41 for each defect type. For example, suppose that a result as shown in FIG.
[0063]
(D) Critical dimensional change rate ε at which devices become electrically defective even if design rules and processes are changed ₁ Is assumed to be constant. In step S244, the critical dimension change rate ε in process B ₁ Defect size W corresponding to _m2 Is calculated. This W _m2 Is the mask defect determination condition size of the defect type A in the process B.
[0064]
As an application example of the first embodiment of the present invention, the case where the design rule of the semiconductor device is changed has been described. However, the size of the mask defect determination condition also changes when the target process is changed. It goes without saying that a method of converting the size of the defect determination condition can be applied.
[0065]
According to the application example of the first embodiment of the present invention, even if the design rule or the manufacturing process of the semiconductor device is changed, the mask defect determination condition can be appropriately converted, and the mask and wafer defect inspection apparatus can be applied. The semiconductor device generation can be expanded, and unnecessary development of a mask and a wafer defect inspection apparatus becomes unnecessary.
[0066]
(Second embodiment)
The mask defect determination method according to the second embodiment of the present invention is an example applied to a photomask for manufacturing a semiconductor logic circuit. A semiconductor logic circuit does not have a regular pattern as in a memory cell array portion of a semiconductor memory, but basically has a random pattern. Further, a semiconductor memory product can obtain a fail bitmap including a physical position in an electrical test process, but it is difficult for a semiconductor logic circuit product to identify an electrical defect position in a chip.
[0067]
As shown in FIG. 16, the mask defect determination system according to the second embodiment of the present invention simulates a risky portion with respect to the circuit behavior and the pattern shape of the semiconductor logic circuit based on the semiconductor logic circuit data and the layout data. The points including the simulator block 2 to be extracted, the layout design editing block 1a for arranging the program defect at the extracted dangerous spot, and the measurement block 7a for measuring the electrical characteristics of the semiconductor logic circuit formed on the wafer are first described. This is different from the first embodiment described above. The other parts are the same as those of the first embodiment, and the duplicated description will be omitted.
[0068]
The simulator block 2 includes a circuit simulator 51, a lithography simulator 53, and a failure simulator 55. The circuit simulator 51 simulates a semiconductor logic circuit based on the logic circuit data and the layout data, and extracts a dangerous location where the behavior of the circuit is likely to change. The lithography simulator 53 simulates photolithography based on the layout data and extracts a dangerous portion where a pattern having a desired size or shape is difficult to be formed. Further, the failure simulator 55 simulates a semiconductor logic circuit in the case where a dangerous part causes an electrical failure based on the simulation results of the circuit simulator 51 and the lithography simulator 53, extracts a pattern of an output signal, and creates a failure dictionary. create.
[0069]
The layout design editing block 1a includes a layout design editing device 11a and a program defect storage unit 13. The layout design / editing device 11a arranges program defects in the dangerous data extracted by the simulations of the circuit simulator 51 and the lithography simulator 53 in the layout data of the semiconductor logic circuit, and creates mask drawing data of the inspection photomask. Further, the layout design editing apparatus 11a stores the coordinate value of the arranged program defect on the mask drawing pattern in the program defect storage unit 13 as program defect information.
[0070]
The measurement block 7a includes an electrical tester 29a, a failure determination device 57, and an electrical test result storage unit 33a. The electrical tester 29a measures electrical characteristics of a semiconductor logic circuit formed on a wafer. The failure determination device 57 determines from the electrical test result of the electrical tester 29a and the failure dictionary acquired from the failure simulator 55 whether or not the dangerous place where the program defect is located causes an electrical failure, and creates a classified failure map. The classification failure map is stored in the electrical test result storage unit 33a.
[0071]
According to the mask defect determination system according to the second embodiment of the present invention, it is possible to derive the type and size of a mask defect of a photomask that causes an electrical failure even in a semiconductor logic circuit, so that an optimum mask defect can be obtained. Determination conditions can be determined.
[0072]
Next, a method of determining a mask defect according to the second embodiment of the present invention will be described with reference to FIG. 16 and in accordance with the procedure of steps S251 to S263 shown in FIG.
[0073]
(A) In step S251, the circuit simulator 51 reads the logic circuit data and the layout data of the semiconductor logic circuit, and extracts a dangerous part where the behavior of the circuit is likely to change due to a change in the semiconductor device dimensions on the wafer.
[0074]
(B) In step S252, the layout data is read by the lithography simulator 53, and a danger point where a semiconductor device pattern having a desired size and shape is difficult to be formed on the wafer is extracted from the lithography model.
[0075]
(C) In step S253, the layout design / editing apparatus 11 arranges the program defect at the dangerous spot extracted from the circuit simulator 51 and the lithography simulator 53, and creates mask drawing data.
[0076]
(D) In step S254, the failure simulator 55 acquires the dangerous spot extracted from the circuit simulator 51 and the lithography simulator 53, and combines the dangerous spot with the circuit data to determine the short circuit or open fault of the dangerous spot. The output signal is simulated. In this way, an output signal pattern for discriminating between a case where a dangerous place where a program defect is arranged causes an electrical failure and a case where an electrical failure does not occur is extracted. The extracted output signal pattern and the coordinates of the program defect are collected as a failure dictionary. At this time, if there are a plurality of dangerous points, a dangerous point is selected so that the quality of each of the dangerous points can be identified. This is because if the output results of the circuits are the same regardless of the different dangerous locations, it becomes impossible to specify which dangerous location has become defective.
[0077]
(E) In step S255, mask drawing data for producing an inspection photomask is created based on the layout data in which the program defects are arranged. As the mask drawing data, a chip layout with a program defect where a program defect is arranged and a chip layout without a program defect without a program defect are prepared.
[0078]
(F) In step S256, the layout design editing device 11a uses the mask defect inspection device 17, the wafer defect inspection device 23, and the electrical tester 29 for the positions of the program defects on the mask drawing data for producing the inspection photomask. The calculation of the coordinate system conversion into is performed in advance. In the second embodiment, the coordinate systems of the mask defect inspection device 17, the wafer defect inspection device 23, and the electrical tester 29 are all processed in the XY coordinate system. The calculation result of the coordinate system conversion is stored in the program defect storage unit 13 as program defect information.
[0079]
(G) In step S257, an inspection photomask is created based on the mask drawing data using a mask manufacturing process.
[0080]
(H) In step S258, the size of the mask defect formed on the inspection photomask is measured by the pattern dimension measuring device 15. In order to identify the location of a mask defect caused by a program defect on the inspection photomask, the pattern dimension measuring device 15 acquires program defect information from the program defect storage unit 13. The measured size of the mask defect on the inspection photomask is stored in the program defect storage unit 13 in addition to the program defect information.
[0081]
(I) In step S259, a semiconductor device manufacturing process is performed using the inspection photomask, and a semiconductor logic circuit product is formed on the wafer. Here, in processes other than the process in which the inspection photomask to be inspected is used, a normal product photomask for manufacturing a semiconductor logic circuit product is used.
[0082]
(V) In step S260, the electrical characteristics of the semiconductor logic circuit are measured by the electrical tester 29 in a test process for inspecting the electrical characteristics of the semiconductor logic circuit formed on the wafer.
[0083]
(G) In step S261, the failure determination device 57 determines the dangerous location where the program defect is located on the wafer and the electrical failure position from the failure dictionary acquired from the failure simulator 55 and the electrical test result of the semiconductor logic circuit. A coordinate comparison is performed. If it is determined in the coordinate comparison that there is a failure at the location of the mask defect, a flag is set at the mask defect position. The failure determination result is stored in the electrical test result storage unit 33a.
[0084]
(ヲ) In step S262, the mask defect determination condition calculation unit 35 performs a coordinate comparison, counts the mask defects flagged for each defect type, and calculates an electrical failure rate. From the result, a size histogram is created for each defect type.
[0085]
(W) In step S263, a mask defect size that causes an electrical failure in the semiconductor logic circuit formed on the wafer is specified by the created size histogram.
[0086]
In the first embodiment of the present invention, the fail bit map and the coordinates of the program defect are compared in order to judge the electrical good / bad of the mask defect location. In the case of a semiconductor logic circuit product, a similar determination is made from the electrical test result and the failure dictionary, a size histogram is created for each defect type, and a mask defect determination condition is calculated.
[0087]
According to the mask defect determination method according to the second embodiment of the present invention, it is possible to determine the optimum determination condition for a photomask defect that causes an electrical failure in a semiconductor device.
[0088]
(Other embodiments)
As described above, the first and second embodiments of the present invention have been described. However, it should not be understood that the description and drawings constituting a part of this disclosure limit the present invention. From this disclosure, various alternative embodiments, examples, and operation techniques will be apparent to those skilled in the art.
[0089]
In the first and second embodiments of the present invention, description has been made using a semiconductor memory and a semiconductor logic circuit as a semiconductor device. However, other semiconductor devices, for example, a semiconductor logic circuit and a semiconductor memory mixed circuit, Of course, a semiconductor analog circuit or the like may be used. In addition, as the exposure apparatus, a reduction projection exposure apparatus such as a stepper or an aligner having a reduction ratio of 1: 4 has been described, but other reduction ratios may be used as the reduction projection exposure apparatus, or a contact exposure method, Of course, an exposure apparatus of a proximity exposure system, a projection exposure system, or the like may be used.
[0090]
As described above, the present invention naturally includes various embodiments and the like not described herein. Therefore, the technical scope of the present invention is defined only by the matters specifying the invention according to the claims that are appropriate from the above description.
[0091]
【The invention's effect】
ADVANTAGE OF THE INVENTION According to the present invention, a mask defect determination system and mask defect of a photomask which can improve the yield of photomask production, reduce cost, or shorten the production period by optimizing the mask defect determination condition and the detection sensitivity of the mask defect device. A determination method can be provided.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of a mask defect determination system according to a first embodiment of the present invention.
FIG. 2 is a flowchart illustrating a mask defect determination method according to the first embodiment of the present invention.
FIG. 3 is a diagram illustrating an example of an arrangement of program defects according to the first embodiment of the present invention.
FIG. 4 is a diagram for explaining a defect type of a program defect according to the first embodiment of the present invention.
FIG. 5 is a diagram illustrating an example of mask drawing data according to the first embodiment of the present invention.
FIG. 6 is a view showing an inspection photomask according to the first embodiment of the present invention.
FIG. 7 is a diagram showing a shot area on a wafer according to the first embodiment of the present invention.
FIG. 8 is a diagram illustrating a fail bit map according to the first embodiment of the present invention.
FIG. 9 is a diagram showing a mask defect size histogram according to the first embodiment of the present invention.
FIG. 10
5 is a flowchart illustrating a sensitivity setting method of the mask defect inspection device according to the first embodiment of the present invention.
FIG. 11
4 is a flowchart illustrating a sensitivity setting method of the wafer defect inspection apparatus according to the first embodiment of the present invention.
FIG.
9 is a flowchart illustrating a method of converting a mask defect determination condition according to an application example of the first embodiment of the present invention.
FIG. 13
FIG. 3 is a diagram illustrating an example of a mask defect and a device defect according to the first embodiment of the present invention.
FIG. 14
FIG. 8 is a diagram illustrating an example of a relationship between a mask defect and a dimensional variation rate according to an application example of the first embodiment of the present invention.
FIG.
FIG. 9 is a diagram illustrating another example of the relationship between the mask defect and the dimensional variation rate according to the application example of the first embodiment of the present invention.
FIG.
FIG. 9 is a configuration diagram of a mask defect determination system according to a second embodiment of the present invention.
FIG.
9 is a flowchart illustrating a mask defect determination method according to a second embodiment of the present invention.
[Explanation of symbols]
1, 1a Layout design editing block
2 Simulator block
3 Mask defect inspection block
5 Wafer defect inspection block
7, 7a Measurement block
9 Judgment condition calculation block
11, 11a Layout design editing device
13 Program defect storage
15 Pattern dimension measuring device
17 Mask defect inspection equipment
19 Mask defect storage
21 Mask Defect Optimal Sensitivity Calculator
23 Wafer defect inspection equipment
25 Wafer defect storage
27 Wafer Defect Optimal Sensitivity Calculator
29, 29a Electrical tester
31 Shape Classifier
33, 33a Electrical test result storage unit
35 Mask Defect Determination Condition Calculation Unit
37 Display
39 mask defect judgment condition converter
41 Process Simulator
51 Circuit Simulator
53 Lithography Simulator
55 Failure Simulator
57 Failure judgment device
101, 101a to 101d Program defect
105, 115 Wiring pattern
107 chip area
111 Mask defect
113 Inspection Photomask
117 Chip area with mask defect
119 Chip area without mask defect
121, 121a Device defect
123 wafer
125 wiring
127, 127i Device defective chip
129 Device defect-free chip
135 Bad memory cell

Claims (16)

A layout design block for arranging a plurality of mask defects having different insertion positions and sizes on the inspection photomask;
A measurement block for measuring the electrical characteristics of the semiconductor device to which the mask defect has been transferred from the inspection photomask, and acquiring a defect map indicating the position of the semiconductor device indicating an electric defect,
A determination condition calculation block for comparing the arrangement coordinate value of the mask defect with the position coordinate value of the defect map, tabulating the mask defect causing the electrical defect with respect to the size, and calculating a mask defect determination condition. A mask defect determination system. The mask defect determination system according to claim 1, further comprising a mask defect inspection block for detecting a mask defect generated on a product photomask for newly manufacturing a semiconductor device according to the mask defect determination condition. A process simulator that calculates a relationship between a size of a new mask defect arranged on a new photomask and a dimensional change rate of a pattern of a new semiconductor device caused by the new mask defect,
A mask defect for calculating a mask defect determination condition of the new photomask from a relationship between a dimensional variation rate corresponding to the mask defect determination condition and a dimensional variation rate of the new semiconductor device pattern caused by the new mask defect; The mask defect determination system according to claim 1, further comprising a determination condition conversion unit. The mask defect determination system according to claim 1, wherein the mask defects are respectively arranged in circuit portions that are electrically independent of each other in a circuit including the semiconductor device. A first danger point where the operation of the circuit is liable to fluctuate due to a change in the pattern shape of the circuit comprising the semiconductor device, and a second danger point where the pattern of the semiconductor device is liable to have a defective shape are extracted. The mask defect determination system according to any one of claims 1 to 4, further comprising a simulator block for simulating an output signal of the circuit when a second dangerous part becomes electrically defective. The measurement block includes a failure determination device that determines an electrical failure of a circuit portion of the circuit including the semiconductor device corresponding to the first and second dangerous points based on an output signal obtained by the simulation. The mask defect determination system according to claim 5, wherein: A wafer defect for detecting a device defect corresponding to the mask defect of the semiconductor device to which the mask defect has been transferred from the inspection photomask, and calculating an optimum sensitivity for detecting the device defect using the mask defect determination condition; 7. The mask defect determination system according to claim 1, further comprising an inspection block. 8. The mask defect determination according to claim 1, wherein the layout design block includes a program defect storage unit that stores a corresponding coordinate value between the inspection photomask and the coordinates of the semiconductor device. 9. system. Creating mask drawing data by inserting a plurality of program defects having different insertion positions and sizes into the layout data of the semiconductor device;
A step of calculating position coordinates of the plurality of program defects on the mask drawing data to create program defect information;
Producing an inspection photomask having a mask defect in which the program defect has been transferred from the mask drawing data, and measuring the size of the mask defect;
A semiconductor device having a device defect in which the mask defect has been transferred from the inspection photomask is manufactured, and an electrical characteristic of the semiconductor device is measured to create a failure map indicating a position of the semiconductor device having an electrical failure. Process and
Comparing the program defect information with the position coordinate values of the defect map, and calculating mask defect determination conditions by totalizing the mask defects that cause an electrical defect with respect to size. The method according to claim 9, further comprising a step of detecting a mask defect occurring on a product photomask for newly manufacturing a semiconductor device according to the mask defect determination condition. Calculating a relationship between the size of the mask defect in the new photomask and the dimensional change rate of the pattern of the new semiconductor device caused by the mask defect;
Calculating a mask defect determination condition of the new photomask from a relationship between a dimensional change rate corresponding to the mask defect determination condition and a dimensional change rate of the new semiconductor device pattern caused by the mask defect. The method according to claim 9, wherein the mask defect is determined. The method according to any one of claims 9 to 11, wherein the mask defects are formed in circuit portions of the circuit made of the semiconductor device that are electrically independent from each other. Extracting a first dangerous location where the electrical characteristics of the circuit comprising the semiconductor device are likely to fluctuate;
Extracting a second dangerous spot where a desired pattern of the semiconductor device is difficult to be formed,
The method according to claim 9, wherein the program defect is inserted into the first and second dangerous locations. 14. The circuit according to claim 13, further comprising: simulating an output signal of the circuit in the case where the first and second danger points cause an electrical failure; 3. The method for determining a mask defect according to item 1. Detecting a device defect corresponding to the mask defect of the semiconductor device to which the mask defect has been transferred from the inspection photomask;
The method according to any one of claims 9 to 14, further comprising: calculating an optimum sensitivity of the device defect detection using the mask defect determination condition. The method according to any one of claims 9 to 15, further comprising a step of storing coordinate values corresponding to the coordinates of the inspection photomask and the semiconductor device.

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