JP2001217294A - Method for finding fundamental cause of failure of faulty chip - Google Patents

Abstract

PROBLEM TO BE SOLVED: To offer a method for finding fundamental causes of failures of a faulty chip by which a larger number of defects which may cause faulty chips can be found. SOLUTION: This invention is to provide a method for finding fundamental causes of failures of a faulty chip. A defect-to-failure matching step is performed according to the characteristics of the defect. This method comprises a step of generating a predicted failure region which can be predicted to be electrically failed due to the defect, and a step of comparing the predicted failure region to be predicted with the real failure region according to the defect. If the predicted failure region which is predicted according to the defect is located within the real failure region, the defect is interpreted to be one of the fundamental causes of the failures of the faulty chip.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of finding the cause of a chip failure by using a computer to find the root cause of a defective chip. And a method of finding a contribution that leads to

[0002]

2. Description of the Related Art The purpose of a semiconductor process is to form a plurality of chips having electrical functions on a semiconductor wafer. Therefore, in the manufacturing process, a specific pattern is repeatedly formed on the surface of the semiconductor wafer, and one chip is formed from each of the repeated patterns. However, an unexpected situation may occur, in which one chip is partially different from the other chips. Such parts that are different from other chips are called defects. For example, when a production line worker touches the surface of a semiconductor wafer, a scratch defect occurs.
Occurs. Further, when particles fall on the surface of the semiconductor wafer, the particles serve as a hard mask in a subsequent etching step, and the material thereunder is not etched, so that a particle defect occurs. These defects are usually associated with erroneous functions and ultimately result in defective chips, thus reducing production line yields. For this reason, semiconductor factories have a very large goal of reducing defects.

[0003] However, not all defects necessarily reduce the yield. For example, if the defect is very small or in an insignificant location, a chip with such a defect can function just like any other chip without defects. Therefore, in order to improve the yield, it is very important to determine what kind of defect leads to a chip failure.
Knowing which defects reduce yield can take some action on such defects. Therefore, finding an association between a defect and a chip failure is an important first step in removing important defects and improving the yield of the production line.

[0004]

In a conventional method for finding defects that lead to a chip failure, a computer is used to compare the location of each defect with an electrically defective area on the defective chip. . However, in this method, the defect is considered to be the root cause of the failure of the chip only when the defect is located in an electrically defective area. For example, a memory chip is tested, and a bit map indicating the position of an electrically defective portion is created. On the other hand,
Defects on the memory chip can be found by scanning during the process. Therefore, a plurality of defect maps can be obtained for one semiconductor wafer depending on which process is to be scanned between the processes. For example, the defect map of the first metal (M1) layer refers to a defect map obtained by performing scanning after forming the pattern of the M1 layer.

In the above-described conventional method, by superimposing the defect map of the M1 layer on the bit map, which of the defects shown in the defect map of the M1 layer has led to the chip as a defect. Can be found. In this case, only the defect in the electrically defective bit is considered to be the root cause of the chip failure. This is called a "hit." However, the hit ratio, that is, the value obtained by dividing the number of defective chips hit by the total number of defective chips, is actually only about 10%.

It should be noted that not all defects necessarily affect the function of the area in which they are located. For example, a memory chip usually includes a memory array region and a peripheral region thereof, and a large number of memory cells contained in the memory array are driven by a driver contained in the peripheral region. Here, if there is a defect in an area of a certain driver, and that driver becomes defective, the memory cell driven by the driver also becomes defective. In this case, the defect
It is clear that this is one of the root causes of the chip failure. However, since the defect is not included in the defective memory array area, the above-described conventional method cannot find a relationship between the defect and a chip defect. As described above, according to the above-described conventional method, it is not possible to sufficiently provide an engineer with information necessary for taking an appropriate measure for a defect.

[0007] In view of the above problems, an object of the present invention is to provide a method for finding the root cause of a defective chip. With the method according to the invention, more defects can be found which lead to chip failure than with the conventional method. Another object of the present invention is to provide an engineer with sufficient information necessary for improving the yield of a production line.

[0008]

SUMMARY OF THE INVENTION To achieve the above objects, the present invention provides a method for finding the root cause of a chip failure. Defective chips are manufactured in a plurality of steps. Further, the defective chip contains at least one defect detected after completing one of the plurality of steps, and one defect is characterized by at least one characteristic. Then, when the defective chip is tested, at least one area that is actually electrically defective is detected. The method for finding the root cause of a defective chip according to the present invention is implemented using a computer and includes the following steps. First, a defect-defective matching process is performed based on the characteristics of each defect.
It is predicted that the defect caused electrical failure,
Generate a poor prediction region. Second, the predicted defective area generated for each defect is compared with an actual electrically defective actual defective area. If the predicted defective area generated based on each defect is located in the actual defective area,
The defect is interpreted as one of the root causes of the failure of the defective chip.

The present invention also provides another method of finding the root cause of a chip failure. A defective chip is manufactured in a plurality of processes, and the defective chip is
It contains at least one defect detected after completing one of the plurality of steps, wherein one defect is characterized by at least one characteristic. When a defective chip is tested, at least one area that is actually electrically defective is detected. Another method for finding the root cause of a defective chip according to the present invention is implemented using a computer and includes the following steps. First, a pattern recognition step is performed to characterize the actual defective area according to the actually defective area and its type.
Second, failure based on the two characteristics of the actual failure area
A defect matching step is performed to generate at least one predicted characteristic region. Third, the characteristics of each defect are compared with the predicted characteristic area. If the characteristics of the defect are within the predicted characteristic range, the defect is interpreted as one of the root causes of the defective chip becoming defective.

[0010]

The above and other objects of the present invention,
In order to clarify the features and advantages, preferred embodiments will be described below in more detail with reference to the drawings. In each of the embodiments described below, the characteristics of a defect include three elements of the position, size, and type of the defect, and the predicted characteristic area of the defect includes a predicted defect area, a predicted defect size area, and a predicted defect type. It consists of three elements. An advantage of the method according to the invention is that, since the three properties of the defect size, location and type are taken into account at the same time, a greater number of defects than those of the prior art can be found which affect the function of the defective chip. For this reason, using the method according to the invention,
Engineers can be provided with useful information necessary for improving production line yield.

The present invention provides a method for finding the root cause of a chip failure using a computer. For simplicity, a memory chip that has become defective in a test will be described below as an example of a defective chip.

FIG. 1 shows a mask used for forming a pattern of a polysilicon layer on a defective chip in the present invention, and FIG. 2 shows a defect and an actual defective area on the defective chip, respectively. In these figures, the defective chip 10
b is manufactured through a plurality of steps such as lithography, etching, and oxidation. Generally, in order to determine the step in which a defect has been formed, it is necessary to add a scanning step after pattern formation of each layer or after removing the photoresist. By comparing the patterns formed on each chip, it is possible to find a defect generated in that layer. Usually, an ID number is assigned to a mask used for pattern formation. The number of each defect means that the defect is a defect that occurred when a pattern was formed using the mask of the ID number. That is, assuming that the number of a certain defect is 130, the defect occurs when the polysilicon layer is patterned by using the mask of the number 130.

FIG. 1 shows a mask of ID 130 used for forming a pattern of a polysilicon layer on a defective chip. The mask 10a of the ID 130 includes the memory array region 12, the x-decoder region 14, and the y-decoder region 1.
6 and so on. The memory array region 12 has a plurality of horizontal word lines for forming a plurality of memory cells. In the figure, columns of the memory array area 12 are 20a to 20d, and rows are 18a to 1d.
8d, for example, the upper leftmost memory cell is described as (18a, 20a). The x-decoder region 14 and the y-decoder region 16 are used to install a driver for driving a memory cell in the memory array region 12. For this reason, the x decoder region 14 and the y decoder region 16
A plurality of small pieces of polysilicon that operate as a gate or system interconnection are formed.

First, when the memory chip is scanned after the formation of the pattern of the polysilicon layer, as shown in FIG. 2, defects 22a to 22f (that is, the defect of number 130) are detected. Here, each of the defects is characterized by at least one characteristic. In this embodiment, the characteristics of the defect include the position, size, and type of the defect. For example, the location is the coordinates of the defect and the size is the approximate size of the defect.
e) and said type is the first source of the defect (origina
l source) or shape. Data relating to each of these defects is identified and recorded by a production line worker or a scanning tool having a pattern recognition function, and finally saved in a computer.

Next, when a function test step is performed, at least one electrically defective real defective area is determined on the defective chip 10b. For example, a column 22 in the memory array area 12 is
It is found that all the memory cells in the column b and the column 22d are defective. In addition, (18a, 20c)
Is also found to be defective. These defective memory cells are represented by hatched square regions as shown in FIG. 2, and are defined as actual defective regions.

[0016] The method according to the invention is implemented using a computer. An object of the present invention is to find a defect that leads to a chip failure. The method according to the invention is characterized by finding defects based on a matching table or a logic rule. On the other hand, in the conventional method, only the influence in the defective area is considered.

FIG. 3 is a flowchart of the first embodiment of the present invention. In the first embodiment of the present invention, a defect which is a real cause of causing a chip to be defective is found by following a possible path from a defect to an actual defective area. Hereinafter, the method according to the first embodiment will be described focusing on one of a plurality of defects on a defective chip.
The method according to the invention can of course be applied to all other defects as well.

First, a defect-defective matching process is performed based on three characteristics of the position, size, and type of the defect, and a prediction is made that the defect is expected to cause an electrical failure. At least one defective area is generated (30). Second, the predicted defective area generated based on the defect is compared with an actual electrically defective actual defective area. If the predicted defective area generated based on the defect is located in the actual defective area, (3
2) The defect is interpreted as one of the root causes of the failure of the defective chip (34). For example, a matching table or logic rule to define a predicted bad region predicted by three characteristics of the position, size, and type of each defect is input to a computer according to mask information and engineer's experience.

For example, the defect 22a in FIG. 2 is a particle type defect having a size of 0.5 μm and located in the field oxide region. However, defects located in the field oxide region usually do not impair the electrical function of the chip. Therefore, the predicted defect area predicted based on the defect 22a is an empty area,
a is not interpreted as the root cause of the failure of the defective chip.

On the other hand, the defect 22d in FIG.
This is a bridge-type defect having a size of 0.3 μm and located in the decoder area. According to a pre-determined matching table or logic rule, the defect 22d is stored in column 18
The memory cell of d may be defective. For this reason,
The predicted defect area predicted based on the defect 22d is an area where the memory cell in the column 18d is located. In this case, since the memory cell in column 18d is included in the actual defective area, this is referred to as "hit", and the defect 22d is interpreted as one of the root causes that led the defective chip to failure. Is done.

For each defect, a predicted defect area and an actual defective area are compared one by one, and a "hit" defect is searched for. Can be found. From the perspective of the entire semiconductor wafer, this method allows to statistically determine how much the yield will be affected by defects in each layer.

Prior to carrying out the method according to the invention, the extent and type of the actual defective area can be defined using a pattern recognition device. By doing so, in the defect-defective matching step, matching can be performed while considering the range and type of the actual defective area. For example, in the defect-defective matching step, for each defect, a type search is performed based on the size and type of the defect, and a defect type in a predicted defective region derived from the defect is predicted. If the defect is of a particle type with a size smaller than 0.1 μm, the defect is simply ignored and processing proceeds to the next defect. In the defect-defective matching step, after performing the type search described above, for each defect, a search for an affected area based on the position of the defect is performed, and a defect range of a predicted defective area derived from the defect is determined. Predict. The defect type of the predicted defect area predicted based on the size and type of the defect is the same as that of the actual defective area, and the predicted defect area predicted based on the defect position is also determined. The defect is interpreted as one of the root causes of the failure of the defective chip only when the range of the defect is located within the actual defective area.

FIG. 4 is a flowchart of the second embodiment of the present invention. In the second embodiment according to the present invention, by tracing a possible path from an actual defective area to a defect, a defect which is a real cause of causing a chip to be defective is found. First, the actual defective area is characterized by the defect range and type of the defective chip using a pattern recognition device (40). Next, a defect-defect matching step is performed based on the defect range and type of the actual defect area,
At least one prediction characteristic area is generated (42). For example, in the present embodiment, the prediction characteristic area includes three elements: a predicted defect area, a predicted defect size area, and a predicted defect type.

Third, the position, size, and type of each defect are compared with the predicted defect area, predicted defect size area, and predicted defect type, respectively. If the characteristics of the defect are included in the predicted characteristic range, the defect is interpreted as one of the root causes that led to the failure of the defective chip. That is, the position and size of the defect
If the defect is included in the predicted defect area and the predicted defect size area, respectively, and the defect type is the same as the predicted defect type (44), the defect causes the defective chip to fail as shown in FIG. Is interpreted as one of the root causes (46). Alternatively, after the pattern recognition step is performed, the actual failure area can be divided into three specific areas by the pattern recognition device. Here, the first specific region is, for example, a defect of a single cell type and the range is (18a, 20c), and the second and third specific regions are, for example, a column type, the ranges of which are column 18b and column 18d is defective.

The matching table or logic rule describes how the real defect area relates to the predicted defect area, predicted defect size area, and predicted defect type on the defective chip.
Can be defined. For example, as a result of checking a matching table or a logic rule, an actual defective area of a single cell type is first identified as the defective cell, that is, the cell (18a, 20a).
and c) having a defect size of 0.3 to
Third, it is determined that a defect has occurred due to a defect that satisfies the condition that any type of defect may be used. Since the defect 22f satisfies all three conditions, it is interpreted as one of the root causes that led the defective chip to failure.

In a similar manner, column 1 on layer 130
The predicted defect area, predicted defect size area, and predicted defect type can be found for the area 8d.
In the present embodiment, the predicted defect area is the column 18d
Wherein the driver for driving the memory is located.
A portion of the decoder region 16, wherein the predicted defect size range is 0.5 to 0.8 μm, and the predicted defect type is a bridge type or a blocked etch. Defect 2
In 2d, the defect type is a bridge type, the size is 0.6 μm, and the position is in the y-decoder 16, and all the predicted conditions are satisfied. For this reason, the defect 22d
Is interpreted as one of the root causes of the failure of the defective chip.

Although the preferred embodiment has been disclosed above,
These in no way limit the scope of the invention,
Anyone skilled in the art should be able to add various variations and colors without departing from the spirit and scope of the present invention.

The defective chip may be a memory chip, an embedded memory chip or a logic chip. input/
Any chip that can test the electrical function at the output port to create a real failure area can be tested using the method according to the present invention.

In the above-described two embodiments, three characteristics are used as the characteristics of the defect. However, even when one characteristic is used, the concept of the present invention can be similarly realized. The point of the present invention is to find the root cause of a chip failure by establishing a relationship between a defect and a defective area. The three characteristics used in the above two embodiments are preferable examples.

[0030]

A feature of the method according to the present invention is that a relationship between a defect and a real defective area is established based on the size, position, and type of the defect. Thus, using the method according to the invention, it is possible to find defects which are responsible for a defective chip. Even if a certain defect is not located in the actual defective area, the method according to the present invention can be used to find out whether the defect affects the function of the defective chip. Therefore, the use of the method according to the present invention can improve the hit ratio, that is, the value obtained by dividing the number of defective chips hit by the total number of defective chips. If the method according to the invention is applied to defects occurring in each layer during the manufacturing process, it is possible to identify in which layer the defects which most adversely affect the yield of the production line occur. Thus, the engineer can improve the yield of the production line by focusing on the identified process and removing defects.

Both the method according to the invention and the conventional method take into account the influence of the location of the defect. The method according to the invention further takes into account the effect of the size and type of the defects. Therefore, using the method according to the present invention, it is possible to find a larger number of defects affecting the defective chip than the conventional method, and to provide engineers with sufficient information useful for improving the production line yield. can do.

[Brief description of the drawings]

FIG. 1 is a view showing a mask used for forming a pattern of a polysilicon layer on a defective chip in the present invention.

FIG. 2 is a diagram showing a defect on a defective chip and an actual defective area in the present invention.

FIG. 3 is a flowchart of the first embodiment of the present invention.

FIG. 4 is a flowchart of a second embodiment of the present invention.

[Explanation of symbols]

 12 memory array area 14 x decoder area 16 y decoder area 20a to 20d columns of memory array area 18a to 18d rows of memory array area

 ──────────────────────────────────────────────────の Continued on the front page (71) Applicant 599002397 Mosel Vitalic Inc., Taiwan, Sinchu, Science-Based Industrial Park, Ricin Road No. 19 (71) Applicant 599002401 Siemens-Ahr Germany, D- 80333, München, Wittelsbacher Platz 2 (72) Inventor Gregory Koni, Hsinchu City, Taiwan, Guanghua, 1st step, 272 F-term (reference) 4M106 AA02 BA14 CA41 CA42 CA43 CA50 DH01 DJ18 DJ20 DJ21 DJ27

Claims (13)

[Claims] Claims: 1. An electronic device comprising at least one defect, characterized by at least one characteristic, manufactured by a plurality of processes and detected after completing one of the plurality of processes, and comprising: A method for finding the cause of a defective semiconductor chip in which at least one defective real defective area is found, and performing a defect-defective matching step based on the characteristics of the defect. Generating a predicted defective area predicted to be electrically defective due to the defect; and comparing the predicted defective area predicted based on the defect with the actual defective area. If the predicted defective area predicted based on the defect is located in the actual defective area, the defect is interpreted as being one of the causes that led to the defective chip. Failure cause discovery methods of chip. 2. The method according to claim 1, wherein the characteristics of the defect include a position of the defect, a size of the defect, and a type of the defect. 3. The method according to claim 2, wherein the real failure area is characterized by a failure type and a failure range. 4. The defect-defective matching step includes performing a type search on the defect based on the size of the defect and the type of the defect, and predicting a defect type of the predicted defective area for the defect. 4. The method according to claim 3, further comprising: performing a search for an affected area based on a position of the defect with respect to the defect, and predicting a defect range of the predicted defective area with respect to the defect. How to find the cause of chip failure. 5. The method according to claim 1, wherein each of the steps is performed by a computer. 6. The method according to claim 1, wherein the defective chip is selected from the group consisting of a memory chip, an embedded memory chip, and a logic chip. 7. The defective chip according to claim 1, wherein the defective chip contains a plurality of memory cells, and the real defective area is used to represent the electrically defective memory cells. How to find the cause of chip failure. 8. The method according to claim 8, wherein the method includes producing at least one defect characterized by at least one characteristic and detecting at least one defect after completing one of the plurality of steps. This is a method for finding the cause of a defective semiconductor chip in which at least one defective real defective area has been found, performing a pattern recognition process, and by performing a defect range and a defect type, Characterizing the actual defect area; performing a defect-defect matching step based on the defect range and the defect type of the actual defect area to generate at least one predicted characteristic area; Comparing the characteristic of the defect with the predicted characteristic region;
When the property of the defect is included in the predicted characteristic area,
The defect is one of the root causes that led the defective chip to failure.
A method for finding the cause of a chip defect, which is interpreted as one. 9. The method according to claim 8, wherein the characteristics of the defect include a position of the defect, a size of the defect, and a type of the defect. 10. The method according to claim 8, wherein the predicted characteristic area includes a predicted defect area, a predicted defect size area, and a predicted defect type. 11. The method according to claim 8, wherein each of the steps is performed by a computer. 12. The method according to claim 8, wherein the defective chip is a memory chip. 13. The semiconductor memory device according to claim 8, wherein said defective chip includes a plurality of memory cells, and said real defective area is used to represent said electrically defective memory cell. How to find the cause of chip failure.