TWI749928B - Composite substrate structure and method for manufacturing the same - Google Patents

Abstract

A composite substrate structure is provided by the present disclosure. The composite substrate includes a first substrate, a first oxide layer, a second substrate, and a porous nanowire layer. The first oxide layer is directly disposed on the first substrate. The second substrate is directly disposed on the first oxide layer. The porous nanowire layer is directly disposed on the second substrate. A method for manufacturing a composite substrate structure is further provided by the present disclosure.

Description

Composite substrate structure and manufacturing method thereof

The present disclosure relates to a composite substrate structure and a manufacturing method thereof, and particularly relates to a composite substrate structure that can relieve stress and a manufacturing method thereof.

With the advancement of the semiconductor integrated circuit (IC) industry, manufacturers need to optimize and improve the manufacturing process to produce products with smaller sizes and better performance. In the semiconductor manufacturing process, the performance of the substrate will affect the subsequent manufacturing process and the quality of IC products. For example, since it is not easy to have large-size homogeneous substrates available for the epitaxy of Group III-V semiconductors, it is generally chosen to perform epitaxial growth on cheap and large-size silicon substrates. However, because the crystal lattices of the third and fifth group semiconductors and the silicon substrate do not match, threading dislocation that extends to the entire surface is prone to occur during epitaxial growth. Moreover, because of the difference between the thermal expansion coefficients of the third and fifth group semiconductors and the substrate, the epitaxial layer cracks during the cooling process after the epitaxial growth. The above two will limit the growth thickness of the epitaxial layer, and the defects and problems they cause will also affect the performance of subsequent devices.

If it is possible to provide a substrate interface with smaller contact for subsequent epitaxial nucleation or insert a thinner insert layer than the epitaxial layer during the epitaxial process, and this thin insert layer can absorb strain, then Improve the effect of stress accumulation or surface cracking caused by epitaxial growth.

In view of the above, there is an urgent need for a composite substrate structure that can solve the above-mentioned problems and a method for forming the composite substrate structure.

In view of this, one objective of the present disclosure is to provide a composite substrate structure that can relieve stress and a manufacturing method thereof.

One aspect of the present disclosure is to provide a composite substrate structure, which includes a first substrate, a first oxide layer, a second substrate, and a porous nanowire layer. The first oxide layer is directly disposed on the first substrate. The second substrate is directly arranged on the first oxide layer. The porous nanowire layer is directly disposed on the second substrate.

According to one or more embodiments of the present disclosure, the composite substrate structure further includes a third substrate and a second oxide layer. The second oxide layer is directly disposed on the porous nanowire layer, and the third substrate is directly disposed on the second oxide layer.

According to one or more embodiments of the present disclosure, the first oxide layer and the second oxide layer each include silicon oxide, gallium oxide, titanium dioxide, or aluminum oxide.

According to one or more embodiments of the present disclosure, the composite substrate structure further includes a filler filled with the porous nanowire layer, and the filler includes air, silicon dioxide, polysilicon or silicon nitride.

According to one or more embodiments of the present disclosure, the diameter of the porous nanowire layer is 50 nanometers to 200 nanometers, and the density of the porous nanowire layer is 20 to 300 nanowires/micrometer square (nanowires/µm ² ).

Another aspect of the present disclosure is to provide a composite substrate structure including a first substrate, a first oxide layer, and a second substrate. The first oxide layer is directly disposed on the first substrate. The second substrate has a first surface and a second surface opposite to each other. The second surface directly contacts the first oxide layer, and the second substrate includes a plurality of grooves recessed from the first surface toward the second surface.

According to one or more embodiments of the present disclosure, each groove has a depth of 300 nm to 5000 nm.

According to one or more embodiments of the present disclosure, the density of the grooves ranges from 10 grooves/micrometer square to 500 grooves/micrometer square.

According to one or more embodiments of the present disclosure, the composite substrate structure further includes a third substrate and a second oxide layer. The second oxide layer is directly disposed on the first surface of the second substrate, and the third substrate is directly disposed on the second oxide layer.

Another aspect of the present disclosure is to provide a method for manufacturing a composite substrate structure, which includes the following operations. A first substrate is provided, and the first substrate has a first surface and a second surface opposite to each other. A porous nanowire layer is formed on the first surface, or a plurality of grooves are formed on the first surface. Provide a second substrate. An oxide layer is formed on the second substrate. The first substrate and the second substrate are joined so that the oxide layer directly contacts the second surface.

In order to make the description of the present disclosure more detailed and complete, the following provides an illustrative description for the implementation aspects and specific embodiments of the present disclosure; this is not the only way to implement or use the specific embodiments of the present disclosure. The embodiments disclosed below can be combined or substituted with each other under beneficial circumstances, and other embodiments can also be added to an embodiment without further description or description.

The following disclosure provides many different embodiments or examples to implement different features of the various embodiments of the disclosure. The following content describes specific examples of each component and its arrangement in order to simplify the description. Of course, these specific examples are not meant to be limiting. The various embodiments of the present disclosure will be described with respect to specific specific embodiments and with reference to certain drawings, but the various embodiments of the present disclosure are not limited to the specific specific embodiments and drawings, but are only limited to the scope of the patent application. The drawings described are only exemplary and non-limiting. In the drawings, for illustrative purposes, the size of some elements may be enlarged and not drawn to scale. The size and relative size do not necessarily correspond to the actual thumbnails used for implementation.

In addition, the terms top, bottom, over, under, and the like in the description and the scope of the patent application are used for the purpose of description, and are not necessarily used to describe relative positions. It should be understood that the terms so used are interchangeable under appropriate circumstances, and the specific embodiments described herein can be operated in other positions than those described or illustrated herein.

It should be noted that the term "comprising" used in the scope of the patent application should not be construed as being limited to the means listed thereafter; it does not exclude other elements or operations. Therefore it is understood to specify the existence or addition of the stated features, wholes, operations or components as mentioned, but does not exclude the existence or addition of one or more other features, wholes, operations or components or groups thereof. Therefore, the description scope of "devices including devices A and B" should not be limited to devices consisting of components A and B only.

One aspect of the present disclosure is to provide a method 10 for manufacturing a composite substrate structure. FIG. 1 shows a flowchart of a method 10 for manufacturing a composite substrate structure according to an embodiment of the present disclosure. It should be understood that additional operations may be performed before, during, and after the method 10, and for additional embodiments of the method 10, some of the operations may be replaced, eliminated, or moved. The method 10 is only an exemplary embodiment, and is not intended to limit the various embodiments of the present disclosure, except as clearly stated in the scope of the patent application. The method 10 for manufacturing a composite substrate structure includes at least operation 110, operation 120, operation 130, operation 140, and operation 150.

In operation 110, a first substrate 210 is provided. In some embodiments of the present disclosure, operation 110 can be further understood with reference to FIG. 2, wherein FIG. 2 is a schematic cross-sectional view of a process stage in the method 10 for manufacturing a composite substrate structure according to an embodiment of the present disclosure. It can be understood that the first substrate 210 has a first surface 211 and a second surface 213 opposite to each other. In various embodiments, the first substrate 210 may be a single crystal silicon substrate, a polycrystalline silicon substrate, a single crystal aluminum nitride substrate, a polycrystalline aluminum nitride substrate, a diamond substrate, a single crystal silicon carbide substrate, a polycrystalline silicon carbide substrate, Single crystal gallium oxide substrate, polycrystalline gallium oxide substrate, single crystal boron nitride substrate or polycrystalline boron nitride substrate.

In various embodiments, after operation 110, the first substrate 210 may be thinned before the surface cleaning is performed. For example, the first substrate 210 can be thinned by grinding and chemical-mechanical polishing (Chemical-Mechanical Planarization, CMP). For another example, the surface of the first substrate 210 can be washed alternately with deionized water and acetone to remove dirt. Then, the first substrate 210 is further immersed in a mixed solution of concentrated sulfuric acid and concentrated hydrogen peroxide at 80° C. for one hour to obtain a first substrate 210 with no environmental contamination attached. In more detail, the volume ratio between concentrated sulfuric acid and concentrated hydrogen peroxide in the mixed solution can be 3:1, so that the mixed solution has better cleaning ability.

The method 10 of manufacturing a composite substrate structure proceeds to operation 120. In some embodiments of the present disclosure, operation 120 can be further understood with reference to FIG. 3, wherein FIG. 3 is a schematic cross-sectional view of a process stage in the method 10 for manufacturing a composite substrate structure according to an embodiment of the present disclosure. In operation 120, a porous nanowire layer 220 is formed on the first surface 211 of the first substrate 210. In many embodiments, the method of forming the porous nanowire layer 220 is specifically as follows.

First, a metal atomic layer is formed to cover the first surface 211 of the first substrate 210 first. In some instances, the coverage of the metal atomic layer is 20 to 300 atoms/micrometer square, for example, 40 atoms/micrometer square, 60 atoms/micrometer square, 70 atoms/micrometer square, 100 atoms/micrometer square, 120 atoms /Micrometer square, 140 atoms/micrometer square, 160 atoms/micrometer square, 170 atoms/micrometer square, 200 atoms/micrometer square, 220 atoms/micrometer square, 240 atoms/micrometer square, 260 atoms/micrometer square or 270 atoms/micrometer square. In some embodiments, the metal atomic layer may be formed on the first surface 211 of the first substrate 210 by suitable physical vapor deposition such as evaporation and sputtering. In many examples, the metal atomic layer includes silver (Ag), gold (Au), or copper (Cu). In many examples, the thickness of the metal atomic layer is about 10 nanometers to 50 nanometers, such as 15 nanometers, 20 nanometers, 25 nanometers, 30 nanometers, 35 nanometers, 40 nanometers, or 45 nanometers. . It is worth mentioning that, in the present disclosure, a very thin layer of metal atoms is plated on the first surface 211 of the first substrate 210 by evaporation or sputtering, so that the metal atoms are naturally deposited on the first substrate 210. A porous network structure is formed on the first surface 211. In other words, the metal atomic layer actually partially covers the first surface 211 of the first substrate 210 in operation. Therefore, the thickness of the metal atomic layer needs to be controlled. If the thickness of the metal atomic layer is less than a certain value, such as 10 nanometers, the first substrate 210 to be etched later will form a porous structure instead of the desired porous nanowire layer; if the thickness of the metal atomic layer is More than a certain value, such as 50 nanometers, will make it difficult for the subsequent etching solution used to etch the first substrate 210 to penetrate the metal atomic layer, and it will be more difficult for the first substrate 210 to form a uniform porous nanowire layer.

Then, the first substrate 210 is etched to form a porous nanowire layer 220 on the first surface 211 of the first substrate 210. It should be noted that the metal atoms in the metal atom layer can induce the etching solution to etch the first substrate 210 thereunder, and the metal atoms are still attached to the etched surface. Furthermore, the first surface 211 of the first substrate 210 has a partial area covered by metal atoms, and the metal atoms are used as a catalyst to be etched downward, while the area not covered by metal atoms will not be etched downward. Down etching.

In various embodiments, the porous nanowire layer 220 includes silicon, silicon germanium, or group III-V semiconductor materials. For example, the above-mentioned Group III and V semiconductor materials include indium phosphide, indium arsenide, gallium arsenide, or gallium phosphide. In many embodiments, the diameter D of the porous nanowire layer 220 is about 50 nanometers to 200 nanometers, for example, it can be 60 nanometers, 70 nanometers, 70 nanometers, 80 nanometers, 100 nanometers, 110nm, 120nm, 130nm, 140nm, 150nm, 160nm, 170nm, 170nm or 180nm. In many embodiments, the density of the porous nanowire layer 220 is 20 to 300 nanowires/micrometer square (nanowires/µm ² ), for example, 40 nanowires/micrometer square, 60 nanowires/micrometer square, 70 nanometer wire/micrometer square, 100 nanometer wire/micrometer square, 120 nanometer wire/micrometer square, 140 nanometer wire/micrometer square, 160 nanometer wire/micrometer square, 170 nanometer wire/micrometer square, 200 nanometer Meter wire/micrometer square, 220 nanometer wire/micrometer square, 240 nanometer wire/micrometer square, 260 nanometer wire/micrometer square or 270 nanometer wire/micrometer square.

For example, the present disclosure uses a sputtering machine to grow a silver film with a thickness of about 20-30 nanometers on the clean first surface 211 of the first substrate 210 in an argon atmosphere. Then, the first substrate 210 with the silver thin film is immersed in an etching solution to perform isotropic wet etching to form a porous nanowire layer 220. For example, the etching solution may be a mixed solution of hydrofluoric acid (concentration of about 0.44M) and hydrogen peroxide (concentration of about 4.6M). It should be noted that the length and diameter of the nanowire in the porous nanowire layer 220 can be determined by the time immersed in the etching solution. For example, when the immersion time in the etching solution is about 35 seconds, the length of the nanowire is about 450 nanometers and its diameter is about 50 to 200 nanometers.

For another example, a metal sputtering machine can also be used to grow a gold film or a copper film on the clean first surface 211 of the first substrate 210. Then, the first substrate 210 with the gold film or the copper film is also immersed in an etching solution to perform isotropic wet etching to form a porous nanowire layer 220.

Finally, the first substrate 210 and the porous nanowire layer 220 are cleaned. In one example, deionized water may be used to rinse the first substrate 210 and the porous nanowire layer 220, and then the first cleaning solution and the second cleaning solution may be used in turn to rinse the first substrate 210 and the porous nanowire layer 220 to Removal of metal atom (for example, silver atom, gold atom, or copper atom) residues. For example, the first cleaning solution may be a mixed solution prepared with a volume ratio of 2:1:5 in the volume ratio of ammonia, hydrogen peroxide solution and water; and the second cleaning solution may be hydrochloric acid, hydrogen peroxide solution and water. The volume ratio is a mixed solution prepared at a ratio of 2:1:8. Finally, the first substrate 210 and the porous nanowire layer 220 are cleaned again with deionized water to remove the above-mentioned cleaning solution, and air-dried with nitrogen gas to obtain the first substrate 210 with the porous nanowire layer 220 on the surface.

Figure 4A is a top view image of the porous nanowire layer 220 according to one embodiment of the disclosure. FIG. 4B is a cross-sectional image diagram of the porous nanowire layer 220 according to an embodiment of the disclosure. After operation 120, the obtained porous nanowire layer 220 can be specifically shown in FIG. 4A and FIG. 4B. It can be clearly seen from Fig. 4A and Fig. 4B that the porous nanowire layer 220 has a plurality of pores. For example, these holes have regular or irregular shapes.

In many embodiments, it may further include filling a filler 250 into the holes of the porous nanowire layer 220. In many examples, the filler 250 includes air, silicon dioxide, polysilicon, or silicon nitride (Si _1-x N _x ). For example, the fillers 250 can be grown using chemical vapor deposition (CVD), melt-gel method, high-temperature furnace tube, and the like.

The method 10 of manufacturing a composite substrate structure proceeds to operation 130. In operation 130, a second substrate 230 is provided. In some embodiments of the present disclosure, operation 130 can be further understood with reference to FIG. 6, wherein FIG. 6 is a schematic cross-sectional view of a process stage in the method 10 for manufacturing a composite substrate structure according to an embodiment of the present disclosure. In various embodiments, the second substrate 230 may be a silicon substrate.

The method 10 of manufacturing a composite substrate structure proceeds to operation 140. In operation 140, an oxide layer 240 is formed on the second substrate 230. In some embodiments of the present disclosure, operation 140 can be further understood with reference to FIG. 6, wherein FIG. 6 is a schematic cross-sectional view of a process stage in the method 10 for manufacturing a composite substrate structure according to an embodiment of the present disclosure. In various embodiments, the oxide layer 240 completely covers the second substrate 230. An oxide layer 240 with high density can be formed on the surface of the second substrate 230 by a high-temperature oxidation process. In many examples, the oxide layer 240 includes silicon oxide, gallium oxide, titanium dioxide, or aluminum oxide. For example, the thickness of the oxide layer 240 may be tens of nanometers to several micrometers, such as 0.5 micrometers.

The method 10 of manufacturing a composite substrate structure proceeds to operation 150. In operation 150, the first substrate 210 and the second substrate 230 are joined so that the oxide layer 240 directly contacts the second surface 213 of the first substrate 210. In some embodiments of the present disclosure, operation 150 can be further understood with reference to FIG. 7, wherein FIG. 7 is a schematic cross-sectional view of a composite substrate structure 70 according to an embodiment of the present disclosure. As shown in FIG. 7, the structure shown in FIG. 5 is connected to the structure shown in FIG. 6 so that the oxide layer 240 directly contacts the second surface 213 of the first substrate 210 to form a composite substrate structure 70. In one embodiment, the present disclosure is to align the structure as shown in Figure 5 with the structure as shown in Figure 6 under a normal pressure vacuum environment, and then maintain it at a high temperature for 1 to 30 minutes to increase the gap between the bonding surfaces. The van der Waals force (for example, OH bonding), and the composite substrate structure 70 with close physical bonding is obtained. Next, the above-mentioned composite substrate structure 70 with tight physical bonding can be subjected to a high temperature heat treatment at a temperature of 600°C to 1150°C for about 1 hour, so that a chemical bond with stronger bonding force (e.g., SiO ₂ -SiO ₂ or SiO ₂ -Si), thereby greatly improving the bonding force between the two structures.

In many embodiments, the structure as shown in FIG. 6 may be first subjected to a planarization process and part of the oxide layer 240 is modified before butting is performed, or the composite substrate structure 70 may be formed before the planarization process and part of the modification are performed Oxide layer 240. The planarization process and modification process are detailed as follows. In one example, a diamond grinding wheel may be used to thin the second substrate 230 to a desired thickness (for example, between 1 μm and 700 μm), and then the wet planarization pre-treatment or the dry planarization pre-treatment The modification is carried out for 0.2 to 30 minutes to obtain a rough surface with high uniformity. In one example, the wet planarization pretreatment may use a mixed solution prepared in different ratios of an acid solution and an alkali solution to modify the surface of the second substrate 230 to obtain a uniform rough surface. For example, the acid solution includes hydrochloric acid (HCl), nitric acid (HNO ₃ ), phosphoric acid (H ₃ PO ₄ ), sulfuric acid (H ₂ SO ₄ ), etc.; the alkaline solution includes potassium hydroxide (KOH), sodium hydroxide (NaOH), etc. )Wait. In this example, the pre-treatment for wet planarization is to modify the surface of the second substrate 230 using a mixed solution of potassium hydroxide and hydrogen peroxide.

In another example, the pre-treatment of dry planarization is to use plasma, specifically, a gas containing fluorine, chlorine, hydrogen and other gases with ion etching capability or gas with macromolecules is physically bombarded to obtain a high uniformity Sexual rough surface. In another example, the aforementioned dry-type pre-planarization treatment can be used first, and then the aforementioned wet-type pre-planarization treatment can be used to obtain a rough surface with high uniformity. Then, the semiconductor substrate after the pre-planarization treatment is subjected to a polishing process. In detail, a chemical polishing solution of appropriate concentration (PH value of about 8-12) is prepared, and the polishing process is performed in a continuous injection mode. In many examples, the chemical polishing solution may contain nano particles, such as metals, metal oxides, ceramic materials, and the like. In this embodiment, the chemical polishing solution contains silicon dioxide nanoparticles. It is understandable that different chemical polishing solutions need to be matched with different process parameters, and the surface polishing is performed under a balanced force. The above-mentioned process parameters include the loading force of both sides during processing, the flow rate of the chemical polishing solution, the processing temperature and time... etc.

It is understandable that the porous nanowire layer 220 in the composite substrate structure 70 of the present disclosure can reduce the subsequent growth of the third and fifth group semiconductor nucleation layer (for example, aluminum nitride, gallium nitride, indium nitride, or the aforementioned three types). The contact density of the ternary compound or quaternary compound). Reducing the contact density can reduce the dislocation density at the heterogeneous interface. Since the composite substrate structure 70 of the present disclosure includes a relatively thin porous nanowire layer 220, it has the technical effect of absorbing the stress of the epitaxial layer. At the same time, because the silicon dioxide of the substrate has a creeping property effect during the high temperature growth process of the epitaxy, this effect can reduce the subsequent growth of the group III and V semiconductor nucleation layer from the 3D island shape. When forming a 2D film, the boundary is arranged differently due to the in-plane rotation of the islands. The porous nanowire layer also has the characteristics of interface trap state and increased dissociation energy on its surface due to the shrinking effect of the size. Therefore, the composite substrate structure 70 can not only reduce the heteroepitaxy stress, but also increase the resistance of the substrate.

FIG. 8 is a schematic cross-sectional view of a composite substrate structure 80 according to another embodiment of the present disclosure. In many embodiments, the oxide layer 820 and the third substrate 810 may be formed on the composite substrate structure 70 as shown in FIG. 7 to form the composite substrate structure 80 as shown in FIG. 8. In more detail, the oxide layer 820 is directly disposed on the porous nanowire layer 220, and the third substrate 810 is directly disposed on the oxide layer 820. In various embodiments, the third substrate 810 may be a silicon substrate. In various embodiments, the thickness of the third substrate 810 may be between 1 um and 700 um, for example, 10 um, 50 um, 100 um, 150 um, 200 um, 250 um, 300 um, 350 um, 400 um, 450 um, 500 um, 550 um, 600 um or 650 um. If the thickness of the third substrate 810 is greater than a certain value, such as 700um, the stress generated by the subsequent epitaxial growth of the third and fifth group semiconductors may not be transmitted to the porous nanowire layer 220 under the third substrate 810, resulting in The porous nanowire layer 220 cannot effectively absorb stress. In various embodiments, the oxide layer 820 includes silicon oxide, gallium oxide, titanium dioxide, or aluminum oxide. The oxide layer 820 can improve the bonding force between the third substrate 810 and the porous nanowire layer 220. In many embodiments, the thickness of the oxide layer 820 can be between 0.01um and 5um, for example, it can be 0.05um, 0.1um, 0.2um, 0.3um, 0.4um, 0.5um, 0.6um, 0.7um, 0.8um, 0.9um, 1.0um, 2.0um, 3.0um or 4.0um. In various embodiments, the manufacturing method of the oxide layer 820 and the third substrate 810 may be the same or similar to the manufacturing method of the oxide layer 240 and the third substrate 230.

The present disclosure further provides a method 10 for manufacturing the composite substrate structure 1100. Please return to FIG. 1, the manufacturing method of the composite substrate structure 1100 is substantially similar to the manufacturing method of the composite substrate structure 70. The method 10 of manufacturing the composite substrate structure 1100 includes at least operation 110, operation 120, operation 130, operation 140, and operation 150. In order to facilitate the comparison of the differences with the above-mentioned embodiments and simplify the description, the same symbols are used to denote the same elements in the following embodiments, and the descriptions are mainly directed to the differences of the embodiments, and no repetition is repeated. Repeat part of the cover.

FIG. 9, FIG. 10, and FIG. 11 are schematic cross-sectional views of a process stage in a method 10 of manufacturing a composite substrate structure 1100 according to another embodiment of the present disclosure. The manufacturing method of the composite substrate structure 1100 is different from the manufacturing method of the composite substrate structure 70 mainly in operation 120. In detail, as shown in FIG. 9, during the process of manufacturing the composite substrate structure 1100, operation 120 is to form a plurality of grooves 1110 on the first surface 211 of the first substrate 210. In various embodiments, a plurality of grooves 1110 may be formed on the first substrate 210 by means of photolithography.

In many embodiments, the diameter of these grooves 1110 is about 10nm to 500nm, for example, 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, 150nm, 200nm, 250nm, 300nm, 350nm, 400nm or 500nm. In many embodiments, the density of the grooves 1110 is about 10/micrometer square to 500/micrometer square, for example, 20 grooves/micrometer square, 30 grooves/micrometer square, 40 grooves/micrometer square, 50 grooves. / Micron square, 60 / micron square, 70 / micron square, 80 / micron square, 90 / micron square, 100 / micron square, 150 / micron square, 200 / micron square, 250 / micron Square, 300/micrometer square, 350/micrometer square, 400/micrometer square, or 500/micrometer square. In various embodiments, the depth of each groove 1110 is about 300 nm to 5000 nm, and may be 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, 900 nm, 1000 nm, 1500 nm, 2000 nm, 2500 nm, 3000 nm, 3500 nm, 4000 nm, or 4500 nm, for example.

In many embodiments, the filler 250 may be filled in the grooves 1110, as shown in FIG. 10. In many examples, the filler 250 includes air, silicon dioxide, polysilicon, or silicon nitride. For example, these fillers 250 can be grown using chemical vapor deposition (CVD), melt-gel method, high-temperature furnace tube, and the like.

Next, the structure shown in FIG. 10 is connected to the structure shown in FIG. 6 so that the oxide layer 240 directly contacts the second surface 213 of the first substrate 210, as shown in FIG. 11. In many embodiments, the method of connecting the two structures and the subsequent method of planarizing and modifying the partial oxide layer 240 have been described in detail above, and will not be repeated here. As shown in FIG. 11, the composite substrate structure 1100 includes a substrate 230, an oxide layer 240 and a substrate 210. Specifically, the oxide layer 240 is directly disposed on the substrate 230. The substrate 210 has a first surface 211 and a second surface 213 opposite to each other. The second surface 213 directly contacts the oxide layer 240, and the substrate 210 includes a plurality of grooves 1110 recessed from the first surface 211 toward the second surface 213. It should be noted that these grooves 1110 do not penetrate the substrate 210. It should be noted that the difference between the composite substrate structure 1100 and the composite substrate structure 70 is that the composite substrate structure 1100 is formed by replacing the porous nanowire layer 220 in the composite substrate structure 70 with a plurality of grooves 1110, and these grooves The technical effect provided by 1110 is roughly the same as that provided by the porous nanowire layer 220.

FIG. 12 is a schematic cross-sectional view of a composite substrate structure 1200 according to another embodiment of the present disclosure. In many embodiments, the oxide layer 1220 and the fourth substrate 1210 may be formed on the composite substrate structure 1100 as shown in FIG. 12, thereby forming the composite substrate structure 1200 as shown in FIG. 12. In more detail, the oxide layer 1220 is directly disposed on the first substrate 210 having a plurality of grooves 1110, and the fourth substrate 1210 is directly disposed on the oxide layer 1220. In various embodiments, the fourth substrate 1210 may be a silicon substrate. In various embodiments, the thickness of the fourth substrate 1210 may be between 1 um and 700 um, for example, 10 um, 50 um, 100 um, 150 um, 200 um, 250 um, 300 um, 350 um, 400 um, 450 um, 500 um, 550 um, 600 um or 650 um. If the thickness of the fourth substrate 1210 is greater than a certain value, such as 700um, the stress generated by the subsequent epitaxial growth of the third and fifth group semiconductors may not be transmitted to the grooves 1100 under the fourth substrate 1210, thereby causing these grooves 1100 cannot effectively absorb stress. In various embodiments, the oxide layer 1220 includes silicon oxide, gallium oxide, titanium dioxide, or aluminum oxide. The oxide layer 1220 can improve the bonding force between the fourth substrate 1210 and the first substrate 210. In many embodiments, the thickness of the oxide layer 1220 can be between 0.01um and 5um, for example, it can be 0.05um, 0.1um, 0.2um, 0.3um, 0.4um, 0.5um, 0.6um, 0.7um, 0.8um, 0.9um, 1.0um, 2.0um, 3.0um or 4.0um. In many embodiments, the manufacturing method of the oxide layer 1220 and the fourth substrate 1210 may be the same or similar to the manufacturing method of the oxide layer 240 and the third substrate 230 described above.

In other embodiments, a transistor structure (not shown) may be further provided on the composite substrate structures 70, 80, 1100, and 1200 of the present disclosure. For example, the transistor structure can be a metal oxide semiconductor field effect transistor, a high electron mobility crystal transistor, or various transistors that need to withstand high voltage.

In summary, the composite substrate structure disclosed in the present disclosure includes a porous nanowire layer or a plurality of grooves provided on the substrate. Poor density of the interface. In addition, since the substrate will have a creep effect during the high temperature growth process of the epitaxy, this effect can reduce the subsequent growth of the group III and V semiconductor nucleation layer from the 3D island shape to the 2D film when the boundary is due to the islands. The boundary difference caused by in-plane rotation. Therefore, the present disclosure provides multiple composite substrate structures capable of growing high-quality Group III and V semiconductor epitaxy and manufacturing methods thereof.

Although this disclosure has been disclosed in the above implementation manner, it is not intended to limit this disclosure. Anyone who is familiar with this technique can make various changes and modifications without departing from the spirit and scope of this disclosure. Therefore, this disclosure is protected The scope shall be subject to the scope of the attached patent application.

10: Method 110: Operation 120: Operation 130: Operation 140: Operation 150: Operation 210: first substrate 211: First Surface 213: second surface 220: Porous nanowire layer 230: second substrate 240: oxide layer 250: filler 70: Composite substrate structure 80: Composite substrate structure 810: oxide layer 820: third substrate 1100: Composite substrate structure 1110: groove 1200: Composite substrate structure 1210: Fourth substrate 1220: oxide layer D: diameter

In order to make the above and other objectives, features, advantages, and embodiments of this disclosure more comprehensible, the description of the accompanying drawings is as follows: FIG. 1 shows a flowchart of a method of manufacturing a composite substrate structure according to an embodiment of the present disclosure. 2 and 3 are schematic cross-sectional views of a process stage in the method for manufacturing a composite substrate structure according to an embodiment of the present disclosure. Figure 4A is a top view image of the porous nanowire layer in one embodiment of the disclosure. FIG. 4B is a cross-sectional image diagram of the porous nanowire layer according to an embodiment of the disclosure. 5 and 6 are schematic cross-sectional views of a process stage in the method for manufacturing a composite substrate structure according to an embodiment of the present disclosure. FIG. 7 is a schematic cross-sectional view of a composite substrate structure according to an embodiment of the present disclosure. FIG. 8 is a schematic cross-sectional view of a composite substrate structure according to another embodiment of the present disclosure. FIG. 9, FIG. 10, and FIG. 11 are schematic cross-sectional views of a process stage in a method for manufacturing a composite substrate structure according to another embodiment of the present disclosure. FIG. 12 is a schematic cross-sectional view of a composite substrate structure according to another embodiment of the present disclosure.

Domestic deposit information (please note in the order of deposit institution, date and number) none Foreign hosting information (please note in the order of hosting country, institution, date, and number) none

70: Composite substrate structure

210: first substrate

220: Porous nanowire layer

230: oxide layer

240: second substrate

250: filler

Claims (9)

A composite substrate structure includes: a first substrate; a first oxide layer directly arranged on the first substrate; a second substrate directly arranged on the first oxide layer; and a porous nanowire layer , Directly arranged on the second substrate. The composite substrate structure according to claim 1, further comprising a second oxide layer directly disposed on the porous nanowire layer, and a third substrate directly disposed on the second oxide layer. The composite substrate structure according to claim 2, wherein the first oxide layer and the second oxide layer each comprise silicon oxide, gallium oxide, titanium dioxide or aluminum oxide. The composite substrate structure according to claim 1, further comprising a filler filled with the porous nanowire layer, which comprises air, silicon dioxide, polysilicon or silicon nitride. The composite substrate structure of claim 1, wherein a diameter of the porous nanowire layer is 50 nanometers to 200 nanometers, and a density of the porous nanowire layer is 20 to 300 nanometers/micrometer square (nanowires/μm ² ). A composite substrate structure includes: a first substrate; a first oxide layer directly disposed on the first substrate; and a second substrate having a first surface and a second surface opposite to each other, wherein the second substrate The surface directly contacts the first oxide layer, and the second substrate includes a plurality of grooves with a depth of 300 nm to 500 nm that are recessed from the first surface toward the second surface. A composite substrate structure includes: a first substrate; a first oxide layer directly disposed on the first substrate; and a second substrate having a first surface and a second surface opposite to each other, wherein the second substrate The surface directly contacts the first oxide layer, and the second substrate includes a plurality of grooves having a density of 10/micrometer square to 500 grooves/micrometer square that are recessed from the first surface toward the second surface. A composite substrate structure includes: a first substrate; a first oxide layer directly disposed on the first substrate; a second substrate having a first surface and a second surface opposite to each other, wherein the second surface Directly contact the first oxide layer, and the second substrate includes a plurality of grooves recessed from the first surface toward the second surface; a second oxide layer is directly disposed on the first surface of the second substrate On; and A third substrate is directly arranged on the second oxide layer. A method for manufacturing a composite substrate structure includes: providing a first substrate; forming an oxide layer on the first substrate; providing a second substrate having a first surface and a second surface opposite to each other; forming a porous A nanowire layer is on the first surface; and the first substrate and the second substrate are joined so that the oxide layer directly contacts the second surface.

Images