JP2012234911A - Method of manufacturing composite substrate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a composite substrate including a highly crystalline semiconductor layer.SOLUTION: There is provided a method of manufacturing a composite substrate comprising: a joining step of joining a semiconductor substrate 20X formed of a semiconductor material to a center of an upper surface 10Xa of a substrate 10X formed of an insulating material; a processing step of forming, in the periphery of the substrate 10X, a peripheral part including an upper surface having an arithmetic mean roughness greater than that of the upper surface to which the semiconductor substrate 20X is joined, and processing the substrate 10X into a supporting substrate 10 including a peripheral part 12 and a main part 11 which is positioned inside the peripheral part 12 and to which the semiconductor substrate 20X is joined; and a thinning step of making the semiconductor substrate 20X into a semiconductor layer 20 by wet-etching the semiconductor substrate 20X from an upper surface and thinning the semiconductor substrate 20X.

Description

  The present invention relates to a method for manufacturing a composite substrate having a semiconductor layer used for manufacturing a semiconductor element.

In recent years, in order to improve the performance of semiconductor devices, development of techniques for reducing parasitic capacitance has been promoted. As a technique for reducing this parasitic capacitance, there is an SOS (Silicon On Sapphire) structure. As a method of forming this SOS structure, for example, there is a technique described in Patent Document 1.

Japanese Patent Laid-Open No. 10-12547

  However, in the technique described in Patent Document 1, lattice defects have occurred in silicon due to the difference in the lattice structure between silicon and sapphire.

  The present invention has been conceived under the above circumstances, and an object thereof is to provide a method for manufacturing a composite substrate having a semiconductor layer with few lattice defects.

  The method for manufacturing a composite substrate of the present invention includes a bonding step of bonding a semiconductor substrate made of a semiconductor material to the center of the upper surface of a base made of an insulating material, and an upper surface where the semiconductor substrate is bonded to the periphery of the base A peripheral portion having an upper surface having a large arithmetic average roughness is formed, and the base body is processed into a support substrate having the peripheral portion and a main portion to which the semiconductor substrate is bonded inside the peripheral portion. And a thinning step for forming a semiconductor layer by wet etching the semiconductor substrate from above.

  ADVANTAGE OF THE INVENTION According to this invention, the manufacturing method of the composite substrate which has a semiconductor layer with few lattice defects can be provided.

(A)-(c) is sectional drawing which shows the manufacturing process of the manufacturing method which concerns on one embodiment of this invention, respectively. It is sectional drawing which shows the modification of the process shown in FIG.1 (b). It is a top view which shows the modification of the process shown in FIG.1 (b). It is sectional drawing which shows schematic structure of the modification of the composite substrate 1 shown in FIG.1 (c).

  An example of an embodiment of a method for producing a composite substrate of the present invention will be described with reference to the drawings.

<Joint process>
First, as shown in FIG. 1A, a semiconductor substrate 20X made of a semiconductor material is bonded to the center of the upper surface 10Xa of the base 10X made of an insulating material. “Center” indicates a relative positional relationship with respect to the peripheral edge of the base body 10X, and does not necessarily need to be “center”. In this example, the semiconductor substrate 20X is bonded so as to cover the entire upper surface 10Xa of the base body 10X.

  The insulating material constituting the base 10X is not particularly limited as long as it is an insulating material, but for example, aluminum oxide single crystal (sapphire), silicon carbide, or the like can be used. In this embodiment, sapphire is used as the substrate 10X.

  The thickness of the base 10X is not particularly limited as long as the semiconductor substrate 20X can be supported, but may be about 600 to 650 μm, for example.

As a semiconductor material constituting the semiconductor substrate 20X, various semiconductor materials such as gallium arsenide and gallium nitride can be used. In this example, a single crystal substrate of silicon (Si) is used. As silicon of the semiconductor substrate 20X, p-type, n-type, or non-doped silicon can be employed. Examples of the p-type dopant concentration include a range of less than 1 × 10 ¹⁶ [atoms / cm ³ ]. Examples of the n-type dopant concentration include a range of less than 5 × 10 ¹⁵ [atoms / cm ³ ]. What is referred to as “non-doped silicon” herein is silicon that is simply not doped with the intention of impurities, and is not limited to intrinsic silicon that does not contain impurities.

  The thickness of the semiconductor substrate 20X is not particularly limited, but a thickness of several μm or more is used.

  Such a base 10X and the semiconductor substrate 20X are bonded and bonded together. Examples of the bonding method include a method of activating and bonding the surfaces of the surfaces to be bonded, and a method of bonding using electrostatic force. Examples of the method for activating the surface include a method of activating by irradiating an ion beam in vacuum and etching the surface, a method of activating by etching the surface with a chemical solution, and the like. You may perform this joining under normal temperature.

In this bonding, a method that does not use an adhesive such as a resin is employed, and the base 10X and the semiconductor substrate 20X are directly bonded by solid state bonding using atomic force or the like. Is done. When joining by this solid phase joining, it is preferable that the base | substrate 10X and the semiconductor substrate 20X have a small surface roughness of the surface to join. This surface roughness is represented by arithmetic mean roughness Ra, for example. Examples of the range of the arithmetic average roughness Ra include less than 10 nm. By reducing the arithmetic average roughness, the pressure applied when joining each other can be reduced. In particular, when Ra is 1 nm or less, bonding can be performed with extremely low pressure.

<Processing process>
Next, a peripheral edge portion 12 having a large arithmetic average roughness is formed on the periphery of the base body 10X as compared with the upper surface to which the semiconductor substrate 20X is bonded. As shown in FIG. The support substrate 10 having the main part 11 which is located inside the part 12 and the peripheral part 12 and to which the semiconductor substrate 20X is bonded is processed. In this example, the peripheral edge portion 12 is formed so as to surround the periphery of the main portion 11.

Specifically, by removing the periphery of the semiconductor substrate 20X, the periphery 12 of the base body 10 is exposed, and the arithmetic average roughness of the exposed surface (the upper surface 12a of the periphery 12) is increased. In order to expose the peripheral edge portion 12 of the base 10 from the semiconductor substrate 20X, the peripheral edge of the semiconductor substrate 20X may be partially removed by, for example, chemical or physical etching or a mechanical technique. Etching includes a chemical method and a physical method such as an ion beam. Then, a photomask is formed on the main surface of the semiconductor substrate 20X that is not bonded to the support base 10X (hereinafter referred to as the upper surface 20Xa), and etching is performed. Examples of the mask include a metal mask and a photomask, and are appropriately selected according to the etching method.

  In order to change the arithmetic average roughness of the upper surface (11a, 12a) between the main portion 11 and the peripheral portion 12, for example, sputtering is performed on the upper surface 12a of the peripheral portion 12, or mechanical processing such as blast processing is performed. You can add it. When the support base is processed to form the peripheral portion 12, conditions such as etching may be adjusted as appropriate so that the surface 12 a is roughened simultaneously with the formation of the peripheral portion 12.

  Here, the upper surface 11a of the main portion 11 preferably has a small arithmetic average roughness from the viewpoint of bonding the support substrate 10 and the semiconductor substrate 20X. As described above, for example, the arithmetic average roughness is less than 10 nm. It is preferable to do. On the other hand, the arithmetic average roughness of the upper surface 12 a of the peripheral portion 12 may be larger than that of the upper surface 11 a of the main portion 11. Specifically, for example, when the arithmetic average roughness of the upper surface 11a of the main portion 11 is less than 1 nm, it may be set to 5 nm or more.

<Thinning process>
Next, as shown in FIG. 1C, the semiconductor substrate 20X is made into the semiconductor layer 20 by wet etching from the upper surface 20Xa of the semiconductor substrate 20X to make it thin.

  The etching solution is preferably one that selectively removes the semiconductor material. For example, when the semiconductor material is silicon and the insulating material is sapphire, hydrofluoric acid, nitric acid, acetic acid, KOH, and a mixed solution thereof are used. Can be used.

  Using such an etchant, the semiconductor substrate 20X is etched from the upper surface 20Xa side to a desired thickness. Examples of the thickness of the semiconductor layer 20 include a range of about 50 nm to about 2 μm.

  Here, the semiconductor material is generally hydrophobic. The silicon in this example is also hydrophobic. It is necessary to hold an etching solution on the upper surface 20Xa of the semiconductor substrate 20X made of such a hydrophobic material. On the other hand, since the arithmetic average roughness of the upper surface 12a of the peripheral portion 12 of the support substrate 10 is large, the wettability of the upper surface 12a of the peripheral portion 12 can be improved. As a result, the etching solution can be held on the upper surface 12a of the peripheral portion 12, and the etching solution can be retained on the semiconductor substrate 20X located inside the peripheral portion 12 in plan view. In other words, the “wall” of the etching solution held by the peripheral edge portion 12 can be formed around the semiconductor substrate 20X. Thereby, even if it is a case where a hydrophobic material is used as the semiconductor substrate 20X, it can etch.

  Such etching is preferably performed by spin etching. By performing spin etching, the film thickness distribution due to etching can be suppressed. Usually, when spin etching is performed, it becomes difficult to hold the etching solution on the semiconductor substrate 20X made of a hydrophobic material, but in this example, the etching solution is held by the peripheral portion 12 having improved wettability of the upper surface 12a. can do.

  In particular, in this example, sapphire, which is a hydrophilic material, is used as the insulating material. For this reason, since the wettability of the upper surface 12a of the peripheral part 12 can further be improved, it can etch more reliably.

Through the steps up to here, the composite substrate 1 in which the semiconductor layer 20 is disposed on the support substrate 10 as shown in FIG. 1C can be manufactured.

  Since the composite substrate 1 manufactured in this manner can use a silicon single crystal having high crystallinity as the semiconductor layer 20, the semiconductor layer can be compared with a case where semiconductor layers having different lattice constants are grown on the support substrate 10. 20 quality can be improved. Further, by directly bonding the base body 10X and the semiconductor substrate 20X, the interposition of impurities between the support substrate 10 and the semiconductor layer 20 can be suppressed, and the high-quality composite substrate 1 can be obtained. Further, since the support substrate 10 made of sapphire having high thermal conductivity is directly bonded to the semiconductor layer 20, the composite substrate 1 having high heat dissipation can be obtained.

  Further, when a semiconductor element is manufactured using the composite substrate 1, the required thickness of the semiconductor layer 20 is much thinner than that of a general silicon single crystal substrate used as the semiconductor substrate 20X. For this reason, it is necessary to process the uniform semiconductor layer 20 without damaging the thick semiconductor substrate 20X. On the other hand, according to this example, the semiconductor substrate 20X and the etching solution can be stably brought into contact with each other by holding the etching solution in the peripheral portion 12. Thereby, the semiconductor substrate 20X can be processed into the semiconductor layer 20 having a desired thickness with a small in-plane thickness distribution. Thus, the composite substrate 1 having the desired thickness and the high-quality semiconductor layer 20 with few defects can be provided only by providing the peripheral edge portion 12 and performing wet etching.

Note that after the composite substrate 1 is manufactured, the composite substrate 1 may be precisely polished. By this precise polishing, the uniformity of the thickness of the semiconductor layer 20 can be improved. Examples of the etching means used for this precise etching include dry etching. This dry etching includes a chemical reaction and a physical collision. Examples of utilizing chemical reactions include reactive gases (gas), ions and ion beams, and those utilizing radicals. Examples of the etching gas used for the reactive ions include sulfur hexafluoride (SF ₆ ) and carbon tetrafluoride (CF ₄ ). Moreover, what uses an ion beam is mentioned as a thing by physical collision. One using this ion beam includes a method using a gas cluster ion beam (GCIB). Further, mechanical polishing such as mechanochemical polishing or abrasive polishing may be performed.

Moreover, in the above-mentioned process, although the process of washing | cleaning a board | substrate etc. is not specified, you may wash | clean a board | substrate as needed. Examples of the substrate cleaning method include various methods such as cleaning using ultrasonic waves, cleaning using an organic solvent, cleaning using chemicals, and cleaning using O ₂ ashing. These cleaning methods may be employed in combination. In particular, when cleaning is performed using pure water or an aqueous solution, the cleaning liquid can be held by the peripheral edge portion 12.

<Modification 1: Processing step>
In the above-described example, the support plate substrate 10 has a flat plate shape, and the main portion 11 and the peripheral portion 12 are described as having no difference in thickness. However, as shown in FIG. It is good also as 10 A of support substrates which have 12A. Specifically, the thickness d2 of the support substrate 10A in the peripheral portion 12A is thinner than the thickness d1 in the main portion 11A. The upper surface 12Aa of the peripheral portion 12A is located below the upper surface 11Aa of the main portion 11A. In this example, the lower surface 11Ab of the main portion 11A and the lower surface 12Ab of the peripheral edge portion 12A are aligned and located on the same plane. Note that the outer peripheral portion of the support substrate 10A may be chamfered to prevent chipping. In this case, the thickness d2 of the peripheral portion 12A is measured between the upper surface 12Aa and the lower surface 12Ab that are parallel to each other.

Thus, in order to change the thickness between the main portion 11A and the peripheral portion 12A, for example, the peripheral portion 12A
May be removed from the semiconductor substrate 20XA, after the outer peripheral portion of the semiconductor substrate 20XA is removed, a part of the base body 10XA in the thickness direction may be removed.

  According to the support substrate 10A, in the thinning step, the etching solution can be held not only on the upper surface 12Aa of the peripheral portion 12A but also on the side surface 11y of the main portion 11A.

  In particular, when the arithmetic average roughness of the side surface 11y of the main portion 11A is made larger than that of the upper surface 11Aa of the main portion 11A, the wettability on the side surface 11y can be further increased, so that the etching solution can be held more stably. be able to.

  In order to increase the arithmetic average roughness of the side surface 11y, chemical or physical etching may be performed, or mechanical processing such as blasting, abrasive polishing, or dicing may be performed.

<Modification 2: Processing step>
In the example shown in FIG. 2, the side surface 11y of the main portion 11A is a surface perpendicular to the upper surface 11Aa and the lower surface 11Ab, but may be inclined. Specifically, the angle formed by the side surface 11y and the lower surface 11Ab of the main part 11A may be an acute angle. With such a configuration, the etching solution can be held more stably.

<Modification 3: Joining process>
In the example shown in FIG. 1A, the case where the base 10X and the semiconductor substrate 20X have substantially the same size in plan view has been described. However, the semiconductor substrate 20X has a shape smaller than the base 10X. It may be used and bonded to the center of the substrate 10X.

  With such a configuration, a region exposed from the semiconductor substrate 20X in advance can be provided on the upper surface 10Xa of the base body 10X. Thereby, the process process implemented following a joining process can be simplified.

<Modification 4: Processing step to thinning step>
In the above example, the semiconductor substrate 20X having a uniform dopant concentration is used, but a semiconductor substrate 20XB having a different dopant concentration depending on the thickness direction may be used. As such a semiconductor substrate 20XB, for example, as a laminated structure of a first layer and a second layer, the base body 10XB is compared with a layer (first layer) located on the main surface side on the side bonded to the support substrate 10. The dopant concentration of the layer (second layer) located on the main surface (upper surface) side that is not bonded to the substrate may be increased.

Specifically, the first layer is formed to have any one of a relatively low concentration of p ⁻ and n ⁻ dopants and non-doped. Examples of the p ⁻ dopant concentration include a range of less than 1 × 10 ¹⁶ [atoms / cm ³ ]. Examples of the n ⁻ dopant concentration include a range of less than 5 × 10 ¹⁵ [atoms / cm ³ ]. What is referred to as “non-doped silicon” herein is silicon that is simply not doped with the intention of impurities, and is not limited to intrinsic silicon that does not contain impurities.

As the second layer, a relatively high concentration of p ⁺⁺ and n ⁺⁺ , and a medium concentration of p ⁺ and n ⁺ can be employed. ^Examples of the p ⁺⁺ dopant concentration include a range of 1 × 10 ^{18 to} 1 × 10 ²¹ [atoms / cm ³ ]. The p ⁺ dopant concentration includes a range of 1 × 10 ¹⁶ or more and less than 1_! (B × 10 ¹⁸ [atoms / cm ³ ]. The n ⁺⁺ dopant concentration is 5 × 10 ¹⁷ or more and 1 × 10 ^21. [Atoms / cm ³ ] The following ranges can be cited: The n ⁺ dopant concentration includes a range of 5 × 10 ¹⁵ or more and less than 5 × 10 ¹⁷ [atoms / cm ³ ], where “p” and “ The description of “++” and “+” written in the upper right of “n” is based on the resistance value of silicon.

Using such a semiconductor substrate 20XB, the thickness of the semiconductor substrate 20XB is reduced by etching from the second layer side in the thinning step. This etching can be performed by employing a selective etching solution in which the etching rate varies greatly depending on the difference in dopant concentration. This selective etching solution is adjusted so that the etching rate is significantly reduced when the dopant concentration exceeds or falls below a predetermined value. Examples of such a selective etching solution include a mixed solution of hydrofluoric acid, nitric acid, and acetic acid, and a mixed solution of hydrofluoric acid, nitric acid, and water. For example, a mixed solution of hydrofluoric acid, nitric acid, and acetic acid is used as the etching solution. For example, when p-type silicon is used, this etching solution is adjusted so that the etching rate is remarkably reduced with the dopant concentration being 7 × 10 ¹⁷ to 2 × 10 ¹⁸ [atoms / cm ³ ] as a boundary. Yes. Other methods for selective etching include an electric field etching method in a 5% hydrogen fluoride solution, a pulse electrode anodizing method in a KOH solution, and the like. By using such an etchant, when reaching the first layer, the etching rate is reduced, and the first layer portion having a low dopant concentration remains. The first layer portion may be the semiconductor layer 20.

  Note that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the present invention.

  For example, in FIG. 2, the support substrate 10 </ b> A has the bottom surfaces of the main portion 11 </ b> A and the peripheral portion 12 </ b> A aligned and has no step, but the bottom surface may not be aligned. That is, you may arrange | position so that the center in the thickness direction of 11 A of main parts and the center in the thickness direction of 12 A of peripheral parts may be equalized.

  1 and 2, the support substrate (10, 10A) is arranged so that the peripheral edge portion (12, 12A) surrounds the main portion (11, 11A), but as shown in FIG. You may arrange | position the peripheral part 12C in a part of peripheral area of the part 11C.

  Further, in FIGS. 1 and 2, the supporting substrate (10, 10A) is arranged with the peripheral portion (12, 12A) and the main portion (11, 11A) being spaced apart in plan view. Similarly, an exposed region 11x that is exposed from the semiconductor layer 20D and has an arithmetic average roughness equivalent to the upper surface 11Da of the main portion 11D is provided between the peripheral edge portion 12D and the main portion 11CD in plan view. Also good.

  In the above example, the example in which the semiconductor substrate 20X is directly bonded to the base body 10X has been described. However, the semiconductor substrate 20X may be bonded via an oxide layer or the like.

DESCRIPTION OF SYMBOLS 1,1C ... Composite board | substrate 10X ... Base | substrate 10Xa ... Upper surface 10, 10A-10D ... Support substrate 11, 11A-11D ... Main part 11a, 11Aa ... Upper surface of main part 11b, 11Ab ... lower surface 11x of main part ... exposed region 11y ... side face 12, 12A-12D ... peripheral edge 20X, 20XA, 20XB ... semiconductor substrate 20, 20A, 20D ... semiconductor layer

Claims (7)

A bonding step of bonding a semiconductor substrate made of a semiconductor material to the center of the upper surface of the base made of an insulating material;
A peripheral portion having an upper surface having a large arithmetic average roughness compared to the upper surface to which the semiconductor substrate is bonded is formed at the peripheral edge of the base, and the base is positioned inside the peripheral portion and the peripheral portion. A processing step of processing into a support substrate having a main part to which the semiconductor substrate is bonded;
A method of manufacturing a composite substrate, comprising a step of thinning a semiconductor layer by wet-etching the semiconductor substrate from above to make it thin.   The said process step WHEREIN: The upper surface of the said peripheral part of the said support substrate is located below the upper surface of the said main part, and the thickness of the said peripheral part is made thin compared with the thickness of the said main part. A method of manufacturing a composite substrate.   3. The composite substrate according to claim 2, wherein, in the processing step, the arithmetic average roughness of the side surface of the main portion between the main portion and the peripheral portion is made larger than the arithmetic average roughness of the upper surface of the main portion. Production method.   The method of manufacturing a composite substrate according to claim 1, wherein in the processing step, the peripheral portion is formed so as to surround the entire periphery of the main portion.   The method of manufacturing a composite substrate according to claim 1, wherein wet etching is performed by spin etching in the thinning step.   The method for manufacturing a composite substrate according to claim 1, wherein a hydrophilic material is used as the insulating material of the base. The method of manufacturing a composite substrate according to claim 2, wherein in the processing step, a side surface of the main portion between the main portion and the peripheral portion is an inclined surface.

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