TWI746137B - Memory structures and methods for forming the same - Google Patents

Abstract

A memory device includes a substrate, an electrical channel layer, a first electrode, a resistive switching layer, a second electrode, and a conductive structure. The electrical channel layer is disposed on the substrate. The first electrode is disposed on the substrate and extends into the electrical channel layer. The resistive switching layer is disposed between the first electrode and the electrical channel layer. The second electrode is disposed on the electrical channel layer. The conductive structure connects the electrical channel layer and the second electrode.

Description

Memory structure and manufacturing method thereof

The present invention relates to semiconductor manufacturing technology, in particular to memory structure and manufacturing method thereof.

With the shrinking of the size of semiconductor devices, the difficulty of manufacturing semiconductor devices has also increased significantly. Unwanted defects may occur during the manufacturing process of the semiconductor devices, and these defects may cause the performance of the device to be reduced or damaged. Therefore, semiconductor devices must be continuously improved to increase yield and improve process margins.

According to some embodiments of the present invention, a memory structure is provided. The memory structure includes a substrate; an electrical channel layer is provided on the substrate; a first electrode is provided on the substrate and extends into the electrical channel layer; the resistance transition layer is provided between the first electrode and the electrical channel layer; The two electrodes are arranged on the electrical channel layer; and the conductive structure connects the electrical channel layer and the second electrode.

According to some embodiments of the present invention, a memory structure is provided. The memory structure includes a substrate; an electrical channel layer is disposed on the substrate and extends in a first direction; a first electrode is disposed on the substrate and extends into the electrical channel layer in a second direction, the second direction is different from the first direction The resistance transition layer is arranged between the first electrode and the electrical channel layer; the second electrode is arranged on the electrical channel layer, wherein the substrate, the electrical channel layer and the second electrode are stacked in the second direction; and the conductive structure The electrical channel layer is connected to the second electrode and extends along the second direction.

According to some embodiments of the present disclosure, a manufacturing method of a memory structure is provided. The method includes forming an electrical channel layer on a substrate; forming a first electrode on the substrate to extend into the electrical channel layer; forming a resistance transition layer between the first electrode and the electrical channel layer; and forming the electrical channel layer The conductive structure is formed on the upper side and is connected to the second electrode.

100, 200: Memory structure

102, 110, 204: contacts

104,212: first electrode

106, 210: Resistance transition layer

108,222: second electrode

202: Base

205: Dielectric layer

206: High dielectric constant layer

208: electrical channel layer

209: Groove

214A, 214B: through hole

216A, 216B, 220: barrier layer

218A, 218B: conductive structure

224: Current

226: Conductive wire

D1: First direction

D2: second direction

D3: Third party

The embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings. It should be noted that, according to industry standard practices, various features are not drawn to scale and are only used for illustration and illustration. In fact, it is possible to arbitrarily enlarge or reduce the size of the element to clearly express the characteristics of the present invention.

FIG. 1 is a schematic cross-sectional view of a memory structure according to some embodiments.

2A to 2E are schematic cross-sectional diagrams illustrating various stages of manufacturing a memory structure according to some embodiments.

FIG. 3 is a schematic cross-sectional view of a memory structure according to some embodiments.

FIG. 4 is a schematic top view of a memory structure according to some embodiments.

Some embodiments are summarized below, so that those with ordinary knowledge in the technical field to which the present invention belongs can more easily understand the present invention. However, these embodiments are only examples and are not intended to limit the present invention. It is understandable that those with ordinary knowledge in the technical field to which the present invention pertains can adjust the embodiments described below according to requirements, such as changing the process sequence and/or including more or less steps than those described herein, and these adjustments have not been made. Beyond the scope of the present invention.

In addition, other elements may be added to the embodiments described below. For example, the description of "form the second element on the first element" may include an embodiment in which the first element is in direct contact with the second element, or may include other elements between the first element and the second element, so that the first element is in contact with the second element. The embodiment in which one element and the second element are not in direct contact, and the up-down relationship between the first element and the second element may change as the device is operated or used in different orientations.

In the following description, the description of "the first element passes through the second element" may include the first element in the second element and extending from the first side of the second element to the opposite second side, where the first element A surface may be flush with a surface of the second element, or a surface of the first element may be outside of a surface of the second element. In addition, the present invention may repeat reference numbers and/or letters in different embodiments, and this repetition is for simplification and clarity, rather than to indicate the relationship between the different embodiments discussed.

Hereinafter, according to some embodiments of the present invention, a memory structure and a manufacturing method thereof are described, and they are particularly suitable for non-volatile memory (NVM), such as resistive random-access memory (NVM). RRAM). In the present invention, the resistive transition layer is arranged to extend into the electrical channel layer, which can increase the number of conductive filaments without increasing the forming voltage and improve data retention.

FIG. 1 is a schematic cross-sectional view of a memory structure 100 according to some embodiments. As shown in Figure 1, the memory structure 100 includes contacts 102 and 110, respectively connected to the first electrode 104 and the second electrode 108, and the memory structure 100 includes the first electrode 104 and the second electrode 108 Resistance transition layer 106.

When a forward voltage is applied to the memory device 100, the oxygen ions in the resistance transition layer 106 migrate to the electrode above it, and an oxygen-vacancy conductive wire (not shown) is formed in the resistance transition layer 106 to make the resistance transition The state layer 106 switches to a low resistance state. Conversely, when a reverse voltage is applied to the memory device 100, oxygen ions return to the resistance transition layer 106 and combine with the oxygen vacancies in the resistance transition layer 106, resulting in the disappearance of the oxygen vacancy conductive filaments, and the resistance transition layer 106 is converted. It is a high resistance state. The memory device 100 converts the resistance value in the above-mentioned manner to store or read data to achieve the memory function.

In some embodiments, the high temperature used in the manufacturing process of the memory structure will reduce the current in the low-resistance state, making data preservation worse. Since the current of the conductive filament is related to the oxygen vacancy concentration, some methods provide more oxygen vacancies by increasing the thickness of the resistive transition layer 106 to increase the current in the low-resistance state, thereby improving data preservation. However, this method also introduces some problems. For example, due to the resistance transition layer 106 The material is less easy to be etched. Increasing the thickness of the resistance transition layer 106 will also increase the difficulty of the etching process. For example, it is difficult to form the resistance transition layer 106 into a desired shape. In addition, increasing the thickness of the resistance transition layer 106 will also increase the forming voltage of the memory structure 100, which is not conducive to the mass production of the memory structure 100. Therefore, the present invention further provides the following embodiments to improve the above-mentioned problems.

2A to 2E are schematic cross-sectional diagrams illustrating the memory structure 200 according to some other embodiments. As shown in FIG. 2A, the memory structure 200 includes a substrate 202. The substrate 202 can use any substrate material suitable for the memory structure 200. For example, the substrate 202 may include oxide.

In some embodiments, the memory structure 200 includes a contact 204 disposed in the substrate 202. The contact 204 may include conductive materials, such as doped or undoped polysilicon, metals, similar materials, or a combination of the foregoing. For example, the metal includes gold, nickel, platinum, palladium, iridium, titanium, chromium, tungsten, aluminum, copper, tantalum, hafnium, similar materials, the foregoing alloys, the foregoing multilayer structure, or a combination of the foregoing. According to some embodiments, the deposition process includes a physical vapor deposition process, a chemical vapor deposition process, an atomic layer deposition process, an evaporation process, an electroplating process, a similar process, or a combination of the foregoing.

Then, according to some embodiments, a dielectric layer 205 is formed on the contact 204 to cover the contact 204. In some embodiments, the dielectric layer 205 and the substrate 202 include the same material, so the interface between the dielectric layer 205 and the substrate 202 is not drawn. In other embodiments, the dielectric layer 205 and the substrate 202 comprise different materials, and the dielectric layer There will be an interface between 205 and substrate 202. The method for forming the dielectric layer 205 may include chemical vapor deposition, atomic layer deposition, similar deposition processes, or a combination of the foregoing.

Then, according to some embodiments, a pair of high dielectric constant layers 206 and an electrical channel layer 208 between the high dielectric constant layers 206 are formed on the dielectric layer 205. The high dielectric constant layer 206 and the electrical channel layer 208 may extend along the first direction D1. The high dielectric constant layer 206 may include a material with a dielectric constant greater than 3.9, such as tantalum oxide, hafnium oxide, aluminum oxide, similar materials, or a combination of the foregoing. The electrical channel layer 208 may include titanium, titanium nitride, tantalum, tantalum nitride, hafnium, hafnium nitride, similar materials, or a combination of the foregoing. The method for forming the high dielectric constant layer 206 and the electrical channel layer 208 can be similar to the method for forming the dielectric layer 205, so the details are not described again.

The number of electrical channel layers 208 is related to the number of currents. Two electrical channel layers 208 are shown here, but the present invention is not limited thereto. More or fewer layers of electrical channel layers 208 can be used according to the amount of current, and a dielectric layer 205 is disposed between these electrical channel layers 208. Then, a dielectric layer 205 is deposited on the uppermost electrical channel layer 208.

Then, according to some embodiments, the memory device 200 is etched out of the trench 209. As shown in FIG. 2A, the trench 209 penetrates the dielectric layer 205, the high dielectric constant layer 206, and the electrical channel layer 208, and exposes the contact 204. The trench 209 may extend in a second direction D2, which is different from the first direction D1. The first direction D1 and the second direction D2 may be substantially perpendicular or orthogonal to each other. Alternatively, the included angle between the first direction D1 and the second direction D2 may be about 80 degrees to about 90 degrees.

In some embodiments, the trench 209 can be formed by disposing a mask layer (not shown) on the dielectric layer 205, and then using the mask layer as an etching mask for an etching process. In some embodiments, the mask layer may include a hard mask, and may be formed of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbide nitride, similar materials, or a combination of the foregoing. The mask layer can be a single-layer structure or a multi-layer structure. The formation of the mask layer may include a deposition process, a lithography process, other suitable processes, or a combination of the foregoing. In some embodiments, the deposition process includes spin coating, chemical vapor deposition, atomic layer deposition, similar deposition processes, or a combination of the foregoing. In some embodiments, the photolithography process may include photoresist coating (such as spin coating), soft baking, mask alignment, exposure, post-exposure baking, developing, rinsing, drying (such as hard baking). Baking), other suitable processes or a combination of the foregoing.

In some embodiments, the etching process of the trench 209 may include a dry etching process, a wet etching process, or a combination of the foregoing. For example, the dry etching process can include reactive ion etch (RIE), inductively-coupled plasma (ICP) etching, neutral beam etch (NBE), and electron cyclotron etching. Electron cyclotron resonance (ERC) etching, a similar etching process, or a combination of the foregoing. For example, the wet etching process can use, for example, hydrofluoric acid, ammonium hydroxide, or any suitable etchant.

Then, according to some embodiments, as shown in FIG. 2B, a resistance transition layer 210 is formed on the sidewall of the trench 209. The resistance transition layer 210 may extend substantially along the second direction D2. In some embodiments, the material of the resistance transition layer 210 may include Transition metal oxides, such as nickel oxide, titanium oxide, hafnium oxide, zirconium oxide, zinc oxide, tungsten oxide, aluminum oxide, tantalum oxide, molybdenum oxide, copper oxide, similar materials, or a combination of the foregoing. The method for forming the resistance transition layer 210 may include an atomic layer deposition process, a chemical vapor deposition process, a physical vapor deposition process, a similar deposition process, or a combination of the foregoing.

Then, according to some embodiments, the first electrode 212 is formed on the remaining part of the trench 209. The first electrode 212 may extend substantially in the second direction D2. The material of the first electrode 212 may include metal or metal nitride, such as platinum, titanium nitride, gold, titanium, tantalum, tantalum nitride, tungsten, tungsten nitride, copper, similar materials, or a combination of the foregoing. In some embodiments, the material of the first electrode 212 includes copper. The method for forming the first electrode 212 may include an atomic layer deposition process, a chemical vapor deposition process, a physical vapor deposition process, a similar deposition process, or a combination of the foregoing.

As shown in FIG. 2B, the resistance transition layer 210 is adjacent to the first electrode 212, and the resistance transition layer 210 is located on the sidewall of the first electrode 212 and exposes the top surface of the first electrode 212. In some embodiments, the resistance transition layer 210 and the first electrode 212 extend through the electrical channel layer 208 toward the substrate 202 and contact the contact 204. According to some embodiments, as shown in FIG. 2B, the resistance transition layer 210 and the first electrode 212 are substantially perpendicular to the top surface of the substrate 202, but the present invention is not limited to this. The resistance transition layer 210 and the first electrode 212 may be connected to the The top surface of the base 202 has any suitable angle. Then, a planarization process, such as a chemical mechanical polishing process, can be performed to remove excess material and provide a flat surface.

Although in the embodiment of FIG. 2B, the first electrode 212 passes through the electrical channel layer 208, that is, the top surface of the first electrode 212 is above the electrical channel layer 208, and the bottom surface of the first electrode 212 is on the electrical channel layer 208. Below 208, but the present invention is not limited to this. For example, the first electrode 212 may partially extend into the electrical channel layer 208 so that the top surface of the first electrode 212 is in the electrical channel layer 208.

Then, according to some embodiments, as shown in FIG. 2C, a dielectric layer 205 is formed on the first electrode 212 to cover the first electrode 212 and the resistance transition layer 210. Then, the memory device 200 is etched out of the through holes 214A and 214B. The through holes 214A and 214B pass through the dielectric layer 205, the high dielectric constant layer 206 and the electrical channel layer 208, and are located on both sides of the first electrode 212. The formation method of the through holes 214A and 214B can be similar to the formation method of the trench 209, and therefore will not be described in detail.

Although in the embodiment of FIG. 2C, the through holes 214A and 214B pass through the electrical channel layer 208, and the bottom surfaces of the through holes 214A and 214B are below the electrical channel layer 208, the present invention is not limited thereto. For example, the through holes 214A and 214B may partially extend into the electrical channel layer 208 such that the bottom surfaces of the through holes 214A and 214B are in the electrical channel layer 208. Alternatively, according to other embodiments, the through holes 214A and 214B may not extend into the electrical channel layer 208, and the bottom surfaces of the through holes 214A and 214B are flush with the top surface of the electrical channel layer 208. In addition, the through holes 214A and 214B may each have a different depth, and the number of through holes may be more or less than two.

Then, according to some embodiments, as shown in FIG. 2D, barrier layers 216A and 216B are formed on the sidewalls of the through holes 214A and 214B, respectively, and conductive structures 218A and 218B are formed on the remaining portions of the through holes 214A and 214B, respectively. Conductive junction The structures 218A and 218B may extend substantially in the second direction D2. In some embodiments, the barrier layers 216A and 216B are located between the conductive structures 218A and 218B and the electrical channel layer 208, respectively. The material of the barrier layers 216A and 216B may include aluminum oxide, and the formation method of the barrier layers 216A and 216B may include an atomic layer deposition process, a chemical vapor deposition process, a physical vapor deposition process, a similar deposition process or a combination of the foregoing . The conductive structures 218A and 218B may include conductive materials, such as metals or metal nitrides. In some embodiments, the material of the conductive structures 218A and 218B includes copper.

As shown in FIG. 2E, the conductive structures 218A and 218B extend to the electrical channel layer 208, and the resistance transition layer 210 is located between the first electrode 212 and the conductive structures 218A and 218B. In some embodiments, the top surfaces of the conductive structures 218A and 218B are higher than the top surface of the first electrode 212. According to some embodiments, as shown in FIG. 2D, the conductive structures 218A and 218B are substantially perpendicular to the top surface of the substrate 202, but the present invention is not limited to this. The conductive structures 218A and 218B can have any suitable angle with the top surface of the substrate 202. . Then, a planarization process, such as a chemical mechanical polishing process, can be performed to remove excess material and provide a flat surface.

The depth of the conductive structures 218A and 218B depends on the depth of the through holes 214A and 214B. Therefore, as discussed above with respect to the through holes 214A and 214B, the conductive structures 218A and 218B may or may not pass through the electrical channel layer 208. Specifically, the bottom surfaces of the conductive structures 218A and 218B may be flush with the top surface of the electrical channel layer 208, or the bottom surfaces of the conductive structures 218A and 218B may be in or below the electrical channel layer 208.

Then, according to some embodiments, as shown in FIG. 2E, a barrier layer 220 and a second electrode 222 are formed on the electrical channel layer 208. The substrate 202, the electrical channel layer 208, and the second electrode 222 may be stacked substantially in the second direction D2. The material of the barrier layer 220 may include titanium, titanium nitride, tungsten nitride, tantalum, tantalum nitride, similar materials, or a combination of the foregoing. The material of the second electrode 222 may include a conductive material, such as metal or metal nitride. The formation method of the barrier layer 220 and the second electrode 222 may each independently include an atomic layer deposition process, a chemical vapor deposition process, a physical vapor deposition process, a similar deposition process, or a combination of the foregoing.

As shown in Figure 2E, the second electrode 222 covers the conductive structures 218A and 218B, and is electrically connected to the conductive structures 218A and 218B, so that the current 224 flows from the first electrode 212 through the electrical channel layer 208, the conductive structures 218A and 218B. The second electrode 222. Although in Figure 2E, the second electrode 222 is electrically connected to the conductive structures 218A and 218B at the same time, two second electrodes 222 may also be provided to be electrically connected to the conductive structures 218A and 218B, respectively.

Please refer to FIG. 3 to describe the formation of the conductive wire 226 to form the path of the current 224. FIG. 3 is a schematic cross-sectional view of a memory structure 200 according to some embodiments. For the convenience of description, in Figure 3, only the first electrode 212, the resistance transition layer 210 and the electrical channel layer 208 are shown, but not all the components in Figure 2E.

As shown in FIG. 3, the resistance transition layer 210 is located between the first electrode 212 and the electrical channel layer 208. When a forward voltage is applied to the memory device 200, the resistive transition layer 210 forms conductive filaments 226 on both sides adjacent to the electrical channel layer 208, and the two electrical channel layers 208 can generate four conductive filaments 226. These conductive wires 226 The first electrode 212 and the electrical channel layer 208 are connected to form a current 224 path as shown in FIG. 2E. Therefore, in the embodiment of the present invention, by providing the resistance transition layer 210 extending into the electrical channel layer 208, the number of conductive wires can be increased without increasing the thickness of the resistance transition layer 210, thereby improving data preservation.

Referring to FIG. 2E, the memory structure 200 includes conductive structures 218A and 218B and two electrical channel layers 208. Since the number of electrical channel layers 208, conductive structures 218A and 218B is related to the amount of current 224, the memory structure 200 A current 224 as shown by the four arrows can be generated. The number of conductive structures and electrical channel layers can be adjusted according to requirements. For example, the conductive structure 218A can be provided only on one side of the first electrode 212, and more electrical channel layers 208 can be provided, so that multiple currents can also be realized in a smaller area.

FIG. 4 is a schematic top view of a memory structure 200 according to some embodiments. As shown in FIG. 4, in the first direction D1, the conductive structures 218A and 218B are disposed on both sides of the first electrode 212. Two memory structures 200 can be provided along the third direction D3, but one or more memory structures 200 can also be provided. The third direction D3 is different from the first direction D1. The first direction D1 and the third direction D3 may be substantially perpendicular or orthogonal to each other. Alternatively, the angle between the first direction D1 and the third direction D3 may be about 80 degrees to about 90 degrees.

In the upper view, the first electrode 212 and the conductive structures 218A and 218B are circular, but may also be, for example, elliptical or other shapes. The barrier layers 216A and 216B may be disposed on the sidewalls of the conductive structures 218A and 218B, respectively, and surround the conductive structures 218A and 218B. The resistance transition layer 210 may be disposed on the first electrode 212 On the sidewall and surround the first electrode 212. By making the resistance transition layer 210 surround the first electrode 212, the embodiment of the present invention can use the same layer of resistance transition layer 210 to form a plurality of memory cells, instead of forming a plurality of resistance transition layers 210 for multiple purposes. Therefore, the cost and the volume of the memory structure 200 can be reduced.

In some embodiments, the area of the top surface of the second electrode 222 may be greater than the area of the top surface of the electrical channel layer 208. The edges of the resistance transition layer 210 and the barrier layers 216A and 216B may be located outside the two sidewalls of the electrical channel layer 208 and inside the two sidewalls of the second electrode 222. In addition, multiple memory structures 200 may be arranged in parallel, and these memory structures 200 may respectively include different numbers of components, such as different numbers of electrical channel layers 208 or conductive structures 218A, 218B. Therefore, the embodiments of the present invention can have good design flexibility.

In summary, the memory structure provided by the present invention can increase the number of conductive wires by arranging the resistance transition layer to extend into the electrical channel layer, thereby improving data preservation without increasing the thickness of the resistance transition layer. Therefore, the problems associated with increasing the thickness can be avoided, such as increasing the difficulty of the etching process and increasing the formation voltage of the memory structure.

In addition, in some embodiments, the number of electrical channel layers and/or conductive structures can be adjusted to generate the required number of conductive filaments, thus having good design flexibility. In addition, according to some embodiments, by increasing the number of electrical channel layers, a plurality of memory cells can be formed without increasing the resistance transition layer, so that the cost and volume can be reduced.

Although the embodiments of the present invention have been described above in terms of multiple embodiments, these embodiments are not intended to limit the embodiments of the present invention. Those with ordinary knowledge in the technical field of the present invention should understand that they can make various changes, substitutions and substitutions based on the embodiments of the present invention to achieve the same purpose as the multiple embodiments described herein. And/or advantages. Those with ordinary knowledge in the technical field to which the present invention pertains can also understand that such modifications or designs do not depart from the spirit and scope of the embodiments of the present invention. Therefore, the scope of protection of the present invention shall be subject to those defined by the attached patent scope.

200: Memory structure

202: Base

204: Contact

205: Dielectric layer

206: High dielectric constant layer

208: electrical channel layer

210: Resistance transition layer

212: first electrode

216A, 216B, 220: barrier layer

218A, 218B: conductive structure

222: second electrode

224: Current

D1: First direction

D2: second direction

Claims (14)

A memory structure including: A base An electrical channel layer disposed on the substrate; A first electrode disposed on the substrate and extending into the electrical channel layer; A resistance transition layer disposed between the first electrode and the electrical channel layer; A second electrode disposed on the electrical channel layer; and A conductive structure connects the electrical channel layer and the second electrode. For example, the memory structure of claim 1, further comprising a plurality of conductive structures connecting the electrical channel layer and the second electrode, wherein the conductive structures are disposed on both sides of the first electrode. For example, the memory structure of claim 1, further comprising a plurality of electrical channel layers disposed between the substrate and the second electrode, and the first electrode passes through the electrical channel layers. Such as the memory structure of claim 1, wherein the resistance transition layer is disposed on the sidewall of the first electrode. For example, the memory structure of claim 1, further comprising a dielectric layer disposed between the first electrode and the second electrode, wherein the conductive structure passes through the dielectric layer. A memory structure including: A base An electrical channel layer disposed on the substrate and extending along a first direction; A first electrode disposed on the substrate and extending into the electrical channel layer along a second direction, the second direction being different from the first direction; A resistance transition layer disposed between the first electrode and the electrical channel layer; A second electrode disposed on the electrical channel layer, wherein the substrate, the electrical channel layer and the second electrode are stacked in the second direction; and A conductive structure connects the electrical channel layer and the second electrode and extends along the second direction. A method for manufacturing a memory structure includes: Forming an electrical channel layer on a substrate; Forming a first electrode on the substrate to extend into the electrical channel layer; Forming a resistance transition layer between the first electrode and the electrical channel layer; and A conductive structure is formed on the electrical channel layer and connected to a second electrode. According to the manufacturing method of the memory structure of claim 7, wherein forming the first electrode and the resistance transition layer includes: Forming a trench in the electrical channel layer; Forming the resistance transition layer on the sidewall of the trench; and The first electrode is formed in the remaining part of the trench. According to claim 8, the method of manufacturing a memory structure, wherein the groove exposes a contact in the substrate. For example, the method for manufacturing a memory structure of claim 7, wherein the formation of the conductive structure includes: Forming a through hole extending to the electrical channel layer; Forming a barrier layer on the sidewall of the through hole; and The conductive structure is formed in the remaining part of the through hole. For example, the manufacturing method of the memory structure of claim 7 further includes: Forming a plurality of conductive structures on both sides of the first electrode to extend to the electrical channel layer; and The second electrode is formed on the electrical channel layer, wherein the second electrode is electrically connected with the conductive structures. According to claim 7, the method for manufacturing a memory structure further includes forming a plurality of electrical channel layers on the substrate, wherein the first electrode extends into the electrical channel layers. According to claim 7, the manufacturing method of the memory structure further includes forming a dielectric layer to cover the first electrode before forming the conductive structure, wherein the forming of the conductive structure includes passing through the dielectric layer. According to the manufacturing method of the memory structure of claim 7, wherein the resistance transition layer surrounds the first electrode and exposes the top surface of the first electrode.

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