CN114665009A

CN114665009A - Memory structure and manufacturing method thereof

Info

Publication number: CN114665009A
Application number: CN202011528044.3A
Authority: CN
Inventors: 许博砚; 吴伯伦; 郭泽绵; 张维哲; 张硕哲
Original assignee: Winbond Electronics Corp
Current assignee: Winbond Electronics Corp
Priority date: 2020-12-22
Filing date: 2020-12-22
Publication date: 2022-06-24

Abstract

The application provides a memory structure and a manufacturing method thereof. The electrical channel layer is disposed on the substrate. The first electrode is disposed on the substrate and extends into the electrical channel layer. The resistance transition layer is arranged between the first electrode and the electric channel layer. The second electrode is disposed on the electrical channel layer. The conductive structure is connected with the electric channel layer and the second electrode. This application can increase the conductive filament quantity, and then improves data storage, and need not increase the thickness on resistance transition state layer.

Description

Memory structure and manufacturing method thereof

Technical Field

The present invention relates generally to semiconductor fabrication, and more particularly to memory structures and methods of fabricating the same.

Background

As the size of semiconductor devices decreases, the difficulty in manufacturing semiconductor devices increases, and unwanted defects may be created during the fabrication of the semiconductor devices, which may cause degradation or damage to the devices. Therefore, improvements in semiconductor devices are required to improve yield and improve process margins.

Disclosure of Invention

According to some embodiments of the invention, a memory structure is provided. The memory structure comprises a substrate; an electrical channel layer (electrical channel layer) disposed on the substrate; the first electrode is arranged on the substrate and extends into the electric channel layer; the resistance state-transition layer is arranged between the first electrode and the electric channel layer; the second electrode is arranged on the electric channel layer; and the conductive structure is connected with the electric channel layer and the second electrode.

According to some embodiments of the invention, a memory structure is provided. The memory structure comprises a substrate; the electric channel layer is arranged on the substrate and extends along a first direction; the first electrode is arranged on the substrate and extends into the electric channel layer along a second direction, and the second direction is different from the first direction; the resistance state-transition layer is arranged between the first electrode and the electric channel layer; the second electrode is arranged on the electric channel layer, wherein the substrate, the electric channel layer and the second electrode are stacked in a second direction; and the conductive structure is connected with the electric channel layer and the second electrode and extends along the second direction.

According to some embodiments of the present disclosure, methods of fabricating memory structures are provided. The method includes forming an electrical channel layer on a substrate; forming a first electrode on the substrate and extending into the electrical channel layer; forming a resistance transition layer between the first electrode and the electrical channel layer; and forming a conductive structure on the electrical channel layer to connect to the second electrode.

Drawings

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale and are merely illustrative. In fact, the dimensions of the elements may be arbitrarily expanded or reduced to clearly illustrate the features of the present invention.

FIG. 1 is a cross-sectional schematic diagram illustrating a memory structure, according to some embodiments.

Fig. 2A-2E are cross-sectional schematic diagrams illustrating various stages in the fabrication of a memory structure according to some embodiments.

FIG. 3 is a cross-sectional schematic diagram illustrating a memory structure, according to some embodiments.

FIG. 4 is a schematic top view of a memory structure according to some embodiments.

[ notation ] to show

100,200 memory structures;

102,110,204, a contact;

104,212, a first electrode;

106,210, a resistance transition layer;

108,222, a second electrode;

202, a substrate;

205 a dielectric layer;

206 high dielectric constant layer;

208, an electrical channel layer;

209, a groove;

214A,214B, perforation;

216A,216B,220: barrier layer;

218A,218B, conductive structures;

224, current;

226 conductive filaments;

d1, a first direction;

d2, a second direction;

d3: third direction.

Detailed Description

The following summarizes some embodiments so that those skilled in the art to which the present invention pertains may more easily understand the present invention. However, these examples are only examples and are not intended to limit the present invention. It is understood that one skilled in the art may modify the embodiments described below, e.g., change the process sequence and/or include more or fewer steps than those described herein, as desired, and such modifications are not beyond the scope of the present invention.

In addition, other elements may be added to the embodiments described below. For example, a description of "forming a second element on a first element" may include embodiments in which the first element is in direct contact with the second element, and may also include embodiments in which there are additional elements between the first element and the second element such that the first element and the second element are not in direct contact, and the relationship between the first element and the second element may change as the device is operated or used in different orientations.

In the following description, a description of a "first element passing through a second element" may include the first element being in the second element and extending from a first side of the second element to an opposite second side, wherein a surface of the first element may be flush with a surface of the second element or a surface of the first element may be outside a surface of the second element. In addition, the present invention may repeat reference numerals and/or letters in the various embodiments, such repetition is for the purpose of simplicity and clarity and has not been used to indicate a relationship between the various embodiments discussed.

Memory structures and methods of fabricating the same are described below, and are particularly applicable to non-volatile memories (NVMs), such as resistive random-access memories (RRAMs), according to some embodiments of the present invention. The resistance transition layer is arranged to extend into the electric channel layer, so that the number of the conductive wires (filament) can be increased and the data retention (data retention) can be improved under the condition of not increasing the forming voltage.

Fig. 1 is a cross-sectional schematic diagram illustrating a memory structure 100, according to some embodiments. As shown in fig. 1, the memory structure 100 includes

contacts

102 and 110 connected to a first electrode 104 and a second electrode 108, respectively, and the memory structure 100 includes a resistance transition layer 106 disposed between the first electrode 104 and the second electrode 108.

When a forward voltage is applied to the memory device 100, oxygen ions in the resistance transition layer 106 migrate to the electrode above the resistance transition layer, and an oxygen vacancy conduction wire (not shown) is formed in the resistance transition layer 106, so that the resistance transition layer 106 is converted into a low resistance state. Conversely, when a reverse voltage is applied to the memory device 100, the oxygen ions return to the resistance transition layer 106 and combine with the oxygen vacancies in the resistance transition layer 106, resulting in the disappearance of the oxygen vacancy conductive filaments and the transition of the resistance transition layer 106 to the high resistance state. The memory device 100 converts the resistance value in the above manner to store or read data, thereby achieving a memory function.

In some embodiments, the high temperatures used during the fabrication of the memory structure can reduce the current in the low resistance state, degrading data retention. Since the current of the conductive filament is related to the concentration of oxygen vacancies, some methods increase the current in the low resistance state by increasing the thickness of the resistive switching layer 106 to provide more oxygen vacancies, thereby improving data retention. However, such methods also introduce some problems. For example, since the material of the resistive transition layer 106 is less easily etched, increasing the thickness of the resistive transition layer 106 also increases the difficulty of the etching process, such as making it difficult to form the resistive transition layer 106 into a desired shape. In addition, increasing the thickness of the resistance transition layer 106 also increases the formation voltage of the memory structure 100, which is not conducive to mass production of the memory structure 100. Accordingly, the present invention further provides the following embodiments, which improve the above-mentioned problems.

Fig. 2A-2E are cross-sectional schematic diagrams illustrating a memory structure 200 according to some other embodiments. As shown in fig. 2A, the memory structure 200 includes a substrate 202. Any suitable substrate material for memory structure 200 may be used for substrate 202. For example, the substrate 202 may comprise an oxide.

In some embodiments, the memory structure 200 includes a contact 204 disposed in a substrate 202. The contacts 204 may comprise a conductive material, such as doped or undoped polysilicon, a metal, similar materials, or combinations of the foregoing. For example, the metal comprises gold, nickel, platinum, palladium, iridium, titanium, chromium, tungsten, aluminum, copper, tantalum, hafnium, similar materials, alloys of the foregoing, multilayer structures of the foregoing, or combinations of the foregoing. According to some embodiments, the deposition process comprises a physical vapor deposition process, a chemical vapor deposition process, an atomic layer deposition process, an evaporation process, an electroplating process, a similar process, or a combination of the foregoing.

Then, according to some embodiments, a dielectric layer 205 is formed over the contacts 204 covering the contacts 204. In some embodiments, the dielectric layer 205 and the substrate 202 comprise the same material, and thus the interface between the dielectric layer 205 and the substrate 202 is not depicted. In other embodiments, the dielectric layer 205 and the substrate 202 comprise different materials, and an interface may exist between the dielectric layer 205 and the substrate 202. The method of forming the dielectric layer 205 may include chemical vapor deposition, atomic layer deposition, similar deposition processes, or a combination of the foregoing.

Then, according to some embodiments, a pair of high-k layers 206 and an electrical channel layer 208 between the high-k layers 206 are formed on the dielectric layer 205. The high-k layer 206 and the electrical channel layer 208 may extend along a first direction D1. The high dielectric constant layer 206 may comprise a material having a dielectric constant greater than 3.9, such as tantalum oxide, hafnium oxide, aluminum oxide, similar materials, or combinations of the foregoing. The electrical via layer 208 may comprise titanium, titanium nitride, tantalum nitride, hafnium nitride, similar materials, or combinations thereof. The formation method of the high-k layer 206 and the electrical channel layer 208 may be similar to the formation method of the dielectric layer 205, and thus, the description thereof is omitted.

The number of the electrical channel layers 208 is related to the amount of current, and two electrical channel layers 208 are illustrated, but the invention is not limited thereto. More or fewer electrical channel layers 208 may be used depending on the amount of current flow, and a dielectric layer 205 may be disposed between the electrical channel layers 208. A dielectric layer 205 is then deposited over the uppermost electrical channel layer 208.

Memory device 200 is then etched to form trench 209, according to some embodiments. As shown in fig. 2A, trench 209 passes through dielectric layer 205, high-k layer 206, and electrical channel layer 208, and exposes contact 204. The trench 209 may extend along a second direction D2, the second direction D2 being different from the first direction D1. The first direction D1 and the second direction D2 may be substantially perpendicular (perpendicular) or orthogonal (orthogonal). Alternatively, the included angle between the first direction D1 and the second direction D2 may be about 80 degrees to about 90 degrees.

In some embodiments, trench 209 may be formed by disposing a mask layer (not shown) on dielectric layer 205, followed by an etching process using the mask layer as an etch mask. In some embodiments, the masking layer may comprise a hard mask and may be formed of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, similar materials, or combinations of the foregoing. The mask layer may be a single layer structure or a multi-layer structure. The formation of the masking layer 104 may include a deposition process, a photolithography process, other suitable processes, or a combination of the foregoing. In some embodiments, the deposition process comprises spin-on coating, chemical vapor deposition, atomic layer deposition, similar deposition processes, or a combination of the foregoing. In some embodiments, the photolithography process may include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, development, cleaning (rinsing), drying (e.g., hard baking), other suitable processes, or a combination of the foregoing.

In some embodiments, the etching process of trench 209 may comprise a dry etching process, a wet etching process, or a combination of the foregoing. For example, the dry etching process may include Reactive Ion Etching (RIE), Inductively Coupled Plasma (ICP) etching, Neutral Beam Etching (NBE), electron cyclotron resonance (ERC) etching, the like, or a combination thereof. For example, the wet etching process may use, for example, hydrofluoric acid, ammonium hydroxide, or any suitable etchant.

Then, according to some embodiments, a resistance inversion layer 210 is formed on the sidewalls of trench 209, as shown in fig. 2B. The resistance transition layer 210 may extend generally along the second direction D2. In some embodiments, the material of the resistive switching layer 210 may comprise a transition metal oxide, such as nickel oxide, titanium oxide, hafnium oxide, zirconium oxide, zinc oxide, tungsten oxide, aluminum oxide, tantalum oxide, molybdenum oxide, copper oxide, similar materials, or combinations of the foregoing. The method of forming the resistive switching layer 210 may include an atomic layer deposition process, a chemical vapor deposition process, a physical vapor deposition process, a similar deposition process, or a combination thereof.

Then, according to some embodiments, a first electrode 212 is formed in the remaining portion of trench 209. The first electrode 212 may extend generally along the second direction D2. The material of the first electrode 212 may comprise a metal or a metal nitride, such as platinum, titanium nitride, gold, titanium, tantalum nitride, tungsten nitride, copper, similar materials, or combinations of the foregoing. In some embodiments, the material of the first electrode 212 comprises copper. The first electrode 212 may be formed by an atomic layer deposition process, a chemical vapor deposition process, a physical vapor deposition process, a similar deposition process, or a combination thereof.

As shown in fig. 2B, the resistive switching layer 210 is adjacent to the first electrode 212, and the resistive switching layer 210 is located on the sidewall of the first electrode 212 and exposes the top surface of the first electrode 212. In some embodiments, the resistive switching layer 210 and the first electrode 212 extend through the electrical via layer 208 toward the substrate 202 and contact the contact 204. According to some embodiments, as shown in fig. 2B, the resistive switching layer 210 and the first electrode 212 are substantially perpendicular to the top surface of the substrate 202, but the invention is not limited thereto, and the resistive switching layer 210 and the first electrode 212 may have any suitable angle with the top surface of the substrate 202. A planarization process, such as a chemical mechanical polishing process, may then be performed to remove excess material and provide a planar surface.

Although in the embodiment of fig. 2B, the first electrode 212 passes through the electrical channel layer 208, i.e., the top surface of the first electrode 212 is above the electrical channel layer 208, and the bottom surface of the first electrode 212 is below the electrical channel layer 208, the invention is not limited thereto. For example, the first electrode 212 may extend partially into the electrical channel layer 208 such that a top surface of the first electrode 212 is in the electrical channel layer 208.

Then, according to some embodiments, as shown in fig. 2C, a dielectric layer 205 is formed on the first electrode 212 covering the first electrode 212 and the resistance transition layer 210. Then, the memory device 200 is etched to form vias 214A and 214B.

Vias

214A and 214B pass through the dielectric layer 205, the high-k layer 206, and the electrical channel layer 208 and are located on both sides of the first electrode 212. The formation method of

vias

214A and 214B may be similar to the formation method of trench 209, and therefore, the description thereof is omitted.

Although in the embodiment of fig. 2C, the

vias

214A and 214B pass through the electrical channel layer 208 and the bottom surfaces of the

vias

214A and 214B are below the electrical channel layer 208, the invention is not limited thereto. For example, vias 214A and 214B may extend partially into electrical channel layer 208 such that the bottom surfaces of

vias

214A and 214B are in electrical channel layer 208. Alternatively, according to other embodiments, the

vias

214A and 214B may not extend into the electrical channel layer 208, and the bottom surfaces of the

vias

214A and 214B are flush with the top surface of the electrical channel layer 208. Further, the

vias

214A and 214B may each have a different depth, and the number of vias may be more or less than two.

Then, according to some embodiments, as shown in fig. 2D, barrier layers 216A and 216B are formed on the sidewalls of

vias

214A and 214B, respectively, and

conductive structures

218A and 218B are formed on the remaining portions of

vias

214A and 214B, respectively. The

conductive structures

218A and 218B may extend generally along the second direction D2. In some embodiments, the barrier layers 216A and 216B are positioned between the

conductive structures

218A and 218B, respectively, and the electrical channel layer 208. The material of

barrier layers

216A and 216B can comprise alumina, and the method of forming

barrier layers

216A and 216B can comprise an atomic layer deposition process, a chemical vapor deposition process, a physical vapor deposition process, a similar deposition process, or a combination of the foregoing. The

conductive structures

218A and 218B may comprise a conductive material, such as a metal or a metal nitride. In some embodiments, the material of the

conductive structures

218A and 218B includes copper.

As shown in fig. 2E, the

conductive structures

218A and 218B extend to the electrical channel layer 208, and the resistive transition layer 210 is located between the first electrode 212 and the

conductive structures

218A and 218B. In some embodiments, the top surfaces of the

conductive structures

218A and 218B are higher than the top surface of the first electrode 212. According to some embodiments, as shown in fig. 2D, the

conductive structures

218A and 218B are substantially perpendicular to the top surface of the substrate 202, although the invention is not limited in this respect and the

conductive structures

218A and 218B may have any suitable angle with respect to the top surface of the substrate 202. A planarization process, such as a chemical mechanical polishing process, may then be performed to remove excess material and provide a planar surface.

The depth of the

conductive structures

218A and 218B is dependent on the depth of the

vias

214A and 214B, and thus, as previously discussed with respect to the

vias

214A and 218B, the

conductive structures

218A and 218B may or may not pass through the electrical channel layer 208. Specifically, the bottom surfaces of the

conductive structures

218A and 218B may be flush with the top surface of the electrical channel layer 208, or the bottom surfaces of the

conductive structures

218A and 218B may be in or below the electrical channel layer 208.

Then, according to some embodiments, as shown in fig. 2E, a barrier layer 220 and a second electrode 222 are formed on the electrical channel layer 208. The substrate 202, the electrical channel layer 208, and the second electrode 222 may be stacked substantially in the second direction D2. The material of barrier layer 220 may comprise titanium, titanium nitride, tungsten nitride, tantalum nitride, similar materials, or combinations thereof. The material of the second electrode 222 may comprise a conductive material, such as a metal or a metal nitride. The method of forming the barrier layer 220 and the second electrode 222 may each independently comprise an atomic layer deposition process, a chemical vapor deposition process, a physical vapor deposition process, a similar deposition process, or a combination of the foregoing.

As shown in FIG. 2E, the second electrode 222 covers the

conductive structures

218A and 218B and is electrically connected to the

conductive structures

218A and 218B, such that the current 224 flows from the first electrode 212 to the second electrode 222 via the electrical channel layer 208 and the

conductive structures

218A and 218B. Although in fig. 2E, the second electrode 222 is electrically connected to the

conductive structures

218A and 218B at the same time, two second electrodes 222 may be provided to be electrically connected to the

conductive structures

218A and 218B, respectively.

Referring to fig. 3, a path for forming the conductive filaments 226 to form the current 224 is described. Fig. 3 is a cross-sectional schematic diagram depicting a memory structure 200 according to some embodiments. For convenience of illustration, in fig. 3, only the first electrode 212, the resistance transition layer 210 and the electrical channel layer 208 are illustrated, and not all of the components in fig. 2E are illustrated.

As shown in FIG. 3, the resistive switching layer 210 is disposed between the first electrode 212 and the electrical channel layer 208. When a forward voltage is applied to the memory device 200, the resistive transition layer 206 forms conductive wires 226 adjacent to two sides of the electrical channel layer 208, and the two electrical channel layers 208 can generate four conductive wires 226. These conductive filaments 226 connect the first electrode 212 and the electrical channel layer 208 and form a path for the current 224 as shown in FIG. 2E. Therefore, in the embodiment of the invention, by providing the resistance transition layer 210 extending into the electrical channel layer 208, the number of the conductive wires can be increased without increasing the thickness of the resistance transition layer 210, thereby improving data storage.

Referring to FIG. 2E, the memory structure 200 includes the

conductive structures

218A and 218B and the two layers of the electrical channel layer 208. since the number of the electrical channel layer 208, the

conductive structures

218A and 218B is related to the number of the electrical current 224, the memory structure 200 can generate the electrical current 224 as shown by the four arrows. The number of the conductive structures and the number of the electrical channel layers can be adjusted according to requirements. For example, the conductive structure 218A may be disposed on only one side of the first electrode 212, and more electrical channel layers 208 may be disposed, so that multiple currents can be realized on a smaller area.

FIG. 4 is a schematic top view of the memory structure 200 according to some embodiments. As shown in fig. 4, in the first direction D1, the

conductive structures

218A and 218B are disposed on both sides of the first electrode 212. Two memory structures 200 may be provided along the third direction D3, but one or more memory structures 200 may also be provided. The third direction D3 is different from the first direction D1. The first direction D1 and the third direction D3 may be substantially perpendicular or orthogonal to each other. Alternatively, the included angle between the first direction D1 and the third direction D3 may be about 80 degrees to about 90 degrees.

In the top view, the first electrode 212, the

conductive structures

218A and 218B are circular, but may be, for example, oval or other shapes. The

barrier layer

216A and 216B may be disposed on sidewalls of the

conductive structures

218A and 218B, respectively, and surround the

conductive structures

218A and 218B. The resistive switching layer 210 may be disposed on a sidewall of the first electrode 210 and surround the first electrode 210. By surrounding the first electrode 210 with the resistive transition layer 210, embodiments of the invention can form a plurality of memory cells with the same resistive transition layer 210, without forming a plurality of resistive transition layers 210 for a plurality of memory cells, thereby reducing the cost and the size of the memory structure 200.

In some embodiments, the area of the top surface of the second electrode 222 may be greater than the area of the top surface of the electrical channel layer 208. The edges of the resistive switching layer 210 and the barrier layers 216A and 216B can be outside the two sidewalls of the electrical channel layer 208 and inside the two sidewalls of the second electrode 222. In addition, a plurality of memory structures 200 may be arranged in parallel, and the memory structures 200 may include different numbers of elements, such as different numbers of electrical channel layers 208 or

conductive structures

218A,218B, respectively. Therefore, the embodiment of the invention can have good design flexibility.

In summary, in the memory structure provided by the present invention, the resistance state transition layer is disposed to extend into the electrical channel layer, so that the number of the conductive wires can be increased, and the data storage can be further improved, without increasing the thickness of the resistance state transition layer, thereby avoiding the problems associated with the increase of the thickness, such as increasing the difficulty of the etching process and increasing the forming voltage of the memory structure.

In addition, in some embodiments, the number of the electrical channel layers and/or the number of the conductive structures may be adjusted to generate the required number of the conductive filaments, thereby providing good design flexibility. In addition, according to some embodiments, by increasing the number of the electrical channel layers, a plurality of memory cells can be formed without increasing the resistance transition layer, thereby reducing the cost and volume.

Although the embodiments of the present invention have been described above with reference to a plurality of embodiments, these embodiments are not intended to limit the embodiments of the present invention. Those skilled in the art should appreciate that they can readily use the present disclosure as a basis for modifying, replacing or replacing various features of the present disclosure to achieve the same purposes and/or advantages of the various embodiments described herein. It will also be appreciated by those skilled in the art that such modifications or arrangements do not depart from the spirit and scope of the embodiments of the invention. Therefore, the protection scope of the present invention is subject to the claims.

Claims

1. A memory structure, comprising:

a substrate;

an electrical channel layer disposed on the substrate;

a first electrode disposed on the substrate and extending into the electrical channel layer;

a resistance transition layer disposed between the first electrode and the electrical channel layer;

a second electrode disposed on the electrical channel layer; and

and the conductive structure is connected with the electric channel layer and the second electrode.

2. The memory structure of claim 1, further comprising a plurality of conductive structures connecting the electrical channel layer and the second electrode, wherein the conductive structures are disposed on both sides of the first electrode.

3. The memory structure of claim 1, further comprising a plurality of electrical channel layers disposed between the substrate and the second electrode, wherein the first electrode passes through the electrical channel layers.

4. The memory structure of claim 1, wherein the resistive switching layer is disposed on a sidewall of the first electrode.

5. The memory structure of claim 1, further comprising a dielectric layer disposed between the first electrode and the second electrode, wherein the conductive structure passes through the dielectric layer.

6. A memory structure, comprising:

a substrate;

the electric channel layer is arranged on the substrate and extends along a first direction;

a first electrode disposed on the substrate and extending into the electrical channel layer along a second direction, the second direction being different from the first direction;

a second electrode disposed on the electrical channel layer, wherein the substrate, the electrical channel layer, and the second electrode are stacked in the second direction; and

and the conductive structure is connected with the electric channel layer and the second electrode and extends along the second direction.

7. A method of fabricating a memory structure, comprising:

forming an electrical channel layer on a substrate;

forming a first electrode on the substrate and extending into the electrical channel layer;

forming a resistance transition layer between the first electrode and the electrical channel layer; and

a conductive structure is formed on the electrical channel layer and connected to a second electrode.

8. The method of claim 7, wherein forming the first electrode and the resistive transition layer comprises:

forming a trench in the electrical channel layer;

forming the resistance state transition layer on the side wall of the groove; and

forming the first electrode in the remaining portion of the trench.

9. The method of claim 8, wherein the trench exposes a contact in the substrate.

10. The method of claim 7, wherein the forming of the conductive structure comprises:

forming a through hole extending to the electrical channel layer;

forming a barrier layer on the side wall of the through hole; and

and forming the conductive structure on the rest part of the through hole.

11. The method of claim 7, further comprising:

forming a plurality of conductive structures on two sides of the first electrode and extending to the electric channel layer; and

forming the second electrode on the electrical channel layer, wherein the second electrode is electrically connected to the conductive structure.

12. The method of claim 7, further comprising forming a plurality of electrical channel layers on the substrate, wherein the first electrode extends into the electrical channel layers.

13. The method of claim 7, further comprising forming a dielectric layer overlying the first electrode prior to forming the conductive structure, wherein forming the conductive structure comprises passing through the dielectric layer.

14. The method of claim 7, wherein the resistive switching layer surrounds the first electrode and exposes a top surface of the first electrode.