TWI743834B - Constant on-time controller and buck regulator device using the same - Google Patents
Constant on-time controller and buck regulator device using the same Download PDFInfo
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Description
本發明關於一種降壓調節器,尤其關於一種使用於降壓調節器裝置的恆定導通時間(constant on-time,COT)控制器。 The present invention relates to a step-down regulator, and more particularly to a constant on-time (COT) controller used in a step-down regulator device.
COT控制器已被廣泛地使用於降壓調節器裝置,其可使用一調節器(regulator)來輸出電壓漣波,並藉此於調節輸出電壓(regulator output voltage)降到一參考電壓時起始一導通時間(on-time)。請參考第1A圖,第1A圖示意了一開關的電流波形以及對應的操作。如第1A圖所示,導通時間(亦即對應的邏輯準位為高準位的期間)可透過電路響應於一些狀況(諸如參考調節輸入電壓(regulator input voltage)的準位)來終止。在脈波呈現導通時間的期間,電能是直接透過電子開關裝置來從調節輸入電壓供應至調節輸出電壓。類似地,當呈現導通時間的脈波終止時,儲存於電感器中的電能會被供應至調節輸出電壓。 COT controllers have been widely used in step-down regulator devices, which can use a regulator to output voltage ripples and thereby start when the regulator output voltage drops to a reference voltage An on-time. Please refer to Figure 1A. Figure 1A illustrates the current waveform of a switch and the corresponding operation. As shown in FIG. 1A, the on-time (that is, the period during which the corresponding logic level is high) can be terminated by the circuit in response to some conditions (such as referring to the level of the regulator input voltage). During the on-time of the pulse wave, electric energy is directly supplied from the regulated input voltage to the regulated output voltage through the electronic switching device. Similarly, when the pulse showing the on-time is terminated, the electric energy stored in the inductor will be supplied to regulate the output voltage.
具備COT控制器的降壓調節器裝置通常包含透過參考調節輸入電壓以及調節輸出電壓來調整脈波的導通時間長度的電路,故即使在責任週期(duty cycle)改變時仍可呈現近乎恆定的頻率。調節輸出電壓漣波(ripple)會受到流 經輸出電容的等效串聯電阻(equivalent series resistance,ESR)的電感器上的漣波電流影響而有很大的範圍變化。若是採用僅有較小等效串聯電阻的多層陶瓷電容(multilayer ceramic capacitor,MLCC),來則自電感器的電壓漣波也會比較小。如此造成了COT控制器的兩個主要問題,即不穩定性以及易受雜訊影響的問題。 A step-down regulator device with a COT controller usually includes a circuit that adjusts the on-time length of the pulse wave by adjusting the input voltage and adjusting the output voltage by reference, so it can still present a nearly constant frequency even when the duty cycle is changed. . Adjust the output voltage ripple (ripple) will be affected by the flow The ripple current on the inductor of the equivalent series resistance (ESR) of the output capacitor has a wide range of changes. If a multilayer ceramic capacitor (MLCC) with only a small equivalent series resistance is used, the voltage ripple from the inductor will also be relatively small. This causes two main problems of the COT controller, namely instability and susceptibility to noise.
一般來說,COT控制器裝置受益於自震盪(self-oscillating)、結構簡單、在輕載時具有高效率、以及快速負載暫態響應(fast load transient response)等特性。然而,COT控制器裝置遇到一些瓶頸,諸如低雜訊抗擾度(low noise immunity)所造成的抖動現象、嚴重的電磁干擾(Electromagnetic Interference,EMI)問題、對於等效串聯電阻的需求、以及不良的直流調節(DC regulation)。因此,實有需要一種新穎的設計來解決以上問題。 Generally speaking, COT controller devices benefit from the characteristics of self-oscillating, simple structure, high efficiency at light loads, and fast load transient response. However, COT controller devices encounter some bottlenecks, such as jitter caused by low noise immunity, severe electromagnetic interference (EMI) problems, the need for equivalent series resistance, and Poor DC regulation. Therefore, there is a need for a novel design to solve the above problems.
本發明的一目的在於提供一種使用於降壓調節器裝置的恆定導通時間(constant on-time,COT)控制器,以在可保持快速負載暫態響應的情況下增加COT控制器的雜訊邊界(noise margin)。 An object of the present invention is to provide a constant on-time (COT) controller used in a step-down regulator device to increase the noise boundary of the COT controller while maintaining fast load transient response. (noise margin).
本發明的另一目的在於提供一種使用於降壓調節器裝置的COT控制器,以降低COT控制器對於雜訊的敏感程度,例如可大幅降低非理想的抖動現象。 Another object of the present invention is to provide a COT controller used in a buck regulator device to reduce the sensitivity of the COT controller to noise, for example, to greatly reduce non-ideal jitter.
本發明的另一目的在於提供一種使用於降壓調節器裝置,其包含降壓調節器以及電連接於該降壓調節器的COT控制器,以解決不穩定性以及易受 雜訊影響的問題。 Another object of the present invention is to provide a device for a step-down regulator, which includes a step-down regulator and a COT controller electrically connected to the step-down regulator to solve the instability and susceptibility Issues affected by noise.
為了至少能達到以上目的,本發明的一實施例提供了一種COT控制器,其包含一分壓電路、一電流漣波擷取電路、一單次導通計時器、一比較電路,以及一邏輯電路。該分壓電路用於根據一降壓調節器(buck regulator)的輸出電壓產生反饋電壓。該電流漣波擷取電路用以感測來自該降壓調節器的電感器的電流,並且根據所感測到的感測電流來產生不具有直流分量(DC component)的擷取之漣波電流(extracted ripple current)。該單次導通計時器(one-shot on-timer),用以根據該降壓調節器的調節輸入電壓以及該輸出電壓來輸出一COT控制信號。該比較電路電連接於該分壓電路以及該電流漣波擷取電路,用以根據一參考電壓訊號、該反饋電壓以及該擷取之漣波電流來輸出一比較結果。該邏輯電路電連接於該單次導通計時器以及該比較電路,用以根據該比較結果以及該恆定導通時間控制訊號來產生一控制訊號至該降壓調節器。該降壓調節器的導通時間(on-time)係根據該恆定導通時間控制訊號來決定,且該降壓調節器的關閉時間(off-time)係根據該比較結果來決定;以及該電流漣波擷取電路於該降壓調節器的關閉時間的一開始偵測當前週期中的感測波形的直流成份(DC component),且將該當前週期感測到的直流成份與該當前週期的下一週期中的感測波形進行比較,以產生該擷取之漣波電流。 In order to at least achieve the above objectives, an embodiment of the present invention provides a COT controller, which includes a voltage divider circuit, a current ripple capture circuit, a single-on timer, a comparison circuit, and a logic Circuit. The voltage divider circuit is used to generate a feedback voltage according to the output voltage of a buck regulator. The current ripple capture circuit is used to sense the current from the inductor of the buck regulator, and generate the captured ripple current without a DC component according to the sensed current. extracted ripple current). The one-shot on-timer is used to output a COT control signal according to the regulated input voltage of the step-down regulator and the output voltage. The comparison circuit is electrically connected to the voltage divider circuit and the current ripple extraction circuit for outputting a comparison result according to a reference voltage signal, the feedback voltage and the extracted ripple current. The logic circuit is electrically connected to the single conduction timer and the comparison circuit for generating a control signal to the step-down regulator according to the comparison result and the constant conduction time control signal. The on-time of the buck regulator is determined according to the constant on-time control signal, and the off-time of the buck regulator is determined according to the comparison result; and the current ripple The wave capture circuit detects the DC component of the sensing waveform in the current cycle at the beginning of the off time of the buck regulator, and the DC component sensed in the current cycle is compared with the lower part of the current cycle. The sensing waveforms in one cycle are compared to generate the captured ripple current.
此外,本發明另一實施例提供了一種降壓調節器裝置,其包含一COT控制器。該COT控制器包含一分壓電路、一電流漣波擷取電路、一單次導通計時器、一比較電路,以及一邏輯電路。該分壓電路用於根據一降壓調節器的輸出電壓產生反饋電壓。該電流漣波擷取電路用以感測來自該降壓調節器的電感器的電流,並且根據所感測到的感測電流來產生不具有直流分量的擷取之漣波 電流。該單次導通計時器,用以根據該降壓調節器的調節輸入電壓以及該輸出電壓來輸出一COT控制信號。該比較電路電連接於該分壓電路以及該電流漣波擷取電路,用以根據一參考電壓訊號,該反饋電壓以及該擷取之漣波電流來輸出一比較結果。該邏輯電路電連接於該單次導通計時器以及該比較電路,用以根據該比較結果以及該恆定導通時間控制訊號來產生一控制訊號至該降壓調節器。該降壓調節器的導通時間係根據該恆定導通時間控制訊號來決定,且該降壓調節器的關閉時間係根據該比較結果來決定;以及該電流漣波擷取電路於該降壓調節器的關閉時間的一開始偵測當前週期中的感測波形的直流成份,且將該當前週期感測到的直流成份與該當前週期的下一週期中的感測波形進行比較,以產生該擷取之漣波電流。 In addition, another embodiment of the present invention provides a step-down regulator device, which includes a COT controller. The COT controller includes a voltage divider circuit, a current ripple capture circuit, a single-on timer, a comparison circuit, and a logic circuit. The voltage divider circuit is used to generate a feedback voltage according to the output voltage of a step-down regulator. The current ripple capture circuit is used to sense the current from the inductor of the buck regulator, and generate a captured ripple without a DC component based on the sensed current Current. The single-on timer is used for outputting a COT control signal according to the regulated input voltage of the step-down regulator and the output voltage. The comparison circuit is electrically connected to the voltage divider circuit and the current ripple extraction circuit for outputting a comparison result according to a reference voltage signal, the feedback voltage and the extracted ripple current. The logic circuit is electrically connected to the single conduction timer and the comparison circuit for generating a control signal to the step-down regulator according to the comparison result and the constant conduction time control signal. The on-time of the buck regulator is determined according to the constant on-time control signal, and the off-time of the buck regulator is determined according to the comparison result; and the current ripple extraction circuit is in the buck regulator Detect the DC component of the sensing waveform in the current period at the beginning of the off time, and compare the DC component sensed in the current period with the sensing waveform in the next period of the current period to generate the capture Take the ripple current.
根據本發明的一實施例,該單次導通計時器包含一電容器、一電阻器以及一遲滯(hysteresis)比較器。該電容器係電連接於地端,且該電阻器係串聯於該電容器,該電阻器用以接收該電感器上的一第一電壓,其中該第一電壓隨著該調節輸入電壓變化。該遲滯比較器係電連接於該電容器的一連接端以及該電阻器,用以將該電容器的該連接端以及該電阻器之間的一第二電壓與該輸出電壓進行比較以產生一遲滯比較結果訊號,來作為該恆定導通時間控制訊號。 According to an embodiment of the present invention, the single-on timer includes a capacitor, a resistor, and a hysteresis comparator. The capacitor is electrically connected to the ground, and the resistor is connected in series with the capacitor. The resistor is used for receiving a first voltage on the inductor, wherein the first voltage changes with the regulating input voltage. The hysteresis comparator is electrically connected to a connection end of the capacitor and the resistor, and is used to compare a second voltage between the connection end of the capacitor and the resistor with the output voltage to generate a hysteresis comparison The result signal is used as the constant on-time control signal.
根據本發明的一實施例,該邏輯電路係為一RS型正反器(RS flip flop),該RS型正反器的一設定端係電連接於一比較器以及該單次導通計時器,以接收該比較結果訊號以及該恆定導通時間控制訊號的一反向結果(inversion),以及該RS型正反器的一重設端係電連接於該單次導通計時器,以接收該恆定導通時間控制訊號。 According to an embodiment of the present invention, the logic circuit is an RS flip flop, and a setting end of the RS flip flop is electrically connected to a comparator and the single-on timer, To receive the comparison result signal and an inversion of the constant on-time control signal, and a reset terminal of the RS-type flip-flop is electrically connected to the single-on timer to receive the constant on-time Control signal.
根據本發明的一實施例,其中該單次導通計時器包含一電容器、一電流源以及一電壓比較器。該電流源係透過該電容器電連接於一地端,並且產生與該調節輸入電壓成比例的電流,以形成跨過該電容器的一第一電壓。該電壓比較器係電連接於該電容器的一連接端以及該電流源,用以將該輸出電壓與該第一電壓進行比較以輸出該恆定導通時間控制訊號。 According to an embodiment of the present invention, the single-on timer includes a capacitor, a current source, and a voltage comparator. The current source is electrically connected to a ground terminal through the capacitor, and generates a current proportional to the regulated input voltage to form a first voltage across the capacitor. The voltage comparator is electrically connected to a connection end of the capacitor and the current source for comparing the output voltage with the first voltage to output the constant on-time control signal.
根據本發明的一實施例,該COT控制器進一步包含一斜波(ramp)產生器,電連接於該比較電路,用以產生一斜波電壓訊號,其中該比較電路根據該反饋電壓、該參考電壓訊號、該斜波電壓訊號以及該擷取之漣波電流來輸出該比較結果。 According to an embodiment of the present invention, the COT controller further includes a ramp generator electrically connected to the comparison circuit for generating a ramp voltage signal, wherein the comparison circuit is based on the feedback voltage and the reference The voltage signal, the ramp voltage signal and the extracted ripple current output the comparison result.
根據本發明的一實施例,電流漣波擷取電路包含一電流感測放大器、一取樣保持電路以及一減法器。該電流感測放大器用以感測來自該降壓調節器的該電感器的該電流以取得該感測電流;該取樣保持(sample/hold)電路電連接於該電流感測放大器,用以對電流作取樣以及對該測得直流成份作保持;該減法器電連接於該電流感測放大器以及該取樣保持電路,該用以自該當前週期的該下一週期中的該感測波形減去該當前週期中的該測得直流成份以產生該擷取之漣波電流。 According to an embodiment of the present invention, the current ripple capture circuit includes a current sense amplifier, a sample-and-hold circuit, and a subtractor. The current sense amplifier is used to sense the current from the inductor of the buck regulator to obtain the sense current; the sample/hold circuit is electrically connected to the current sense amplifier for The current is sampled and the measured DC component is held; the subtractor is electrically connected to the current sense amplifier and the sample-and-hold circuit, and is used to subtract the sensed waveform in the next cycle from the current cycle The measured DC component in the current cycle generates the extracted ripple current.
根據本發明的一實施例,該比較電路包含一放大器、一電容器、一加法器以及一調變器。該放大器用以接收該參考電壓訊號以及該反饋電壓以產生一調節後參考電壓訊號;該電容器具有兩個端點,分別電連接於該放大器以及地端;該加法器電連接於該放大器,用以自關聯於該擷取之漣波電流的一第 一電壓訊號減去該調節後參考電壓訊號以產生一第二電壓訊號;該調變器(modulator)電連接於該加法器,用以根據該第二電壓訊號以及該反饋電壓來產生該比較結果。 According to an embodiment of the present invention, the comparison circuit includes an amplifier, a capacitor, an adder, and a modulator. The amplifier is used to receive the reference voltage signal and the feedback voltage to generate an adjusted reference voltage signal; the capacitor has two terminals, which are electrically connected to the amplifier and the ground terminal; the adder is electrically connected to the amplifier, To self-correlate to the first one of the captured ripple current A voltage signal is subtracted from the adjusted reference voltage signal to generate a second voltage signal; the modulator is electrically connected to the adder for generating the comparison result according to the second voltage signal and the feedback voltage .
根據本發明的一實施例,該比較電路包含一加法器以及一調變器。該加法器用以自關聯於該擷取之漣波電流的減去該參考電壓訊號,以產生一第二電壓訊號;該調變器電連接於該加法器,用以根據該第二電壓訊號以及該反饋電壓來產生該比較結果。 According to an embodiment of the present invention, the comparison circuit includes an adder and a modulator. The adder is used for subtracting the reference voltage signal from the extracted ripple current to generate a second voltage signal; the modulator is electrically connected to the adder for generating a second voltage signal according to the second voltage signal and The feedback voltage is used to generate the comparison result.
根據本發明的一實施例,該分壓電路包含互相串聯的多個電阻器。 According to an embodiment of the present invention, the voltage divider circuit includes a plurality of resistors connected in series with each other.
綜上所述,本發明為降壓調節器裝置中使用的一COT控制器提供了增強的訊邊界和改善的負載暫態響應,且在某些實施例中還可以消除或減輕非理想的抖動現象,藉此,COT控制器可以進一步具有改善的穩定性和抗擾性。 In summary, the present invention provides an enhanced signal boundary and improved load transient response for a COT controller used in a buck regulator device, and in some embodiments, it can also eliminate or reduce non-ideal jitter. In this way, the COT controller can further have improved stability and immunity.
100:降壓調節器裝置 100: Buck regulator device
11:COT控制器 11: COT controller
12:降壓調節器 12: Buck regulator
M1,M2:電晶體 M1, M2: Transistor
121:預驅動電路 121: Pre-drive circuit
122:電子開關裝置 122: Electronic Switch Device
VIN:調節輸入電壓 V IN : adjust the input voltage
VOUT:調節輸入電壓 V OUT : Adjust the input voltage
RCO:輸出電阻器 R CO : output resistor
CO:輸出電容器 C O : output capacitor
ISW:電流 I SW : current
111:電流漣波擷取電路 111: Current ripple capture circuit
112:分壓電路 112: Voltage divider circuit
113:比較電路 113: comparison circuit
114:單次導通計時器 114: One-shot on timer
115:RS型正反器 115: RS type flip-flop
116:斜波產生器 116: ramp generator
VCOT:電壓訊號 V COT : Voltage signal
RFBH,RFBL:電阻器 R FBH , R FBL : resistor
FB:反饋電壓 FB: Feedback voltage
LX:電感器 L X : Inductor
RLOAD:負載 R LOAD : load
VREF:參考電壓訊號 V REF : Reference voltage signal
TON,TON:訊號 T ON , T ON : signal
S:設定端 S: Setting terminal
R:重設端 R: reset terminal
Q,Q:輸出端 Q, Q: output
21:遲滯比較器 21: Hysteresis comparator
R1:電阻器 R 1 : resistor
C1,C2:電容器 C 1 , C 2 : Capacitor
GND:地端 GND: Ground
31:電流感測放大器 31: Current Sense Amplifier
32:取樣保持電路 32: sample and hold circuit
33:減法器 33: Subtractor
41:放大器 41: Amplifier
42:加法器 42: adder
43:調變器 43: Modulator
VREF’:調節後參考電壓訊號 V REF ': reference voltage signal after adjustment
VSW:電壓 V SW : Voltage
R CO :電阻值 R CO : Resistance value
f sw :頻率 f sw : frequency
VREFX:比較電壓訊號 V REFX : compare voltage signal
第1A圖示意了一開關的電流波形以及對應的操作。 Figure 1A shows the current waveform of a switch and the corresponding operation.
第1B圖係為根據本發明一實施例的降壓調節器裝置的電路圖。 FIG. 1B is a circuit diagram of a step-down regulator device according to an embodiment of the present invention.
第2A圖係為根據本發明一實施例的單次導通計時器(one-shot on-timer)的電路圖。 FIG. 2A is a circuit diagram of a one-shot on-timer according to an embodiment of the invention.
第2B圖係為根據本發明另一實施例的單次導通計時器的電路圖。 FIG. 2B is a circuit diagram of a single-on timer according to another embodiment of the present invention.
第3圖係為根據本發明一實施例的電流漣波擷取電路的電路圖。 FIG. 3 is a circuit diagram of a current ripple extraction circuit according to an embodiment of the invention.
第4A圖係為根據本發明一實施例的比較電路的電路圖。 FIG. 4A is a circuit diagram of a comparison circuit according to an embodiment of the present invention.
第4B圖係為根據本發明另一實施例的比較電路的電路圖。 FIG. 4B is a circuit diagram of a comparison circuit according to another embodiment of the present invention.
第5A圖係為根據本發明一實施例的降壓調節器裝置的訊號的波形圖。 FIG. 5A is a waveform diagram of a signal of a buck regulator device according to an embodiment of the present invention.
第5B圖是第5A圖所示的方案的一較不理想調變情形,其說明了一種在關閉時間週期的終點上偵測感測電流的直流值的情境。 Figure 5B is a less ideal modulation situation of the scheme shown in Figure 5A, which illustrates a situation where the DC value of the sensing current is detected at the end of the off time period.
第5C圖示意了第5A圖以及第5B圖的方案之間的比較。 Figure 5C illustrates the comparison between the schemes of Figure 5A and Figure 5B.
為了使本領域技術人員更容易理解本發明的目的、特徵以及效果,本發明提供實施例以及附圖以進行詳細說明。 In order to make it easier for those skilled in the art to understand the purpose, features, and effects of the present invention, the present invention provides embodiments and drawings for detailed description.
本發明實施例提供了一降壓調節器裝置,包含一恆定導通時間(constant on-time,COT)控制器(例如第1B圖中的COT控制器11)以及電連接於COT控制器的降壓調節器(例如第1B圖中的降壓調節器12),其中COT控制器的一電流漣波擷取電路自電感器感測流經一輸出電容器的等效串聯電阻(equivalent series resistance,ESR)(其用以感測降壓調節器的低測電流)以移除感測電流的直流(DC)成份,藉此產生一擷取之漣波電流,並且根據該擷取之漣波電流產生一漣波電壓訊號至COT控制器的一比較器,以在可保持快速負載暫態響應的情況下增加COT控制器的雜訊邊界(noise margin)。
The embodiment of the present invention provides a step-down regulator device, including a constant on-time (COT) controller (for example, the
另外,在本發明另一實施例中,斜波產生器被使用於COT控制器中以提供一斜波電壓訊號至COT控制器的比較器,COT對於雜訊的敏感度可因此降低,且抖動現象也可實質地降低。簡單來說,以上所提供的降壓調節器裝置的COT控制器能夠解決低穩定性以及對雜訊敏感等問題。 In addition, in another embodiment of the present invention, the ramp generator is used in the COT controller to provide a ramp voltage signal to the comparator of the COT controller, the COT sensitivity to noise can be reduced, and jitter The phenomenon can also be substantially reduced. Simply put, the COT controller of the buck regulator device provided above can solve the problems of low stability and sensitivity to noise.
請參考第1B圖,第1B圖係為根據本發明一實施例的降壓調節器裝置的電路圖,降壓調節器裝置100包含COT控制器11以及電連接於COT控制器11的降壓調節器12,然而COT控制器11並不侷限於恆定導通時間的用途。降壓調節器12的導通與關閉係由COT控制器11來控制。當降壓調節器12係為導通時,COT控制器11透過包含有電晶體M1以及M2的電子開關裝置122來將調節輸入電壓VIN的能量傳至調節輸入電壓VOUT。舉例來說,上述操作可藉由導通電晶體M1以及關閉電晶體M2來實現。當電晶體M1係為關閉且電晶體M2係為導通時,儲存在電感器LX中的能量會供應給調節輸出電壓VOUT。請注意,本發明所採用的電晶體M1或M2實際上可用任何類型的開關元件來取代。
Please refer to Figure 1B. Figure 1B is a circuit diagram of a step-down regulator device according to an embodiment of the present invention. The step-down
COT控制器11接收調節輸出電壓VOUT,並且感測電感器LX上的電流ISW,電流ISW接著會流過一輸出電容器的等效串聯電阻(亦即串聯的輸出電阻器RCO以及輸出電容器CO的加總電阻),而電流ISW亦為降壓調節器12的低側(low side)電流。COT控制器11根據調節輸出電壓VOUT來產生一反饋電壓FB,並且根據感測電流來產生擷取之漣波電流。COT控制器11可根據反饋電壓FB以及該擷取之漣波電流來決定出降壓調節器12的關閉時間(亦即降壓調節器12係為關閉的期間),並且根據調節輸入電壓VIN以及調節輸出電壓VOUT來決定出降壓調節器12的導通時間。
在相關技術中,由於擷取之漣波電流具有電流ISW的直流分量,電流ISW的直流分量會於COT控制器11中被放大,致使COT控制器11的雜訊邊界不夠理想,導致COT控制器11無法精確地控制降壓調節器12的關閉時間。如此一來,上述直流分量會對負載暫態(load transient)帶來更多的壓降(voltage drop)或電壓過衝(voltage overshoot),這意味著負載暫態響應會惡化。此現象會稍後
於第5C圖的實施例中作進一步的描述,而除此之外,相關技術中的非理想抖動現象也是需要解決的問題。
In the related art, since the captured ripple current has the DC component of the current I SW , the DC component of the current I SW will be amplified in the
關於降壓調節器12的細節說明如下,降壓調節器12包含一預驅動(pre-driving)電路121(其可用一邏輯電路來取代)、電晶體M1和M2、電感器LX、輸出電容器CO以及輸出電阻器RCO,其中輸出負載RLOAD可電連接於調節輸出電壓VOUT。輸出電容器CO係以串聯的方式電連接於輸出電阻器RCO,其中輸出電阻器RCO係透過輸出電容器CO而電連接於地端。
The detailed description of the
調節輸出電壓VOUT係電連接於輸出電阻器RCO以及電感器LX,而電子開關裝置122至少包含電晶體M1以及M2(雖然在本實施例繪成NMOS電晶體,但在本發明一些變化例中亦可用PMOS來取代)。電晶體M1以及M2的閘極係電連接於預驅動電路121,電晶體M1的汲極係電連接於調節輸入電壓VIN,電晶體M1的源極係電連接於電感器LX以及電晶體M2的汲極,且電晶體M2的源極係電連接於地端。換言之,電晶體M1以及M2係電連接於COT控制器11,使得COT控制器11能夠對電流ISW作感測。
The regulated output voltage V OUT is electrically connected to the output resistor R CO and the inductor L X , and the
預驅動電路121係用以自COT控制器11接收控制訊號,並且根據該控制訊號來輸出閘控制訊號至電晶體M1、M2的閘極。當電晶體M1係為導通時(此時電晶體M2係為關閉),整個降壓調節器12會因此導通,使得調節輸入電壓VIN的電能被傳送至調節輸出電壓VOUT(亦即電流ISW會增大);以及當電晶體M2係為導通時(此時電晶體M1係為關閉),整個降壓調節器12會因此而關閉,使得儲存於電感器LX中的電能會被提供給調節輸出電壓VOUT(電流ISW會因此下降)。
The
COT控制器11的細節說明如下,COT控制器11包含一電流漣波擷取電路111、一分壓電路112、一比較電路113、一單次導通計時器114、一RS型正反器(RS flip flop)115以及一斜波產生器116。電流漣波擷取電路111係電連接於電晶體M2的汲極,且另電連接於比較電路113。分壓電路112係電連接於調節輸出電壓VOUT以及比較電路113。斜波產生器116係電連接於比較電路113。比較電路113的輸入節點係電連接於參考電壓訊號VREF,且比較電路113的輸出節點係電連接於RS型正反器115。RS型正反器115係電連接於預驅動電路121以及單次導通計時器114。
The details of the
電流漣波擷取電路111會感測電感器LX上流經輸出電容器的等效串聯電阻的電流ISW(亦即降壓調節器12的下側電流)以產生感測電流,並且移除該感測電流中的直流分量以產生擷取之漣波電流(此特徵於稍後描述)。接著,電流漣波擷取電路111會根據擷取之漣波電流來產生漣波電壓訊號至比較電路113。
The current
斜波產生器116係用以產生斜波電壓訊號至比較電路113,其中斜波電壓訊號以及漣波電壓訊號會合併成電壓訊號VCOT。如上所述,斜波電壓訊號係用以減少因雜訊所造成的抖動現象,倘若抖動現象本身並不嚴重,亦可視情況省略斜波電壓訊號的使用。
The
分壓電路112包含電阻器RFBH、RFBL,其中電阻器RFBH係電連接於調節輸出電壓VOUT、比較電路113以及電阻器RFBL,且電阻器RFBL係電連接於地端。分壓電路112根據調節輸出電壓VOUT來產生跨過電阻器RFBL的反饋電壓FB,且反
饋電壓FB會被提供至比較電路113。
The
比較電路113根據電壓訊號VCOT、反饋電壓FB以及參考電壓訊號VREF的相加來產生相加結果,並且將相加結果輸出至RS型正反器115的設定端(圖中標示為"S")。舉例來說,當電壓訊號VCOT與反饋電壓FB的相加結果係小於參考電壓訊號VREF時,RS型正反器115可輸出具有高邏輯準位的控制訊號至預驅動電路121,使得預驅動電路121所產生的閘極控制訊號能夠導通電晶體M1以及關閉電晶體M2。也就是說,當電壓訊號VCOT與反饋電壓FB的相加結果小於參考電壓訊號VREF時,降壓調節器12的關閉時間可被終止。
The
單次導通計時器114接收調節輸入電壓VIN以及調節輸出電壓VOUT,並且根據調節輸入電壓VIN以及調節輸出電壓VOUT來產生導通時間控制訊號TON(如第2A圖以及第2B圖所示)以及導通時間控制訊號TON的一反相(inversion)訊號。導通時間控制訊號TON以及反向訊號會分別被輸入至RS型正反器115的一重設端(圖中標示為"R")以及該設定端。
The one-time turn-on
當導通時間控制訊號TON係為低邏輯準位時,RS型正反器115會輸出具有高邏輯準位的控制訊號至預驅動電路121,且預驅動電路121所產生的閘極控制訊號會導通電晶體M2並且關閉電晶體M1。也就是說,當導通時間控制訊號TON係為低邏輯準位時,降壓調節器12的導通時間會終止。藉此,COT控制器11得以能夠控制降壓調節器12的導通時間和關閉時間。
When the on-time control signal T ON is at a low logic level, the RS-type flip-flop 115 will output a control signal with a high logic level to the
請注意第1B圖中COT控制器11的實作方式並非作為本發明的限制,本領域通常知識者可瞭解能夠達到本發明COT控制器11的功能的一些變化例亦
當屬於本發明的範疇。舉例來說,在一變化例中,RS型正反器115可被另一種類型的正反器所取代。
Please note that the implementation of the
請參考第1B圖以及第2A圖,第2A圖係為根據本發明一實施例的單次導通計時器的電路圖,其中第2A圖可為第1B圖中單次導通計時器114的一範例,但本發明並不以此為限。單次導通計時器114包含一遲滯比較器21、一電阻器R1以及一電容器C1。電阻器R1係電連接於電晶體M1的汲極的電壓VSW以及電晶體M2的源極(亦即電感器LX的一端上的電壓),並且進一步透過電容器C1電連接於地端GND。遲滯比較器21的正輸入端係電連接於調節輸出電壓VOUT,且遲滯比較器21的負輸入端係電連接於電容器C1以及電阻器R1。
Please refer to FIG. 1B and FIG. 2A. FIG. 2A is a circuit diagram of a single-on timer according to an embodiment of the present invention. FIG. 2A may be an example of the single-on
遲滯比較器21將跨過電容器C1的電壓與調節輸出電壓VOUT進行比較以輸出一遲滯比較結果訊號以作為導通時間控制訊號TON。電壓VSW會隨著調節輸入電壓VIN而改變,跨過電容器C1的電壓係根據電壓VSW而產生,且導通時間控制訊號TON係根據電壓VSW以及調節輸出電壓VOUT來決定。也就是說,降壓調節器12的導通時間係根據調節輸入電壓VIN以及調節輸出電壓VOUT來決定。
The
請一併參考第1B圖以及第2B圖,第2B圖係為根據本發明另一實施例的單次導通計時器114的電路圖,但本發明不限於此。單次導通計時器114包含一電流源22、一電壓比較器23以及一電容器CT_ON。電流源22係電連接於一供應電壓VDD,且透過電容器CT_ON電連接於地端。電壓比較器23的正輸入端係電連接於電流源22以及電容器CT_ON,且電壓比較器23的負輸入端係電連接於調節輸出電壓VOUT。
Please refer to FIG. 1B and FIG. 2B together. FIG. 2B is a circuit diagram of a single-on
電流源22根據調節輸入電壓VIN產生流經電容器CT_ON的電流,其中該電流係成比例於調節輸入電壓VIN。流經電容器CT_ON的電流形成跨過電容器CT_ON的電壓VC,且電壓比較器23將電壓VC與調節輸出電壓VOUT進行比較以產生比較結果訊號來作為導通時間控制訊號TON。因此,降壓調節器12的導通時間得以根據調節輸入電壓VIN以及調節輸出電壓VOUT來決定。
The current source 22 generates a current flowing through the capacitor C T_ON according to the regulated input voltage V IN , wherein the current is proportional to the regulated input voltage V IN . The current flowing through the capacitor C T_ON forms a voltage V C across the capacitor C T_ON , and the
接下來,請一併參考第1B圖以及第3圖,第3圖係為根據本發明一實施例的電流漣波擷取電路的電路圖,其中第3圖係為第1B圖中電流漣波擷取電路111的一範例,但本發明不限於此。電流漣波擷取電路111包含一電流感測放大器31(標示為CS_AMP),一取樣保持電路32(標示為S/H)以及一減法器33。電流感測放大器31的一輸入端係電連接於電晶體M1的汲極以及電感器LX,以接收降壓調節器12的低側電流(亦即電流ISW),且電流感測放大器31的另一輸入端係電連接於地端。電流感測放大器31的輸出端係電連接於減法器33以及取樣保持電路32,且減法器33係電連接於取樣保持電路32以及比較器113。
Next, please refer to Figure 1B and Figure 3 together. Figure 3 is a circuit diagram of a current ripple capture circuit according to an embodiment of the present invention. Figure 3 is a current ripple capture circuit in Figure 1B. Take an example of the
電流感測放大器31係用以對電流ISW進行感測,其中感測電流係由電流感測放大器31所產生並且被傳送至減法器33以及取樣保持電路32(在第3圖中標示為S/H)。感測電流的直流分量可被取樣保持電路32所取樣和保持,此外,減法器33可自感測電流減去被保持的直流分量(亦即先前感測到的電流的直流分量)以產生擷取之漣波電流,且該擷取之漣波電流會被輸出作為漣波電壓訊號。減法器33可進一步將斜波電壓訊號從斜波產生器116加到漣波電壓訊號以在比較電路113的輸入端形成電壓訊號VCOT。
The
接下來,請參考第1B圖以及第4A圖,第4A圖係為根據本發明一實施
例的比較電路的電路圖,其中第4A圖可為第1B圖中比較電路113的一範例,但本發明不限於此。比較電路113包含一放大器41(標示為AMP)、一電容器C2、一加法器42以及一調變器43。放大器41的輸出端係電連接於電容器C2的一端,而放大器41的兩個輸入端係分別電連接於反饋電壓FB以及參考電壓訊號VREF。電容器C2的另一端係電連接於地端。調變器43的兩個輸入端係分別電連接於反饋電壓FB以及加法器42的輸出端,且調變器43的輸出端係電連接於RS型正反器115。加法器42的正輸入端係電連接於放大器41的輸出端,且加法器42的負輸入端係電連接於電壓訊號VCOT。
Next, please refer to FIG. 1B and FIG. 4A. FIG. 4A is a circuit diagram of a comparison circuit according to an embodiment of the present invention. FIG. 4A may be an example of the
根據反饋電壓FB以及參考電壓訊號VREF,放大器41可產生一調節後參考電壓訊號VREF’。加法器42自調節後參考電壓訊號VREF’減去電壓訊號VCOT以產生一電壓訊號VREFX。接著,調變器43會根據電壓訊號VREFX以及反饋電壓FB來產生比較結果。
According to the feedback voltage FB and the reference voltage signal V REF , the
請注意,由於放大器41僅用以調節參考電壓訊號VREF,故其準確度不會受到雜訊邊界的補償所影響,但本發明並不受限於以上設計。第4B圖係為根據本發明另一實施例的比較電路的電路圖,在第4B圖的實施例中,放大器41以及第4A圖的電容器C2係被移除。因此,第4B圖中的加法器42會將參考電壓訊號VREF和電壓訊號VCOT相加以產生電壓訊號VREFX,且調變器43根據電壓訊號VREFX以及反饋電壓FB來產生比較結果。
Please note that since the
接著,請參考第5A圖,第5A圖係為根據本發明一實施例的降壓調節器裝置12的訊號的波形圖。如第5A圖所示,首先,在降壓調節器12導通後電流ISW會增大,並於之後降壓調節器12關閉後減小。電壓VSW在降壓調節器12的導
通時間係為正值,並且在降壓調節器12的關閉時間係為負值。感測電流會於關閉時間週期的起始點就被取樣和保持,以取得感測電流的最大直流值。因為在關閉時間週期內感測電流會隨著時間下降,故於關閉時間週期的起始點偵測最大直流值可取得較精確和準確的直流值,而於關閉時間週期的其它時間點進行偵測則會得到較不穩定的結果。
Next, please refer to FIG. 5A, which is a waveform diagram of the signal of the step-down
舉例來說,請參考第5B圖以及第5C圖。第5B圖是第5A圖所示的方案的一較不理想調變情形,其說明了一種在關閉時間週期的終點上偵測感測電流的直流值的情境,第5C圖則示意了第5A圖以及第5B圖的方案之間的比較。在第5C圖左上方的子圖中,直流值會於關閉時間週期的終點被取樣,並且用以減去下一個關閉時間週期的波形以取得相減結果。理想的相減結果應不含直流分量(例如第5C圖右下方的子圖所示偵測到的理想波形)。然而,一旦下一個關閉時間週期中偵測到的電流有改變,偵測結果便會不正確。舉例來說,第5C圖右上方子圖中的偵測結果仍然含有直流分量,這導致第1B圖中COT控制器11會有非理想的調節輸出電壓VOUT。
For example, please refer to Figure 5B and Figure 5C. Figure 5B is a less ideal modulation situation of the scheme shown in Figure 5A, which illustrates a situation where the DC value of the sensed current is detected at the end of the off time period, and Figure 5C shows the scenario of Figure 5A. Figure and the comparison between the schemes in Figure 5B. In the upper left subgraph of Figure 5C, the DC value will be sampled at the end of the off time period and used to subtract the waveform of the next off time period to obtain the subtraction result. The ideal subtraction result should not contain DC components (for example, the ideal waveform detected in the lower right subgraph of Figure 5C). However, once the detected current changes in the next off time period, the detection result will be incorrect. For example, the detection result in the upper right sub-picture in Fig. 5C still contains a DC component, which causes the
從以上可知,於關閉時間週期的起始點偵測最大直流值的操作對於取得乾淨的擷取之漣波電流是有很大幫助的(在此"乾淨"一詞可指不含直流分量或僅包含微量的直流分量),這對於實現理想的COT控制器裝置是極為重要的。換言之,若直流分量能夠被完全移除,則調節輸入電壓VOUT的變化(亦即△VOUT)可透過△IL來得知,其中△IL不具任何直流分量。請參考第1B圖的右半部份,△VOUT可根據以下公式來計算:
其中R CO 代表電阻器RCO的電阻值,f sw 代表使用的頻率。 Where R CO represents the resistance value of the resistor R CO , and f sw represents the frequency used.
如上所述,由於擷取之漣波電流並不具有電流ISW的直流分量,因此最後也不會發生電流ISW的直流分量在COT控制器11處放大的情形,藉此,可增加COT控制器11的雜訊邊界,且COT控制器11可精確地控制降壓調節器12的關閉時間。由於降壓調節器12導通/關閉的精確度已得到加強,故也隨之改善了負載暫態響應。此外,考量到因雜訊所導致的抖動現象,COT控制器11可進一步產生一斜波電壓訊號,並且根據反饋電壓FB、擷取之漣波電流以及該斜波電壓訊號來決定降壓調節器12的關閉時間。借助於斜波電壓訊號,COT控制器11對於雜訊的敏感程度可被降低,故能降低雜訊所導致的抖動現象。此外,從第5A圖的最底列所示的可看出反饋電壓FB與擷取之漣波電流的比較圖可知,COT控制器的雜訊邊界確實被大幅改善。
As described above, since the capture of the ripple current does not have a DC component of the current I SW, and therefore it will not last DC component current I SW is amplified at the COT happens the
感測電流的直流分量可根據取樣保持開關來被取樣及保持。漣波電流擷取電路111可自當前感測到的電流減去被保持的直流分量,以產生擷取之漣波電流。擷取之漣波電流以及參考電壓訊號VREF可被用來產生上述比較電壓訊號VREFX。反饋電壓FB以及比較電壓訊號VREFX可用來決定降壓調節器12的關閉時間。尤其,當反饋電壓FB小於比較電壓訊號VREFX時,降壓調節器12的關閉時間會終止。
The DC component of the sensing current can be sampled and held according to the sample-and-hold switch. The ripple
總結來說,本發明提供了一種使用於降壓調節器裝置的COT控制器,且所提供的COT控制器可透過感測電感器上流經輸出電容器的等效串聯電阻的電流來取得擷取之漣波電流,其中擷取之漣波電流以及反饋電壓可用來決定降壓調節器的關閉時間。由於擷取之漣波電流不具有直流分量,所提供的COT 控制器可具有增強的負載暫態響應。此外,上述的抖動現象可藉由使用斜波電壓訊號來改善,進而補償擷取之漣波電流的斜率(slope),並藉此使得控制器具有更好的穩定性和抗雜訊能力。 In summary, the present invention provides a COT controller for use in a buck regulator device, and the provided COT controller can obtain the extraction by sensing the current flowing through the equivalent series resistance of the output capacitor on the inductor The ripple current, the extracted ripple current and the feedback voltage can be used to determine the turn-off time of the buck regulator. Since the extracted ripple current does not have a DC component, the COT provided The controller may have an enhanced load transient response. In addition, the above-mentioned jitter phenomenon can be improved by using a ramp voltage signal to compensate for the slope of the captured ripple current, and thereby make the controller have better stability and anti-noise ability.
儘管已經透過特定實施例描述了本發明,但是本領域技術人員可以在不脫離本發明申請專利範圍所教導的範疇和精神的情況下進行各種修改和變化。 Although the present invention has been described through specific embodiments, those skilled in the art can make various modifications and changes without departing from the scope and spirit taught in the scope of the patent application of the present invention.
以上所述僅為本發明之較佳實施例,凡依本發明申請專利範圍所做之均等變化與修飾,皆應屬本發明之涵蓋範圍。 The foregoing descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made in accordance with the scope of the patent application of the present invention shall fall within the scope of the present invention.
100:降壓調節器裝置 100: Buck regulator device
11:COT控制器 11: COT controller
12:降壓調節器 12: Buck regulator
M1,M2:電晶體 M1, M2: Transistor
121:預驅動電路 121: Pre-drive circuit
122:電子開關裝置 122: Electronic Switch Device
VIN:調節輸入電壓 V IN : adjust the input voltage
VOUT:調節輸入電壓 V OUT : Adjust the input voltage
RCO:輸出電阻器 R CO : output resistor
CO:輸出電容器 C O : output capacitor
ISW:電流 I SW : current
VSW:電壓 V SW : Voltage
111:電流漣波擷取電路 111: Current ripple capture circuit
112:分壓電路 112: Voltage divider circuit
113:比較電路 113: comparison circuit
114:單次導通計時器 114: One-shot on timer
115:RS型正反器 115: RS type flip-flop
116:斜波產生器 116: ramp generator
VCOT:電壓訊號 V COT : Voltage signal
RFBH,RFBL:電阻器 R FBH , R FBL : resistor
FB:反饋電壓 FB: Feedback voltage
LX:電感器 L X : Inductor
RLOAD:負載 R LOAD : load
VREF:參考電壓訊號 V REF : Reference voltage signal
TON,TON:訊號 T ON , T ON : signal
S:設定端 S: Setting terminal
R:重設端 R: reset terminal
Q,Q:輸出端 Q, Q: output
Claims (16)
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TW109120046A TWI743834B (en) | 2020-06-15 | 2020-06-15 | Constant on-time controller and buck regulator device using the same |
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Citations (5)
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US7714547B2 (en) * | 2008-08-08 | 2010-05-11 | Semtech Corporation | Method and apparatus for constant on-time switch mode converters |
TW201214935A (en) * | 2010-07-26 | 2012-04-01 | Richtek Technology Corp | Constant on-time switching regulator, and control method and on-time calculation circuit therefor |
TW201236338A (en) * | 2011-02-24 | 2012-09-01 | Richtek Technology Corp | Control circuit and method for a ripple regulator |
TW201801434A (en) * | 2016-01-11 | 2018-01-01 | 半導體組件工業公司 | Over-current protection circuit and method for voltage regulators |
US20200127569A1 (en) * | 2018-10-17 | 2020-04-23 | Texas Instruments Incorporated | Ultra-low Iq Buck Converter with Switchable Error Amplifier |
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US7714547B2 (en) * | 2008-08-08 | 2010-05-11 | Semtech Corporation | Method and apparatus for constant on-time switch mode converters |
TW201214935A (en) * | 2010-07-26 | 2012-04-01 | Richtek Technology Corp | Constant on-time switching regulator, and control method and on-time calculation circuit therefor |
TW201236338A (en) * | 2011-02-24 | 2012-09-01 | Richtek Technology Corp | Control circuit and method for a ripple regulator |
TW201801434A (en) * | 2016-01-11 | 2018-01-01 | 半導體組件工業公司 | Over-current protection circuit and method for voltage regulators |
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