TWI699640B - Contstant on-time controller and buck regulator device using the same - Google Patents
Contstant on-time controller and buck regulator device using the same Download PDFInfo
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本發明係有關於一降壓變換器,尤指一種用於一降壓變換器裝置的一固定開路時間(constant on-time)控制器。 The present invention relates to a buck converter, in particular to a constant on-time controller used in a buck converter device.
固定開路時間控制器可以被用在降壓變換器裝置中,無論何時當調節器輸出電壓降至低於參考電壓,固定開路時間控制器可以使用調節器輸出電壓漣波來起始一段開路時間。開路時間可以透過電路對其他條件反應(像是調節器輸入電壓的位準)來終止(產生一開路時間脈波)。在開路時間脈波其間,能量會經由電子開關裝置直接從調節器輸入電壓供給至調節器輸出電壓。相似地,當開路時間脈波已經被終止時,被儲存在能量儲存電感的能量會被供給至調節器輸出電壓。 The fixed open circuit time controller can be used in a buck converter device. Whenever the regulator output voltage drops below the reference voltage, the fixed open circuit time controller can use the regulator output voltage ripple to initiate an open circuit time. The open circuit time can be terminated by the circuit's response to other conditions (such as the level of the regulator input voltage) (generating an open circuit time pulse). During the open-circuit time pulse, energy is directly supplied from the regulator input voltage to the regulator output voltage via the electronic switching device. Similarly, when the open-circuit time pulse has been terminated, the energy stored in the energy storage inductor will be supplied to the regulator output voltage.
具有固定開路時間控制器的降壓變換器裝置通常包含有電路其以調節器輸入電壓與調節器輸出電壓的一函數來調整開路時間脈波的間期,因此在工作週期(duty cycle)改變時仍可得到幾乎固定的頻率。該調節器的輸出電壓漣波在很大的程度上是透過在能量儲存電感中流經輸出電容的等效串聯電阻(equivalent series resistance,ESR)的一漣波電流所決定。在一些應用中,積層陶瓷電容(multilayer ceramic capacitor)具有較小ESR,以至於來自能量儲存電感的 電壓漣波也較小。這會對固定開路時間控制器造成兩個問題,穩定性與對雜訊的雜訊易感性。 A buck converter device with a fixed open-circuit time controller usually includes a circuit that adjusts the interval of the open-circuit time pulse wave as a function of the regulator input voltage and the regulator output voltage, so when the duty cycle is changed Almost a fixed frequency can still be obtained. The output voltage ripple of the regulator is determined to a large extent by a ripple current flowing through the equivalent series resistance (ESR) of the output capacitor in the energy storage inductor. In some applications, multilayer ceramic capacitors have so small ESR that the energy storage inductors The voltage ripple is also small. This will cause two problems for the fixed open time controller, stability and susceptibility to noise.
本發明的目的之一在於提供一種用於降壓變換器裝置的固定開路時間控制器,以延展固定開路時間控制器的一雜訊容限(noise margin)。 One of the objectives of the present invention is to provide a fixed open-circuit time controller for a buck converter device to extend a noise margin of the fixed open-circuit time controller.
本發明之另一目的在於提供一種用於降壓變換器裝置的固定開路時間控制器,以最小化該固定開路時間控制器對雜訊的雜訊易感性(susceptibility),以至於訊號的抖動可以大幅地減少。 Another object of the present invention is to provide a fixed open-circuit time controller for a buck converter device to minimize the susceptibility of the fixed open-circuit time controller to noise, so that the jitter of the signal can be reduced. Significantly reduced.
本發明之另一目的在於提供一種包含降壓變換器固定開路時間控制器的降壓變換器裝置,其電性連接於該降壓變換器,以至於解決穩定性與對雜訊的雜訊易感性的問題。 Another object of the present invention is to provide a buck converter device including a buck converter fixed open-circuit time controller, which is electrically connected to the buck converter, so as to solve the stability and ease of noise. Perceptual question.
為了至少達成上述目的之一,本發明提一種固定開路時間控制器包含分壓器,電流漣波萃取器,單發開路計時器,比較器以及正反器。分壓器根據一調節器輸出電壓來產生一迴授電壓。電流漣波萃取器感測降壓變換器的能量儲存電感中的電流,其流經輸出電容的等效串聯電阻,並據以產生不具有直流分量的萃取漣波電流。單發開路計時器根據降壓變換器輸入電壓與調節器輸出電壓來輸出固定開路時間控制訊號。調變電路根據參考電壓訊號,迴授電壓以及萃取漣波電流來輸出調變訊號。正反器根據該調變訊號與固定開路時間控制訊號來產生控制訊號至降壓變換器。降壓變換器的斷路時間係根據調變訊號所決定。 In order to achieve at least one of the above objectives, the present invention provides a fixed open-circuit time controller including a voltage divider, a current ripple extractor, a single-shot open-circuit timer, a comparator and a flip-flop. The voltage divider generates a feedback voltage according to the output voltage of a regulator. The current ripple extractor senses the current in the energy storage inductor of the buck converter, which flows through the equivalent series resistance of the output capacitor, and accordingly generates an extracted ripple current without a DC component. The single-shot open-circuit timer outputs a fixed open-circuit time control signal based on the input voltage of the buck converter and the output voltage of the regulator. The modulation circuit outputs the modulation signal according to the reference voltage signal, the feedback voltage and the extracted ripple current. The flip-flop generates a control signal to the buck converter according to the modulation signal and the fixed open time control signal. The off time of the buck converter is determined by the modulation signal.
為了至少達成上述目的之一,本發明提供一種降壓變換器裝置包含降壓變換器與固定開路時間控制器其電性連接於降壓變換器。 In order to achieve at least one of the above objectives, the present invention provides a buck converter device including a buck converter and a fixed open-circuit time controller electrically connected to the buck converter.
在本發明之一實施例中,正反器係為一置位復位(reset-set,RS)正反器,RS正反器的一置位端電性連接於比較器與單發開路計時器以接收比較結果訊號與固定開路時間控制訊號之一反相訊號,並且RS正反器的一復位端電性連接於單發開路計時器以接收固定開路時間控制訊號。 In an embodiment of the present invention, the flip-flop is a reset-set (RS) flip-flop, and a set terminal of the RS flip-flop is electrically connected to the comparator and the single-shot open-circuit timer To receive the comparison result signal and an inverted signal of the fixed open time control signal, and a reset terminal of the RS flip-flop is electrically connected to the single-shot open timer to receive the fixed open time control signal.
在本發明之一實施例中,單發開路計時器包含電容,電流源與電壓比較器。電流源經由電容電性連接於地,適用於產生正比於調節器輸入電壓的電流,以至於橫跨電容形成第電壓。電壓比較器電性連接於電容與電流源的連接端,適用於比較調節器輸出電壓與第電壓以輸出固定開路時間控制訊號。 In an embodiment of the present invention, the single-shot open-circuit timer includes a capacitor, a current source and a voltage comparator. The current source is electrically connected to the ground via the capacitor, and is suitable for generating a current proportional to the input voltage of the regulator so as to form a first voltage across the capacitor. The voltage comparator is electrically connected to the connection end of the capacitor and the current source, and is suitable for comparing the output voltage of the regulator with the first voltage to output a fixed open-circuit time control signal.
在本發明之一實施例中,固定開路時間控制器更進一步包含斜坡產生器。斜坡產生器電性連接於調變電路以產生斜坡電壓訊號。調變電路根據迴授電壓,參考電壓訊號,斜坡電壓訊號與萃取漣波電流來輸出調變訊號。 In an embodiment of the present invention, the fixed open time controller further includes a ramp generator. The ramp generator is electrically connected to the modulation circuit to generate a ramp voltage signal. The modulation circuit outputs a modulation signal according to the feedback voltage, the reference voltage signal, the ramp voltage signal and the extracted ripple current.
在本發明之一實施例中,該電流漣波萃取器包含電流感測放大器,抽樣保持電路與減法器。電流感測放大器感測降壓變換器的能量儲存電感中的電流,其流經輸出電容的等效串聯電阻以獲得感測到的電流。抽樣保持電路電性連接於電流感測放大器,適用於抽樣並且保持感測到的電流的直流分量。減法器電性連接於電流感測放大器以及抽樣保持電路,適用於自感測到的電流減去所保持的直流分量以產生萃取漣波電流。 In an embodiment of the present invention, the current ripple extractor includes a current sense amplifier, a sample-and-hold circuit, and a subtractor. The current sense amplifier senses the current in the energy storage inductor of the buck converter, which flows through the equivalent series resistance of the output capacitor to obtain the sensed current. The sample and hold circuit is electrically connected to the current sense amplifier, and is suitable for sampling and holding the DC component of the sensed current. The subtractor is electrically connected to the current sensing amplifier and the sample-and-hold circuit, and is suitable for subtracting the held DC component from the sensed current to generate an extraction ripple current.
在本發明之一實施例中,調變電路包含放大器,電容,加法器以及調變器。放大器接收參考電壓訊號與迴授電壓以產生調節過的參考電壓訊號。電容的兩端分別電性連接於放大器與地。加法器電性連接於放大器,適用於自與萃取漣波電流相關聯的第一電壓訊號減去調節過的參考電壓訊號以產生第二電壓訊號。調變器電性連接於加法器,適用於根據第二電壓訊號與迴授電壓來產生調變訊號。 In an embodiment of the present invention, the modulation circuit includes an amplifier, a capacitor, an adder and a modulator. The amplifier receives the reference voltage signal and the feedback voltage to generate an adjusted reference voltage signal. The two ends of the capacitor are electrically connected to the amplifier and the ground respectively. The adder is electrically connected to the amplifier and is adapted to subtract the adjusted reference voltage signal from the first voltage signal associated with the extracted ripple current to generate the second voltage signal. The modulator is electrically connected to the adder and is suitable for generating a modulating signal according to the second voltage signal and the feedback voltage.
在本發明之一實施例中,調變電路包含加法器以及調變器。加法器電性連接於放大器,適用於自與萃取漣波電流相關聯的第一電壓訊號減去參考電壓訊號以產生第二電壓訊號。調變器電性連接於加法器,適用於根據第二電壓訊號以及迴授電壓來產生調變訊號。 In an embodiment of the present invention, the modulation circuit includes an adder and a modulator. The adder is electrically connected to the amplifier and is adapted to subtract the reference voltage signal from the first voltage signal associated with the extracted ripple current to generate the second voltage signal. The modulator is electrically connected to the adder and is suitable for generating a modulating signal according to the second voltage signal and the feedback voltage.
在本發明之一實施例中,分壓器包含電性串聯連接的多個電阻。 In an embodiment of the present invention, the voltage divider includes a plurality of resistors electrically connected in series.
縱上所述,本發明提供一種固定開路時間控制器,其用於加強降壓變換器裝置的雜訊容限。此外,訊號抖動在一些實施例中可以獲得改善,因此所提供的固定開路時間控制器可以更進一步有改善的穩定性與雜訊容限。 In summary, the present invention provides a fixed open-circuit time controller for enhancing the noise tolerance of the buck converter device. In addition, the signal jitter can be improved in some embodiments, so the provided fixed open-circuit time controller can further improve the stability and noise tolerance.
11:固定開路時間控制器 11: fixed open time controller
111:電流漣波萃取器 111: Current ripple extractor
112:分壓器 112: Voltage divider
113:調變電路 113: Modulation circuit
114:單發開路計時器 114: Single open timer
115:RS正反器 115: RS flip-flop
116:斜坡產生器 116: ramp generator
12:降壓變換器 12: Buck converter
121:預驅動器 121: pre-driver
21:磁滯比較器 21: Hysteresis comparator
22:電流源 22: current source
23:電壓比較器 23: Voltage comparator
31:電流感測放大器 31: current sense amplifier
32:抽樣保持電路 32: sample and hold circuit
33:減法器 33: Subtractor
41:放大器 41: Amplifier
42:加法器 42: adder
43:調變器 43: Modulator
C1、C2、CT_ON:電容 C 1 , C 2 , C T_ON : capacitance
CO:輸出電容 C O : output capacitance
FB:迴授電壓 FB: Feedback voltage
GND:地 GND: ground
ISW:電流 I SW : current
LX:能量儲存電感 L X : Energy storage inductance
M1、M2:電晶體 M1, M2: Transistor
RCO:輸出電阻 R CO : output resistance
R1、RFBH、RFBL:電阻 R 1 , R FBH , R FBL : resistance
RLOAD:輸出負載 R LOAD : output load
VC:電壓 V C : Voltage
VCOT:電壓訊號 V COT : Voltage signal
VDD:供應電壓 V DD : supply voltage
VIN:輸入電壓 V IN : Input voltage
VREF、VREF’:參考電壓訊號 V REF , V REF ': reference voltage signal
VREFX:比較電壓訊號 V REFX : compare voltage signal
VOUT:輸出電壓 V OUT : output voltage
VSW:電壓 V SW : Voltage
TON:開路時間控制訊號 T ON : open circuit time control signal
圖1為本發明降壓變換器裝置之一實施例的電路圖;圖2A為本發明單發開路計時器之一實施例的電路圖;圖2B為本發明單發開路計時器又一實施例的電路圖;圖3為本發明電流漣波萃取器之一實施例的電路圖;圖4A為本發明調變電路之一實施例的電路圖;圖4B為本發明調變電路又一實施例的電路圖;圖5為本發明降壓變換器裝置之一實施例的訊號波形圖。 Fig. 1 is a circuit diagram of an embodiment of a buck converter device of the present invention; Fig. 2A is a circuit diagram of an embodiment of a single-shot open-circuit timer of the present invention; Fig. 2B is a circuit diagram of another embodiment of a single-shot open-circuit timer of the present invention Figure 3 is a circuit diagram of an embodiment of the current ripple extractor of the present invention; Figure 4A is a circuit diagram of an embodiment of the modulation circuit of the present invention; Figure 4B is a circuit diagram of another embodiment of the modulation circuit of the present invention; FIG. 5 is a signal waveform diagram of an embodiment of the buck converter device of the present invention.
為了使審查委員更容易了解本發明之目的、功效與技術特徵,本發明之實施例的詳細說明係與附圖一併提供。 In order to make it easier for the examiner to understand the purpose, efficacy and technical features of the present invention, a detailed description of the embodiments of the present invention is provided together with the accompanying drawings.
本發明之一實施例提供一種降壓變換器裝置,其包含一固定開路時間控制器以及一降壓變換器其電性連接於該降壓變換器,其中該固定開路時間控制器之一電流漣波萃取器係用來感測流動於能量儲存電感中之一電流其流經一輸出電容的等效串聯電阻(也就是用來感測該降壓變換器的一低邊(low side)電流),以移除一感測到的電流中的一直流電流分量,以產生一萃取漣波電流,並且根據該萃取漣波電流來產生一漣波電壓訊號至該固定開路時間控制器的一比較器,以展延該固定開路時間控制器的一雜訊容限(noise margin)。 An embodiment of the present invention provides a buck converter device, which includes a fixed open time controller and a buck converter electrically connected to the buck converter, wherein a current ripple of the fixed open time controller is The wave extractor is used to sense the equivalent series resistance of a current flowing in the energy storage inductor and flowing through an output capacitor (that is, used to sense a low side current of the buck converter) , To remove the DC current component in a sensed current to generate an extracted ripple current, and generate a ripple voltage signal to a comparator of the fixed open time controller according to the extracted ripple current , In order to extend a noise margin of the fixed open time controller.
進一步說,在本發明之另一實施例中,一斜坡產生器在該固定開路時間控制器中被用來提供一斜坡電壓訊號至該固定開路時間控制器的比較器,並且因此最小化該固定開路時間控制器對雜訊的雜訊易感性(susceptibility),以及大幅減少訊號的抖動。簡言之,所提供的該降壓變換器裝置的固定開路時間控制器可以解決穩定性與對雜訊的雜訊易感性的問題。 Furthermore, in another embodiment of the present invention, a ramp generator is used in the fixed open time controller to provide a ramp voltage signal to the comparator of the fixed open time controller, and thus minimize the fixed The open circuit time controller is susceptibility to noise and greatly reduces signal jitter. In short, the provided fixed open-circuit time controller of the buck converter device can solve the problems of stability and susceptibility to noise.
參考圖1,圖1為本發明降壓變換器裝置之一實施例的電路圖。降壓變換器裝置1包含固定開路時間控制器11以及降壓變換器12電性連接於固定開路時間控制器11。降壓變換器12係由固定開路時間控制器11所控制來打開或關閉。當降壓變換器12打開時,降壓變換器12經由一電子開關裝置(電晶體M1與M2所構成)傳遞調節器輸入電壓VIN的能量至調節器輸出電壓VOUT。當降壓變換器12關閉時,在能量儲存電感LX中儲存的能量被供給至調節器輸出電壓VOUT。
Referring to FIG. 1, FIG. 1 is a circuit diagram of an embodiment of a buck converter device of the present invention. The
固定開路時間控制器11接收調節器輸出電壓VOUT,並且感測能量儲存電感LX中流經一輸出電容的等效串聯電阻(也就是輸出電容CO的電阻RCO的阻抗)的電流ISW。電流ISW也是降壓變換器12的低邊電流。固定開路時間控制器11根據調節器輸出電壓VOUT來產生迴授電壓FB,並且根據一感測到的電流來產生一萃取漣波電流。固定開路時間控制器11可以根據迴授電壓FB與萃取漣波
電流來決定降壓變換器12的斷路時間(也就是降壓變換器12關閉的間期),並且根據調節器輸入電壓VIN與調節器輸出電壓VOUT來決定降壓變換器12的一開路時間(也就是降壓變換器12打開的間期)。因為萃取漣波電流不具電流ISW的直流分量,電流ISW的直流分量不會在固定開路時間控制器11中被放大,以至於固定開路時間控制器11的雜訊容限可以被展延,並且固定開路時間控制器11可以精準地控制降壓變換器12的斷路時間。
The fixed open-
更進一步說,為了考量雜訊所造成的訊號抖動,固定開路時間控制器11進一步產生一斜坡電壓訊號,並且根據不只迴授電壓FB與萃取漣波電流,還有斜坡電壓訊號來決定降壓變換器12的斷路時間。因為加入斜坡電壓訊號的考量,固定開路時間控制器11對雜訊的易感性得以降低,並且雜訊造成的訊號抖動得以減少。
Furthermore, in order to consider the signal jitter caused by noise, the fixed
降壓變換器12的說明將詳述如下。降壓變換器12包含預驅動器(pre-driver)121(或一邏輯電路),電晶體M1,M2,能量儲存電感LX,輸出電容CO以及輸出電阻RCO。輸出負載RLOAD可以電性連接於調節器輸出電壓VOUT。輸出電容CO以串聯連接的方式電性連接於輸出電阻RCO,其中輸出電阻RCO經由輸出電容CO電性連接於地。
The description of the
調節器輸出電壓VOUT電性連接輸出電阻RCO與能量儲存電感LX。電晶體M1與M2(例如,PMOS電晶體)組成電子開關裝置。電晶體M1與M2的閘極電性連接於預驅動器121,電晶體M1的源極電性連接於調節器輸入電壓VIN,電晶體M1的汲極電性連接於能量儲存電感LX與電晶體M2的源極,並且電晶體M2的汲極電性連接於地。電晶體M1與M2汲極亦電性連接於固定開路時間控制器11,以至於固定開路時間控制器11可以感測電流ISW。
The regulator output voltage V OUT is electrically connected to the output resistor R CO and the energy storage inductor L X. Transistors M1 and M2 (for example, PMOS transistors) form an electronic switching device. The gates of the transistors M1 and M2 are electrically connected to the pre-driver 121, the source of the transistor M1 is electrically connected to the regulator input voltage V IN , and the drain of the transistor M1 is electrically connected to the energy storage inductor L X and the electric The source of the transistor M2 and the drain of the transistor M2 are electrically connected to the ground. The drains of the transistors M1 and M2 are also electrically connected to the fixed
預驅動器121用來接收來自固定開路時間控制器11的一控制訊號。預驅動器121根據控制訊號來輸出閘極控制訊號至電晶體M1與M2的閘極。
當電晶體M1導通時(同時間,電晶體M2關閉),降壓變換器12被打開,以至於調節器輸入電壓VIN的能量被傳遞至調節器輸出電壓VOUT(也就是電流ISW會增加);以及當電晶體M2導通時(同時間,電晶體M1關閉),降壓變換器12被關閉,以至於能量儲存電感LX中儲存的能量被供給至調節器輸出電壓VOUT(也就是電流ISW會減少)。
The pre-driver 121 is used to receive a control signal from the fixed
繼續參考圖1,固定開路時間控制器11的說明將下述如下。固定開路時間控制器11包含電流漣波萃取器111,分壓器112,調變電路113,單發開路計時器114,置位復位(reset-set,RS)正反器115以及一斜坡產生器116。電流漣波萃取器111電性連接於電晶體M2的汲極,並且進一步電性連接於調變電路113。分壓器112電性連接於調節器輸出電壓VOUT與調變電路113。斜坡產生器116電性連接於調變電路113。調變電路113電性連接於參考電壓訊號VREF與RS正反器115。RS正反器115電性連接於預驅動器121與單發開路計時器114。
With continued reference to FIG. 1, the description of the fixed
電流漣波萃取器111感測能量儲存電感LX中流經一輸出電容的等效串聯電阻(也就是降壓變換器12的低邊電流)的電流ISW以產生感測到的電流,並且移除感測到的電流的直流分量以產生萃取漣波電流。接著,電流漣波萃取器111根據萃取漣波電流來產生一漣波電壓訊號至調變電路113。
The
斜坡產生器116用來產生一斜坡電壓訊號至調變電路113,並且斜坡電壓訊號與漣波電壓訊號結合形成電壓訊號VCOT。如上所述,斜坡電壓訊號係用來減少雜訊造成的訊號抖動,故若是訊號抖動不影響結果(也就是當電壓訊號VCOT是漣波電壓訊號)本發明是可以不需要有斜坡產生器116。
The
分壓器112包含電阻RFBH與RFBL,其中電阻RFBH電性連接於調節器輸出電壓VOUT,調變電路113以及電阻RFBL,且電阻RFBL電性連接於地。分壓器112根據調節器輸出電壓VOUT來產生橫跨電阻RFBL的迴授電壓FB,並且迴授電壓FB係由調變電路113接收。
The
調變電路113根據電壓訊號VCOT與迴授電壓FB的加成結果以及參考電壓訊號VREF來產生一調變訊號,並且輸出調變訊號至RS正反器115的置位端。例如,當電壓訊號VCOT與迴授電壓FB的加成結果小於參考電壓訊號VREF(或自參考電壓訊號VREF產生的參考調節過的電壓訊號)時,RS正反器115輸出邏輯位準高的控制訊號至預驅動器121,並且由預驅動器121產生的閘極控制訊號導通電晶體M1並且關閉電晶體M2。也就是說,當電壓訊號VCOT與迴授電壓FB的加成結果小於參考電壓訊號VREF(或自參考電壓訊號VREF產生的參考調節過的電壓訊號)時,降壓變換器的斷路時間可以被終止。
The
單發開路計時器114接收調節器輸入電壓VIN與調節器輸出電壓VOUT,並且根據調節器輸入電壓VIN與調節器輸出電壓VOUT來產生開路時間控制訊號TON(如圖2A與2B中所示)以及開路時間控制訊號TON的一反相訊號。開路時間控制訊號TON與開路時間控制訊號TON的反相訊號分別輸入至RS正反器115的復位端與置位端。
The single-shot
當開路時間控制訊號TON邏輯位準低時,RS正反器115輸出邏輯位準高的控制訊號至預驅動器121,並且由預驅動器121所產生的閘極控制訊號導通電晶體M2並且關閉電晶體M1。也就是說,當開路時間控制訊號TON的加成結果在邏輯位準低時,降壓變換器的開路時間被終止。於是,固定開路時間控制器11可以控制降壓變換器12的開路時間以及斷路時間。
When the open-circuit time control signal T ON has a low logic level, the RS flip-
值得注意的是,圖1中固定開路時間控制器11的實施態樣並非用來限制本發明。可達成固定開路時間控制器11的功能的其它實施態樣亦可由本領域具有通常知識者在參考本發明後所得。例如,在另一實施例中,RS正反器15可以由別種正反器所取代。
It should be noted that the implementation of the fixed
參考圖1與圖2A,圖2A為本發明單發開路計時器之一實施例的電路圖。值得注意的是圖2A繪示了圖1單發開路計時器114之一實施例,本發明
不以此為限。單發開路計時器114包含磁滯比較器21,電阻R1與電容C1。電阻R1於電晶體M1的汲極與電晶體M2的源極電性連接於電壓VSW(也就是位於能量儲存電感LX的一端的電壓),並進一步經由電容C1電性連接於地。磁滯比較器21的正輸入端與負輸入端正輸入端與負輸入端分別電性連接於調節器輸出電壓VOUT以及電容C1與電阻R1的連接點。
1 and 2A, FIG. 2A is a circuit diagram of an embodiment of a single-shot open-circuit timer of the present invention. It is worth noting that FIG. 2A illustrates an embodiment of the single-shot open-
磁滯比較器21比較橫跨電容C1的電壓與調節器輸出電壓VOUT以輸出一磁滯比較結果訊號作為開路時間控制訊號TON。電壓VSW根據調節器輸入電壓VIN變動,橫跨電容C1的電壓係根據電壓VSW所產生,並且開路時間控制訊號TON係根據電壓VSW與調節器輸出電壓VOUT所決定。也就說,降壓變換器12的開路時間係根據調節器輸入電壓VIN與調節器輸出電壓VOUT所決定。
The
參考圖1與圖B,圖2B為本發明單發開路計時器又一實施例的電路圖。值得注意的是圖2B繪示了圖1中單發開路計時器114之又一實施例,本發明不以此為限。單發開路計時器114包含電流源22,電壓比較器23以及電容CT_ON。電流源22經由電容CT_ON電性連接供應電壓VDD與地。電壓比較器23的正輸入端與負輸入端分別電性連接於電流源22與電容CT_ON的連接點以及調節器輸出電壓VOUT。
1 and FIG. B, FIG. 2B is a circuit diagram of another embodiment of a single-shot open-circuit timer of the present invention. It is worth noting that FIG. 2B illustrates another embodiment of the single-shot open-
電流源22來根據調節器輸入電壓VIN產生流經電容CT_ON的一電流,其中電流正比於調節器輸入電壓VIN。電流流經電容CT_ON形成橫跨電容CT_ON之電壓VC,並且電壓比較器23比較電壓VC與調節器輸出電壓VOUT以產生比較結果訊號作為開路時間控制訊號TON。於是,降壓變換器12的開路時間根據調節器輸入電壓VIN與調節器輸出電壓VOUT所決定。
The
接著,參考圖1與圖3,圖3為本發明電流漣波萃取器之一實施例的電路圖。值得注意的是,圖3繪示了圖1中電流漣波萃取器111的一實施例,本發明不以此為限。電流漣波萃取器111包含電流感測放大器31,抽樣保持電
路32以及減法器33。電流感測放大器31的一輸入端電性連接於電晶體M1的汲極與能量儲存電感LX以接收降壓變換器12的低邊電流(也就是電流ISW),且電流感測放大器31的另一輸入端電性連接於地。電流感測放大器31的一輸出端電性連接於減法器33與抽樣保持電路32。減法器33電性連接於抽樣保持電路32與比較器113。
Next, referring to FIGS. 1 and 3, FIG. 3 is a circuit diagram of an embodiment of the current ripple extractor of the present invention. It is worth noting that FIG. 3 illustrates an embodiment of the
電流感測放大器31用來感測電流ISW。感測到的電流係由電流感測放大器31所產生並且送至減法器33與抽樣保持電路32。感測到的電流的直流分量可以由抽樣保持電路32取樣並且保持。減法器33可以自感測到的電流減去所保持的直流分量(也就是之前感測到的電流的直流分量)以產生萃取漣波電流,且萃取漣波電流輸出一漣波電壓訊號。減法器33可進一步將來自斜坡產生器116的斜坡電壓訊號加入漣波電壓訊號以於調變電路113的輸入端形成電壓訊號VCOT。
The
接著,參考圖1與圖4A,圖4A為本發明調變電路之一實施例的電路圖。值得注意的是圖4A繪示了圖1中調變電路113之一實施例,且本發明不以此為限。調變電路113包含放大器41,電容C2,加法器42以及調變器43。放大器41的一輸出端電性連接於電容C2的一端。放大器41的兩輸入端分別電性連接於迴授電壓FB與參考電壓訊號VREF。電容C2的另一端電性連接於地。調變器43的兩輸入端分別電性連接於迴授電壓FB與加法器42的一輸出端,且調變器43的一輸出端電性連接於RS正反器115。加法器42的兩輸入端分別電性連接於電壓訊號VCOT與放大器41的輸出端。
Next, referring to FIGS. 1 and 4A, FIG. 4A is a circuit diagram of an embodiment of the modulation circuit of the present invention. It is worth noting that FIG. 4A illustrates an embodiment of the
根據迴授電壓FB與參考電壓訊號VREF,放大器41產生調節過的參考電壓訊號VREF’。加法器42自調節過的參考電壓訊號VREF’減去電壓訊號VCOT以產生電壓訊號VREFX。接著,調變器43根據電壓訊號VREFX與迴授電壓FB來產生調變訊號。
According to the feedback voltage FB and the reference voltage signal V REF , the
值得注意的是放大器41係用來調節參考電壓訊號VREF,因此正確性並不會受到雜訊容限的影響。然而,本發明不以此為限。參考圖4B,圖4B為本發明調變電路又一實施例的電路圖。在本實施例中,不包含圖4A中的放大器41與電容C2。因此,圖4B中的加法器42相加參考電壓訊號VREF與電壓訊號VCOT以產生電壓訊號VREFX,且調變器43根據電壓訊號VREFX與迴授電壓FB來產生調變訊號。
It is worth noting that the
接著,參考圖1,圖4A與圖5,圖5為本發明降壓變換器裝置之一實施例的訊號波形圖。當降壓變換器12打開時,電流ISW係增加,當當降壓變換器12關閉時,電流ISW係減少。當降壓變換器12關閉時,電壓VSW為正值且降低,當降壓變換器12關閉時,電壓VSW為負值並增加。
Next, referring to FIG. 1, FIG. 4A and FIG. 5. FIG. 5 is a signal waveform diagram of an embodiment of the buck converter device of the present invention. When the
感測到的電流有直流分量,且因此感測到的電流的直流分量可以根據取樣/保持觸發被取樣並且保持。漣波電流萃取器111可以自目前感測到的電流減去所保持的感測到的電流的直流分量,以產生萃取漣波電流。萃取漣波電流與參考電壓訊號VREF可以用來產生上述比較電壓訊號VREFX。迴授電壓FB與比較電壓訊號VREFX可以用來決定降壓變換器12的斷路時間。特別是,當迴授電壓FB小於比較電壓訊號VREFX時,降壓變換器12的斷路時間會被終止。
The sensed current has a direct current component, and therefore the direct current component of the sensed current can be sampled and held according to the sample/hold trigger. The ripple
總結來說,本發明提供一種固定開路時間控制器其用於降壓變換器裝置中,並且提供固定開路時間控制器其可透過能量儲存電感中流經輸出電容的ESR的感測電流獲得萃取漣波電流,其中萃取漣波電流與迴授電壓可以被用來決定降壓變換器的斷路時間。因為萃取漣波電流不具直流分量,所述固定開路時間控制器可以有加強過的雜訊容限。進一步說,訊號波動也可透過使用斜坡電壓訊號來補償萃取漣波電流的斜率來獲得改善,並且因此所述的固定開路時間控制器具有改良的穩定性與抗噪性。 In summary, the present invention provides a fixed open-circuit time controller for use in a buck converter device, and provides a fixed open-circuit time controller which can obtain the extraction ripple through the sensing current of the ESR flowing through the output capacitor in the energy storage inductor The current, the extracted ripple current and the feedback voltage can be used to determine the off time of the buck converter. Because the extracted ripple current does not have a DC component, the fixed open-circuit time controller can have an enhanced noise tolerance. Furthermore, the signal fluctuation can also be improved by using the ramp voltage signal to compensate the slope of the extracted ripple current, and therefore the fixed open-circuit time controller has improved stability and noise immunity.
雖然本發明是以特定實施例來進行說明,但本領域具通常知識者可在不背離本發明之精神與不超出申請專利範圍所界定的範疇中作出修改與變化。 Although the present invention is described with specific embodiments, those skilled in the art can make modifications and changes without departing from the spirit of the present invention and within the scope defined by the patent application.
11:固定開路時間控制器 11: fixed open time controller
111:電流漣波萃取器 111: Current ripple extractor
112:分壓器 112: Voltage divider
113:調變電路 113: Modulation circuit
114:單發開路計時器 114: Single open timer
115:RS正反器 115: RS flip-flop
116:斜坡產生器 116: ramp generator
12:降壓變換器 12: Buck converter
121:預驅動器 121: pre-driver
CO:輸出電容 C O : output capacitance
FB:迴授電壓 FB: Feedback voltage
ISW:電流 I SW : current
LX:能量儲存電感 L X : Energy storage inductance
M1、M2:電晶體 M1, M2: Transistor
RCO:輸出電阻 R CO : output resistance
RFBH、RFBL:電阻 R FBH , R FBL : resistance
RLOAD:輸出負載 R LOAD : output load
VCOT:電壓訊號 V COT : Voltage signal
VIN:輸入電壓 V IN : Input voltage
VREF:參考電壓 V REF : Reference voltage
VOUT:輸出電壓 V OUT : output voltage
VSW:電壓 V SW : Voltage
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