TWI740544B - Package structure and manufacturing method therefore - Google Patents
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- TWI740544B TWI740544B TW109120435A TW109120435A TWI740544B TW I740544 B TWI740544 B TW I740544B TW 109120435 A TW109120435 A TW 109120435A TW 109120435 A TW109120435 A TW 109120435A TW I740544 B TWI740544 B TW I740544B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
Abstract
Description
本發明是有關於一種半導體元件及其製造方法,且特別是有關於一種封裝結構及其製造方法。The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a packaging structure and a manufacturing method thereof.
傳統半導體封裝的內部接合方式可分為打線接合(wire bonding)、捲帶式自動接合與覆晶接合,其中打線接合由於製程成熟、成本低、佈線彈性高,是目前應用最廣的接合技術。然而,打線接合的缺點是有輸入/輸出(Input/Output,簡稱I/O)接腳數的限制。此外,在先進製程封裝希望封裝尺寸微小化的情況下,因為使用打線接合有弧高及距離的限制,因此使得封裝尺寸無法往微小化來前進。The internal bonding methods of traditional semiconductor packages can be divided into wire bonding, tape-and-reel automatic bonding, and flip chip bonding. Among them, wire bonding is the most widely used bonding technology due to its mature process, low cost, and high wiring flexibility. However, the disadvantage of wire bonding is the limitation of the number of input/output (Input/Output, I/O) pins. In addition, in the case of advanced process packaging that requires miniaturization of the package size, the use of wire bonding has limitations on arc height and distance, so that the package size cannot be miniaturized.
本發明提供一種封裝結構及其製造方法,其可使得封裝尺寸更微小化。The present invention provides a package structure and a manufacturing method thereof, which can make the package size more miniaturized.
本發明提出一種封裝結構,包括導線架結構、晶粒、黏著劑層與至少一條三維列印導線。導線架結構包括載板與導線架。載板具有凹槽。導線架設置在載板上。晶粒設置在凹槽中。晶粒包括至少一個接墊。黏著劑層設置在晶粒的底面與載板之間以及晶粒的側壁與載板之間。三維列印導線設置在導線架、黏著劑層與接墊上,且電性連接於導線架與接墊之間。The present invention provides a package structure including a lead frame structure, a die, an adhesive layer and at least one three-dimensional printed wire. The lead frame structure includes a carrier board and a lead frame. The carrier has grooves. The lead frame is arranged on the carrier board. The die is arranged in the groove. The die includes at least one pad. The adhesive layer is arranged between the bottom surface of the die and the carrier and between the sidewall of the die and the carrier. The three-dimensional printed wires are arranged on the lead frame, the adhesive layer and the pads, and are electrically connected between the lead frame and the pads.
本發明提出一種封裝結構的製造方法,包括以下步驟。提供導線架結構。導線架結構包括載板與導線架。載板具有凹槽。導線架設置在載板上。將黏著劑填入凹槽中。將晶粒放置在凹槽中,使得黏著劑由晶粒的底面與載板之間溢出至晶粒的側壁與載板之間,而形成黏著劑層。晶粒包括至少一個接墊。使用三維列印製程在導線架、黏著劑層與接墊上形成至少一條三維列印導線。三維列印導線電性連接於導線架與接墊之間。The present invention provides a manufacturing method of a package structure, which includes the following steps. Provide lead frame structure. The lead frame structure includes a carrier board and a lead frame. The carrier has grooves. The lead frame is arranged on the carrier board. Fill the adhesive into the groove. The die is placed in the groove so that the adhesive overflows from between the bottom surface of the die and the carrier to between the sidewall of the die and the carrier to form an adhesive layer. The die includes at least one pad. A three-dimensional printing process is used to form at least one three-dimensional printed wire on the lead frame, the adhesive layer and the pad. The three-dimensional printed wire is electrically connected between the lead frame and the pad.
基於上述,在本發明所提出的封裝結構及其製造方法中,將晶粒設置在凹槽中,且使用三維列印導線將導線架與接墊進行電性連接,因此不存在打線接合的弧高及距離的限制,進而可縮小晶粒與導線架的間距並降低封裝結構的厚度,以使得封裝尺寸微小化。此外,由於不存在打線接合的弧高及距離的限制,因此有利於增加I/O接腳數。另外,藉由本發明所提出的封裝結構及其製造方法,可省略重佈線層(redistribution layer,RDL)製程與打線接合製程等製程,因此可有效地簡化製程。Based on the above, in the package structure and its manufacturing method proposed by the present invention, the die is arranged in the groove, and the lead frame and the pad are electrically connected by three-dimensional printed wires, so there is no arc of wire bonding. The limitations of height and distance can further reduce the distance between the die and the lead frame and reduce the thickness of the package structure, so that the package size can be miniaturized. In addition, since there are no restrictions on the arc height and distance of wire bonding, it is beneficial to increase the number of I/O pins. In addition, with the package structure and the manufacturing method provided by the present invention, the redistribution layer (RDL) process and the wire bonding process can be omitted, so the process can be effectively simplified.
為讓本發明的上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.
圖1A至圖1E為本發明一實施例的封裝結構的製造流程立體圖。圖2A至圖2E為沿著圖1A至圖1E中的I-I’剖面線的剖面圖。1A to 1E are perspective views of a manufacturing process of a package structure according to an embodiment of the invention. Figs. 2A to 2E are cross-sectional views taken along the line I-I' in Figs. 1A to 1E.
請參照圖1A與圖2A,提供導線架結構100。導線架結構100包括載板102與導線架104。載板102可用以固定與承載導線架104。載板102具有凹槽R。凹槽R可用以容置晶粒。載板102可覆蓋部分導線架104,而使得載板102高於導線架104。載板102的材料可包括模製化合物(molding compound),如環氧模製化合物(epoxy molding compound,EMC)。1A and 2A, a
導線架104設置在載板102上。導線架104的底部BP2可低於載板102的底部BP1。導線架104可包括多個導腳104a。導線架104的材料可包括銅合金或鐵鎳合金。The
請參照圖1B與圖2B,將黏著劑106填入凹槽R中。黏著劑106的材料可包括丙烯酸黏著劑、聚氨酯黏著劑、矽膠黏著劑或橡膠黏著劑等。Please refer to FIG. 1B and FIG. 2B to fill the
請參照圖1C與圖2C,將晶粒108放置在凹槽R中,使得黏著劑106由晶粒108的底面BS與載板102之間溢出至晶粒108的側壁SW與載板102之間,而形成黏著劑層106a。亦即,部分黏著劑層106a可位在晶粒108的側壁SW上。晶粒108可為積體電路(integrated circuit,IC)元件。晶粒108包括至少一個接墊110。在本實施例中,接墊110的數量是以多個為例,但只要接墊110的數量為至少一個即屬於本發明所涵蓋的範圍。1C and 2C, the
在本實施例中,晶粒108的頂面TS1的高度可等於導線架104的頂面TS2的高度,藉此有利於後續使用三維列印製程形成導線。此處的「等高」一詞所指的是「實質上等高」,亦即可存在可容許的誤差。在其他實施例中,晶粒108的頂面TS1的高度可高於導線架104的頂面TS2的高度。另外,黏著劑層106a的頂面TS3可等於或高於晶粒108的頂面TS1與導線架104的頂面TS2,藉此有利於後續使用三維列印製程形成導線。在黏著劑層106a的頂面TS3高於晶粒108的頂面TS1與導線架104的頂面TS2的情況下,黏著劑層106a不會完全覆蓋接墊110與導線架104,以防止黏著劑層106a在後續三維列印製程中阻礙導線架104與接墊110之間的電性連接。In this embodiment, the height of the top surface TS1 of the
另一方面,凹槽R與晶粒108可具有相同的上視形狀。在本實施例中,凹槽R與晶粒108的上視形狀是以矩形為例,但本發明並不以此為限。凹槽R的上視面積可大於晶粒108的上視面積,以利於將晶粒108放置在凹槽R中。凹槽R的上視面積可為晶粒108的上視面積等比例放大1.05倍至1.5倍。在一些實施例中,凹槽R的上視面積可為晶粒108的上視面積等比例放大1.1倍至1.3倍。On the other hand, the groove R and the
請參照圖1D與圖2D,使用三維列印製程在導線架104、黏著劑層106a與接墊110上形成至少一條三維列印導線112。三維列印導線112電性連接於導線架104與接墊110之間。舉例來說,可利用三維列印機的噴頭200進行列印。三維列印導線112可直接設置在導線架104的頂面TS2、黏著劑層106a的頂面TS3與晶粒108的頂面TS1上。三維列印導線112的數量可依據接墊110的數量進行調整。三維列印導線112的材料可包括導電墨水,如奈米銀墨水或奈米銅銀合金墨水等金屬墨水。Referring to FIGS. 1D and 2D, at least one 3D printed
請參照圖1E與圖2E,可形成覆蓋晶粒108、三維列印導線112與部分導線架結構100的包封體114。包封體114的材料可包括模製化合物,如環氧模製化合物。包封體114的形成方法例如是模製(molding)製程。Referring to FIGS. 1E and 2E, an
以下,藉由圖1D、圖1E、圖2D與圖2E來說明本實施例的封裝結構10。此外,雖然封裝結構10的形成方法是以上述方法為例進行說明,但本發明並不以此為限。Hereinafter, the
請參照圖1D、圖1E、圖2D與圖2E,封裝結構10包括導線架結構100、晶粒108、黏著劑層106a與至少一條三維列印導線112。此外,封裝結構10更可包括包封體114。導線架結構100包括載板102與導線架104。載板102具有凹槽R。導線架104設置在載板102上。晶粒108設置在凹槽R中。晶粒108包括至少一個接墊110。黏著劑層106a設置在晶粒108的底面BS與載板102之間以及晶粒108的側壁SW與載板102之間。三維列印導線112設置在導線架104、黏著劑層106a與接墊110上,且電性連接於導線架104與接墊110之間。包封體114覆蓋晶粒108、三維列印導線112與部分導線架結構100。此外,封裝結構10中的各構件的材料、設置方式、形成方法與功效已於上述實施例進行詳盡地說明,於此不再說明。1D, 1E, 2D, and 2E, the
基於上述實施例可知,在上述封裝結構10及其製造方法中,將晶粒108設置在凹槽R中,且使用三維列印導線112將導線架104與接墊110進行電性連接,因此不存在打線接合的弧高及距離的限制,進而可縮小晶粒108與導線架104的間距並降低封裝結構10的厚度,以使得封裝尺寸微小化。此外,由於不存在打線接合的弧高及距離的限制,因此有利於增加I/O接腳數。另外,藉由上述封裝結構10及其製造方法,可省略重佈線層製程與打線接合製程等製程,因此可有效地簡化製程。Based on the above-mentioned embodiment, in the above-mentioned
綜上所述,在上述實施例的封裝結構及其製造方法中,可利用三維列印導線將導線架與接墊進行電性連接,藉此可使得封裝尺寸更微小化且可有效地簡化製程。In summary, in the package structure and manufacturing method of the above-mentioned embodiment, the lead frame and the pads can be electrically connected by three-dimensional printed wires, which can make the package size more miniaturized and can effectively simplify the manufacturing process. .
雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明的精神和範圍內,當可作些許的更動與潤飾,故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be subject to those defined by the attached patent application scope.
10:封裝結構
100:導線架結構
102:載板
104:導線架
104a:導腳
106:黏著劑
106a:黏著劑層
108:晶粒
110:接墊
112:三維列印導線
114:包封體
200:噴頭
BP1, BP2:底部
BS:底面
R:凹槽
SW:側壁
TS1, TS2, TS3:頂面
10: Package structure
100: Lead frame structure
102: carrier board
104: Lead
圖1A至圖1E為本發明一實施例的封裝結構的製造流程立體圖。 圖2A至圖2E為沿著圖1A至圖1E中的I-I’剖面線的剖面圖。 1A to 1E are perspective views of a manufacturing process of a package structure according to an embodiment of the invention. Figs. 2A to 2E are cross-sectional views taken along the line I-I' in Figs. 1A to 1E.
10:封裝結構 10: Package structure
100:導線架結構 100: Lead frame structure
102:載板 102: carrier board
104:導線架 104: Lead frame
104a:導腳 104a: guide foot
106a:黏著劑層 106a: Adhesive layer
108:晶粒 108: Die
110:接墊 110: pad
112:三維列印導線 112: 3D printing wire
200:噴頭 200: print head
BP1,BP2:底部 BP1, BP2: bottom
R:凹槽 R: groove
SW:側壁 SW: side wall
TS1,TS2,TS3:頂面 TS1, TS2, TS3: top surface
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US9935028B2 (en) * | 2013-03-05 | 2018-04-03 | Global Circuit Innovations Incorporated | Method and apparatus for printing integrated circuit bond connections |
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US9935028B2 (en) * | 2013-03-05 | 2018-04-03 | Global Circuit Innovations Incorporated | Method and apparatus for printing integrated circuit bond connections |
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