TWI737765B - Stacked stud bump contacts for wafer test contactors, and associated methods - Google Patents

Abstract

Systems and methods for testing semiconductor wafers are disclosed herein. In one embodiment, an apparatus for testing dies on a semiconductor wafer includes a test contactor for contacting the dies. The test contactor has a substrate having a wafer-side facing the wafer, and an inquiry-side facing away from the wafer-side. The test contactor also has a wafer-side contact pad carried by the wafer-side of the substrate, and a stud bump pin attached to the wafer-side contact pad. The stud bump pin terminates in a stud bump tip for probing a contact pad of a die.

Description

Stacked post bump contact and related method for wafer test contact

Integrated circuits are used in various products. Integrated circuits have been declining in price and increasing in performance, and they have become ubiquitous in modern electronic devices. These improvements in the performance/cost ratio are based at least in part on miniaturization, which enables more semiconductor dies to be produced from one of the next generation wafers with integrated circuit manufacturing technology. In addition, the total number of signal and power/ground contacts on a semiconductor die has generally increased with new, more complex die designs. Before shipping semiconductor dies to customers, test the performance of integrated circuits based on a statistical sample or by testing each die. An electrical test of a semiconductor die usually includes powering the die through a power/ground contact, transmitting a signal to the input contact of the die, and measuring the resulting signal at the output contact of the die. Therefore, during electrical testing, at least some of the contacts on the die must be electrically contacted to connect the die to the source of power and test signals. Conventional test contacts include an array of contact pins attached to a substrate, which may be a relatively rigid printed circuit board (PCB). In operation, the test contact is pressed against a wafer, so that the contact pins of the array and the die of the wafer (ie, the device under test or DUT) on the corresponding array die (such as pads or solder balls) are in contact with each other. Electrical contact. Then, a wafer tester sends an electrical test sequence (such as a test vector) through the test contact to the input contact of the die of the wafer. In response to the test sequence, the integrated circuit of the tested die generates output signals, which are routed back to the wafer tester through the test contacts for analysis and determine whether a specific die passes the test. Then, the test contact is stepped onto another die or a group of die tested in parallel to continue testing until the entire wafer is tested. Generally speaking, an increased number of die contacts distributed over a reduced area of the die results in smaller contacts separated by a smaller distance (eg, a smaller pitch). In addition, the characteristic diameter of the contact pin of the test contact usually scales with one of the characteristic dimensions of the semiconductor die or the contact structure on the package. Therefore, as the contact structure on the die becomes smaller and/or has a smaller pitch, the contact pins of the test contacts also become smaller. However, it is difficult to significantly reduce the diameter and pitch of the contact pins of the test contacts (for example, due to difficulties in processing and assembling these small parts), resulting in low production and inconsistency between one test contact and another test contact efficacy. In addition, the contact pins of the test contacts can be relatively more easily damaged due to their small size. In addition, repeated application of the contact pin of the test contact to one of the contact pads of the device under test can wear the contact pin. Accordingly, there is still a need for cost-effective test contacts whose equivalent size can be scaled with the size and pitch of the contact structure on the die.

The present invention generally relates to equipment used for semiconductor wafer testing. More specifically, the present invention relates to a method and system for contacting ("probing") the dies of the semiconductor wafer, wherein the contact pins are constructed by wire bonding to post bumps. In addition, the present invention relates to the electroplating of wire bonding pillar bumps and contact pads. A brief description, revealing methods and devices for testing the dies on the semiconductor wafers. The semiconductor wafers can be produced in different diameters, such as 150 mm, 200 mm, 300 mm, 450 mm, etc. The disclosed method and system enable operators to test such devices with pads, solder balls, and/or other contact structures with small sizes and/or pitches. The solder balls, pads and/or other suitable conductive elements on the dies are collectively referred to herein as "contact pads." In some embodiments, a wafer side of the test contact (eg, a wafer translator) carries the wafer side contacts of relatively small size and/or pitch (collectively, "scale") structure. The wafer-side contact structures of the test contact are electrically connected to the corresponding interrogation-side contact structures, and the interrogation-side contact structures may have relatively large sizes and/or sections at the opposite and interrogation sides of the test contact. distance. Therefore, once the wafer-side contact structures are properly aligned to contact the semiconductor wafers, the larger size/pitch of the relative interrogation-side contact structures enables more robust contacts (e.g., requiring less precision). The larger size/pitch of the interrogation side contact structures can provide more reliable contact and easier alignment against the pins of the probe card or other contact elements. In some embodiments, the interrogation side contacts may have a millimeter scale, and the wafer side contacts have a sub-millimeter or micrometer scale. In some embodiments, the contact structures at the wafer side of the test contact may be pillar bumps manufactured by wire bonding. For example, the wire bonds can be attached to the wafer side of the test contact, and then the wire bonds are cut to leave a pillar bump on the test contact (e.g., a wafer translation Device or another contact used to detect the wafer). In some embodiments, a plurality of stud bumps are stacked to form a stacked stud bump contact for probing the wafer. In some embodiments, the pillar bumps can be shaped and/or sharpened using a shaped wafer. In some embodiments, the pillar bumps may be coated with a relatively wear-resistant material (for example, platinum iridium (PtIr) alloy). In some embodiments, the contact pads on the space converter and/or the test contact are coated to improve the resistance of the contact pins (such as snake needles) of the probe card.

This application claims the rights of U.S. Provisional Application No. 62/360068 filed on July 8, 2016 and U.S. Provisional Application No. 62/436713 filed on December 20, 2016. The entire contents of the two cases are based on The way of reference is incorporated into this article. Specific details of several embodiments of representative wafer translators and related methods for use and manufacturing are described below. Those familiar with the art will also understand that the present technology may have additional embodiments, and may be practiced without some of the details of the embodiments described below with reference to FIGS. 1A to 8. FIG. 1A is an exploded view of a part of a test stack 100 for testing semiconductor wafers according to the prior art. The test stack 100 routes signals and power from a tester (not shown) to a wafer or other substrate carrying one or more devices under test (DUT), and transfers signals from these DUTs (such as semiconductor dies) The output signal of) is transferred back to the tester for analysis and seeking to determine the performance of a specific DUT (for example, whether the DUT is suitable for packaging and transportation to customers). The signals and power from the tester are routed to a wafer translator 10 through a test contact 30 and further to the semiconductor dies on the wafer 20. The cable 39 is used to route the signals and power from the tester to the test contact 30. Conductive traces 38 carried by a test contact substrate 32 can electrically connect cables 39 to contacts 36 on the opposite side of the test contact substrate 32. In operation, the test contact 30 can contact an interrogation side 13 of a wafer translator 10, as indicated by arrow A. In at least some embodiments, the relatively large interrogation side contact structure 14 can improve the alignment with the corresponding contact 36 of the test contact 30. The contact structure 14 at the interrogation side 13 is electrically connected to a relatively small wafer-side contact structure 16 on a wafer side 15 of the translator 10 through conductive traces 18 of a wafer translator substrate 12. The size and/or pitch of the wafer-side contact structure 16 is suitable for contacting the corresponding die contact 26 of the wafer 20. The arrow B indicates that one of the wafer translators 10 moves to make contact with the active side 25 of the wafer 20. As explained above, the signals and power from the tester can test the DUTs of the wafer 20, and the output signals from the tested DUTs can be routed back to the tester for analysis and Seek to determine whether these DUTs are suitable for packaging and transportation to customers. A wafer chuck 40 supports the wafer 20. The arrow C indicates the direction in which the wafer 20 and the wafer chuck 40 are matched. In operation, the wafer 20 can be held against the wafer chuck 40 using, for example, a vacuum V or a mechanical clamp. 1B and 1C are respectively a partial schematic top view and a bottom view of a wafer translator configured according to an embodiment of the disclosed technology. FIG. 1B shows the interrogation side 13 of the wafer translator 10. The distance (eg, pitch) between adjacent interrogation-side contact structures 14 is indicated as P ₁ in the horizontal direction and as P ₂ in the vertical direction. The illustrated interrogation side contact structure 14 has a width D ₁ and a height D ₂ . Depending on the individual embodiment, the interrogation side contact structure 14 may be square, rectangular, circular, or other shapes. In addition, the interrogation side contact structure 14 may have a uniform pitch (for example, P ₁ and P ₂ are equal across the wafer translator 10) or a non-uniform pitch. FIG. 1C shows the wafer side 15 of the wafer translator 10. In some embodiments, the pitch between adjacent wafer-side contact structures 16 may be p ₁ in the horizontal direction and p ₂ in the vertical direction. The width and height ("characteristic dimensions") of the wafer-side contact structure 16 are indicated as d ₁ and d ₂ . In some embodiments, the wafer-side contact structure 16 may be a pin that touches the corresponding die on the wafer 20. These pins are described in more detail in Figure 2 below. Generally speaking, the size/pitch of the interrogation-side contact structure 14 is larger than the size/pitch of the wafer-side contact structure 16, thereby improving the alignment and contact between the test contact and the wafer translator. The individual dies of the wafer 20 are usually separated from each other by a wafer channel 19. FIG. 2 is a side view of a representative contact structure 16 according to the prior art. In one example, the contact structure 16 has a crowned tip 16a for contacting the solder ball 26a on the wafer or the single die. In another example, the contact structure 16 has a conical tip 16b for contacting a relatively flat contact 26b on the wafer or on the single die. Generally speaking, the tips 16a/16b can wear relatively quickly, thus limiting the effectiveness of the contact structure 16. Fig. 3A is an isometric view of chip wire bonding according to the prior art. FIG. 3A shows a substrate (such as a PCB) 50 that carries semiconductor dies 20a and 20b, in which one semiconductor die 20a is disposed above two semiconductor dies 20b. Each semiconductor die 20a, 20b has an array of die contact pads 26 at the periphery. The die contact pad 26 is connected to the corresponding substrate contact pad 56 using bonding wires (wire bonding) 55. In operation, the wire bonding 55 transfers power and signals between the dies and the substrate 50. Fig. 3B is a side view of the chip wire bonding according to the prior art. In operation, a bonding wire adapter 60 distributes bonding wires 55 from a bonding pin 55t (also referred to as a "capillary tube"). The tip of the bonding wire 55 can be melted by an electric arc or by ultrasonic waves. The fusion bonding wire 55 forms a solder ball due to the surface tension of the molten metal in the solder ball. The molten solder ball is then attached to the die contact pad 26 as a pillar bump 54 to form a permanent electrical contact with the die 20. Next, the opposite side of the bonding wire 55 is bonded to a contact pad 56 on the substrate 50, thereby establishing an electrical connection from the die 20 to the substrate 50 and further to other components of the system (such as power supply, signal source, etc.) . The wire bonding process can continue to the next pair of contact pads 26/56, until the die contact pad 26 of the die 20 is completely bonded to the substrate 50 by wire bonding. FIG. 4 is a cross-sectional side view of a test contact 100 according to an embodiment of the disclosed technology. In some embodiments, the test contact 1000 may be a translator that has the smaller pitch/size of the contacts on the wafer side and the larger pitch of the contacts on the interrogation side /size. In some embodiments, the test contact 1000 includes a substrate 120 (such as a PCB or ceramic board) having a wafer side 150 and an interrogation side 130. Generally speaking, the interrogation side 130 can be connected to a tester (not shown) having a source of power/signal and/or an instrument for signal measurement. In some embodiments, vias 180 electrically connect contact pads 260 to contact pads 140 at the wafer side 150. The substrate 120 may also include one or more routing transfer layers 181 for electrical traces for interconnecting the contact pads 260/140. In some embodiments, the pillar bump pin 160 (also referred to as the wafer-side contact structure 160) is formed by the wire bonding on the contact pad 260. For example, a stud bump can be formed by the wire bonding, then attaching the stud bump to the contact pad 260, and removing the additional wire bonding to form a stud bump pin 160 on the contact pad 260. In some embodiments, as the additional wire bonding is removed (for example, by pulling, repeatedly bending, or heating the wire bonding 55), a stud bump tip 161 is formed as a narrowed portion on the stud bump Around the pin 160. As the wafer side 150 of the test contact 100 makes contact with the dies on the wafer, the stud bump tip 161 can provide more precise contact with the contact pads on the wafer and the contacts Better removal of these surface oxides on the liner. In some embodiments, the resistance and inductance of the pillar bump pin 160 are relatively low due to its shape (for example, relatively bulky and non-long/slender shape) and size (for example, having a relatively large cross-section). In some embodiments, the pillar bump pin 160 may be made of copper or copper alloy wire bonding. FIG. 5 is a cross-sectional side view of the test contact 1000 according to an embodiment of the disclosed technology. In some embodiments, the pillar bump pin 160-i may be stacked on the contact pad 260. For example, two stud bump pins 160-1 and 160-2 can form a stack 160S. In some embodiments, the pillar bump pins 160-i may be formed by successively forming individual pillar bump pins 160-i on top of each other. In some embodiments, the stud bump pin 160-i can be pre-formed away from the test contact 1000, and then by, for example, heating the stud bump pin 160-i to about its equivalent melting point and then stacking them equal to each other The top is stacked on the contact pad 260. FIG. 6 is a cross-sectional side view of the test contact 1000 according to an embodiment of the disclosed technology. In some embodiments, the stacks of post bump pins 160 may include two, three, four or more post bump pins to achieve the desired height of the stack 160S. In some embodiments, the last stud bump pin 160 in the stack 160S ends in the stud bump pin 161 that contacts the contact pads on the wafer. FIG. 7 is an exploded side view of a test stack 2000 according to an embodiment of the disclosed technology. The illustrated test stack 2000 includes a wafer chuck 40 which carries a wafer 20. The active side 25 of the wafer 20 (that is, the side carrying the dies) faces the wafer side 150 of the test contact 1000, and a probe card 300 faces the interrogation side 130 of the test contact 1000. The test stack 2000 may be electrically connected to the tester (not shown) through the tester cable 39. In operation, the signals/powers from the tester propagate through a space transformer 330 and contact pins 310 (also referred to as pin pins or snake pins), and further pass through the contact 100 to the wafer 20. The dies of the wafer 20 respond to the input signals/power from the tester by generating output signals that are routed back to the tester to determine whether a particular die is operating according to specifications. In some embodiments, all or most of the dies on the wafer can be contacted and tested in parallel. In other embodiments, a single die or a group of die (for example, two, three, or four dies) can be contacted and tested in parallel. In many embodiments, the test contact 1000 can be reused over multiple wafers 25, thus subjecting the stack 160-S to wear. In some embodiments, the stack 160S may be electroplated by an electroplating 170 to, for example, improve the wear resistance of the stack, reduce corrosion, change the hardness of the material of the stack, and so on. In some embodiments, a platinum iridium (PtIr) plating 170 may be deposited on the stack 160-S by electrolysis or by ion sputtering. In some embodiments, the electroplating 170 may include hard precious materials, such as rhodium, platinum, iridium, palladium, fetters, osmium, and/or alloys thereof. In some embodiments, the electroplating 170 may be about 10 microns thick. In some embodiments, the electroplating may extend to the contact pad 260. In some embodiments, the contact pins (such as snake pins) 310 are held in position by a first guide plate 321 and a second guide plate 322. When the contact pin 310 touches the interrogation side of the test contact 1000, the tip of the contact pin 310 usually drills slightly into the contact pad and then slides horizontally across the contact pad. This movement of the tip of the contact pin 310 relative to the contact pad is sometimes referred to as "scrubbing." Multiple scrubbing on the contact pad 140 of the contact 100 may result in additional wear of the material of the contact pad and/or accumulation of the material of the contact pad above the contact pin 310. In some embodiments, an electroplating 370 may be placed on the contact pad 140 to reduce the wear/abrasion of the contact pad 140. In addition, the electroplating 370 can be placed above the contact pad 340 of the space converter 330 to protect the contact pad 340 from abrasion/abrasion. In some embodiments, the electroplating 370 may be a flat pillar bump made of PtIr alloy. For example, a pillar bump can first be manufactured following a process similar to the process described with reference to FIG. 4. Then, the pillar bump can be flattened by, for example, forging, rolling, or crushing the pillar bump. Once the stud bump is planarized into the plating 370, it can be attached to the contact pad 340 or 140. In some embodiments, electroplating 170/370 can be deposited by electrolysis or by ion sputtering. In some embodiments, the contact pad 140 is made of copper or aluminum. FIG. 8 is a cross-sectional side view of a system for forming a contact structure according to an embodiment of the disclosed technology. In some embodiments, the system includes test contacts 100 and a formed wafer 500. In some embodiments, the shaped wafer 500 repeatedly contacts the stack 160-S to shape it. The test contact 100 or the formed wafer 500 or both can be moved into contact by one or more actuators (not shown) in a Z direction shown by a coordinate system CS. The actuation may be provided by a pressure driven actuator, electric motor, or other actuator. In some embodiments, the movement of the wafer translator 10 and/or the formed wafer 500 may be restricted to control the forming of the stack 160-S. For example, the test contact 100 may be moved to a position Z ₁ to repeat the N ₁ cycle, and then the test contact 100 may be forced to repeat the N _{2 cycle to a position Z 2} , where Z ₂ is greater than Z ₁ . In some embodiments, N ₁ and/or N ₂ may be hundreds or thousands of cycles. As a result of repeated contact between the side surface 510, the side and/or the tip of the stack 160-S of the formed wafer 500, the stack 160-S is shaped to approximate the shape of the chambers formed by the surface 510 . In at least some embodiments, this shaping of the tip/side of the stack 160-S can bring the stack 160-S back to its equivalent internal dimensions. For example, a previously out-of-specification stack 160-S with an out-of-specification pitch p ₁ can again become suitable for testing semiconductor wafers on a production wafer by forming the stack 160-S back to the in-specification pitch p ₂ grain. Similarly, the out-of-specification height or width of the stack 160-S can be brought to specifications by using the shaped wafer 500 to shape the stack 160-S. In some embodiments, the forming of the stack 160-S may include abrasion or plastic deformation of the stack 160-S. In some embodiments, a single pillar bump 160 can be used instead of a stack 160-S. In some embodiments, the stack 160S or the stud bump pin 160 may include electroplating 170. The repeated contacts between the stack 160-S or the pillar bump pins 160 and the formed wafer 500 can be referred to as embossing or forging of the contact structures. In some embodiments, the shaped wafer 500 may be made of silicon or metal. The side surface 510 may be made by, for example, lithographic definition etching. Since the position accuracy is defined by the accuracy of a lithography mask above the formed wafer 500, the resulting position accuracy of the side surface 510 is also relatively high. In at least some embodiments, the accuracy (eg, tolerance) of the position of the side surface 510 substantially corresponds to the accuracy of the position of the die contact 26. Many embodiments of the technology described above can be in the form of computer or controller executable instructions, including routines executed by a programmable computer or controller. Those familiar with this technology will understand that this technology can be practiced on computer/controller systems other than the computer/controller systems shown and described below. The technology can be embodied in a dedicated computer, controller, or data processor that is specially programmed, configured, or constructed to execute one or more of the computer-executable instructions described below. Accordingly, the terms "computer" and "controller" as commonly used in this article refer to any data processor and may include Internet equipment and handheld devices (including palmtops, wearable computers, cellular or mobile phones, Microprocessor systems, processor-based or programmable consumer electronics, network computers, mini-computers and the like). The information held by such computers can be presented by any suitable display medium (including a CRT display or LCD). From the foregoing, it will be understood that specific embodiments of the technology have been described herein for illustrative purposes, but various modifications can be made without departing from the invention. In addition, although various advantages and features associated with certain embodiments have been disclosed in the content of these embodiments, other embodiments can also exhibit these advantages and/or features and not all embodiments must exhibit these advantages And/or features fall within the scope of this technology. Therefore, the present invention may cover other embodiments that are not explicitly shown or described herein. The exclusive ownership or special rights claimed in the embodiments of the present invention are defined as the scope of the following patent applications.

10‧‧‧Wafer translator 12‧‧‧Wafer translator substrate 13‧‧‧Interrogation side 14‧‧‧Contact structure 15‧‧‧wafer side 16‧‧‧wafer side contact structure 16a‧‧‧Crown Tip 16b‧‧‧Conical tip 18‧‧‧Conductive trace 19‧‧‧Wafer channel 20‧‧‧Wafer 20a‧‧‧Semiconductor die 20b‧‧‧Semiconductor die 25‧‧‧Active side 26‧ ‧‧Die contact 26a‧‧‧Solder ball 26b‧‧‧Flat contact 30‧‧‧Test contact 32‧‧‧Test contact substrate 36‧‧‧Contact 38‧‧‧Conductive trace 39‧‧‧Cable 40‧‧‧wafer chuck 50‧‧‧substrate 54‧‧‧post bump 55‧‧‧bonding wire 55t‧‧‧bonding pin 56‧‧‧contact pad 60‧‧‧bonding wire adapter 100‧ Test stack 120 ‧‧‧Pillar bump pin 160S‧‧‧Stack 161 300‧‧‧Probe card 310‧‧‧Contact pin 321‧‧‧First guide plate 322‧‧‧Second guide plate 330‧‧‧Space converter 340‧‧‧Contact pad 370‧‧‧Plating 500‧ shaped side surface of the wafer 510‧‧‧ ‧‧ 1000‧‧‧ test contact 2000‧‧‧ test stack A‧‧‧ B‧‧‧ arrow arrow coordinate system CS‧‧‧ C‧‧‧ arrow D ₁ ‧‧‧ Width D ₂ ‧‧‧Height d ₁ ‧‧‧Width d ₂ ‧‧‧Height P ₁ ‧‧‧Pitch P ₂ ‧‧‧Pitch p ₁ ‧‧‧Pitch p ₂ ‧‧‧Pitch

The aspect of the present invention can be better understood with reference to the following drawings. The components in the drawing are not necessarily drawn to scale. Instead, the emphasis is placed on clearly explaining the principles of the present invention. FIG. 1A is an exploded view of a part of a test stack used to test semiconductor wafers according to the prior art. FIG. 1B is a schematic top view of a part of a wafer translator configured according to the prior art. Fig. 1C is a schematic bottom view of a part of a wafer translator configured according to the prior art. Figure 2 is a side view of a representative contact structure according to the prior art. Fig. 3A is an isometric view of chip wire bonding according to the prior art. Fig. 3B is a side view of the chip wire bonding according to the prior art. 4 to 6 are cross-sectional side views of test contacts according to embodiments of the disclosed technology. Fig. 7 is an exploded side view of a test stack according to an embodiment of the disclosed technology. FIG. 8 is a cross-sectional side view of a system for forming a contact structure according to an embodiment of the disclosed technology.

20‧‧‧wafer

26‧‧‧grain contact

39‧‧‧Cable

40‧‧‧Wafer Chuck

100‧‧‧Test Stack

120‧‧‧Substrate

130‧‧‧Inquiry side

140‧‧‧Contact pad

150‧‧‧wafer side

160-1‧‧‧Post Bump Pin

160-2‧‧‧Column Bump Pin

160S‧‧‧Stack

161‧‧‧The tip of the column bump

170‧‧‧Platinum Iridium (PtIr) Plating

260‧‧‧Contact pad

300‧‧‧Probe card

310‧‧‧Contact pin

321‧‧‧First guide plate

322‧‧‧Second guide plate

330‧‧‧Space Converter

340‧‧‧Contact pad

370‧‧‧Plating

2000‧‧‧Test Stack

Claims (23)

An apparatus for testing the dies of a semiconductor wafer, which includes: a test contact configured to contact the dies, and includes: a substrate having a substrate configured to face the wafer A wafer side, and an interrogation side facing away from the wafer side; a wafer side contact pad carried by the wafer side of the substrate; and a pillar bump pin attached to the wafer Round side contact pad, where the pillar bump pin terminates in the tip of a pillar bump configured to detect a contact pad of a die, and wherein the pillar bump pin is plated by a pillar bump pin Electroplating, which extends to the contact pad. Such as the device of claim 1, wherein the upright bump pin is a first upright bump pin and the tip of the upright bump is a first upright bump tip, the device further includes a bump pin stacked on the first upright An upper second pillar bump pin, wherein the second pillar bump pin terminates in the tip of a second pillar bump configured to detect the contact pad of the die. Such as the device of claim 2, wherein the first pillar bump pin and the second pillar bump pin form a stacked pillar bump pin, and the device further includes a plurality of contact pads configured to detect the die Pillar bump pins for stacking. Such as the device of claim 3, wherein the test contact is configured to contact all or most of the dies on the wafer in parallel. For example, the device of claim 3, which further includes a plurality of interrogation side contact pads carried by the test contact, wherein the stacked pillar bump pins have a first scale, and the interrogation side contact structures have a The second scale, and wherein the first scale is smaller than the second scale. Such as the equipment of claim 1, wherein the pillar bump pin plating is a platinum iridium (PtIr) plating. Such as the device of claim 6, wherein the pillar bump pin plating is 10 microns thick. For example, the device of claim 1, which further includes: an interrogation-side contact pad carried by the interrogation side of the substrate; and an interrogation-side contact pad plating, which is arranged above the interrogation-side contact pad, wherein The electroplating is a platinum iridium (PtIr) electroplating. For example, the device of claim 1, which further includes: a probe card, which includes: a plurality of contact pins, wherein each contact pin has a first end configured to contact the interrogation side of the test contact, and Configured to contact a second end of a contact pad of a space transformer; and the space transformer carrying a plurality of the contact pads facing the second end of the contact pins; and a plating, It is above the contact pads of the space converter. The device of claim 9, wherein the plating above the contact pads of the space converter is a platinum iridium (PtIr) plating. The device of claim 1, which further includes: a formed wafer, which includes: a formed wafer substrate, and a plurality of chambers in the formed wafer substrate, wherein individual chambers face individual columns of the test contact Bump pins, and the individual pillar bump pins are formed by the surfaces of the chambers of the formed wafer substrate. Such as the equipment of claim 11, wherein the pillar bump pins are formed by wear or plastic deformation. The device of claim 10, wherein the shaped wafer substrate includes silicon. A method for testing a semiconductor wafer, which includes: Contacting a die on the semiconductor wafer with a wafer side of a test contact, wherein the test contact includes a stud bump pin attached to a contact pad at the wafer side, and The pillar bump pin terminates in the tip of a pillar bump detecting a contact pad of a die, the pillar bump pin is electroplated by a pillar bump pin electroplating, and the electroplating extends to the contact pad. Such as the method of claim 14, wherein the pillar bump pin is electroplated with a platinum iridium (PtIr) electroplating. The method of claim 14, further comprising: contacting a contact pad on an interrogation side of the test contact with a probe card, wherein the interrogation side of the test contact faces away from the test contact The wafer side, and wherein the contact pad on the interrogation side of the test contact is electroplated by an electroplating. The method of claim 16, wherein the wafer side of the test contact carries pillar bump pins with a first scale, and the interrogation side of the wafer translator carries the wafers with a second scale Contacting the pad, and wherein the first scale is smaller than the second scale. Such as the method of claim 16, which further includes testing the dies on the semiconductor wafer. Such as the method of claim 16, wherein the probe card includes: a plurality of contact pins, wherein each contact pin has a first end configured to contact the interrogation side of the test contact, and configured to contact a One of the space transformers is in contact with a second end of the pad; the space transformer carries a plurality of the contact pads facing the second end of the contact pins; and a plating, which is on the space transformer These touch the top of the pad. The method of claim 19, wherein the plating above the contact pads of the space converter is a platinum iridium (PtIr) plating. Such as the method of claim 14, wherein the stud bump pin has a first stud bump tip and a first stud bump pin, and the device further includes a second stud stacked above the first stud bump pin Bump pin, wherein the second pillar bump pin terminates in the tip of a second pillar bump configured to detect the contact pad of the die. The method of claim 14, further comprising: forming the stud bump pin by: aligning the test contact with a formed wafer, wherein the stud bump pin faces a cavity of the formed wafer ; The surface of the cavity of the shaped wafer repeatedly contacts the stud bump pin; and the stud bump pin is formed to a specification internal value by wear or plastic deformation of the stud bump pin. Such as the method of claim 22, which further comprises: moving the test contact to a position Z ₁ and repeating N ₁ cycle; and moving the test contact to a position Z ₂ and repeating N ₂ cycle, where Z ₂ is greater than Z ₁ .

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