TWI735675B - 半導體元件及其製作方法 - Google Patents

半導體元件及其製作方法 Download PDF

Info

Publication number
TWI735675B
TWI735675B TW106134510A TW106134510A TWI735675B TW I735675 B TWI735675 B TW I735675B TW 106134510 A TW106134510 A TW 106134510A TW 106134510 A TW106134510 A TW 106134510A TW I735675 B TWI735675 B TW I735675B
Authority
TW
Taiwan
Prior art keywords
polysilicon
fin structure
dummy
semiconductor device
line pattern
Prior art date
Application number
TW106134510A
Other languages
English (en)
Other versions
TW201916112A (zh
Inventor
徐筱淋
劉恩銓
Original Assignee
聯華電子股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 聯華電子股份有限公司 filed Critical 聯華電子股份有限公司
Priority to TW106134510A priority Critical patent/TWI735675B/zh
Priority to US15/806,295 priority patent/US10170369B1/en
Priority to US16/200,670 priority patent/US10600692B2/en
Publication of TW201916112A publication Critical patent/TW201916112A/zh
Application granted granted Critical
Publication of TWI735675B publication Critical patent/TWI735675B/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7855—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with at least two independent gates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7856—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with an non-uniform gate, e.g. varying doping structure, shape or composition on different sides of the fin, or different gate insulator thickness or composition on opposing fin sides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Abstract

一種半導體元件，包含一基底，其上具有一溝渠絕緣結構及一鰭狀結構沿著一第一方向延伸，其中鰭狀結構突出於該溝渠絕緣結構的上表面，具有一第一高度；以及複數條閘極線，包含一第一閘極線及一第二閘極線，沿著一第二方向延伸，跨過鰭狀結構，其中第一閘極線於一閘極切斷區域內為不連續，而第二閘極線係鄰近於一虛設鰭狀結構區域，且不重疊於虛設鰭狀結構區域。鰭狀結構於虛設鰭狀結構區域內具有一第二高度，且第二高度小於第一高度。

Description

半導體元件及其製作方法
本發明係有關於半導體技術領域，特別是有關於一種鰭式半導體元件及其製作方法。
近年來，由於各種消費類電子產品的小型化，使得半導體元件的尺寸也必須微小化，以滿足高積集度、高性能、低功耗及各種產品需求。然而，隨著電子產品的小型化，現有的平面型場效電晶體(planar FET)已逐漸不符產品的要求。因此，該技術領域已發展出諸如鰭式場效電晶體(Fin-FET)等非平面型場效電晶體，以實現高驅動電流並減緩短通道效應。
已知，鰭式場效電晶體可以利用槽切優先(slot-cut first)製程來製作，所述槽切優先製程係在覆蓋於鰭狀結構上的一多晶矽層中預先形成多晶矽細線圖案的截斷區域，再以微影製程及蝕刻製程於多晶矽層中定義出多晶矽細線圖案。然而，過去的槽切優先製程會造成在塗布有機介電層(organic dielectric layer，ODL)的負載效應，影響製程良率。因此，該技術領域仍需要一種改良的製作方法。
本發明的主要目的在提供一種改良的半導體元件及其製作方法，以解決先前技藝的不足與缺點。
根據本發明一實施例，提供一種製作半導體元件的方法。首先提供一基底，其上具有一溝渠絕緣結構及複數個鰭狀結構沿著一第一方向延伸，其 中該複數個鰭狀結構突出於該溝渠絕緣結構的一上表面。再於該基底上全面沉積一多晶矽層。再於該多晶矽層中形成一多晶矽切口及一虛設開孔。於該基底上全面沉積一有機介電層，使該有機介電層填入該多晶矽切口及該虛設開孔。於該有機介電層上全面沉積一硬遮罩層。再於該硬遮罩層上形成複數個光阻細線圖案，包含沿著一第二方向延伸的一第一光阻細線圖案及一第二光阻細線圖案，其中該第一光阻細線圖案重疊該多晶矽切口，該第二光阻細線圖案係鄰近該虛設開孔，不重疊於該虛設開孔。再將該複數個光阻細線圖案轉移至該多晶矽層中，如此形成複數條沿著該第二方向延伸的多晶矽細線圖案。
根據本發明另一實施例，提供一種半導體元件，包含一基底，其上具有一溝渠絕緣結構及一鰭狀結構沿著一第一方向延伸，其中該鰭狀結構突出於該溝渠絕緣結構的上表面，具有一第一高度；以及複數條閘極線，包含一第一閘極線及一第二閘極線，沿著一第二方向延伸，跨過該鰭狀結構，其中該第一閘極線於一閘極切斷區域內為不連續，而該第二閘極線係鄰近於一虛設鰭狀結構區域，且不重疊於該虛設鰭狀結構區域，其中該鰭狀結構於該虛設鰭狀結構區域內具有一第二高度，且該第二高度小於該第一高度。
為讓本發明之上述目的、特徵及優點能更明顯易懂，下文特舉較佳實施方式，並配合所附圖式，作詳細說明如下。然而如下之較佳實施方式與圖式僅供參考與說明用，並非用來對本發明加以限制者。
1:半導體元件
11:密集圖案區域
11a:虛設鰭狀結構區域
12:非密集區域
12a:閘極切斷區域
100:基底
102:溝渠絕緣結構
102a:上表面
102b:凹陷結構
110:鰭狀結構
110a:上表面
200:多晶矽層
210:多晶矽細線圖案
210a:第一多晶矽細線圖案
210b:第二多晶矽細線圖案
301:有機介電層
302:底部抗反射層
303:硬遮罩層
310:光阻細線圖案
310a:第一光阻細線圖案
310b:第二光阻細線圖案
410:源/汲極接觸區域
501:介電層
510:金屬閘極線
510a:第一閘極線
510b:第二閘極線
h1:第一高度
h2:第二高度
PO:多晶矽切口
DO1、DO2:虛設開孔
第1A圖係依據本發明一實施例所繪示的在完成鰭狀結構及全面沉積多晶矽層之後的半導體基底的上視圖。
第1B圖為沿著第1A圖中切線I-I’所示的剖面示意圖。
第2A圖係依據本發明一實施例所繪示的在多晶矽層中形成多晶矽切口及虛 設開孔之後的半導體基底的上視圖。
第2B圖為沿著第2A圖中切線I-I’所示的剖面示意圖。
第3A圖係依據本發明一實施例所繪示的形成光阻細線圖案之後的半導體基底的上視圖。
第3B圖為沿著第3A圖中切線I-I’所示的剖面示意圖。
第4A圖係依據本發明一實施例所繪示的完成光阻細線圖案轉移之後的半導體基底的上視圖。
第4B圖為沿著第4A圖中切線I-I’所示的剖面示意圖。
第5A圖係依據本發明一實施例所繪示的完成置換金屬閘極製程之後的半導體基底的上視圖。
第5B圖為沿著第5A圖中切線I-I’所示的剖面示意圖。
在下文中，將參照附圖說明細節，該些附圖中之內容亦構成說明書細節描述的一部份，並且以可實行該實施例之特例描述方式來繪示。下文實施例已描述足夠的細節俾使該領域之一般技藝人士得以具以實施。
當然，亦可採行其他的實施例，或是在不悖離文中所述實施例的前提下作出任何結構性、邏輯性、及電性上的改變。因此，下文之細節描述不應被視為是限制，反之，其中所包含的實施例將由隨附的申請專利範圍來加以界定。
首先，請參閱第1A圖及第1B圖，其中第1A圖係依據本發明一實施例所繪示的在完成鰭狀結構及全面沉積多晶矽層之後的半導體基底的上視圖，第1B圖為沿著第1A圖中切線I-I’所示的剖面示意圖。
根據本發明一實施例，本發明披露一種製作半導體元件1的方法，例如，半導體元件1可以是一鰭式半導體元件或鰭式電晶體半導體元件，但不限於 此。首先，在一基底100上形成溝渠絕緣結構102及複數個鰭狀結構110。根據本發明一實施例，基底100可以是一半導體基底，例如矽基底，但不限於此。鰭狀結構110沿著一第一方向(即參考座標x軸方向)延伸。鰭狀結構110突出於溝渠絕緣結構102的一上表面102a。
如第1A圖所示，複數個鰭狀結構110構成密集圖案區域11，而在基底100上可以另有一非密集區域12，在非密集區域12中僅有溝渠絕緣結構102，未形成有鰭狀結構110。
根據本發明一實施例，密集圖案區域11包括一虛設鰭狀結構區域11a，鄰近非密集區域12。根據本發明一實施例，通過虛設鰭狀結構區域11a的鰭狀結構110上，不會用來形成任何的電路元件，例如電晶體、摻雜區或接觸元件等。根據本發明一實施例，在非密集區域12設有一閘極切斷區域12a。閘極切斷區域12a可以與溝渠絕緣結構102完全重疊，而不與鰭狀結構110重疊，但不限於此。
根據本發明一實施例，接著，於基底100上全面沉積一多晶矽層200。多晶矽層200覆蓋密集圖案區域11內的複數個鰭狀結構110，及非密集區域12內的溝渠絕緣結構102。從第1B圖可看到，鰭狀結構110突出於溝渠絕緣結構102的上表面102a，而具有一第一高度h1。在密集圖案區域11與非密集區域12的交界區構成一高低落差。
請參閱第2A圖及第2B圖，其中第2A圖係依據本發明一實施例所繪示的在多晶矽層中形成多晶矽切口及虛設開孔之後的半導體基底的上視圖，第2B圖為沿著第2A圖中切線I-I’所示的剖面示意圖。
如第2A圖及第2B圖所示，於多晶矽層200中形成一多晶矽切口PO、一虛設開孔DO1及一虛設開孔DO2。形成多晶矽切口PO、虛設開孔DO1及虛設開孔DO2的方式，可以利用微影製程及蝕刻製程同步完成。
根據本發明一實施例，虛設開孔DO1係直接位於虛設鰭狀結構區域11a上，且虛設開孔DO1顯露出虛設鰭狀結構區域11a內的鰭狀結構110。多晶矽切口PO係直接位於閘極切斷區域12a上，並與閘極切斷區域12a完全重疊。虛設開孔DO2則是鄰近於多晶矽切口PO，且直接位於溝渠絕緣結構102上。
根據本發明一實施例，經由虛設開孔DO1，虛設鰭狀結構區域11a內的部分的鰭狀結構110可以進一步被蝕刻掉，使得鰭狀結構110於虛設鰭狀結構區域11a內具有一第二高度h2，且該第二高度h2小於該第一高度h1。
此外，本發明方法另包含經由多晶矽切口PO及虛設開孔DO2凹陷蝕刻溝渠絕緣結構102，因此於閘極切斷區域12a內及虛設開孔DO2內的溝渠絕緣結構102中設有一凹陷結構102b。
根據本發明一實施例，虛設鰭狀結構區域11a內的鰭狀結構110的上表面110a仍高於溝渠絕緣結構102的上表面102a。
請參閱第3A圖及第3B圖，其中第3A圖係依據本發明一實施例所繪示的形成光阻細線圖案之後的半導體基底的上視圖，第3B圖為沿著第3A圖中切線I-I’所示的剖面示意圖。
如第3A圖及第3B圖所示，於多晶矽層200中形成多晶矽切口PO、虛設開孔DO1及虛設開孔DO2之後，接著於基底100上全面沉積一有機介電層(organic dielectric layer，ODL)301，使有機介電層301填入多晶矽切口PO及虛設開孔DO1及DO2。接著，可以於有機介電層301上形成一底部抗反射層302。然後，可以於底部抗反射層302上全面沉積一硬遮罩層303，例如，氮化矽層。
再於硬遮罩層303上形成複數個光阻細線圖案310，包含沿著一第二方向(即參考座標y軸方向)延伸的一第一光阻細線圖案310a及一第二光阻細線圖案310b，其中第一光阻細線圖案310a重疊多晶矽切口PO，第二光阻細線圖案310b係鄰近虛設開孔DO1，不重疊於虛設開孔DO1。根據本發明一實施例，複數 個光阻細線圖案310均不與虛設開孔DO1或虛設開孔DO2重疊。
請參閱第4A圖及第4B圖，其中第4A圖係依據本發明一實施例所繪示的完成光阻細線圖案轉移之後的半導體基底的上視圖，第4B圖為沿著第4A圖中切線I-I’所示的剖面示意圖。
如第4A圖及第4B圖所示，接著將複數個光阻細線圖案310轉移至多晶矽層200中，如此形成複數條沿著第二方向延伸的多晶矽細線圖案210。其中，複數條多晶矽細線圖案210包含對應於第一光阻細線圖案310a的一第一多晶矽細線圖案210a，其中第一多晶矽細線圖案210a被多晶矽切口PO截斷。
根據本發明一實施例，複數條多晶矽細線圖案210還包含對應於第二光阻細線圖案310b的一第二多晶矽細線圖案210b，其中第二多晶矽細線圖案210b與虛設鰭狀結構區域11a不重疊。
根據本發明一實施例，第二多晶矽細線圖案210b與虛設鰭狀結構區域11a之間設有一源/汲極接觸區域410。
請參閱第5A圖及第5B圖，其中第5A圖係依據本發明一實施例所繪示的完成置換金屬閘極(replacement metal gate，RMG)製程之後的半導體基底的上視圖，第5B圖為沿著第5A圖中切線I-I’所示的剖面示意圖。
如第5A圖及第5B圖所示，接著於基底100上形成一介電層501，並進行平坦化製程。然後，利用置換金屬閘極製程，將複數條多晶矽細線圖案210置換成複數條金屬閘極線510，包含一第一閘極線510a及一第二閘極線510b，沿著一第二方向延伸，跨過鰭狀結構110，其中第一閘極線510a於閘極切斷區域12a內為不連續，而第二閘極線510b係鄰近於虛設鰭狀結構區域11a，且不重疊於虛設鰭狀結構區域11a。
以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
1:半導體元件
11:密集圖案區域
11a:虛設鰭狀結構區域
12:非密集區域
12a:閘極切斷區域
100:基底
102:溝渠絕緣結構
102a:上表面
102b:凹陷結構
110:鰭狀結構
110a:上表面
200:多晶矽層
301:有機介電層
302:底部抗反射層
303:硬遮罩層
310:光阻細線圖案
310a:第一光阻細線圖案
310b:第二光阻細線圖案
h1:第一高度
h2:第二高度
PO:多晶矽切口
DO1、DO2:虛設開孔

Claims (12)

  1. 一種製作半導體元件的方法，包含：提供一基底，其上具有一溝渠絕緣結構及複數個鰭狀結構沿著一第一方向延伸，其中該複數個鰭狀結構突出於該溝渠絕緣結構的一上表面；於該基底上全面沉積一多晶矽層；於該多晶矽層中形成一多晶矽切口及一虛設開孔；於該基底上全面沉積一有機介電層，使該有機介電層填入該多晶矽切口及該虛設開孔；於該有機介電層上全面沉積一硬遮罩層；於該硬遮罩層上形成複數個光阻細線圖案，包含沿著一第二方向延伸的一第一光阻細線圖案及一第二光阻細線圖案，其中該第一光阻細線圖案重疊該多晶矽切口，該第二光阻細線圖案係鄰近該虛設開孔，不重疊於該虛設開孔；以及將該複數個光阻細線圖案轉移至該多晶矽層中，如此形成複數條沿著該第二方向延伸的多晶矽細線圖案。
  2. 如請求項1所述的製作半導體元件的方法，其中另包含：在全面沉積該硬遮罩層之前，於該有機介電層上形成一底部抗反射層。
  3. 如請求項1所述的製作半導體元件的方法，其中該複數條多晶矽細線圖案包含對應於該第一光阻細線圖案的一第一多晶矽細線圖案，其中該第一多晶矽細線圖案被該多晶矽切口截斷。
  4. 如請求項3所述的製作半導體元件的方法，其中該虛設開孔係直接位於一虛設鰭狀結構區域上，且該複數條多晶矽細線圖案包含對應於該第二光阻 細線圖案的一第二多晶矽細線圖案，其中該第二多晶矽細線圖案與該虛設鰭狀結構區域不重疊。
  5. 如請求項4所述的製作半導體元件的方法，其中於該第二多晶矽細線圖案與該虛設鰭狀結構區域之間設有一源/汲極接觸區域。
  6. 如請求項4所述的製作半導體元件的方法，其中該虛設鰭狀結構區域內的部分該複數個鰭狀結構係被去除。
  7. 如請求項6所述的製作半導體元件的方法，其中該複數個光阻細線圖案不與該虛設開孔重疊。
  8. 如請求項1所述的製作半導體元件的方法，其中該多晶矽切口係與該溝渠絕緣結構完全重疊，而不與任一該複數個鰭狀結構重疊。
  9. 如請求項8所述的製作半導體元件的方法，其中另包含經由該多晶矽切口凹陷蝕刻該溝渠絕緣結構。
  10. 一種半導體元件，包含：一基底，其上具有一溝渠絕緣結構及一鰭狀結構沿著一第一方向延伸，其中該鰭狀結構突出於該溝渠絕緣結構的上表面，具有一第一高度；以及複數條閘極線，包含一第一閘極線及一第二閘極線，沿著一第二方向延伸，跨過該鰭狀結構，其中該第一閘極線於一閘極切斷區域內為不連續，而該第二閘極線係鄰近於一虛設鰭狀結構區域，且不重疊於該虛設鰭狀結構區域，其中 該鰭狀結構於該虛設鰭狀結構區域內具有一第二高度，且該第二高度小於該第一高度，其中，在該溝渠絕緣結構上方設置有一非密集區域和一凹陷結構，該凹陷結構部分的沿該第一方向設置在該閘極切斷區域內的該非密集區域的底部。
  11. 如請求項10所述的半導體元件，其中該閘極切斷區域係與該溝渠絕緣結構完全重疊，而不與該鰭狀結構重疊。
  12. 如請求項10所述的半導體元件，其中該虛設鰭狀結構區域內的該鰭狀結構的上表面高於該溝渠絕緣結構的上表面。
TW106134510A 2017-10-06 2017-10-06 半導體元件及其製作方法 TWI735675B (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
TW106134510A TWI735675B (zh) 2017-10-06 2017-10-06 半導體元件及其製作方法
US15/806,295 US10170369B1 (en) 2017-10-06 2017-11-07 Semiconductor device and fabrication method thereof
US16/200,670 US10600692B2 (en) 2017-10-06 2018-11-27 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW106134510A TWI735675B (zh) 2017-10-06 2017-10-06 半導體元件及其製作方法

Publications (2)

Publication Number Publication Date
TW201916112A TW201916112A (zh) 2019-04-16
TWI735675B true TWI735675B (zh) 2021-08-11

Family

ID=64736649

Family Applications (1)

Application Number Title Priority Date Filing Date
TW106134510A TWI735675B (zh) 2017-10-06 2017-10-06 半導體元件及其製作方法

Country Status (2)

Country Link
US (2) US10170369B1 (zh)
TW (1) TWI735675B (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113241324B (zh) * 2021-05-08 2023-09-22 福建省晋华集成电路有限公司 形成半导体存储器件的方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201539543A (zh) * 2014-04-01 2015-10-16 Taiwan Semiconductor Mfg Co Ltd 半導體裝置之製造方法
US9685336B1 (en) * 2016-02-29 2017-06-20 Globalfoundries Inc. Process monitoring for gate cut mask

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10026737B1 (en) * 2016-12-30 2018-07-17 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201539543A (zh) * 2014-04-01 2015-10-16 Taiwan Semiconductor Mfg Co Ltd 半導體裝置之製造方法
US9685336B1 (en) * 2016-02-29 2017-06-20 Globalfoundries Inc. Process monitoring for gate cut mask

Also Published As

Publication number Publication date
US10600692B2 (en) 2020-03-24
US10170369B1 (en) 2019-01-01
US20190109050A1 (en) 2019-04-11
TW201916112A (zh) 2019-04-16

Similar Documents

Publication Publication Date Title
TWI397973B (zh) 具反向源極／汲極金屬接點的場效電晶體及其製造方法
US9660022B2 (en) Semiconductive device with a single diffusion break and method of fabricating the same
TWI706483B (zh) 在積體電路產品上形成接觸結構之方法
US9570468B2 (en) Semiconductor device with three or four-terminal-FinFET
TWI783064B (zh) 半導體裝置及其形成方法
US10096522B2 (en) Dummy MOL removal for performance enhancement
CN111564371A (zh) 鳍状结构及其制造方法
TWI694614B (zh) 位在矽覆絕緣層上的鰭狀場效電晶體及其形成方法
US20240153940A1 (en) Semiconductor device having fin structure
TW201703140A (zh) 半導體裝置及其製作方法
TWI735675B (zh) 半導體元件及其製作方法
TW202137572A (zh) 積體晶片
TWI748346B (zh) 多閘極之半導體結構及其製造方法
US11264488B2 (en) Manufacturing method of semiconductor structure
CN110690219B (zh) 一种三维存储器及其制备方法、一种光刻掩膜版
US10475895B2 (en) Semiconductor device and method for manufacturing the same
CN105448968B (zh) 鳍式场效应晶体管的制作方法
US9349813B2 (en) Method for fabricating semiconductor device
CN203277389U (zh) 半导体装置
US20200294853A1 (en) Semiconductor device and forming method thereof
TWI704690B (zh) 半導體裝置以及其製作方法
TW201444086A (zh) 半導體裝置及其製作方法
CN113394215A (zh) 一种鳍式场效应晶体管标准单元结构
CN115692416A (zh) 半导体结构及其形成方法
CN113658865A (zh) 半导体结构的形成方法